diff --git a/cores/arduino/stm32/LL/stm32yyxx_ll.h b/cores/arduino/stm32/LL/stm32yyxx_ll.h index 432af97d92..8df3b10289 100644 --- a/cores/arduino/stm32/LL/stm32yyxx_ll.h +++ b/cores/arduino/stm32/LL/stm32yyxx_ll.h @@ -22,6 +22,7 @@ #include "stm32yyxx_ll_exti.h" #include "stm32yyxx_ll_fmac.h" #include "stm32yyxx_ll_fmc.h" +#include "stm32yyxx_ll_fmpi2c.h" #include "stm32yyxx_ll_fsmc.h" #include "stm32yyxx_ll_gpio.h" #include "stm32yyxx_ll_hrtim.h" diff --git a/cores/arduino/stm32/LL/stm32yyxx_ll_fmpi2c.h b/cores/arduino/stm32/LL/stm32yyxx_ll_fmpi2c.h new file mode 100644 index 0000000000..ed68d4eeb3 --- /dev/null +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_fmpi2c.h @@ -0,0 +1,12 @@ +#ifndef _STM32YYXX_LL_FMPI2C_H_ +#define _STM32YYXX_LL_FMPI2C_H_ +/* LL raised several warnings, ignore them */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wunused-parameter" +#pragma GCC diagnostic ignored "-Wstrict-aliasing" + +#ifdef STM32F4xx + #include "stm32f4xx_ll_fmpi2c.h" +#endif +#pragma GCC diagnostic pop +#endif /* _STM32YYXX_LL_FMPI2C_H_ */ diff --git a/cores/arduino/stm32/usb/cdc/usbd_cdc.c b/cores/arduino/stm32/usb/cdc/usbd_cdc.c index eb3d681172..9ee0d7885a 100644 --- a/cores/arduino/stm32/usb/cdc/usbd_cdc.c +++ b/cores/arduino/stm32/usb/cdc/usbd_cdc.c @@ -45,7 +45,7 @@ * This software component is licensed by ST under Ultimate Liberty license * SLA0044, the "License"; You may not use this file except in compliance with * the License. You may obtain a copy of the License at: - * http://www.st.com/SLA0044 + * www.st.com/SLA0044 * ****************************************************************************** */ @@ -97,32 +97,17 @@ * @{ */ - -static uint8_t USBD_CDC_Init(USBD_HandleTypeDef *pdev, - uint8_t cfgidx); - -static uint8_t USBD_CDC_DeInit(USBD_HandleTypeDef *pdev, - uint8_t cfgidx); - -static uint8_t USBD_CDC_Setup(USBD_HandleTypeDef *pdev, - USBD_SetupReqTypedef *req); - -static uint8_t USBD_CDC_DataIn(USBD_HandleTypeDef *pdev, - uint8_t epnum); - -static uint8_t USBD_CDC_DataOut(USBD_HandleTypeDef *pdev, - uint8_t epnum); - -static uint8_t USBD_CDC_EP0_RxReady(USBD_HandleTypeDef *pdev); - -static uint8_t *USBD_CDC_GetFSCfgDesc(uint16_t *length); - -static uint8_t *USBD_CDC_GetHSCfgDesc(uint16_t *length); - -static uint8_t *USBD_CDC_GetOtherSpeedCfgDesc(uint16_t *length); - -static uint8_t *USBD_CDC_GetOtherSpeedCfgDesc(uint16_t *length); - +static uint8_t USBD_CDC_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx); +static uint8_t USBD_CDC_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx); +static uint8_t USBD_CDC_Setup(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); +static uint8_t USBD_CDC_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum); +static uint8_t USBD_CDC_DataOut(USBD_HandleTypeDef *pdev, uint8_t epnum); +static uint8_t USBD_CDC_EP0_RxReady(USBD_HandleTypeDef *pdev); + +static uint8_t *USBD_CDC_GetFSCfgDesc(uint16_t *length); +static uint8_t *USBD_CDC_GetHSCfgDesc(uint16_t *length); +static uint8_t *USBD_CDC_GetOtherSpeedCfgDesc(uint16_t *length); +static uint8_t *USBD_CDC_GetOtherSpeedCfgDesc(uint16_t *length); uint8_t *USBD_CDC_GetDeviceQualifierDescriptor(uint16_t *length); /* USB Standard Device Descriptor */ @@ -167,283 +152,254 @@ USBD_ClassTypeDef USBD_CDC = { }; /* USB CDC device Configuration Descriptor */ -__ALIGN_BEGIN uint8_t USBD_CDC_CfgHSDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END = { - /*Configuration Descriptor*/ - 0x09, /* bLength: Configuration Descriptor size */ - USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */ - USB_CDC_CONFIG_DESC_SIZ, /* wTotalLength:no of returned bytes */ +__ALIGN_BEGIN static uint8_t USBD_CDC_CfgHSDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END = { + /* Configuration Descriptor */ + 0x09, /* bLength: Configuration Descriptor size */ + USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */ + USB_CDC_CONFIG_DESC_SIZ, /* wTotalLength:no of returned bytes */ 0x00, - 0x02, /* bNumInterfaces: 2 interface */ - 0x01, /* bConfigurationValue: Configuration value */ - 0x00, /* iConfiguration: Index of string descriptor describing the configuration */ - 0xC0, /* bmAttributes: self powered */ - 0x32, /* MaxPower 0 mA */ - + 0x02, /* bNumInterfaces: 2 interface */ + 0x01, /* bConfigurationValue: Configuration value */ + 0x00, /* iConfiguration: Index of string descriptor describing the configuration */ + 0xC0, /* bmAttributes: self powered */ + 0x32, /* MaxPower 0 mA */ /*---------------------------------------------------------------------------*/ - /*Interface Descriptor */ - 0x09, /* bLength: Interface Descriptor size */ - USB_DESC_TYPE_INTERFACE, /* bDescriptorType: Interface */ + /* Interface Descriptor */ + 0x09, /* bLength: Interface Descriptor size */ + USB_DESC_TYPE_INTERFACE, /* bDescriptorType: Interface */ /* Interface descriptor type */ - 0x00, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x01, /* bNumEndpoints: One endpoints used */ - 0x02, /* bInterfaceClass: Communication Interface Class */ - 0x02, /* bInterfaceSubClass: Abstract Control Model */ - 0x00, /* bInterfaceProtocol: No specific protocol */ - 0x00, /* iInterface: */ - - /*Header Functional Descriptor*/ - 0x05, /* bLength: Endpoint Descriptor size */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x00, /* bDescriptorSubtype: Header Func Desc */ - 0x10, /* bcdCDC: spec release number */ + 0x00, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x01, /* bNumEndpoints: One endpoints used */ + 0x02, /* bInterfaceClass: Communication Interface Class */ + 0x02, /* bInterfaceSubClass: Abstract Control Model */ + 0x00, /* bInterfaceProtocol: No specific protocol */ + 0x00, /* iInterface: */ + /* Header Functional Descriptor */ + 0x05, /* bLength: Endpoint Descriptor size */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x00, /* bDescriptorSubtype: Header Func Desc */ + 0x10, /* bcdCDC: spec release number */ 0x01, - - /*Call Management Functional Descriptor*/ - 0x05, /* bFunctionLength */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x01, /* bDescriptorSubtype: Call Management Func Desc */ - 0x00, /* bmCapabilities: D0+D1 */ - 0x01, /* bDataInterface: 1 */ - - /*ACM Functional Descriptor*/ - 0x04, /* bFunctionLength */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x02, /* bDescriptorSubtype: Abstract Control Management desc */ - 0x02, /* bmCapabilities */ - - /*Union Functional Descriptor*/ - 0x05, /* bFunctionLength */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x06, /* bDescriptorSubtype: Union func desc */ - 0x00, /* bMasterInterface: Communication class interface */ - 0x01, /* bSlaveInterface0: Data Class Interface */ - - /*Endpoint 2 Descriptor*/ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ - CDC_CMD_EP, /* bEndpointAddress */ - 0x03, /* bmAttributes: Interrupt */ - LOBYTE(CDC_CMD_PACKET_SIZE), /* wMaxPacketSize: */ + /* Call Management Functional Descriptor */ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x01, /* bDescriptorSubtype: Call Management Func Desc */ + 0x00, /* bmCapabilities: D0+D1 */ + 0x01, /* bDataInterface: 1 */ + /* ACM Functional Descriptor */ + 0x04, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x02, /* bDescriptorSubtype: Abstract Control Management desc */ + 0x02, /* bmCapabilities */ + /* Union Functional Descriptor */ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x06, /* bDescriptorSubtype: Union func desc */ + 0x00, /* bMasterInterface: Communication class interface */ + 0x01, /* bSlaveInterface0: Data Class Interface */ + /* Endpoint 2 Descriptor */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + CDC_CMD_EP, /* bEndpointAddress */ + 0x03, /* bmAttributes: Interrupt */ + LOBYTE(CDC_CMD_PACKET_SIZE), /* wMaxPacketSize: */ HIBYTE(CDC_CMD_PACKET_SIZE), - CDC_HS_BINTERVAL, /* bInterval: */ + CDC_HS_BINTERVAL, /* bInterval: */ /*---------------------------------------------------------------------------*/ - - /*Data class interface descriptor*/ - 0x09, /* bLength: Endpoint Descriptor size */ - USB_DESC_TYPE_INTERFACE, /* bDescriptorType: */ - 0x01, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x02, /* bNumEndpoints: Two endpoints used */ - 0x0A, /* bInterfaceClass: CDC */ - 0x00, /* bInterfaceSubClass: */ - 0x00, /* bInterfaceProtocol: */ - 0x00, /* iInterface: */ - - /*Endpoint OUT Descriptor*/ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ - CDC_OUT_EP, /* bEndpointAddress */ - 0x02, /* bmAttributes: Bulk */ + /* Data class interface descriptor */ + 0x09, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_INTERFACE, /* bDescriptorType: */ + 0x01, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x02, /* bNumEndpoints: Two endpoints used */ + 0x0A, /* bInterfaceClass: CDC */ + 0x00, /* bInterfaceSubClass: */ + 0x00, /* bInterfaceProtocol: */ + 0x00, /* iInterface: */ + /* Endpoint OUT Descriptor */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + CDC_OUT_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ LOBYTE(CDC_DATA_HS_MAX_PACKET_SIZE), /* wMaxPacketSize: */ HIBYTE(CDC_DATA_HS_MAX_PACKET_SIZE), - 0x00, /* bInterval: ignore for Bulk transfer */ - - /*Endpoint IN Descriptor*/ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ - CDC_IN_EP, /* bEndpointAddress */ - 0x02, /* bmAttributes: Bulk */ + 0x00, /* bInterval: ignore for Bulk transfer */ + /* Endpoint IN Descriptor */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + CDC_IN_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ LOBYTE(CDC_DATA_HS_MAX_PACKET_SIZE), /* wMaxPacketSize: */ HIBYTE(CDC_DATA_HS_MAX_PACKET_SIZE), - 0x00 /* bInterval: ignore for Bulk transfer */ -} ; + 0x00 /* bInterval: ignore for Bulk transfer */ +}; /* USB CDC device Configuration Descriptor */ -__ALIGN_BEGIN uint8_t USBD_CDC_CfgFSDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END = { - /*Configuration Descriptor*/ - 0x09, /* bLength: Configuration Descriptor size */ - USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */ - USB_CDC_CONFIG_DESC_SIZ, /* wTotalLength:no of returned bytes */ +__ALIGN_BEGIN static uint8_t USBD_CDC_CfgFSDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END = { + /* Configuration Descriptor */ + 0x09, /* bLength: Configuration Descriptor size */ + USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */ + USB_CDC_CONFIG_DESC_SIZ, /* wTotalLength:no of returned bytes */ 0x00, - 0x02, /* bNumInterfaces: 2 interface */ - 0x01, /* bConfigurationValue: Configuration value */ - 0x00, /* iConfiguration: Index of string descriptor describing the configuration */ - 0xC0, /* bmAttributes: self powered */ - 0x32, /* MaxPower 0 mA */ - + 0x02, /* bNumInterfaces: 2 interface */ + 0x01, /* bConfigurationValue: Configuration value */ + 0x00, /* iConfiguration: Index of string descriptor describing the configuration */ + 0xC0, /* bmAttributes: self powered */ + 0x32, /* MaxPower 0 mA */ /*---------------------------------------------------------------------------*/ - - /*Interface Descriptor */ - 0x09, /* bLength: Interface Descriptor size */ - USB_DESC_TYPE_INTERFACE, /* bDescriptorType: Interface */ + /* Interface Descriptor */ + 0x09, /* bLength: Interface Descriptor size */ + USB_DESC_TYPE_INTERFACE, /* bDescriptorType: Interface */ /* Interface descriptor type */ - 0x00, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x01, /* bNumEndpoints: One endpoints used */ - 0x02, /* bInterfaceClass: Communication Interface Class */ - 0x02, /* bInterfaceSubClass: Abstract Control Model */ - 0x00, /* bInterfaceProtocol: No specific protocol */ - 0x00, /* iInterface: */ - - /*Header Functional Descriptor*/ - 0x05, /* bLength: Endpoint Descriptor size */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x00, /* bDescriptorSubtype: Header Func Desc */ - 0x10, /* bcdCDC: spec release number */ + 0x00, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x01, /* bNumEndpoints: One endpoints used */ + 0x02, /* bInterfaceClass: Communication Interface Class */ + 0x02, /* bInterfaceSubClass: Abstract Control Model */ + 0x00, /* bInterfaceProtocol: No specific protocol */ + 0x00, /* iInterface: */ + /* Header Functional Descriptor */ + 0x05, /* bLength: Endpoint Descriptor size */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x00, /* bDescriptorSubtype: Header Func Desc */ + 0x10, /* bcdCDC: spec release number */ 0x01, - - /*Call Management Functional Descriptor*/ - 0x05, /* bFunctionLength */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x01, /* bDescriptorSubtype: Call Management Func Desc */ - 0x00, /* bmCapabilities: D0+D1 */ - 0x01, /* bDataInterface: 1 */ - - /*ACM Functional Descriptor*/ - 0x04, /* bFunctionLength */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x02, /* bDescriptorSubtype: Abstract Control Management desc */ - 0x02, /* bmCapabilities */ - - /*Union Functional Descriptor*/ - 0x05, /* bFunctionLength */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x06, /* bDescriptorSubtype: Union func desc */ - 0x00, /* bMasterInterface: Communication class interface */ - 0x01, /* bSlaveInterface0: Data Class Interface */ - - /*Endpoint 2 Descriptor*/ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ - CDC_CMD_EP, /* bEndpointAddress */ - 0x03, /* bmAttributes: Interrupt */ - LOBYTE(CDC_CMD_PACKET_SIZE), /* wMaxPacketSize: */ + /* Call Management Functional Descriptor */ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x01, /* bDescriptorSubtype: Call Management Func Desc */ + 0x00, /* bmCapabilities: D0+D1 */ + 0x01, /* bDataInterface: 1 */ + /* ACM Functional Descriptor */ + 0x04, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x02, /* bDescriptorSubtype: Abstract Control Management desc */ + 0x02, /* bmCapabilities */ + /* Union Functional Descriptor */ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x06, /* bDescriptorSubtype: Union func desc */ + 0x00, /* bMasterInterface: Communication class interface */ + 0x01, /* bSlaveInterface0: Data Class Interface */ + /* Endpoint 2 Descriptor */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + CDC_CMD_EP, /* bEndpointAddress */ + 0x03, /* bmAttributes: Interrupt */ + LOBYTE(CDC_CMD_PACKET_SIZE), /* wMaxPacketSize: */ HIBYTE(CDC_CMD_PACKET_SIZE), - CDC_FS_BINTERVAL, /* bInterval: */ + CDC_FS_BINTERVAL, /* bInterval: */ /*---------------------------------------------------------------------------*/ - - /*Data class interface descriptor*/ - 0x09, /* bLength: Endpoint Descriptor size */ - USB_DESC_TYPE_INTERFACE, /* bDescriptorType: */ - 0x01, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x02, /* bNumEndpoints: Two endpoints used */ - 0x0A, /* bInterfaceClass: CDC */ - 0x00, /* bInterfaceSubClass: */ - 0x00, /* bInterfaceProtocol: */ - 0x00, /* iInterface: */ - - /*Endpoint OUT Descriptor*/ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ - CDC_OUT_EP, /* bEndpointAddress */ - 0x02, /* bmAttributes: Bulk */ + /* Data class interface descriptor */ + 0x09, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_INTERFACE, /* bDescriptorType: */ + 0x01, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x02, /* bNumEndpoints: Two endpoints used */ + 0x0A, /* bInterfaceClass: CDC */ + 0x00, /* bInterfaceSubClass: */ + 0x00, /* bInterfaceProtocol: */ + 0x00, /* iInterface: */ + /* Endpoint OUT Descriptor */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + CDC_OUT_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ LOBYTE(CDC_DATA_FS_MAX_PACKET_SIZE), /* wMaxPacketSize: */ HIBYTE(CDC_DATA_FS_MAX_PACKET_SIZE), - 0x00, /* bInterval: ignore for Bulk transfer */ - - /*Endpoint IN Descriptor*/ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ - CDC_IN_EP, /* bEndpointAddress */ - 0x02, /* bmAttributes: Bulk */ + 0x00, /* bInterval: ignore for Bulk transfer */ + /* Endpoint IN Descriptor */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + CDC_IN_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ LOBYTE(CDC_DATA_FS_MAX_PACKET_SIZE), /* wMaxPacketSize: */ HIBYTE(CDC_DATA_FS_MAX_PACKET_SIZE), - 0x00 /* bInterval: ignore for Bulk transfer */ -} ; + 0x00 /* bInterval: ignore for Bulk transfer */ +}; -__ALIGN_BEGIN uint8_t USBD_CDC_OtherSpeedCfgDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END = { - 0x09, /* bLength: Configuation Descriptor size */ +__ALIGN_BEGIN static uint8_t USBD_CDC_OtherSpeedCfgDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END = { + 0x09, /* bLength: Configuation Descriptor size */ USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION, USB_CDC_CONFIG_DESC_SIZ, 0x00, - 0x02, /* bNumInterfaces: 2 interfaces */ - 0x01, /* bConfigurationValue: */ - 0x04, /* iConfiguration: */ - 0xC0, /* bmAttributes: */ - 0x32, /* MaxPower 100 mA */ - + 0x02, /* bNumInterfaces: 2 interfaces */ + 0x01, /* bConfigurationValue: */ + 0x04, /* iConfiguration: */ + 0xC0, /* bmAttributes: */ + 0x32, /* MaxPower 100 mA */ /*Interface Descriptor */ - 0x09, /* bLength: Interface Descriptor size */ - USB_DESC_TYPE_INTERFACE, /* bDescriptorType: Interface */ + 0x09, /* bLength: Interface Descriptor size */ + USB_DESC_TYPE_INTERFACE, /* bDescriptorType: Interface */ /* Interface descriptor type */ - 0x00, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x01, /* bNumEndpoints: One endpoints used */ - 0x02, /* bInterfaceClass: Communication Interface Class */ - 0x02, /* bInterfaceSubClass: Abstract Control Model */ - 0x00, /* bInterfaceProtocol: No specific protocol */ - 0x00, /* iInterface: */ - - /*Header Functional Descriptor*/ - 0x05, /* bLength: Endpoint Descriptor size */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x00, /* bDescriptorSubtype: Header Func Desc */ - 0x10, /* bcdCDC: spec release number */ + 0x00, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x01, /* bNumEndpoints: One endpoints used */ + 0x02, /* bInterfaceClass: Communication Interface Class */ + 0x02, /* bInterfaceSubClass: Abstract Control Model */ + 0x00, /* bInterfaceProtocol: No specific protocol */ + 0x00, /* iInterface: */ + /* Header Functional Descriptor */ + 0x05, /* bLength: Endpoint Descriptor size */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x00, /* bDescriptorSubtype: Header Func Desc */ + 0x10, /* bcdCDC: spec release number */ 0x01, - /*Call Management Functional Descriptor*/ - 0x05, /* bFunctionLength */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x01, /* bDescriptorSubtype: Call Management Func Desc */ - 0x00, /* bmCapabilities: D0+D1 */ - 0x01, /* bDataInterface: 1 */ - + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x01, /* bDescriptorSubtype: Call Management Func Desc */ + 0x00, /* bmCapabilities: D0+D1 */ + 0x01, /* bDataInterface: 1 */ /*ACM Functional Descriptor*/ - 0x04, /* bFunctionLength */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x02, /* bDescriptorSubtype: Abstract Control Management desc */ - 0x02, /* bmCapabilities */ - + 0x04, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x02, /* bDescriptorSubtype: Abstract Control Management desc */ + 0x02, /* bmCapabilities */ /*Union Functional Descriptor*/ - 0x05, /* bFunctionLength */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x06, /* bDescriptorSubtype: Union func desc */ - 0x00, /* bMasterInterface: Communication class interface */ - 0x01, /* bSlaveInterface0: Data Class Interface */ - + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x06, /* bDescriptorSubtype: Union func desc */ + 0x00, /* bMasterInterface: Communication class interface */ + 0x01, /* bSlaveInterface0: Data Class Interface */ /*Endpoint 2 Descriptor*/ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ - CDC_CMD_EP, /* bEndpointAddress */ - 0x03, /* bmAttributes: Interrupt */ - LOBYTE(CDC_CMD_PACKET_SIZE), /* wMaxPacketSize: */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + CDC_CMD_EP, /* bEndpointAddress */ + 0x03, /* bmAttributes: Interrupt */ + LOBYTE(CDC_CMD_PACKET_SIZE), /* wMaxPacketSize: */ HIBYTE(CDC_CMD_PACKET_SIZE), - CDC_FS_BINTERVAL, /* bInterval: */ - + CDC_FS_BINTERVAL, /* bInterval: */ /*---------------------------------------------------------------------------*/ - /*Data class interface descriptor*/ - 0x09, /* bLength: Endpoint Descriptor size */ - USB_DESC_TYPE_INTERFACE, /* bDescriptorType: */ - 0x01, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x02, /* bNumEndpoints: Two endpoints used */ - 0x0A, /* bInterfaceClass: CDC */ - 0x00, /* bInterfaceSubClass: */ - 0x00, /* bInterfaceProtocol: */ - 0x00, /* iInterface: */ - + 0x09, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_INTERFACE, /* bDescriptorType: */ + 0x01, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x02, /* bNumEndpoints: Two endpoints used */ + 0x0A, /* bInterfaceClass: CDC */ + 0x00, /* bInterfaceSubClass: */ + 0x00, /* bInterfaceProtocol: */ + 0x00, /* iInterface: */ /*Endpoint OUT Descriptor*/ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ - CDC_OUT_EP, /* bEndpointAddress */ - 0x02, /* bmAttributes: Bulk */ - 0x40, /* wMaxPacketSize: */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + CDC_OUT_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + 0x40, /* wMaxPacketSize: */ 0x00, - 0x00, /* bInterval: ignore for Bulk transfer */ - + 0x00, /* bInterval: ignore for Bulk transfer */ /*Endpoint IN Descriptor*/ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ - CDC_IN_EP, /* bEndpointAddress */ - 0x02, /* bmAttributes: Bulk */ - 0x40, /* wMaxPacketSize: */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + CDC_IN_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + 0x40, /* wMaxPacketSize: */ 0x00, - 0x00 /* bInterval */ + 0x00 /* bInterval */ }; /** @@ -463,65 +419,72 @@ __ALIGN_BEGIN uint8_t USBD_CDC_OtherSpeedCfgDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIG */ static uint8_t USBD_CDC_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { - uint8_t ret = 0U; UNUSED(cfgidx); USBD_CDC_HandleTypeDef *hcdc; + hcdc = USBD_malloc(sizeof(USBD_CDC_HandleTypeDef)); + + if (hcdc == NULL) { + pdev->pClassData = NULL; + return (uint8_t)USBD_EMEM; + } + + pdev->pClassData = (void *)hcdc; + if (pdev->dev_speed == USBD_SPEED_HIGH) { /* Open EP IN */ - USBD_LL_OpenEP(pdev, CDC_IN_EP, USBD_EP_TYPE_BULK, - CDC_DATA_HS_IN_PACKET_SIZE); + (void)USBD_LL_OpenEP(pdev, CDC_IN_EP, USBD_EP_TYPE_BULK, + CDC_DATA_HS_IN_PACKET_SIZE); pdev->ep_in[CDC_IN_EP & 0xFU].is_used = 1U; /* Open EP OUT */ - USBD_LL_OpenEP(pdev, CDC_OUT_EP, USBD_EP_TYPE_BULK, - CDC_DATA_HS_OUT_PACKET_SIZE); + (void)USBD_LL_OpenEP(pdev, CDC_OUT_EP, USBD_EP_TYPE_BULK, + CDC_DATA_HS_OUT_PACKET_SIZE); pdev->ep_out[CDC_OUT_EP & 0xFU].is_used = 1U; + /* Set bInterval for CDC CMD Endpoint */ + pdev->ep_in[CDC_CMD_EP & 0xFU].bInterval = CDC_HS_BINTERVAL; } else { /* Open EP IN */ - USBD_LL_OpenEP(pdev, CDC_IN_EP, USBD_EP_TYPE_BULK, - CDC_DATA_FS_IN_PACKET_SIZE); + (void)USBD_LL_OpenEP(pdev, CDC_IN_EP, USBD_EP_TYPE_BULK, + CDC_DATA_FS_IN_PACKET_SIZE); pdev->ep_in[CDC_IN_EP & 0xFU].is_used = 1U; /* Open EP OUT */ - USBD_LL_OpenEP(pdev, CDC_OUT_EP, USBD_EP_TYPE_BULK, - CDC_DATA_FS_OUT_PACKET_SIZE); + (void)USBD_LL_OpenEP(pdev, CDC_OUT_EP, USBD_EP_TYPE_BULK, + CDC_DATA_FS_OUT_PACKET_SIZE); pdev->ep_out[CDC_OUT_EP & 0xFU].is_used = 1U; + + /* Set bInterval for CMD Endpoint */ + pdev->ep_in[CDC_CMD_EP & 0xFU].bInterval = CDC_FS_BINTERVAL; } + /* Open Command IN EP */ - USBD_LL_OpenEP(pdev, CDC_CMD_EP, USBD_EP_TYPE_INTR, CDC_CMD_PACKET_SIZE); + (void)USBD_LL_OpenEP(pdev, CDC_CMD_EP, USBD_EP_TYPE_INTR, CDC_CMD_PACKET_SIZE); pdev->ep_in[CDC_CMD_EP & 0xFU].is_used = 1U; - pdev->pClassData = USBD_malloc(sizeof(USBD_CDC_HandleTypeDef)); + /* Init physical Interface components */ + ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Init(); - if (pdev->pClassData == NULL) { - ret = 1U; - } else { - hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData; + /* Init Xfer states */ + hcdc->TxState = 0U; + hcdc->RxState = 0U; - /* Init physical Interface components */ - ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Init(); - - /* Init Xfer states */ - hcdc->TxState = 0U; - hcdc->RxState = 0U; - - if (pdev->dev_speed == USBD_SPEED_HIGH) { - /* Prepare Out endpoint to receive next packet */ - USBD_LL_PrepareReceive(pdev, CDC_OUT_EP, hcdc->RxBuffer, - CDC_DATA_HS_OUT_PACKET_SIZE); - } else { - /* Prepare Out endpoint to receive next packet */ - USBD_LL_PrepareReceive(pdev, CDC_OUT_EP, hcdc->RxBuffer, - CDC_DATA_FS_OUT_PACKET_SIZE); - } + if (pdev->dev_speed == USBD_SPEED_HIGH) { + /* Prepare Out endpoint to receive next packet */ + (void)USBD_LL_PrepareReceive(pdev, CDC_OUT_EP, hcdc->RxBuffer, + CDC_DATA_HS_OUT_PACKET_SIZE); + } else { + /* Prepare Out endpoint to receive next packet */ + (void)USBD_LL_PrepareReceive(pdev, CDC_OUT_EP, hcdc->RxBuffer, + CDC_DATA_FS_OUT_PACKET_SIZE); } - return ret; + + return (uint8_t)USBD_OK; } /** @@ -533,25 +496,26 @@ static uint8_t USBD_CDC_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx) */ static uint8_t USBD_CDC_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { - uint8_t ret = 0U; UNUSED(cfgidx); + uint8_t ret = 0U; /* Close EP IN */ - USBD_LL_CloseEP(pdev, CDC_IN_EP); + (void)USBD_LL_CloseEP(pdev, CDC_IN_EP); pdev->ep_in[CDC_IN_EP & 0xFU].is_used = 0U; /* Close EP OUT */ - USBD_LL_CloseEP(pdev, CDC_OUT_EP); + (void)USBD_LL_CloseEP(pdev, CDC_OUT_EP); pdev->ep_out[CDC_OUT_EP & 0xFU].is_used = 0U; /* Close Command IN EP */ - USBD_LL_CloseEP(pdev, CDC_CMD_EP); + (void)USBD_LL_CloseEP(pdev, CDC_CMD_EP); pdev->ep_in[CDC_CMD_EP & 0xFU].is_used = 0U; + pdev->ep_in[CDC_CMD_EP & 0xFU].bInterval = 0U; /* DeInit physical Interface components */ if (pdev->pClassData != NULL) { ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->DeInit(); - USBD_free(pdev->pClassData); + (void)USBD_free(pdev->pClassData); pdev->pClassData = NULL; } @@ -571,26 +535,26 @@ static uint8_t USBD_CDC_Setup(USBD_HandleTypeDef *pdev, USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData; uint8_t ifalt = 0U; uint16_t status_info = 0U; - uint8_t ret = USBD_OK; + USBD_StatusTypeDef ret = USBD_OK; switch (req->bmRequest & USB_REQ_TYPE_MASK) { - case USB_REQ_TYPE_CLASS : - if (req->wLength) { - if (req->bmRequest & 0x80U) { + case USB_REQ_TYPE_CLASS: + if (req->wLength != 0U) { + if ((req->bmRequest & 0x80U) != 0U) { ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest, - (uint8_t *)(void *)hcdc->data, + (uint8_t *)hcdc->data, req->wLength); - USBD_CtlSendData(pdev, (uint8_t *)(void *)hcdc->data, req->wLength); + (void)USBD_CtlSendData(pdev, (uint8_t *)hcdc->data, req->wLength); } else { hcdc->CmdOpCode = req->bRequest; hcdc->CmdLength = (uint8_t)req->wLength; - USBD_CtlPrepareRx(pdev, (uint8_t *)(void *)hcdc->data, req->wLength); + (void)USBD_CtlPrepareRx(pdev, (uint8_t *)hcdc->data, req->wLength); } } else { ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest, - (uint8_t *)(void *)req, 0U); + (uint8_t *)req, 0U); } break; @@ -598,7 +562,7 @@ static uint8_t USBD_CDC_Setup(USBD_HandleTypeDef *pdev, switch (req->bRequest) { case USB_REQ_GET_STATUS: if (pdev->dev_state == USBD_STATE_CONFIGURED) { - USBD_CtlSendData(pdev, (uint8_t *)(void *)&status_info, 2U); + (void)USBD_CtlSendData(pdev, (uint8_t *)&status_info, 2U); } else { USBD_CtlError(pdev, req); ret = USBD_FAIL; @@ -607,7 +571,7 @@ static uint8_t USBD_CDC_Setup(USBD_HandleTypeDef *pdev, case USB_REQ_GET_INTERFACE: if (pdev->dev_state == USBD_STATE_CONFIGURED) { - USBD_CtlSendData(pdev, &ifalt, 1U); + (void)USBD_CtlSendData(pdev, &ifalt, 1U); } else { USBD_CtlError(pdev, req); ret = USBD_FAIL; @@ -621,6 +585,9 @@ static uint8_t USBD_CDC_Setup(USBD_HandleTypeDef *pdev, } break; + case USB_REQ_CLEAR_FEATURE: + break; + default: USBD_CtlError(pdev, req); ret = USBD_FAIL; @@ -634,7 +601,7 @@ static uint8_t USBD_CDC_Setup(USBD_HandleTypeDef *pdev, break; } - return ret; + return (uint8_t)ret; } /** @@ -646,27 +613,26 @@ static uint8_t USBD_CDC_Setup(USBD_HandleTypeDef *pdev, */ static uint8_t USBD_CDC_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum) { - USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassData; + USBD_CDC_HandleTypeDef *hcdc; PCD_HandleTypeDef *hpcd = pdev->pData; - USBD_CDC_ItfTypeDef *ctrl = (USBD_CDC_ItfTypeDef *)pdev->pUserData; - if (pdev->pClassData != NULL) { - if ((pdev->ep_in[epnum].total_length > 0U) && ((pdev->ep_in[epnum].total_length % hpcd->IN_ep[epnum].maxpacket) == 0U)) { - /* Update the packet total length */ - pdev->ep_in[epnum].total_length = 0U; - - /* Send ZLP */ - USBD_LL_Transmit(pdev, epnum, NULL, 0U); - } else { - hcdc->TxState = 0U; - if (ctrl->Transferred) { - ctrl->Transferred(); - } - } - return USBD_OK; + if (pdev->pClassData == NULL) { + return (uint8_t)USBD_FAIL; + } + hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassData; + + if ((pdev->ep_in[epnum].total_length > 0U) && ((pdev->ep_in[epnum].total_length % hpcd->IN_ep[epnum].maxpacket) == 0U)) { + /* Update the packet total length */ + pdev->ep_in[epnum].total_length = 0U; + + /* Send ZLP */ + (void)USBD_LL_Transmit(pdev, epnum, NULL, 0U); } else { - return USBD_FAIL; + hcdc->TxState = 0U; + ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->TransmitCplt(hcdc->TxBuffer, &hcdc->TxLength, epnum); } + + return (uint8_t)USBD_OK; } /** @@ -678,20 +644,21 @@ static uint8_t USBD_CDC_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum) */ static uint8_t USBD_CDC_DataOut(USBD_HandleTypeDef *pdev, uint8_t epnum) { - USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData; + USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassData; + + if (pdev->pClassData == NULL) { + return (uint8_t)USBD_FAIL; + } /* Get the received data length */ hcdc->RxLength = USBD_LL_GetRxDataSize(pdev, epnum); /* USB data will be immediately processed, this allow next USB traffic being NAKed till the end of the application Xfer */ - if (pdev->pClassData != NULL) { - ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Receive(hcdc->RxBuffer, &hcdc->RxLength); - return USBD_OK; - } else { - return USBD_FAIL; - } + ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Receive(hcdc->RxBuffer, &hcdc->RxLength); + + return (uint8_t)USBD_OK; } /** @@ -702,16 +669,17 @@ static uint8_t USBD_CDC_DataOut(USBD_HandleTypeDef *pdev, uint8_t epnum) */ static uint8_t USBD_CDC_EP0_RxReady(USBD_HandleTypeDef *pdev) { - USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData; + USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassData; if ((pdev->pUserData != NULL) && (hcdc->CmdOpCode != 0xFFU)) { ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(hcdc->CmdOpCode, - (uint8_t *)(void *)hcdc->data, + (uint8_t *)hcdc->data, (uint16_t)hcdc->CmdLength); hcdc->CmdOpCode = 0xFFU; } - return USBD_OK; + + return (uint8_t)USBD_OK; } /** @@ -723,7 +691,8 @@ static uint8_t USBD_CDC_EP0_RxReady(USBD_HandleTypeDef *pdev) */ static uint8_t *USBD_CDC_GetFSCfgDesc(uint16_t *length) { - *length = sizeof(USBD_CDC_CfgFSDesc); + *length = (uint16_t)sizeof(USBD_CDC_CfgFSDesc); + return USBD_CDC_CfgFSDesc; } @@ -736,7 +705,8 @@ static uint8_t *USBD_CDC_GetFSCfgDesc(uint16_t *length) */ static uint8_t *USBD_CDC_GetHSCfgDesc(uint16_t *length) { - *length = sizeof(USBD_CDC_CfgHSDesc); + *length = (uint16_t)sizeof(USBD_CDC_CfgHSDesc); + return USBD_CDC_CfgHSDesc; } @@ -749,7 +719,8 @@ static uint8_t *USBD_CDC_GetHSCfgDesc(uint16_t *length) */ static uint8_t *USBD_CDC_GetOtherSpeedCfgDesc(uint16_t *length) { - *length = sizeof(USBD_CDC_OtherSpeedCfgDesc); + *length = (uint16_t)sizeof(USBD_CDC_OtherSpeedCfgDesc); + return USBD_CDC_OtherSpeedCfgDesc; } @@ -761,7 +732,8 @@ static uint8_t *USBD_CDC_GetOtherSpeedCfgDesc(uint16_t *length) */ uint8_t *USBD_CDC_GetDeviceQualifierDescriptor(uint16_t *length) { - *length = sizeof(USBD_CDC_DeviceQualifierDesc); + *length = (uint16_t)sizeof(USBD_CDC_DeviceQualifierDesc); + return USBD_CDC_DeviceQualifierDesc; } @@ -774,14 +746,13 @@ uint8_t *USBD_CDC_GetDeviceQualifierDescriptor(uint16_t *length) uint8_t USBD_CDC_RegisterInterface(USBD_HandleTypeDef *pdev, USBD_CDC_ItfTypeDef *fops) { - uint8_t ret = USBD_FAIL; - - if (fops != NULL) { - pdev->pUserData = fops; - ret = USBD_OK; + if (fops == NULL) { + return (uint8_t)USBD_FAIL; } - return ret; + pdev->pUserData = fops; + + return (uint8_t)USBD_OK; } /** @@ -791,15 +762,14 @@ uint8_t USBD_CDC_RegisterInterface(USBD_HandleTypeDef *pdev, * @retval status */ uint8_t USBD_CDC_SetTxBuffer(USBD_HandleTypeDef *pdev, - uint8_t *pbuff, - uint16_t length) + uint8_t *pbuff, uint32_t length) { - USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData; + USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassData; hcdc->TxBuffer = pbuff; hcdc->TxLength = length; - return USBD_OK; + return (uint8_t)USBD_OK; } @@ -809,14 +779,13 @@ uint8_t USBD_CDC_SetTxBuffer(USBD_HandleTypeDef *pdev, * @param pbuff: Rx Buffer * @retval status */ -uint8_t USBD_CDC_SetRxBuffer(USBD_HandleTypeDef *pdev, - uint8_t *pbuff) +uint8_t USBD_CDC_SetRxBuffer(USBD_HandleTypeDef *pdev, uint8_t *pbuff) { - USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData; + USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassData; hcdc->RxBuffer = pbuff; - return USBD_OK; + return (uint8_t)USBD_OK; } /** @@ -827,27 +796,27 @@ uint8_t USBD_CDC_SetRxBuffer(USBD_HandleTypeDef *pdev, */ uint8_t USBD_CDC_TransmitPacket(USBD_HandleTypeDef *pdev) { - USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData; + USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassData; + USBD_StatusTypeDef ret = USBD_BUSY; - if (pdev->pClassData != NULL) { - if (hcdc->TxState == 0U) { - /* Tx Transfer in progress */ - hcdc->TxState = 1U; + if (pdev->pClassData == NULL) { + return (uint8_t)USBD_FAIL; + } - /* Update the packet total length */ - pdev->ep_in[CDC_IN_EP & 0xFU].total_length = hcdc->TxLength; + if (hcdc->TxState == 0U) { + /* Tx Transfer in progress */ + hcdc->TxState = 1U; - /* Transmit next packet */ - USBD_LL_Transmit(pdev, CDC_IN_EP, hcdc->TxBuffer, - (uint16_t)hcdc->TxLength); + /* Update the packet total length */ + pdev->ep_in[CDC_IN_EP & 0xFU].total_length = hcdc->TxLength; - return USBD_OK; - } else { - return USBD_BUSY; - } - } else { - return USBD_FAIL; + /* Transmit next packet */ + (void)USBD_LL_Transmit(pdev, CDC_IN_EP, hcdc->TxBuffer, hcdc->TxLength); + + ret = USBD_OK; } + + return (uint8_t)ret; } @@ -859,27 +828,23 @@ uint8_t USBD_CDC_TransmitPacket(USBD_HandleTypeDef *pdev) */ uint8_t USBD_CDC_ReceivePacket(USBD_HandleTypeDef *pdev) { - USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData; + USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassData; - /* Suspend or Resume USB Out process */ - if (pdev->pClassData != NULL) { - if (pdev->dev_speed == USBD_SPEED_HIGH) { - /* Prepare Out endpoint to receive next packet */ - USBD_LL_PrepareReceive(pdev, - CDC_OUT_EP, - hcdc->RxBuffer, - CDC_DATA_HS_OUT_PACKET_SIZE); - } else { - /* Prepare Out endpoint to receive next packet */ - USBD_LL_PrepareReceive(pdev, - CDC_OUT_EP, - hcdc->RxBuffer, - CDC_DATA_FS_OUT_PACKET_SIZE); - } - return USBD_OK; + if (pdev->pClassData == NULL) { + return (uint8_t)USBD_FAIL; + } + + if (pdev->dev_speed == USBD_SPEED_HIGH) { + /* Prepare Out endpoint to receive next packet */ + (void)USBD_LL_PrepareReceive(pdev, CDC_OUT_EP, hcdc->RxBuffer, + CDC_DATA_HS_OUT_PACKET_SIZE); } else { - return USBD_FAIL; + /* Prepare Out endpoint to receive next packet */ + (void)USBD_LL_PrepareReceive(pdev, CDC_OUT_EP, hcdc->RxBuffer, + CDC_DATA_FS_OUT_PACKET_SIZE); } + + return (uint8_t)USBD_OK; } uint8_t USBD_CDC_ClearBuffer(USBD_HandleTypeDef *pdev) @@ -888,9 +853,9 @@ uint8_t USBD_CDC_ClearBuffer(USBD_HandleTypeDef *pdev) if (pdev->pClassData != NULL) { /* Prepare Out endpoint to receive next packet */ USBD_LL_PrepareReceive(pdev, CDC_OUT_EP, 0, 0); - return USBD_OK; + return (uint8_t)USBD_OK; } else { - return USBD_FAIL; + return (uint8_t)USBD_FAIL; } } diff --git a/cores/arduino/stm32/usb/cdc/usbd_cdc.h b/cores/arduino/stm32/usb/cdc/usbd_cdc.h index 1d9bd051e3..5395708c06 100644 --- a/cores/arduino/stm32/usb/cdc/usbd_cdc.h +++ b/cores/arduino/stm32/usb/cdc/usbd_cdc.h @@ -12,7 +12,7 @@ * This software component is licensed by ST under Ultimate Liberty license * SLA0044, the "License"; You may not use this file except in compliance with * the License. You may obtain a copy of the License at: - * http://www.st.com/SLA0044 + * www.st.com/SLA0044 * ****************************************************************************** */ @@ -95,8 +95,7 @@ typedef struct _USBD_CDC_Itf { int8_t (* DeInit)(void); int8_t (* Control)(uint8_t cmd, uint8_t *pbuf, uint16_t length); int8_t (* Receive)(uint8_t *Buf, uint32_t *Len); - int8_t (* Transferred)(void); - + int8_t (* TransmitCplt)(uint8_t *Buf, uint32_t *Len, uint8_t epnum); } USBD_CDC_ItfTypeDef; @@ -111,8 +110,7 @@ typedef struct { __IO uint32_t TxState; __IO uint32_t RxState; -} -USBD_CDC_HandleTypeDef; +} USBD_CDC_HandleTypeDef; @@ -140,17 +138,12 @@ extern USBD_ClassTypeDef USBD_CDC; uint8_t USBD_CDC_RegisterInterface(USBD_HandleTypeDef *pdev, USBD_CDC_ItfTypeDef *fops); -uint8_t USBD_CDC_SetTxBuffer(USBD_HandleTypeDef *pdev, - uint8_t *pbuff, - uint16_t length); - -uint8_t USBD_CDC_SetRxBuffer(USBD_HandleTypeDef *pdev, - uint8_t *pbuff); +uint8_t USBD_CDC_SetTxBuffer(USBD_HandleTypeDef *pdev, uint8_t *pbuff, + uint32_t length); +uint8_t USBD_CDC_SetRxBuffer(USBD_HandleTypeDef *pdev, uint8_t *pbuff); uint8_t USBD_CDC_ReceivePacket(USBD_HandleTypeDef *pdev); - uint8_t USBD_CDC_ClearBuffer(USBD_HandleTypeDef *pdev); - uint8_t USBD_CDC_TransmitPacket(USBD_HandleTypeDef *pdev); /** * @} diff --git a/cores/arduino/stm32/usb/cdc/usbd_cdc_if.c b/cores/arduino/stm32/usb/cdc/usbd_cdc_if.c index dcae9cb0cd..c09675f95e 100644 --- a/cores/arduino/stm32/usb/cdc/usbd_cdc_if.c +++ b/cores/arduino/stm32/usb/cdc/usbd_cdc_if.c @@ -12,7 +12,7 @@ * This software component is licensed by ST under Ultimate Liberty license * SLA0044, the "License"; You may not use this file except in compliance with * the License. You may obtain a copy of the License at: - * http://www.st.com/SLA0044 + * www.st.com/SLA0044 * ****************************************************************************** */ @@ -67,14 +67,14 @@ static int8_t USBD_CDC_Init(void); static int8_t USBD_CDC_DeInit(void); static int8_t USBD_CDC_Control(uint8_t cmd, uint8_t *pbuf, uint16_t length); static int8_t USBD_CDC_Receive(uint8_t *pbuf, uint32_t *Len); -static int8_t USBD_CDC_Transferred(void); +static int8_t USBD_CDC_TransmitCplt(uint8_t *pbuf, uint32_t *Len, uint8_t epnum); USBD_CDC_ItfTypeDef USBD_CDC_fops = { USBD_CDC_Init, USBD_CDC_DeInit, USBD_CDC_Control, USBD_CDC_Receive, - USBD_CDC_Transferred + USBD_CDC_TransmitCplt }; USBD_CDC_LineCodingTypeDef linecoding = { @@ -100,7 +100,7 @@ static int8_t USBD_CDC_Init(void) receivePended = true; USBD_CDC_SetRxBuffer(&hUSBD_Device_CDC, CDC_ReceiveQueue_ReserveBlock(&ReceiveQueue)); - return (USBD_OK); + return ((int8_t)USBD_OK); } /** @@ -111,7 +111,7 @@ static int8_t USBD_CDC_Init(void) */ static int8_t USBD_CDC_DeInit(void) { - return (USBD_OK); + return ((int8_t)USBD_OK); } @@ -201,7 +201,7 @@ static int8_t USBD_CDC_Control(uint8_t cmd, uint8_t *pbuf, uint16_t length) break; } - return (USBD_OK); + return ((int8_t)USBD_OK); } /** @@ -211,7 +211,7 @@ static int8_t USBD_CDC_Control(uint8_t cmd, uint8_t *pbuf, uint16_t length) * * @note * This function will issue a NAK packet on any OUT packet received on - * USB endpoint untill exiting this function. If you exit this function + * USB endpoint until exiting this function. If you exit this function * before transfer is complete on CDC interface (ie. using DMA controller) * it will result in receiving more data while previous ones are still * not sent. @@ -237,16 +237,31 @@ static int8_t USBD_CDC_Receive(uint8_t *Buf, uint32_t *Len) if (!CDC_resume_receive()) { USBD_CDC_ClearBuffer(&hUSBD_Device_CDC); } - return USBD_OK; + return ((int8_t)USBD_OK); } -static int8_t USBD_CDC_Transferred(void) +/** + * @brief USBD_CDC_TransmitCplt + * Data transmited callback + * + * @note + * This function is IN transfer complete callback used to inform user that + * the submitted Data is successfully sent over USB. + * + * @param Buf: Buffer of data to be received + * @param Len: Number of data received (in bytes) + * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL + */ +static int8_t USBD_CDC_TransmitCplt(uint8_t *Buf, uint32_t *Len, uint8_t epnum) { + UNUSED(Buf); + UNUSED(Len); + UNUSED(epnum); transmitStart = 0; CDC_TransmitQueue_CommitRead(&TransmitQueue); CDC_continue_transmit(); - return (USBD_OK); + return ((int8_t)USBD_OK); } void CDC_init(void) @@ -284,9 +299,9 @@ bool CDC_connected() if (transmitTime) { transmitTime = HAL_GetTick() - transmitTime; } - return hUSBD_Device_CDC.dev_state == USBD_STATE_CONFIGURED - && transmitTime < USB_CDC_TRANSMIT_TIMEOUT - && lineState; + return ((hUSBD_Device_CDC.dev_state == USBD_STATE_CONFIGURED) + && (transmitTime < USB_CDC_TRANSMIT_TIMEOUT) + && lineState); } void CDC_continue_transmit(void) @@ -296,7 +311,7 @@ void CDC_continue_transmit(void) USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *) hUSBD_Device_CDC.pClassData; /* * TS: This method can be called both in the main thread - * (via USBSerial::write) and in the IRQ stream (via USBD_CDC_Transferred), + * (via USBSerial::write) and in the IRQ stream (via USBD_CDC_TransmistCplt), * BUT the main thread cannot pass this condition while waiting for a IRQ! * This is not possible because TxState is not zero while waiting for data * transfer ending! The IRQ thread is uninterrupted, since its priority diff --git a/cores/arduino/stm32/usb/cdc/usbd_cdc_if.h b/cores/arduino/stm32/usb/cdc/usbd_cdc_if.h index 4baa116e36..b415ac16de 100644 --- a/cores/arduino/stm32/usb/cdc/usbd_cdc_if.h +++ b/cores/arduino/stm32/usb/cdc/usbd_cdc_if.h @@ -12,7 +12,7 @@ * This software component is licensed by ST under Ultimate Liberty license * SLA0044, the "License"; You may not use this file except in compliance with * the License. You may obtain a copy of the License at: - * http://www.st.com/SLA0044 + * www.st.com/SLA0044 * ****************************************************************************** */ diff --git a/cores/arduino/stm32/usb/hid/usbd_hid_composite.c b/cores/arduino/stm32/usb/hid/usbd_hid_composite.c index fb12d1165b..c7aafed319 100644 --- a/cores/arduino/stm32/usb/hid/usbd_hid_composite.c +++ b/cores/arduino/stm32/usb/hid/usbd_hid_composite.c @@ -33,7 +33,7 @@ * This software component is licensed by ST under Ultimate Liberty license * SLA0044, the "License"; You may not use this file except in compliance with * the License. You may obtain a copy of the License at: - * http://www.st.com/SLA0044 + * www.st.com/SLA0044 * ****************************************************************************** */ @@ -79,37 +79,22 @@ * @} */ - - - /** @defgroup USBD_HID_Private_FunctionPrototypes * @{ */ -static uint8_t USBD_HID_Init(USBD_HandleTypeDef *pdev, - uint8_t cfgidx); - -static uint8_t USBD_HID_DeInit(USBD_HandleTypeDef *pdev, - uint8_t cfgidx); - -static uint8_t USBD_COMPOSITE_HID_Setup(USBD_HandleTypeDef *pdev, - USBD_SetupReqTypedef *req); - -static uint8_t USBD_HID_MOUSE_Setup(USBD_HandleTypeDef *pdev, - USBD_SetupReqTypedef *req); - -static uint8_t USBD_HID_KEYBOARD_Setup(USBD_HandleTypeDef *pdev, - USBD_SetupReqTypedef *req); - -static uint8_t *USBD_HID_GetFSCfgDesc(uint16_t *length); +static uint8_t USBD_HID_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx); +static uint8_t USBD_HID_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx); +static uint8_t USBD_COMPOSITE_HID_Setup(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); +static uint8_t USBD_HID_MOUSE_Setup(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); +static uint8_t USBD_HID_KEYBOARD_Setup(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); -static uint8_t *USBD_HID_GetHSCfgDesc(uint16_t *length); +static uint8_t *USBD_HID_GetFSCfgDesc(uint16_t *length); +static uint8_t *USBD_HID_GetHSCfgDesc(uint16_t *length); +static uint8_t *USBD_HID_GetOtherSpeedCfgDesc(uint16_t *length); +static uint8_t *USBD_HID_GetDeviceQualifierDesc(uint16_t *length); +static uint8_t USBD_HID_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum); -static uint8_t *USBD_HID_GetOtherSpeedCfgDesc(uint16_t *length); - -static uint8_t *USBD_HID_GetDeviceQualifierDesc(uint16_t *length); - -static uint8_t USBD_HID_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum); /** * @} */ @@ -122,11 +107,11 @@ USBD_ClassTypeDef USBD_COMPOSITE_HID = { USBD_HID_Init, USBD_HID_DeInit, USBD_COMPOSITE_HID_Setup, - NULL, /*EP0_TxSent*/ - NULL, /*EP0_RxReady*/ - USBD_HID_DataIn, /*DataIn*/ - NULL, /*DataOut*/ - NULL, /*SOF */ + NULL, /* EP0_TxSent */ + NULL, /* EP0_RxReady */ + USBD_HID_DataIn, /* DataIn */ + NULL, /* DataOut */ + NULL, /* SOF */ NULL, NULL, USBD_HID_GetHSCfgDesc, @@ -137,276 +122,267 @@ USBD_ClassTypeDef USBD_COMPOSITE_HID = { /* USB HID device FS Configuration Descriptor */ __ALIGN_BEGIN static uint8_t USBD_HID_CfgFSDesc[USB_COMPOSITE_HID_CONFIG_DESC_SIZ] __ALIGN_END = { - 0x09, /* bLength: Configuration Descriptor size */ - USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */ - LOBYTE(USB_COMPOSITE_HID_CONFIG_DESC_SIZ), /* wTotalLength: Bytes returned */ + 0x09, /* bLength: Configuration Descriptor size */ + USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */ + LOBYTE(USB_COMPOSITE_HID_CONFIG_DESC_SIZ), /* wTotalLength: Bytes returned */ HIBYTE(USB_COMPOSITE_HID_CONFIG_DESC_SIZ), - 0x02, /*bNumInterfaces: 2 interface*/ - 0x01, /*bConfigurationValue: Configuration value*/ - 0x00, /*iConfiguration: Index of string descriptor describing - the configuration*/ - 0xC0, /*bmAttributes: bus powered and no Support Remote Wake-up */ - 0x32, /*MaxPower 100 mA: this current is used for detecting Vbus*/ - + 0x02, /* bNumInterfaces: 2 interface */ + 0x01, /* bConfigurationValue: Configuration value */ + 0x00, /* iConfiguration: Index of string descriptor describing the configuration */ + 0xC0, /* bmAttributes: bus powered and no Support Remote Wake-up */ + 0x32, /* MaxPower 100 mA: this current is used for detecting Vbus */ /************** Descriptor of Joystick Mouse interface ****************/ /* 09 */ - 0x09, /*bLength: Interface Descriptor size*/ - USB_DESC_TYPE_INTERFACE,/*bDescriptorType: Interface descriptor type*/ - HID_MOUSE_INTERFACE, /*bInterfaceNumber: Number of Interface*/ - 0x00, /*bAlternateSetting: Alternate setting*/ - 0x01, /*bNumEndpoints*/ - 0x03, /*bInterfaceClass: HID*/ - 0x01, /*bInterfaceSubClass : 1=BOOT, 0=no boot*/ - 0x02, /*nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse*/ - 0x00, /*iInterface: Index of string descriptor*/ + 0x09, /* bLength: Interface Descriptor size */ + USB_DESC_TYPE_INTERFACE, /* bDescriptorType: Interface descriptor type */ + HID_MOUSE_INTERFACE, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x01, /* bNumEndpoints */ + 0x03, /* bInterfaceClass: HID */ + 0x01, /* bInterfaceSubClass : 1=BOOT, 0=no boot */ + 0x02, /* nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse */ + 0x00, /* iInterface: Index of string descriptor */ /******************** Descriptor of Joystick Mouse HID ********************/ /* 18 */ - 0x09, /*bLength: HID Descriptor size*/ - HID_DESCRIPTOR_TYPE, /*bDescriptorType: HID*/ - 0x11, /*bcdHID: HID Class Spec release number*/ + 0x09, /* bLength: HID Descriptor size */ + HID_DESCRIPTOR_TYPE, /* bDescriptorType: HID */ + 0x11, /* bcdHID: HID Class Spec release number */ 0x01, - 0x00, /*bCountryCode: Hardware target country*/ - 0x01, /*bNumDescriptors: Number of HID class descriptors to follow*/ - 0x22, /*bDescriptorType*/ - HID_MOUSE_REPORT_DESC_SIZE,/*wItemLength: Total length of Report descriptor*/ + 0x00, /* bCountryCode: Hardware target country */ + 0x01, /* bNumDescriptors: Number of HID class descriptors to follow */ + 0x22, /* bDescriptorType */ + HID_MOUSE_REPORT_DESC_SIZE, /* wItemLength: Total length of Report descriptor */ 0x00, /******************** Descriptor of Mouse endpoint ********************/ /* 27 */ - 0x07, /*bLength: Endpoint Descriptor size*/ - USB_DESC_TYPE_ENDPOINT, /*bDescriptorType:*/ - - HID_MOUSE_EPIN_ADDR, /*bEndpointAddress: Endpoint Address (IN)*/ - 0x03, /*bmAttributes: Interrupt endpoint*/ - HID_MOUSE_EPIN_SIZE, /*wMaxPacketSize: 4 Byte max */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: */ + HID_MOUSE_EPIN_ADDR, /* bEndpointAddress: Endpoint Address (IN) */ + 0x03, /* bmAttributes: Interrupt endpoint*/ + HID_MOUSE_EPIN_SIZE, /* wMaxPacketSize: 4 Byte max */ 0x00, - HID_FS_BINTERVAL, /*bInterval: Polling Interval*/ - + HID_FS_BINTERVAL, /* bInterval: Polling Interval*/ /******************************************************************** Keyboard *********************************************************************/ /************** Descriptor of HID Keyboard interface ****************/ /* 34 */ - 0x09, /*bLength: Interface Descriptor size*/ - USB_DESC_TYPE_INTERFACE,/*bDescriptorType: Interface descriptor type*/ - HID_KEYBOARD_INTERFACE, /*bInterfaceNumber: Number of Interface*/ - 0x00, /*bAlternateSetting: Alternate setting*/ - 0x01, /*bNumEndpoints*/ - 0x03, /*bInterfaceClass: HID*/ - 0x01, /*bInterfaceSubClass : 1=BOOT, 0=no boot*/ - 0x01, /*nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse*/ - 0x00, /*iInterface: Index of string descriptor*/ + 0x09, /* bLength: Interface Descriptor size */ + USB_DESC_TYPE_INTERFACE, /* bDescriptorType: Interface descriptor type */ + HID_KEYBOARD_INTERFACE, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x01, /* bNumEndpoints */ + 0x03, /* bInterfaceClass: HID */ + 0x01, /* bInterfaceSubClass : 1=BOOT, 0=no boot */ + 0x01, /* nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse */ + 0x00, /* iInterface: Index of string descriptor */ /******************** HID Descriptor ********************/ /* 43 */ - 0x09, /*bLength: HID Descriptor size*/ - HID_DESCRIPTOR_TYPE, /*bDescriptorType: HID*/ - 0x11, /*bcdHID: HID Class Spec release number*/ + 0x09, /* bLength: HID Descriptor size */ + HID_DESCRIPTOR_TYPE, /* bDescriptorType: HID */ + 0x11, /* bcdHID: HID Class Spec release number */ 0x01, - 0x00, /*bCountryCode: Hardware target country*/ - 0x01, /*bNumDescriptors: Number of HID class descriptors to follow*/ - 0x22, /*bDescriptorType*/ - HID_KEYBOARD_REPORT_DESC_SIZE,/*wItemLength: Total length of Report descriptor*/ + 0x00, /* bCountryCode: Hardware target country */ + 0x01, /* bNumDescriptors: Number of HID class descriptors to follow */ + 0x22, /* bDescriptorType */ + HID_KEYBOARD_REPORT_DESC_SIZE, /* wItemLength: Total length of Report descriptor */ 0x00, /******************** Descriptor of Keyboard endpoint ********************/ /* 52 */ - 0x07, /*bLength: Endpoint Descriptor size*/ - USB_DESC_TYPE_ENDPOINT, /*bDescriptorType:*/ - HID_KEYBOARD_EPIN_ADDR, /*bEndpointAddress: Endpoint Address (IN)*/ - 0x03, /*bmAttributes: Interrupt endpoint*/ - HID_KEYBOARD_EPIN_SIZE, /*wMaxPacketSize: 8 Byte max */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: */ + HID_KEYBOARD_EPIN_ADDR, /* bEndpointAddress: Endpoint Address (IN) */ + 0x03, /* bmAttributes: Interrupt endpoint */ + HID_KEYBOARD_EPIN_SIZE, /* wMaxPacketSize: 8 Byte max */ 0x00, - HID_FS_BINTERVAL /*bInterval: Polling Interval*/ + HID_FS_BINTERVAL /* bInterval: Polling Interval */ /* 59 */ } ; /* USB HID device HS Configuration Descriptor */ __ALIGN_BEGIN static uint8_t USBD_HID_CfgHSDesc[USB_COMPOSITE_HID_CONFIG_DESC_SIZ] __ALIGN_END = { - 0x09, /* bLength: Configuration Descriptor size */ - USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */ - LOBYTE(USB_COMPOSITE_HID_CONFIG_DESC_SIZ), /* wTotalLength: Bytes returned */ + 0x09, /* bLength: Configuration Descriptor size */ + USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */ + LOBYTE(USB_COMPOSITE_HID_CONFIG_DESC_SIZ), /* wTotalLength: Bytes returned */ HIBYTE(USB_COMPOSITE_HID_CONFIG_DESC_SIZ), - 0x02, /*bNumInterfaces: 2 interface*/ - 0x01, /*bConfigurationValue: Configuration value*/ - 0x00, /*iConfiguration: Index of string descriptor describing - the configuration*/ - 0xC0, /*bmAttributes: bus powered and no Support Remote Wake-up */ - 0x32, /*MaxPower 100 mA: this current is used for detecting Vbus*/ - + 0x02, /* bNumInterfaces: 2 interface */ + 0x01, /* bConfigurationValue: Configuration value */ + 0x00, /* iConfiguration: Index of string descriptor describing the configuration */ + 0xC0, /* bmAttributes: bus powered and no Support Remote Wake-up */ + 0x32, /* MaxPower 100 mA: this current is used for detecting Vbus */ /************** Descriptor of Joystick Mouse interface ****************/ /* 09 */ - 0x09, /*bLength: Interface Descriptor size*/ - USB_DESC_TYPE_INTERFACE,/*bDescriptorType: Interface descriptor type*/ - HID_MOUSE_INTERFACE, /*bInterfaceNumber: Number of Interface*/ - 0x00, /*bAlternateSetting: Alternate setting*/ - 0x01, /*bNumEndpoints*/ - 0x03, /*bInterfaceClass: HID*/ - 0x01, /*bInterfaceSubClass : 1=BOOT, 0=no boot*/ - 0x02, /*nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse*/ - 0, /*iInterface: Index of string descriptor*/ + 0x09, /* bLength: Interface Descriptor size */ + USB_DESC_TYPE_INTERFACE, /* bDescriptorType: Interface descriptor type */ + HID_MOUSE_INTERFACE, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x01, /* bNumEndpoints */ + 0x03, /* bInterfaceClass: HID */ + 0x01, /* bInterfaceSubClass : 1=BOOT, 0=no boot */ + 0x02, /* nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse */ + 0, /* iInterface: Index of string descriptor */ /******************** Descriptor of Joystick Mouse HID ********************/ /* 18 */ - 0x09, /*bLength: HID Descriptor size*/ - HID_DESCRIPTOR_TYPE, /*bDescriptorType: HID*/ - 0x11, /*bcdHID: HID Class Spec release number*/ + 0x09, /* bLength: HID Descriptor size */ + HID_DESCRIPTOR_TYPE, /* bDescriptorType: HID */ + 0x11, /* bcdHID: HID Class Spec release number */ 0x01, - 0x00, /*bCountryCode: Hardware target country*/ - 0x01, /*bNumDescriptors: Number of HID class descriptors to follow*/ - 0x22, /*bDescriptorType*/ - HID_MOUSE_REPORT_DESC_SIZE,/*wItemLength: Total length of Report descriptor*/ + 0x00, /* bCountryCode: Hardware target country */ + 0x01, /* bNumDescriptors: Number of HID class descriptors to follow */ + 0x22, /* bDescriptorType */ + HID_MOUSE_REPORT_DESC_SIZE, /* wItemLength: Total length of Report descriptor */ 0x00, /******************** Descriptor of Mouse endpoint ********************/ /* 27 */ - 0x07, /*bLength: Endpoint Descriptor size*/ - USB_DESC_TYPE_ENDPOINT, /*bDescriptorType:*/ - - HID_MOUSE_EPIN_ADDR, /*bEndpointAddress: Endpoint Address (IN)*/ - 0x03, /*bmAttributes: Interrupt endpoint*/ - HID_MOUSE_EPIN_SIZE, /*wMaxPacketSize: 4 Byte max */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: */ + HID_MOUSE_EPIN_ADDR, /* bEndpointAddress: Endpoint Address (IN) */ + 0x03, /* bmAttributes: Interrupt endpoint */ + HID_MOUSE_EPIN_SIZE, /* wMaxPacketSize: 4 Byte max */ 0x00, - HID_HS_BINTERVAL, /*bInterval: Polling Interval*/ - + HID_HS_BINTERVAL, /* bInterval: Polling Interval*/ /******************************************************************** Keyboard *********************************************************************/ /************** Descriptor of HID Keyboard interface ****************/ /* 34 */ - 0x09, /*bLength: Interface Descriptor size*/ - USB_DESC_TYPE_INTERFACE,/*bDescriptorType: Interface descriptor type*/ - HID_KEYBOARD_INTERFACE, /*bInterfaceNumber: Number of Interface*/ - 0x00, /*bAlternateSetting: Alternate setting*/ - 0x01, /*bNumEndpoints*/ - 0x03, /*bInterfaceClass: HID*/ - 0x01, /*bInterfaceSubClass : 1=BOOT, 0=no boot*/ - 0x01, /*nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse*/ - 0x00, /*iInterface: Index of string descriptor*/ + 0x09, /* bLength: Interface Descriptor size */ + USB_DESC_TYPE_INTERFACE, /* bDescriptorType: Interface descriptor type */ + HID_KEYBOARD_INTERFACE, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x01, /* bNumEndpoints */ + 0x03, /* bInterfaceClass: HID */ + 0x01, /* bInterfaceSubClass : 1=BOOT, 0=no boot */ + 0x01, /* nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse */ + 0x00, /* iInterface: Index of string descriptor */ /******************** HID Descriptor ********************/ /* 43 */ - 0x09, /*bLength: HID Descriptor size*/ - HID_DESCRIPTOR_TYPE, /*bDescriptorType: HID*/ - 0x11, /*bcdHID: HID Class Spec release number*/ + 0x09, /* bLength: HID Descriptor size */ + HID_DESCRIPTOR_TYPE, /* bDescriptorType: HID */ + 0x11, /* bcdHID: HID Class Spec release number */ 0x01, - 0x00, /*bCountryCode: Hardware target country*/ - 0x01, /*bNumDescriptors: Number of HID class descriptors to follow*/ - 0x22, /*bDescriptorType*/ - HID_KEYBOARD_REPORT_DESC_SIZE,/*wItemLength: Total length of Report descriptor*/ + 0x00, /* bCountryCode: Hardware target country */ + 0x01, /* bNumDescriptors: Number of HID class descriptors to follow */ + 0x22, /* bDescriptorType */ + HID_KEYBOARD_REPORT_DESC_SIZE, /* wItemLength: Total length of Report descriptor */ 0x00, /******************** Descriptor of Keyboard endpoint ********************/ /* 52 */ - 0x07, /*bLength: Endpoint Descriptor size*/ - USB_DESC_TYPE_ENDPOINT, /*bDescriptorType:*/ - HID_KEYBOARD_EPIN_ADDR, /*bEndpointAddress: Endpoint Address (IN)*/ - 0x03, /*bmAttributes: Interrupt endpoint*/ - HID_KEYBOARD_EPIN_SIZE, /*wMaxPacketSize: 8 Byte max */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: */ + HID_KEYBOARD_EPIN_ADDR, /* bEndpointAddress: Endpoint Address (IN) */ + 0x03, /* bmAttributes: Interrupt endpoint */ + HID_KEYBOARD_EPIN_SIZE, /* wMaxPacketSize: 8 Byte max */ 0x00, - HID_HS_BINTERVAL /*bInterval: Polling Interval*/ + HID_HS_BINTERVAL /* bInterval: Polling Interval */ /* 59 */ } ; /* USB HID device Other Speed Configuration Descriptor */ __ALIGN_BEGIN static uint8_t USBD_HID_OtherSpeedCfgDesc[USB_COMPOSITE_HID_CONFIG_DESC_SIZ] __ALIGN_END = { - 0x09, /* bLength: Configuration Descriptor size */ - USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */ - LOBYTE(USB_COMPOSITE_HID_CONFIG_DESC_SIZ), /* wTotalLength: Bytes returned */ + 0x09, /* bLength: Configuration Descriptor size */ + USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */ + LOBYTE(USB_COMPOSITE_HID_CONFIG_DESC_SIZ), /* wTotalLength: Bytes returned */ HIBYTE(USB_COMPOSITE_HID_CONFIG_DESC_SIZ), - 0x02, /*bNumInterfaces: 2 interface*/ - 0x01, /*bConfigurationValue: Configuration value*/ - 0x00, /*iConfiguration: Index of string descriptor describing - the configuration*/ - 0xC0, /*bmAttributes: bus powered and no Support Remote Wake-up */ - 0x32, /*MaxPower 100 mA: this current is used for detecting Vbus*/ + 0x02, /* bNumInterfaces: 2 interface */ + 0x01, /* bConfigurationValue: Configuration value */ + 0x00, /* iConfiguration: Index of string descriptor describing the configuration */ + 0xC0, /* bmAttributes: bus powered and no Support Remote Wake-up */ + 0x32, /* MaxPower 100 mA: this current is used for detecting Vbus */ /************** Descriptor of Joystick Mouse interface ****************/ /* 09 */ - 0x09, /*bLength: Interface Descriptor size*/ - USB_DESC_TYPE_INTERFACE,/*bDescriptorType: Interface descriptor type*/ - HID_MOUSE_INTERFACE, /*bInterfaceNumber: Number of Interface*/ - 0x00, /*bAlternateSetting: Alternate setting*/ - 0x01, /*bNumEndpoints*/ - 0x03, /*bInterfaceClass: HID*/ - 0x01, /*bInterfaceSubClass : 1=BOOT, 0=no boot*/ - 0x02, /*nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse*/ - 0, /*iInterface: Index of string descriptor*/ + 0x09, /* bLength: Interface Descriptor size */ + USB_DESC_TYPE_INTERFACE, /* bDescriptorType: Interface descriptor type */ + HID_MOUSE_INTERFACE, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x01, /* bNumEndpoints */ + 0x03, /* bInterfaceClass: HID */ + 0x01, /* bInterfaceSubClass : 1=BOOT, 0=no boot */ + 0x02, /* nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse */ + 0, /* iInterface: Index of string descriptor */ /******************** Descriptor of Joystick Mouse HID ********************/ /* 18 */ - 0x09, /*bLength: HID Descriptor size*/ - HID_DESCRIPTOR_TYPE, /*bDescriptorType: HID*/ - 0x11, /*bcdHID: HID Class Spec release number*/ + 0x09, /* bLength: HID Descriptor size */ + HID_DESCRIPTOR_TYPE, /* bDescriptorType: HID */ + 0x11, /* bcdHID: HID Class Spec release number */ 0x01, - 0x00, /*bCountryCode: Hardware target country*/ - 0x01, /*bNumDescriptors: Number of HID class descriptors to follow*/ - 0x22, /*bDescriptorType*/ - HID_MOUSE_REPORT_DESC_SIZE,/*wItemLength: Total length of Report descriptor*/ + 0x00, /* bCountryCode: Hardware target country */ + 0x01, /* bNumDescriptors: Number of HID class descriptors to follow */ + 0x22, /* bDescriptorType */ + HID_MOUSE_REPORT_DESC_SIZE, /* wItemLength: Total length of Report descriptor */ 0x00, /******************** Descriptor of Mouse endpoint ********************/ /* 27 */ - 0x07, /*bLength: Endpoint Descriptor size*/ - USB_DESC_TYPE_ENDPOINT, /*bDescriptorType:*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: */ - HID_MOUSE_EPIN_ADDR, /*bEndpointAddress: Endpoint Address (IN)*/ - 0x03, /*bmAttributes: Interrupt endpoint*/ - HID_MOUSE_EPIN_SIZE, /*wMaxPacketSize: 4 Byte max */ + HID_MOUSE_EPIN_ADDR, /* bEndpointAddress: Endpoint Address (IN) */ + 0x03, /* bmAttributes: Interrupt endpoint */ + HID_MOUSE_EPIN_SIZE, /* wMaxPacketSize: 4 Byte max */ 0x00, - HID_FS_BINTERVAL, /*bInterval: Polling Interval*/ + HID_FS_BINTERVAL, /* bInterval: Polling Interval */ /******************************************************************** Keyboard *********************************************************************/ /************** Descriptor of HID Keyboard interface ****************/ /* 34 */ - 0x09, /*bLength: Interface Descriptor size*/ - USB_DESC_TYPE_INTERFACE,/*bDescriptorType: Interface descriptor type*/ - HID_KEYBOARD_INTERFACE, /*bInterfaceNumber: Number of Interface*/ - 0x00, /*bAlternateSetting: Alternate setting*/ - 0x01, /*bNumEndpoints*/ - 0x03, /*bInterfaceClass: HID*/ - 0x01, /*bInterfaceSubClass : 1=BOOT, 0=no boot*/ - 0x01, /*nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse*/ - 0x00, /*iInterface: Index of string descriptor*/ + 0x09, /* bLength: Interface Descriptor size */ + USB_DESC_TYPE_INTERFACE, /* bDescriptorType: Interface descriptor type */ + HID_KEYBOARD_INTERFACE, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x01, /* bNumEndpoints */ + 0x03, /* bInterfaceClass: HID */ + 0x01, /* bInterfaceSubClass : 1=BOOT, 0=no boot */ + 0x01, /* nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse */ + 0x00, /* iInterface: Index of string descriptor */ /******************** HID Descriptor ********************/ /* 43 */ - 0x09, /*bLength: HID Descriptor size*/ - HID_DESCRIPTOR_TYPE, /*bDescriptorType: HID*/ - 0x11, /*bcdHID: HID Class Spec release number*/ + 0x09, /* bLength: HID Descriptor size */ + HID_DESCRIPTOR_TYPE, /* bDescriptorType: HID */ + 0x11, /* bcdHID: HID Class Spec release number */ 0x01, - 0x00, /*bCountryCode: Hardware target country*/ - 0x01, /*bNumDescriptors: Number of HID class descriptors to follow*/ - 0x22, /*bDescriptorType*/ - HID_KEYBOARD_REPORT_DESC_SIZE,/*wItemLength: Total length of Report descriptor*/ + 0x00, /* bCountryCode: Hardware target country */ + 0x01, /* bNumDescriptors: Number of HID class descriptors to follow */ + 0x22, /* bDescriptorType */ + HID_KEYBOARD_REPORT_DESC_SIZE, /* wItemLength: Total length of Report descriptor */ 0x00, /******************** Descriptor of Keyboard endpoint ********************/ /* 52 */ - 0x07, /*bLength: Endpoint Descriptor size*/ - USB_DESC_TYPE_ENDPOINT, /*bDescriptorType:*/ - HID_KEYBOARD_EPIN_ADDR, /*bEndpointAddress: Endpoint Address (IN)*/ - 0x03, /*bmAttributes: Interrupt endpoint*/ - HID_KEYBOARD_EPIN_SIZE, /*wMaxPacketSize: 8 Byte max */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: */ + HID_KEYBOARD_EPIN_ADDR, /* bEndpointAddress: Endpoint Address (IN) */ + 0x03, /* bmAttributes: Interrupt endpoint */ + HID_KEYBOARD_EPIN_SIZE, /* wMaxPacketSize: 8 Byte max */ 0x00, - HID_FS_BINTERVAL /*bInterval: Polling Interval*/ + HID_FS_BINTERVAL /* bInterval: Polling Interval */ /* 59 */ } ; /* USB HID device Configuration Descriptor */ __ALIGN_BEGIN static uint8_t USBD_MOUSE_HID_Desc[USB_HID_DESC_SIZ] __ALIGN_END = { - 0x09, /*bLength: HID Descriptor size*/ - HID_DESCRIPTOR_TYPE, /*bDescriptorType: HID*/ - 0x11, /*bcdHID: HID Class Spec release number*/ + 0x09, /* bLength: HID Descriptor size */ + HID_DESCRIPTOR_TYPE, /* bDescriptorType: HID */ + 0x11, /* bcdHID: HID Class Spec release number */ 0x01, - 0x00, /*bCountryCode: Hardware target country*/ - 0x01, /*bNumDescriptors: Number of HID class descriptors to follow*/ - 0x22, /*bDescriptorType*/ - HID_MOUSE_REPORT_DESC_SIZE,/*wItemLength: Total length of Report descriptor*/ + 0x00, /* bCountryCode: Hardware target country */ + 0x01, /* bNumDescriptors: Number of HID class descriptors to follow */ + 0x22, /* bDescriptorType */ + HID_MOUSE_REPORT_DESC_SIZE, /* wItemLength: Total length of Report descriptor */ 0x00 }; /* USB HID device Configuration Descriptor */ __ALIGN_BEGIN static uint8_t USBD_KEYBOARD_HID_Desc[USB_HID_DESC_SIZ] __ALIGN_END = { - 0x09, /*bLength: HID Descriptor size*/ - HID_DESCRIPTOR_TYPE, /*bDescriptorType: HID*/ - 0x11, /*bcdHID: HID Class Spec release number*/ + 0x09, /* bLength: HID Descriptor size */ + HID_DESCRIPTOR_TYPE, /* bDescriptorType: HID */ + 0x11, /* bcdHID: HID Class Spec release number */ 0x01, - 0x00, /*bCountryCode: Hardware target country*/ - 0x01, /*bNumDescriptors: Number of HID class descriptors to follow*/ - 0x22, /*bDescriptorType*/ - HID_KEYBOARD_REPORT_DESC_SIZE,/*wItemLength: Total length of Report descriptor*/ + 0x00, /* bCountryCode: Hardware target country */ + 0x01, /* bNumDescriptors: Number of HID class descriptors to follow */ + 0x22, /* bDescriptorType */ + HID_KEYBOARD_REPORT_DESC_SIZE, /* wItemLength: Total length of Report descriptor */ 0x00, }; @@ -522,31 +498,39 @@ static uint8_t USBD_HID_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { UNUSED(cfgidx); - uint8_t ret = USBD_OK; + USBD_HID_HandleTypeDef *hhid; + + hhid = USBD_malloc(sizeof(USBD_HID_HandleTypeDef)); + + if (hhid == NULL) { + pdev->pClassData = NULL; + return (uint8_t)USBD_EMEM; + } + + pdev->pClassData = (void *)hhid; + + if (pdev->dev_speed == USBD_SPEED_HIGH) { + pdev->ep_in[HID_MOUSE_EPIN_ADDR & 0xFU].bInterval = HID_HS_BINTERVAL; + pdev->ep_in[HID_KEYBOARD_EPIN_ADDR & 0xFU].bInterval = HID_HS_BINTERVAL; + } else { + /* LOW and FULL-speed endpoints */ + pdev->ep_in[HID_MOUSE_EPIN_ADDR & 0xFU].bInterval = HID_FS_BINTERVAL; + pdev->ep_in[HID_KEYBOARD_EPIN_ADDR & 0xFU].bInterval = HID_FS_BINTERVAL; + } /* Open EP IN */ - USBD_LL_OpenEP(pdev, - HID_MOUSE_EPIN_ADDR, - USBD_EP_TYPE_INTR, - HID_MOUSE_EPIN_SIZE); + (void)USBD_LL_OpenEP(pdev, HID_MOUSE_EPIN_ADDR, USBD_EP_TYPE_INTR, + HID_MOUSE_EPIN_SIZE); pdev->ep_in[HID_MOUSE_EPIN_ADDR & 0xFU].is_used = 1U; /* Open EP IN */ - USBD_LL_OpenEP(pdev, - HID_KEYBOARD_EPIN_ADDR, - USBD_EP_TYPE_INTR, - HID_KEYBOARD_EPIN_SIZE); + (void)USBD_LL_OpenEP(pdev, HID_KEYBOARD_EPIN_ADDR, USBD_EP_TYPE_INTR, + HID_KEYBOARD_EPIN_SIZE); pdev->ep_in[HID_KEYBOARD_EPIN_ADDR & 0xFU].is_used = 1U; + hhid->Mousestate = HID_IDLE; + hhid->Keyboardstate = HID_IDLE; - pdev->pClassData = USBD_malloc(sizeof(USBD_HID_HandleTypeDef)); - - if (pdev->pClassData == NULL) { - ret = USBD_FAIL; - } else { - ((USBD_HID_HandleTypeDef *)pdev->pClassData)->Mousestate = HID_IDLE; - ((USBD_HID_HandleTypeDef *)pdev->pClassData)->Keyboardstate = HID_IDLE; - } - return ret; + return (uint8_t)USBD_OK; } /** @@ -561,11 +545,9 @@ static uint8_t USBD_HID_DeInit(USBD_HandleTypeDef *pdev, { UNUSED(cfgidx); /* Close HID EPs */ - USBD_LL_CloseEP(pdev, - HID_MOUSE_EPIN_ADDR); + (void)USBD_LL_CloseEP(pdev, HID_MOUSE_EPIN_ADDR); pdev->ep_in[HID_MOUSE_EPIN_ADDR & 0xFU].is_used = 0U; - USBD_LL_CloseEP(pdev, - HID_KEYBOARD_EPIN_ADDR); + USBD_LL_CloseEP(pdev, HID_KEYBOARD_EPIN_ADDR); pdev->ep_in[HID_KEYBOARD_EPIN_ADDR & 0xFU].is_used = 0U; /* Free allocated memory */ @@ -574,7 +556,7 @@ static uint8_t USBD_HID_DeInit(USBD_HandleTypeDef *pdev, pdev->pClassData = NULL; } - return USBD_OK; + return (uint8_t)USBD_OK; } /** @@ -605,25 +587,21 @@ static uint8_t USBD_COMPOSITE_HID_Setup(USBD_HandleTypeDef *pdev, static uint8_t USBD_HID_MOUSE_Setup(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { - USBD_HID_HandleTypeDef *hhid = (USBD_HID_HandleTypeDef *) pdev->pClassData; + USBD_HID_HandleTypeDef *hhid = (USBD_HID_HandleTypeDef *) pdev->pClassData; uint16_t len = 0U; uint8_t *pbuf = NULL; uint16_t status_info = 0U; USBD_StatusTypeDef ret = USBD_OK; switch (req->bmRequest & USB_REQ_TYPE_MASK) { - case USB_REQ_TYPE_CLASS : + case USB_REQ_TYPE_CLASS: switch (req->bRequest) { - - case HID_REQ_SET_PROTOCOL: hhid->Protocol = (uint8_t)(req->wValue); break; case HID_REQ_GET_PROTOCOL: - USBD_CtlSendData(pdev, - (uint8_t *)&hhid->Protocol, - 1U); + (void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->Protocol, 1U); break; case HID_REQ_SET_IDLE: @@ -631,9 +609,7 @@ static uint8_t USBD_HID_MOUSE_Setup(USBD_HandleTypeDef *pdev, break; case HID_REQ_GET_IDLE: - USBD_CtlSendData(pdev, - (uint8_t *)&hhid->IdleState, - 1U); + (void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->IdleState, 1U); break; default: @@ -647,39 +623,39 @@ static uint8_t USBD_HID_MOUSE_Setup(USBD_HandleTypeDef *pdev, switch (req->bRequest) { case USB_REQ_GET_STATUS: if (pdev->dev_state == USBD_STATE_CONFIGURED) { - USBD_CtlSendData(pdev, (uint8_t *)(void *)&status_info, 2U); + (void)USBD_CtlSendData(pdev, (uint8_t *)&status_info, 2U); } else { USBD_CtlError(pdev, req); ret = USBD_FAIL; } break; case USB_REQ_GET_DESCRIPTOR: - if (req->wValue >> 8 == HID_REPORT_DESC) { + if ((req->wValue >> 8) == HID_REPORT_DESC) { len = MIN(HID_MOUSE_REPORT_DESC_SIZE, req->wLength); pbuf = HID_MOUSE_ReportDesc; - } else if (req->wValue >> 8 == HID_DESCRIPTOR_TYPE) { - pbuf = USBD_MOUSE_HID_Desc; - len = MIN(USB_HID_DESC_SIZ, req->wLength); } else { - USBD_CtlError(pdev, req); - ret = USBD_FAIL; - break; + if ((req->wValue >> 8) == HID_DESCRIPTOR_TYPE) { + pbuf = USBD_MOUSE_HID_Desc; + len = MIN(USB_HID_DESC_SIZ, req->wLength); + } else { + USBD_CtlError(pdev, req); + ret = USBD_FAIL; + break; + } } - USBD_CtlSendData(pdev, - pbuf, - len); + (void)USBD_CtlSendData(pdev, pbuf, len); break; - case USB_REQ_GET_INTERFACE : + case USB_REQ_GET_INTERFACE: if (pdev->dev_state == USBD_STATE_CONFIGURED) { - USBD_CtlSendData(pdev, (uint8_t *)&hhid->AltSetting, 1U); + (void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->AltSetting, 1U); } else { USBD_CtlError(pdev, req); ret = USBD_FAIL; } break; - case USB_REQ_SET_INTERFACE : + case USB_REQ_SET_INTERFACE: if (pdev->dev_state == USBD_STATE_CONFIGURED) { hhid->AltSetting = (uint8_t)(req->wValue); } else { @@ -701,7 +677,7 @@ static uint8_t USBD_HID_MOUSE_Setup(USBD_HandleTypeDef *pdev, break; } - return ret; + return (uint8_t)ret; } /** @@ -714,14 +690,14 @@ static uint8_t USBD_HID_MOUSE_Setup(USBD_HandleTypeDef *pdev, static uint8_t USBD_HID_KEYBOARD_Setup(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { - USBD_HID_HandleTypeDef *hhid = (USBD_HID_HandleTypeDef *) pdev->pClassData; + USBD_HID_HandleTypeDef *hhid = (USBD_HID_HandleTypeDef *) pdev->pClassData; uint16_t len = 0U; uint8_t *pbuf = NULL; uint16_t status_info = 0U; USBD_StatusTypeDef ret = USBD_OK; switch (req->bmRequest & USB_REQ_TYPE_MASK) { - case USB_REQ_TYPE_CLASS : + case USB_REQ_TYPE_CLASS: switch (req->bRequest) { @@ -730,9 +706,7 @@ static uint8_t USBD_HID_KEYBOARD_Setup(USBD_HandleTypeDef *pdev, break; case HID_REQ_GET_PROTOCOL: - USBD_CtlSendData(pdev, - (uint8_t *)&hhid->Protocol, - 1U); + (void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->Protocol, 1U); break; case HID_REQ_SET_IDLE: @@ -740,9 +714,7 @@ static uint8_t USBD_HID_KEYBOARD_Setup(USBD_HandleTypeDef *pdev, break; case HID_REQ_GET_IDLE: - USBD_CtlSendData(pdev, - (uint8_t *)&hhid->IdleState, - 1U); + (void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->IdleState, 1U); break; default: @@ -756,40 +728,39 @@ static uint8_t USBD_HID_KEYBOARD_Setup(USBD_HandleTypeDef *pdev, switch (req->bRequest) { case USB_REQ_GET_STATUS: if (pdev->dev_state == USBD_STATE_CONFIGURED) { - USBD_CtlSendData(pdev, (uint8_t *)(void *)&status_info, 2U); + (void)USBD_CtlSendData(pdev, (uint8_t *)&status_info, 2U); } else { USBD_CtlError(pdev, req); ret = USBD_FAIL; } break; case USB_REQ_GET_DESCRIPTOR: - if (req->wValue >> 8 == HID_REPORT_DESC) { + if ((req->wValue >> 8) == HID_REPORT_DESC) { len = MIN(HID_KEYBOARD_REPORT_DESC_SIZE, req->wLength); pbuf = HID_KEYBOARD_ReportDesc; - } else if (req->wValue >> 8 == HID_DESCRIPTOR_TYPE) { - pbuf = USBD_KEYBOARD_HID_Desc; - len = MIN(USB_HID_DESC_SIZ, req->wLength); } else { - USBD_CtlError(pdev, req); - ret = USBD_FAIL; - break; + if ((req->wValue >> 8) == HID_DESCRIPTOR_TYPE) { + pbuf = USBD_KEYBOARD_HID_Desc; + len = MIN(USB_HID_DESC_SIZ, req->wLength); + } else { + USBD_CtlError(pdev, req); + ret = USBD_FAIL; + break; + } } - USBD_CtlSendData(pdev, - pbuf, - len); - + (void)USBD_CtlSendData(pdev, pbuf, len); break; - case USB_REQ_GET_INTERFACE : + case USB_REQ_GET_INTERFACE: if (pdev->dev_state == USBD_STATE_CONFIGURED) { - USBD_CtlSendData(pdev, (uint8_t *)&hhid->AltSetting, 1U); + (void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->AltSetting, 1U); } else { USBD_CtlError(pdev, req); ret = USBD_FAIL; } break; - case USB_REQ_SET_INTERFACE : + case USB_REQ_SET_INTERFACE: if (pdev->dev_state == USBD_STATE_CONFIGURED) { hhid->AltSetting = (uint8_t)(req->wValue); } else { @@ -811,7 +782,7 @@ static uint8_t USBD_HID_KEYBOARD_Setup(USBD_HandleTypeDef *pdev, break; } - return ret; + return (uint8_t)ret; } /** @@ -825,18 +796,23 @@ uint8_t USBD_HID_MOUSE_SendReport(USBD_HandleTypeDef *pdev, uint8_t *report, uint16_t len) { - USBD_HID_HandleTypeDef *hhid = (USBD_HID_HandleTypeDef *)pdev->pClassData; + USBD_HID_HandleTypeDef *hhid; + + if (pdev->pClassData == NULL) { + return (uint8_t)USBD_FAIL; + } + + hhid = (USBD_HID_HandleTypeDef *)pdev->pClassData; if (pdev->dev_state == USBD_STATE_CONFIGURED) { if (hhid->Mousestate == HID_IDLE) { hhid->Mousestate = HID_BUSY; - USBD_LL_Transmit(pdev, - HID_MOUSE_EPIN_ADDR, - report, - len); + (void)USBD_LL_Transmit(pdev, HID_MOUSE_EPIN_ADDR, report, len); + } else { + return (uint8_t)USBD_BUSY; } } - return USBD_OK; + return (uint8_t)USBD_OK; } /** @@ -850,18 +826,23 @@ uint8_t USBD_HID_KEYBOARD_SendReport(USBD_HandleTypeDef *pdev, uint8_t *report, uint16_t len) { - USBD_HID_HandleTypeDef *hhid = (USBD_HID_HandleTypeDef *)pdev->pClassData; + USBD_HID_HandleTypeDef *hhid; + + if (pdev->pClassData == NULL) { + return (uint8_t)USBD_FAIL; + } + + hhid = (USBD_HID_HandleTypeDef *)pdev->pClassData; if (pdev->dev_state == USBD_STATE_CONFIGURED) { if (hhid->Keyboardstate == HID_IDLE) { hhid->Keyboardstate = HID_BUSY; - USBD_LL_Transmit(pdev, - HID_KEYBOARD_EPIN_ADDR, - report, - len); + (void)USBD_LL_Transmit(pdev, HID_KEYBOARD_EPIN_ADDR, report, len); + } else { + return (uint8_t)USBD_BUSY; } } - return USBD_OK; + return (uint8_t)USBD_OK; } /** @@ -883,7 +864,7 @@ uint32_t USBD_HID_GetPollingInterval(USBD_HandleTypeDef *pdev) } else { /* LOW and FULL-speed endpoints */ /* Sets the data transfer polling interval for low and full speed transfers */ - polling_interval = HID_FS_BINTERVAL; + polling_interval = HID_FS_BINTERVAL; } return ((uint32_t)(polling_interval)); @@ -896,9 +877,9 @@ uint32_t USBD_HID_GetPollingInterval(USBD_HandleTypeDef *pdev) * @param length : pointer data length * @retval pointer to descriptor buffer */ -static uint8_t *USBD_HID_GetFSCfgDesc(uint16_t *length) +static uint8_t *USBD_HID_GetFSCfgDesc(uint16_t *length) { - *length = sizeof(USBD_HID_CfgFSDesc); + *length = (uint16_t)sizeof(USBD_HID_CfgFSDesc); return USBD_HID_CfgFSDesc; } @@ -909,9 +890,9 @@ static uint8_t *USBD_HID_GetFSCfgDesc(uint16_t *length) * @param length : pointer data length * @retval pointer to descriptor buffer */ -static uint8_t *USBD_HID_GetHSCfgDesc(uint16_t *length) +static uint8_t *USBD_HID_GetHSCfgDesc(uint16_t *length) { - *length = sizeof(USBD_HID_CfgHSDesc); + *length = (uint16_t)sizeof(USBD_HID_CfgHSDesc); return USBD_HID_CfgHSDesc; } @@ -924,7 +905,7 @@ static uint8_t *USBD_HID_GetHSCfgDesc(uint16_t *length) */ static uint8_t *USBD_HID_GetOtherSpeedCfgDesc(uint16_t *length) { - *length = sizeof(USBD_HID_OtherSpeedCfgDesc); + *length = (uint16_t)sizeof(USBD_HID_OtherSpeedCfgDesc); return USBD_HID_OtherSpeedCfgDesc; } @@ -935,8 +916,8 @@ static uint8_t *USBD_HID_GetOtherSpeedCfgDesc(uint16_t *length) * @param epnum: endpoint index * @retval status */ -static uint8_t USBD_HID_DataIn(USBD_HandleTypeDef *pdev, - uint8_t epnum) +static uint8_t USBD_HID_DataIn(USBD_HandleTypeDef *pdev, + uint8_t epnum) { /* Ensure that the FIFO is empty before a new transfer, this condition could @@ -946,7 +927,7 @@ static uint8_t USBD_HID_DataIn(USBD_HandleTypeDef *pdev, } else if (epnum == (HID_MOUSE_EPIN_ADDR & 0x7F)) { ((USBD_HID_HandleTypeDef *)pdev->pClassData)->Mousestate = HID_IDLE; } - return USBD_OK; + return (uint8_t)USBD_OK; } @@ -956,9 +937,9 @@ static uint8_t USBD_HID_DataIn(USBD_HandleTypeDef *pdev, * @param length : pointer data length * @retval pointer to descriptor buffer */ -static uint8_t *USBD_HID_GetDeviceQualifierDesc(uint16_t *length) +static uint8_t *USBD_HID_GetDeviceQualifierDesc(uint16_t *length) { - *length = sizeof(USBD_HID_DeviceQualifierDesc); + *length = (uint16_t)sizeof(USBD_HID_DeviceQualifierDesc); return USBD_HID_DeviceQualifierDesc; } #endif /* USBD_USE_HID_COMPOSITE */ diff --git a/cores/arduino/stm32/usb/hid/usbd_hid_composite.h b/cores/arduino/stm32/usb/hid/usbd_hid_composite.h index c376538469..7ff3d58657 100644 --- a/cores/arduino/stm32/usb/hid/usbd_hid_composite.h +++ b/cores/arduino/stm32/usb/hid/usbd_hid_composite.h @@ -12,7 +12,7 @@ * This software component is licensed by ST under Ultimate Liberty license * SLA0044, the "License"; You may not use this file except in compliance with * the License. You may obtain a copy of the License at: - * http://www.st.com/SLA0044 + * www.st.com/SLA0044 * ****************************************************************************** */ @@ -82,8 +82,7 @@ extern "C" { typedef enum { HID_IDLE = 0, HID_BUSY, -} -HID_StateTypeDef; +} HID_StateTypeDef; typedef struct { @@ -92,8 +91,7 @@ typedef struct { uint32_t AltSetting; HID_StateTypeDef Mousestate; HID_StateTypeDef Keyboardstate; -} -USBD_HID_HandleTypeDef; +} USBD_HID_HandleTypeDef; /** * @} */ diff --git a/cores/arduino/stm32/usb/hid/usbd_hid_composite_if.c b/cores/arduino/stm32/usb/hid/usbd_hid_composite_if.c index dc760c97e1..6b7feb3e17 100644 --- a/cores/arduino/stm32/usb/hid/usbd_hid_composite_if.c +++ b/cores/arduino/stm32/usb/hid/usbd_hid_composite_if.c @@ -6,29 +6,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2016 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 * ****************************************************************************** */ diff --git a/cores/arduino/stm32/usb/hid/usbd_hid_composite_if.h b/cores/arduino/stm32/usb/hid/usbd_hid_composite_if.h index ec4bc40cda..4f9688e716 100644 --- a/cores/arduino/stm32/usb/hid/usbd_hid_composite_if.h +++ b/cores/arduino/stm32/usb/hid/usbd_hid_composite_if.h @@ -5,29 +5,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2016 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 * ****************************************************************************** */ diff --git a/cores/arduino/stm32/usb/usbd_conf.c b/cores/arduino/stm32/usb/usbd_conf.c index 87aff1fe32..109f2f56f5 100644 --- a/cores/arduino/stm32/usb/usbd_conf.c +++ b/cores/arduino/stm32/usb/usbd_conf.c @@ -665,7 +665,7 @@ USBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_a USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, - uint16_t size) + uint32_t size) { HAL_PCD_EP_Transmit(pdev->pData, ep_addr, pbuf, size); return USBD_OK; @@ -682,7 +682,7 @@ USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev, USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, - uint16_t size) + uint32_t size) { HAL_PCD_EP_Receive(pdev->pData, ep_addr, pbuf, size); return USBD_OK; diff --git a/cores/arduino/stm32/usb/usbd_conf.h b/cores/arduino/stm32/usb/usbd_conf.h index 9ba06ecc93..c1a4808380 100644 --- a/cores/arduino/stm32/usb/usbd_conf.h +++ b/cores/arduino/stm32/usb/usbd_conf.h @@ -73,14 +73,40 @@ extern "C" { #define USBD_MAX_NUM_INTERFACES 2U #endif /* USBD_MAX_NUM_INTERFACES */ +#ifndef USBD_MAX_NUM_CONFIGURATION +#define USBD_MAX_NUM_CONFIGURATION 1U +#endif /* USBD_MAX_NUM_CONFIGURATION */ + #ifndef USBD_MAX_STR_DESC_SIZ #define USBD_MAX_STR_DESC_SIZ 0x100U #endif /* USBD_MAX_STR_DESC_SIZ */ +#ifndef USBD_SELF_POWERED +#define USBD_SELF_POWERED 1U +#endif /* USBD_SELF_POWERED */ + #ifndef USBD_DEBUG_LEVEL #define USBD_DEBUG_LEVEL 0U #endif /* USBD_DEBUG_LEVEL */ +/* ECM, RNDIS, DFU Class Config */ +#ifndef USBD_SUPPORT_USER_STRING_DESC +#define USBD_SUPPORT_USER_STRING_DESC 0U +#endif /* USBD_SUPPORT_USER_STRING_DESC */ + +/* BillBoard Class Config */ +#ifndef USBD_CLASS_USER_STRING_DESC +#define USBD_CLASS_USER_STRING_DESC 1U +#endif /* USBD_CLASS_USER_STRING_DESC */ + +#ifndef USBD_CLASS_BOS_ENABLED +#define USBD_CLASS_BOS_ENABLED 0U +#endif /* USBD_CLASS_BOS_ENABLED */ + +#ifndef USB_BB_MAX_NUM_ALT_MODE +#define USB_BB_MAX_NUM_ALT_MODE 0x2U +#endif /* USB_BB_MAX_NUM_ALT_MODE */ + /* MSC Class Config */ #ifndef MSC_MEDIA_PACKET #define MSC_MEDIA_PACKET 8192U @@ -125,6 +151,9 @@ extern "C" { #ifndef USBD_memcpy #define USBD_memcpy memcpy #endif /* USBD_memcpy */ +#ifndef USBD_Delay +#define USBD_Delay HAL_Delay +#endif /* USBD_Delay */ /* DEBUG macros */ #if (USBD_DEBUG_LEVEL > 0U) diff --git a/cores/arduino/stm32/usb/usbd_desc.c b/cores/arduino/stm32/usb/usbd_desc.c index 318d8f9320..229112ea5f 100644 --- a/cores/arduino/stm32/usb/usbd_desc.c +++ b/cores/arduino/stm32/usb/usbd_desc.c @@ -105,10 +105,12 @@ uint8_t *USBD_Class_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *leng uint8_t *USBD_Class_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length); uint8_t *USBD_Class_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length); -#ifdef USB_SUPPORT_USER_STRING_DESC - uint8_t *USBD_Class_USRStringDesc(USBD_SpeedTypeDef speed, uint8_t idx, uint16_t *length); -#endif /* USB_SUPPORT_USER_STRING_DESC */ - +#if (USBD_CLASS_USER_STRING_DESC == 1) + uint8_t *USBD_Class_UserStrDescriptor(USBD_SpeedTypeDef speed, uint8_t idx, uint16_t *length); +#endif /* USB_CLASS_USER_STRING_DESC */ +#if ((USBD_LPM_ENABLED == 1) || (USBD_CLASS_BOS_ENABLED == 1)) + uint8_t *USBD_USR_BOSDescriptor(USBD_SpeedTypeDef speed, uint16_t *length); +#endif /* Private variables ---------------------------------------------------------*/ USBD_DescriptorsTypeDef USBD_Desc = { USBD_Class_DeviceDescriptor, @@ -118,6 +120,13 @@ USBD_DescriptorsTypeDef USBD_Desc = { USBD_SerialStrDescriptor, USBD_Class_ConfigStrDescriptor, USBD_Class_InterfaceStrDescriptor, +#if (USBD_CLASS_USER_STRING_DESC == 1) + USBD_Class_UserStrDescriptor, +#endif + +#if ((USBD_LPM_ENABLED == 1) || (USBD_CLASS_BOS_ENABLED == 1)) + USBD_USR_BOSDescriptor, +#endif }; #ifdef USBD_USE_HID_COMPOSITE @@ -125,7 +134,12 @@ USBD_DescriptorsTypeDef USBD_Desc = { __ALIGN_BEGIN uint8_t USBD_Class_DeviceDesc[USB_LEN_DEV_DESC] __ALIGN_END = { 0x12, /* bLength */ USB_DESC_TYPE_DEVICE, /* bDescriptorType */ +#if ((USBD_LPM_ENABLED == 1) || (USBD_CLASS_BOS_ENABLED == 1)) + 0x01, /*bcdUSB */ /* changed to USB version 2.01 + in order to support BOS Desc */ +#else 0x00, /* bcdUSB */ +#endif 0x02, 0x00, /* bDeviceClass */ 0x00, /* bDeviceSubClass */ @@ -149,7 +163,12 @@ __ALIGN_BEGIN uint8_t USBD_Class_DeviceDesc[USB_LEN_DEV_DESC] __ALIGN_END = { __ALIGN_BEGIN uint8_t USBD_Class_DeviceDesc[USB_LEN_DEV_DESC] __ALIGN_END = { 0x12, /* bLength */ USB_DESC_TYPE_DEVICE, /* bDescriptorType */ +#if ((USBD_LPM_ENABLED == 1) || (USBD_CLASS_BOS_ENABLED == 1)) + 0x01, /*bcdUSB */ /* changed to USB version 2.01 + in order to support BOS Desc */ +#else 0x00, /* bcdUSB */ +#endif 0x02, 0x02, /* bDeviceClass */ 0x02, /* bDeviceSubClass */ @@ -168,6 +187,108 @@ __ALIGN_BEGIN uint8_t USBD_Class_DeviceDesc[USB_LEN_DEV_DESC] __ALIGN_END = { }; /* USB_DeviceDescriptor */ #endif /* USBD_USE_CDC */ +/* USB Device LPM BOS descriptor */ +#if (USBD_LPM_ENABLED == 1) +__ALIGN_BEGIN uint8_t USBD_BOSDesc[USB_SIZ_BOS_DESC] __ALIGN_END = { + 0x5, + USB_DESC_TYPE_BOS, + 0xC, + 0x0, + 0x1, /* 1 device capability */ + /* device capability */ + 0x7, + USB_DEVICE_CAPABITY_TYPE, + 0x2, + 0x6, /*LPM capability bit set */ + 0x0, + 0x0, + 0x0 +}; +#endif + +/* USB Device Billboard BOS descriptor Template */ +#if (USBD_CLASS_BOS_ENABLED == 1) +__ALIGN_BEGIN uint8_t USBD_BOSDesc[USB_SIZ_BOS_DESC] __ALIGN_END = { + 0x05, /* bLength */ + USB_DESC_TYPE_BOS, /* Device Descriptor Type */ + USB_SIZ_BOS_DESC, /* Total length of BOS descriptor and all of its sub descs */ + 0x00, + 0x04, /* The number of separate device capability descriptors in the BOS */ + + /* ----------- Device Capability Descriptor: CONTAINER_ID ---------- */ + 0x14, /* bLength */ + 0x10, /* bDescriptorType: DEVICE CAPABILITY Type */ + 0x04, /* bDevCapabilityType: CONTAINER_ID */ + 0x00, /* bReserved */ + 0xa7, 0xd6, 0x1b, 0xfa, /* ContainerID: This is a Unique 128-bit number GUID */ + 0x91, 0xa6, 0xa8, 0x4e, + 0xa8, 0x21, 0x9f, 0x2b, + 0xaf, 0xf7, 0x94, 0xd4, + + /* ----------- Device Capability Descriptor: BillBoard ---------- */ + 0x34, /* bLength */ + 0x10, /* bDescriptorType: DEVICE CAPABILITY Type */ + 0x0D, /* bDevCapabilityType: BILLBOARD_CAPABILITY */ + USBD_BB_URL_STRING_INDEX, /* iAddtionalInfoURL: Index of string descriptor providing a URL where the user can go to get more + detailed information about the product and the various Alternate Modes it supports */ + + 0x02, /* bNumberOfAlternateModes: Number of Alternate modes supported. The + maximum value that this field can be set to is MAX_NUM_ALT_MODE. */ + + 0x00, /* bPreferredAlternateMode: Index of the preferred Alternate Mode. System + software may use this information to provide the user with a better user experience. */ + + 0x00, 0x00, /* VCONN Power needed by the adapter for full functionality 000b = 1W */ + + 0x01, 0x00, 0x00, 0x00, /* bmConfigured. 01b: Alternate Mode configuration not attempted or exited */ + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x21, 0x01, /* bcdVersion = 0x0121 */ + 0x00, /* bAdditionalFailureInfo */ + 0x00, /* bReserved */ + LOBYTE(USBD_VID), + HIBYTE(USBD_VID), /* wSVID[0]: Standard or Vendor ID. This shall match one of the SVIDs + returned in response to a USB PD Discover SVIDs command */ + + 0x00, /* bAlternateMode[0] Index of the Alternate Mode within the SVID as + returned in response to a Discover Modes command. Example: + 0 � first Mode entry + 1 � second mode entry */ + + USBD_BB_ALTMODE0_STRING_INDEX, /* iAlternateModeString[0]: Index of string descriptor describing protocol. + It is optional to support this string. */ + LOBYTE(USBD_VID), + HIBYTE(USBD_VID), /* wSVID[1]: Standard or Vendor ID. This shall match one of the SVIDs + returned in response to a USB PD Discover SVIDs command */ + + 0x01, /* bAlternateMode[1] Index of the Alternate Mode within the SVID as + returned in response to a Discover Modes command. Example: + 0 � first Mode entry + 1 � second Mode entry */ + + USBD_BB_ALTMODE1_STRING_INDEX, /* iAlternateModeString[1]: Index of string descriptor describing protocol. + It is optional to support this string. */ + /* Alternate Mode Desc */ + /* ----------- Device Capability Descriptor: BillBoard Alternate Mode Desc ---------- */ + 0x08, /* bLength */ + 0x10, /* bDescriptorType: Device Descriptor Type */ + 0x0F, /* bDevCapabilityType: BILLBOARD ALTERNATE MODE CAPABILITY */ + 0x00, /* bIndex: Index of Alternate Mode described in the Billboard Capability Desc */ + 0x10, 0x00, 0x00, 0x00, /* dwAlternateModeVdo: contents of the Mode VDO for the alternate mode identified by bIndex */ + + 0x08, /* bLength */ + 0x10, /* bDescriptorType: Device Descriptor Type */ + 0x0F, /* bDevCapabilityType: BILLBOARD ALTERNATE MODE CAPABILITY */ + 0x01, /* bIndex: Index of Alternate Mode described in the Billboard Capability Desc */ + 0x20, 0x00, 0x00, 0x00, /* dwAlternateModeVdo: contents of the Mode VDO for the alternate mode identified by bIndex */ +}; +#endif + /* USB Standard Device Descriptor */ __ALIGN_BEGIN uint8_t USBD_LangIDDesc[USB_LEN_LANGID_STR_DESC] __ALIGN_END = { USB_LEN_LANGID_STR_DESC, @@ -312,6 +433,43 @@ static void Get_SerialNum(void) } } + +#if ((USBD_LPM_ENABLED == 1) || (USBD_CLASS_BOS_ENABLED == 1)) +/** + * @brief USBD_USR_BOSDescriptor + * return the BOS descriptor + * @param speed : current device speed + * @param length : pointer to data length variable + * @retval pointer to descriptor buffer + */ +uint8_t *USBD_USR_BOSDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) +{ + UNUSED(speed); + *length = sizeof(USBD_BOSDesc); + return (uint8_t *)USBD_BOSDesc; +} +#endif + + +#if (USBD_CLASS_USER_STRING_DESC == 1) +/** + * @brief Returns the Class User string descriptor. + * @param speed: Current device speed + * @param idx: index of string descriptor + * @param length: Pointer to data length variable + * @retval Pointer to descriptor buffer + */ +uint8_t *USBD_Class_UserStrDescriptor(USBD_SpeedTypeDef speed, uint8_t idx, uint16_t *length) +{ + static uint8_t USBD_StrDesc[255]; + UNUSED(speed); + UNUSED(idx); + UNUSED(length); + return USBD_StrDesc; +} +#endif + + /** * @brief Convert Hex 32Bits value into char * @param value: value to convert diff --git a/cores/arduino/stm32/usb/usbd_desc.h b/cores/arduino/stm32/usb/usbd_desc.h index b226367560..3264b93263 100644 --- a/cores/arduino/stm32/usb/usbd_desc.h +++ b/cores/arduino/stm32/usb/usbd_desc.h @@ -27,11 +27,33 @@ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ #define DEVICE_ID1 (UID_BASE) - #define DEVICE_ID2 (UID_BASE+0x4) - #define DEVICE_ID3 (UID_BASE+0x8) + #define DEVICE_ID2 (UID_BASE + 0x4) + #define DEVICE_ID3 (UID_BASE + 0x8) + + /* + * USB Billboard Class USER string desc Defines Template + * index should start form 0x10 to avoid using the reserved device string desc indexes + */ + #if (USBD_CLASS_USER_STRING_DESC == 1) + #define USBD_BB_IF_STRING_INDEX 0x10U + #define USBD_BB_URL_STRING_INDEX 0x11U + #define USBD_BB_ALTMODE0_STRING_INDEX 0x12U + #define USBD_BB_ALTMODE1_STRING_INDEX 0x13U + /* Add Specific USER string Desc */ + #define USBD_BB_IF_STR_DESC (uint8_t *)"STM32 BillBoard Interface" + #define USBD_BB_URL_STR_DESC (uint8_t *)"www.st.com" + #define USBD_BB_ALTMODE0_STR_DESC (uint8_t *)"STM32 Alternate0 Mode" + #define USBD_BB_ALTMODE1_STR_DESC (uint8_t *)"STM32 Alternate1 Mode" + #endif #define USB_SIZ_STRING_SERIAL 0x1A + #if (USBD_LPM_ENABLED == 1) + #define USB_SIZ_BOS_DESC 0x0CU + #elif (USBD_CLASS_BOS_ENABLED == 1) + #define USB_SIZ_BOS_DESC 0x5DU + #endif + /* Exported macro ------------------------------------------------------------*/ /* Exported functions ------------------------------------------------------- */ extern USBD_DescriptorsTypeDef USBD_Desc; diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_fmpsmbus.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_fmpsmbus.c new file mode 100644 index 0000000000..54f05569e2 --- /dev/null +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_fmpsmbus.c @@ -0,0 +1,3 @@ +#ifdef STM32F4xx + #include "stm32f4xx_hal_fmpsmbus.c" +#endif diff --git a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_fmpi2c.c b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_fmpi2c.c new file mode 100644 index 0000000000..2ffb0ebbcd --- /dev/null +++ b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_fmpi2c.c @@ -0,0 +1,3 @@ +#ifdef STM32F4xx + #include "stm32f4xx_ll_fmpi2c.c" +#endif diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f401xc.h b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f401xc.h index 4d9edd2082..adbde13893 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f401xc.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f401xc.h @@ -12,29 +12,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f401xe.h b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f401xe.h index 066b7bb3c1..9d1df022ae 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f401xe.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f401xe.h @@ -12,29 +12,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h index 101160e653..3d400724d7 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h @@ -12,29 +12,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h index 42b030323f..ef0421dbe1 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h @@ -12,29 +12,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f410cx.h b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f410cx.h index 038fa73ec5..3c1cd0e3fc 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f410cx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f410cx.h @@ -12,29 +12,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f410rx.h b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f410rx.h index 70b709ff52..2851ee38bf 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f410rx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f410rx.h @@ -12,29 +12,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f410tx.h b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f410tx.h index a39675bd6c..19b019f559 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f410tx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f410tx.h @@ -12,29 +12,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f411xe.h b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f411xe.h index 90cec7db39..d585fa5b49 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f411xe.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f411xe.h @@ -12,29 +12,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f412cx.h b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f412cx.h index e778f2de8d..44295176c9 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f412cx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f412cx.h @@ -12,29 +12,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f412rx.h b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f412rx.h index 1ef28af64d..f29c16f136 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f412rx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f412rx.h @@ -12,29 +12,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f412vx.h b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f412vx.h index 04e17d75b3..27a1206633 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f412vx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f412vx.h @@ -12,29 +12,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f412zx.h b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f412zx.h index 2efa2bd751..05d8bb513c 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f412zx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f412zx.h @@ -12,29 +12,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f413xx.h b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f413xx.h index e5375d84a1..69b3f69412 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f413xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f413xx.h @@ -12,29 +12,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f415xx.h b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f415xx.h index 6730fec2e7..8d7b7aa0bb 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f415xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f415xx.h @@ -12,29 +12,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f417xx.h b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f417xx.h index 552df81621..37ed0556c9 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f417xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f417xx.h @@ -12,29 +12,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f423xx.h b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f423xx.h index 35c06c7442..698945beae 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f423xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f423xx.h @@ -12,29 +12,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f427xx.h b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f427xx.h index 58789ca66b..cea0e3a0a8 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f427xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f427xx.h @@ -12,29 +12,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f429xx.h b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f429xx.h index 6a032aca79..8c226ac870 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f429xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f429xx.h @@ -12,29 +12,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f437xx.h b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f437xx.h index 92a4d2b91b..f37db7e76d 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f437xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f437xx.h @@ -12,29 +12,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f439xx.h b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f439xx.h index 4597e3bbf4..df0d0fba75 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f439xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f439xx.h @@ -12,29 +12,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h index 40305655c0..633a0a04f1 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f446xx.h @@ -12,29 +12,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f469xx.h b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f469xx.h index 079faaadf3..505f6299e9 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f469xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f469xx.h @@ -12,29 +12,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f479xx.h b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f479xx.h index 48dfb35811..5057242478 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f479xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f479xx.h @@ -12,29 +12,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h index 3805721b82..ba3d062f9f 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h @@ -16,29 +16,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -122,11 +106,11 @@ #endif /* USE_HAL_DRIVER */ /** - * @brief CMSIS version number V2.6.4 + * @brief CMSIS version number V2.6.5 */ #define __STM32F4xx_CMSIS_VERSION_MAIN (0x02U) /*!< [31:24] main version */ #define __STM32F4xx_CMSIS_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */ -#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x04U) /*!< [15:8] sub2 version */ +#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x05U) /*!< [15:8] sub2 version */ #define __STM32F4xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32F4xx_CMSIS_VERSION ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\ |(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Release_Notes.html b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Release_Notes.html index a56fad23e1..4fb55f8072 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Release_Notes.html +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Release_Notes.html @@ -100,7 +100,12 @@

Update History

-

V2.6.4 / 06-December-2019

+

V2.6.5 / 10-February-2020

+       Main +Changes
 + + +

V2.6.4 / 06-December-2019

      Main Changes
 diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f401xc.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f401xc.s index 3cb58bab8d..0ecc2a6f68 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f401xc.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f401xc.s @@ -14,29 +14,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f401xe.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f401xe.s index aa95a94b9d..5d9d289c3a 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f401xe.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f401xe.s @@ -14,29 +14,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f405xx.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f405xx.s index b07997ab38..c6f10c4055 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f405xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f405xx.s @@ -14,29 +14,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -513,4 +497,3 @@ g_pfnVectors: /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f407xx.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f407xx.s index 9fbc042179..607e9d0bc5 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f407xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f407xx.s @@ -14,29 +14,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f410cx.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f410cx.s index 719bbad555..e4a6658150 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f410cx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f410cx.s @@ -14,29 +14,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f410rx.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f410rx.s index f70887b166..c2ac639de1 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f410rx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f410rx.s @@ -14,29 +14,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f410tx.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f410tx.s index 85f86b7fa3..c6454ef9ae 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f410tx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f410tx.s @@ -14,29 +14,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f411xe.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f411xe.s index b87ef3432b..d3a13aa789 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f411xe.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f411xe.s @@ -14,29 +14,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412cx.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412cx.s index 115d845602..c609c5c33a 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412cx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412cx.s @@ -14,29 +14,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412rx.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412rx.s index 5fdb422698..a1709cea1f 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412rx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412rx.s @@ -14,29 +14,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412vx.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412vx.s index 253ab5ae2a..85af9ac46e 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412vx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412vx.s @@ -14,29 +14,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412zx.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412zx.s index a7a205da19..c9380123f0 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412zx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f412zx.s @@ -14,29 +14,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f413xx.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f413xx.s index 857174895c..3ef7925bf1 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f413xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f413xx.s @@ -14,29 +14,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f415xx.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f415xx.s index 67109e9098..ae7151cd07 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f415xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f415xx.s @@ -14,29 +14,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f417xx.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f417xx.s index 06ba6d42d3..a06a098c23 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f417xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f417xx.s @@ -14,29 +14,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f423xx.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f423xx.s index 25022243ca..5c4faf6a3e 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f423xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f423xx.s @@ -14,29 +14,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f427xx.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f427xx.s index 7c9d417500..b6ddd062c6 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f427xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f427xx.s @@ -14,29 +14,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -548,4 +532,3 @@ g_pfnVectors: .thumb_set DMA2D_IRQHandler,Default_Handler /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f429xx.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f429xx.s index d6cc19a17e..8bd7c511da 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f429xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f429xx.s @@ -14,29 +14,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -554,6 +538,3 @@ g_pfnVectors: .thumb_set DMA2D_IRQHandler,Default_Handler /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - - - diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f437xx.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f437xx.s index 2bba8a2640..aaba6477e1 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f437xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f437xx.s @@ -14,29 +14,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -552,7 +536,3 @@ g_pfnVectors: /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - - - - diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f439xx.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f439xx.s index 90ff42d88c..42169a4bc5 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f439xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f439xx.s @@ -14,29 +14,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -561,8 +545,3 @@ Infinite_Loop: /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - - - - - diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f446xx.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f446xx.s index 1328886af3..19c3f22a38 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f446xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f446xx.s @@ -14,29 +14,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -549,4 +533,3 @@ g_pfnVectors: .thumb_set FMPI2C1_ER_IRQHandler,Default_Handler /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f469xx.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f469xx.s index 1bfef8de05..01c52ae63a 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f469xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f469xx.s @@ -14,29 +14,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -565,8 +549,3 @@ Infinite_Loop: /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - - - - - diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f479xx.s b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f479xx.s index b7ca3e60dd..47fe1409f9 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f479xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/startup_stm32f479xx.s @@ -14,29 +14,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -568,8 +552,3 @@ Infinite_Loop: /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - - - - - diff --git a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c index caa7551e34..449d1d9c0a 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c +++ b/system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c @@ -22,29 +22,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT 2017 STMicroelectronics

+ *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f722xx.h b/system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f722xx.h index 881ca2c617..ec44141164 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f722xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f722xx.h @@ -12,29 +12,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2016 STMicroelectronics

+ *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -1196,28 +1180,32 @@ typedef struct /* Analog to Digital Converter */ /* */ /******************************************************************************/ +#define VREFINT_CAL_ADDR_CMSIS ((uint16_t*) (0x1FF07A2A)) /*!
© COPYRIGHT(c) 2016 STMicroelectronics

+ *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -1212,28 +1196,32 @@ typedef struct /* Analog to Digital Converter */ /* */ /******************************************************************************/ +#define VREFINT_CAL_ADDR_CMSIS ((uint16_t*) (0x1FF07A2A)) /*!
© COPYRIGHT(c) 2016 STMicroelectronics
+ *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -1246,28 +1230,32 @@ typedef struct /* Analog to Digital Converter */ /* */ /******************************************************************************/ +#define VREFINT_CAL_ADDR_CMSIS ((uint16_t*) (0x1FF07A2A)) /*!
© COPYRIGHT(c) 2016 STMicroelectronics
+ *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -1230,28 +1214,32 @@ typedef struct /* Analog to Digital Converter */ /* */ /******************************************************************************/ +#define VREFINT_CAL_ADDR_CMSIS ((uint16_t*) (0x1FF07A2A)) /*!
© COPYRIGHT(c) 2016 STMicroelectronics
+ *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -1246,28 +1230,32 @@ typedef struct /* Analog to Digital Converter */ /* */ /******************************************************************************/ +#define VREFINT_CAL_ADDR_CMSIS ((uint16_t*) (0x1FF07A2A)) /*!
© COPYRIGHT(c) 2016 STMicroelectronics
+ *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -1378,28 +1362,32 @@ typedef struct /* Analog to Digital Converter */ /* */ /******************************************************************************/ +#define VREFINT_CAL_ADDR_CMSIS ((uint16_t*) (0x1FF0F44A)) /*!
© COPYRIGHT(c) 2016 STMicroelectronics
+ *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -1433,28 +1417,32 @@ typedef struct /* Analog to Digital Converter */ /* */ /******************************************************************************/ +#define VREFINT_CAL_ADDR_CMSIS ((uint16_t*) (0x1FF0F44A)) /*!
© COPYRIGHT(c) 2016 STMicroelectronics
+ *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -1508,28 +1492,32 @@ typedef struct /* Analog to Digital Converter */ /* */ /******************************************************************************/ +#define VREFINT_CAL_ADDR_CMSIS ((uint16_t*) (0x1FF0F44A)) /*!
© COPYRIGHT(c) 2016 STMicroelectronics
+ *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -1508,28 +1492,32 @@ typedef struct /* Analog to Digital Converter */ /* */ /******************************************************************************/ +#define VREFINT_CAL_ADDR_CMSIS ((uint16_t*) (0x1FF0F44A)) /*!
© COPYRIGHT(c) 2016 STMicroelectronics
+ *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -1535,28 +1519,32 @@ typedef struct /* Analog to Digital Converter */ /* */ /******************************************************************************/ +#define VREFINT_CAL_ADDR_CMSIS ((uint16_t*) (0x1FF0F44A)) /*!
© COPYRIGHT(c) 2016 STMicroelectronics
+ *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -1629,28 +1613,32 @@ typedef struct /* Analog to Digital Converter */ /* */ /******************************************************************************/ +#define VREFINT_CAL_ADDR_CMSIS ((uint16_t*) (0x1FF0F44A)) /*!
© COPYRIGHT(c) 2016 STMicroelectronics
+ *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -1712,28 +1696,32 @@ typedef struct /* Analog to Digital Converter */ /* */ /******************************************************************************/ +#define VREFINT_CAL_ADDR_CMSIS ((uint16_t*) (0x1FF0F44A)) /*!
© COPYRIGHT(c) 2016 STMicroelectronics
+ *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -1704,28 +1688,32 @@ typedef struct /* Analog to Digital Converter */ /* */ /******************************************************************************/ +#define VREFINT_CAL_ADDR_CMSIS ((uint16_t*) (0x1FF0F44A)) /*!
© COPYRIGHT(c) 2016 STMicroelectronics
+ *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -1787,28 +1771,32 @@ typedef struct /* Analog to Digital Converter */ /* */ /******************************************************************************/ +#define VREFINT_CAL_ADDR_CMSIS ((uint16_t*) (0x1FF0F44A)) /*!
© COPYRIGHT(c) 2016 STMicroelectronics
+ *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -72,10 +56,10 @@ /* Uncomment the line below according to the target STM32 device used in your application */ -#if !defined (STM32F756xx) && !defined (STM32F746xx) && !defined (STM32F745xx) && !defined (STM32F767xx) && \ - !defined (STM32F769xx) && !defined (STM32F777xx) && !defined (STM32F779xx) && !defined (STM32F722xx) && \ - !defined (STM32F723xx) && !defined (STM32F732xx) && !defined (STM32F733xx) && !defined (STM32F730xx) && \ - !defined (STM32F750xx) +#if !defined (STM32F756xx) && !defined (STM32F746xx) && !defined (STM32F745xx) && !defined (STM32F765xx) && \ + !defined (STM32F767xx) && !defined (STM32F769xx) && !defined (STM32F777xx) && !defined (STM32F779xx) && \ + !defined (STM32F722xx) && !defined (STM32F723xx) && !defined (STM32F732xx) && !defined (STM32F733xx) && \ + !defined (STM32F730xx) && !defined (STM32F750xx) /* #define STM32F756xx */ /*!< STM32F756VG, STM32F756ZG, STM32F756ZG, STM32F756IG, STM32F756BG, STM32F756NG Devices */ @@ -113,11 +97,11 @@ #endif /* USE_HAL_DRIVER */ /** - * @brief CMSIS Device version number V1.2.4 + * @brief CMSIS Device version number V1.2.5 */ #define __STM32F7_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */ #define __STM32F7_CMSIS_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */ -#define __STM32F7_CMSIS_VERSION_SUB2 (0x04) /*!< [15:8] sub2 version */ +#define __STM32F7_CMSIS_VERSION_SUB2 (0x05) /*!< [15:8] sub2 version */ #define __STM32F7_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32F7_CMSIS_VERSION ((__STM32F7_CMSIS_VERSION_MAIN << 24)\ |(__STM32F7_CMSIS_VERSION_SUB1 << 16)\ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F7xx/Release_Notes.html b/system/Drivers/CMSIS/Device/ST/STM32F7xx/Release_Notes.html index 026f55cf33..044ced569c 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F7xx/Release_Notes.html +++ b/system/Drivers/CMSIS/Device/ST/STM32F7xx/Release_Notes.html @@ -1,222 +1,325 @@ - - - - - -Release Notes for STM32F7xx CMSIS - - - - - -
-


-

-
- - - - - - -
- - - - - - - - - -
Back to Release page
-

Release -Notes for STM32F7xx CMSIS

-

Copyright -2016 STMicroelectronics

-

-
-

 

- - - - - - -
- -

Update History

-

V1.2.4/ 08-February-2019

-       Main Changes
-
    -
  • CRYP
    • -
    • Update CMSIS devices with correct CRYP data input register name: DIN instead of DR
  • SAI
    • Fix frame length in SAI_xFRCR_FSALL & SAI_xFRCR_FRL bits description
  • USB
    • Add missing Bits Definitions in USB_OTG_DOEPMSK register
      • USB_OTG_DOEPMSK_AHBERRM
      • USB_OTG_DOEPMSK_OTEPSPRM
      • USB_OTG_DOEPMSK_BERRM
      • USB_OTG_DOEPMSK_NAKM
      • USB_OTG_DOEPMSK_NYETM
    • Add missing Bits Definitions in USB_OTG_DIEPINT register
      • USB_OTG_DIEPINT_INEPNM
      • USB_OTG_DIEPINT_AHBERR
      • USB_OTG_DOEPINT_OUTPKTERR
      •  USB_OTG_DOEPINT_NAK
      • USB_OTG_DOEPINT_STPKTRX
    • Add missing Bits Definitions in USB_OTG_DCFG register
      • USB_OTG_DCFG_XCVRDLY
        • -
      • USB_OTG_DCFG_ERRATIM
        • + + + + + + + Release Notes for STM32F7xx CMSIS + + + + + +
        +
        +
        +
        +
        +

        Release Notes for STM32F7xx CMSIS

        +

        Copyright © 2019 STMicroelectronics
        +

        + +
        +
        +
        +

        License

        +

        This software component is licensed by ST under BSD 3-Clause license, the “License”; You may not use this file except in compliance with the License. You may obtain a copy of the License at:

        +
        +https://opensource.org/licenses/BSD-3-Clause +
        +
        +
        +

        Update History

        +
        + +
        +

        Main Changes

        +
          +
        • Add ADC missing calibration address for Vref and Temperature sensor.
          • +
        • Align GPIO Bits Definitions to use _POS and _MSK.
          • +
        • Add IS_UART_WAKEUP_FROMSTOP_INSTANCE macro for STM32F765xx, STM32F767xx, STM32F769xx,STM32F777xx and STM32F779xx devices.
          • +
        • Add missing USART Bits Definitions in USART_CR1, USART_CR3, USART_ISR and USART_ICR registers for STM32F765xx, STM32F767xx, STM32F769xx,STM32F777xx and STM32F779xx devices.
          • +
        • Add USB missing Bit Definition in USB_OTG_GUSBCFG register for STM32F722xx and STM32F732xx devices
          • +
        • Remove dublicated Bits Definitions for OTG register
          • +
        • Remove IS_TIM_SYNCHRO_INSTANCE macro.
          • +
        +
        +
        +
        + +
        +

        Main Changes

        +
          +
        • CRYP +
            +
          • Update CMSIS devices with correct CRYP data input register name: DIN instead of DR
            +
            • +
          • +
        • SAI -Fix frame length in SAI_xFRCR_FSALL & SAI_xFRCR_FRL bits description
          • +
        • USB +
            +
          • Add missing Bits Definitions in USB_OTG_DOEPMSK register +
              +
            • USB_OTG_DOEPMSK_AHBERRM
              • +
            • USB_OTG_DOEPMSK_OTEPSPRM
              • +
            • USB_OTG_DOEPMSK_BERRM
              • +
            • USB_OTG_DOEPMSK_NAKM
              • +
            • USB_OTG_DOEPMSK_NYETM
              • +
            • +
          • Add missing Bits Definitions in USB_OTG_DIEPINT register +
              +
            • USB_OTG_DIEPINT_INEPNM
              • +
            • USB_OTG_DIEPINT_AHBERR
              • +
            • USB_OTG_DOEPINT_OUTPKTERR
              • +
            • USB_OTG_DOEPINT_NAK
              • +
            • USB_OTG_DOEPINT_STPKTRX
              • +
            • +
          • Add missing Bits Definitions in USB_OTG_DCFG register +
              +
            • USB_OTG_DCFG_XCVRDLY
              • +
            • USB_OTG_DCFG_ERRATIM
              • +
            • +
          • Add IS_PCD_ALL_INSTANCE() and IS_HCD_ALL_INSTANCE() defines
            • +
          • Remove GADPCTL parameter from USB_OTG_GlobalTypeDef() structure
            • +
          • Remove GPWRDN parameter from USB_OTG_GlobalTypeDef5° STRUCTURE
            • +
          • +
        • DFSDM +
            +
          • Align Bit naming for DFSDM_FLTICR register: DFSDM_FLTICR_CLRSCSDF–> DFSDM_FLTICR_CLRSCDF
            • +
          • +
        • CEC +
            +
          • Align Bit naming for CEC_RXDR register: CEC_TXDR_RXD–> CEC_RXDR_RXD
            • +
          • +
        • QSPI +
            +
          • Update FLEVEL field in QuadSPI Status register definition to be compliant with user manual
            • +
          • +
        +
        +
        +
        + +
        +

        Main Changes

        +
          +
        • Add the support of STM32F730xx and STM32F750xx devices +
            +
          • Add “stm32f730xx.h” and “stm32f750xx.h” header files
            • +
          • Add startup files “startup_stm32f730xx.s” and “startup_stm32f750xx.s” for EWARM, MDK-ARM and SW4STM32 toolchains
            • +
          • Add Linker files “stm32f730xx_flash.icf”, “stm32f730xx_sram.icf” and “stm32f730xx_ITCM_flash.icf” used within EWARM Workspaces
            • +
          • Add Linker files “stm32f750xx_flash.icf”, “stm32f750xx_sram.icf” and “stm32f750xx_ITCM_flash.icf” used within EWARM Workspaces
            • +
          • +
        +
        +
        +
        + +
        +

        Main Changes

        +
          +
        • Update bits definition for USBPHYC_PLL1 and USBPHYC_LDO registers to be inline with products documentation.
          • +
        +
        +
        +
        + +
        +

        Main Changes

        +
          +
        • Update FLASHSIZE_BASE and UID_BASE defined values for STM32F72x and STM32F73x devices.
          • +
        • Update stm32f7xx.h to include stm32f7xx_hal.h file instead of stm32f7xx_hal_conf.h file
          • +
        • Remove Date and Version from header files
          • +
        +
        +
        +
        + +
        +

        Main Changes

        +
          +
        • Add the support of STM32F722xx, STM32F723xx, STM32F732xx and STM32F733xx devices +
            +
          • Add “stm32f722xx.h”, “stm32f723xx.h”, “stm32f732xx.h” and “stm32f733xx.h” header files
            • +
          • Add startup files “startup_stm32f722xx.s”, “startup_stm32f723xx.s”, “startup_stm32f732xx.s” and “startup_stm32f733xx.s” for EWARM, MDK-ARM and SW4STM32 toolchains
            • +
          • Add Linker files “stm32f722xx_flash.icf”, “stm32f722xx_sram.icf” and “stm32f722xx_ITCM_flash.icf” used within EWARM Workspaces
            • +
          • Add Linker files “stm32f723xx_flash.icf”, “stm32f723xx_sram.icf” and “stm32f723xx_ITCM_flash.icf” used within EWARM Workspaces
            • +
          • Add Linker files “stm32f732xx_flash.icf”, “stm32f732xx_sram.icf” and “stm32f732xx_ITCM_flash.icf” used within EWARM Workspaces
            • +
          • Add Linker files “stm32f733xx_flash.icf”, “stm32f733xx_sram.icf” and “stm32f733xx_ITCM_flash.icf” used within EWARM Workspaces
            • +
          • +
        • All devices header files +
            +
          • Use _Pos and _Mask macro for all Bit Definitions
            • +
          • Use DAC1 instance instead of DAC
            • +
          • Add IS_SMBUS_ALL_INSTANCE macro
            • +
          • Add ADC123_COMMON instance
            • +
          • Add DMA_SxPAR_PA, DMA_SxM0AR_M0A and DMA_SxM1AR_M1A registers Bits Definition
            • +
          • Add DBGMCU_APB1_FZ_DBG_LPTIM1_STOP and DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT Bits Definition
            • +
          • Add FLASH_OTP_BASE and FLASH_OTP_END defines
            • +
          • Add MACDBGR register Bits Definition
            • +
          • Add GPIO_AFRL and GPIO_AFRH registers Bits Definition
            • +
          • Add TIM2_OR, TIM5_OR and TIM11_OR registers Bits Definition
            • +
          • Add TIM1_AF1_BKINP Bit Definition for TIM1_AF1 register
            • +
          • Add IS_TIM_32B_COUNTER_INSTANCE, IS_TIM_BREAK_INSTANCE, IS_TIM_BREAKSOURCE_INSTANCE and IS_TIM_BKIN2_INSTANCE, IS_TIM_CLOCK_DIVISION_INSTANCE, IS_TIM_REPETITION_COUNTER_INSTANCE, IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE, IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE, IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE and IS_TIM_COMMUTATION_EVENT_INSTANCE macros
            • +
          • Add IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE, IS_UART_HALFDUPLEX_INSTANCE and IS_UART_LIN_INSTANCE macros
            • +
          • Remove TIM_SMCR_OCCS Bit Definition for TIM_SMCR register
            • +
          • Remove USART_ISR_WUF and USART_ISR_REACK Bits Definition from USART_ISR register
            • +
          • Rename USART_CR1_M_0 / USART_CR1_M_1 defines to USART_CR1_M0 / USART_CR1_M1
            • +
          • Rename PACKAGESIZE_BASE define to PACKAGE_BASE
            • +
          • Rename RTC_OR_ALARMTYPE Bit Definition to RTC_OR_ALARMOUTTYPE
            • +
          • Rename RTC_CR_BCK Bit Definition to RTC_CR_BKP in RTC_CR register
            • +
          • +
        +
        +
        +
        + +
        +

        Main Changes

        +
          +
        • stm32f7xx.h +
            +
          • update to respectively associate STM32F778xx and STM32F768xx devices to STM32F779xx and STM32F769xx devices
            • +
          • +
        +
        +
        +
        + +
        +

        Main Changes

        +
          +
        • Add the support of STM32F765xx, STM32F767xx, STM32F768xx, STM32F769xx, STM32F777xx, STM32F778xx and STM32F779xx devices +
            +
          • Add “stm32f765xx.h”, “stm32f767xx.h”, “stm32f769xx.h”, “stm32f777xx.h” and “stm32f779xx.h” header files
            • +
          • Add startup files “startup_stm32f765xx.s”, “startup_stm32f767xx.s”, “startup_stm32f769xx.s”, “startup_stm32f777xx.s” and “startup_stm32f779xx.s” for EWARM, MDK-ARM and SW4STM32 toolchains
            • +
          • Add Linker files “stm32f765xx_flash.icf”, “stm32f765xx_sram.icf” and “stm32f765xx_ITCM_flash.icf” used within EWARM Workspaces
            • +
          • Add Linker files “stm32f767xx_flash.icf”, “stm32f767xx_sram.icf” and “stm32f767xx_ITCM_flash.icf” used within EWARM Workspaces
            • +
          • Add Linker files “stm32f769xx_flash.icf”, “stm32f769xx_sram.icf” and “stm32f769xx_ITCM_flash.icf” used within EWARM Workspaces
            • +
          • Add Linker files “stm32f777xx_flash.icf”, “stm32f777xx_sram.icf” and “stm32f777xx_ITCM_flash.icf” used within EWARM Workspaces
            • +
          • Add Linker files “stm32f779xx_flash.icf”, “stm32f779xx_sram.icf” and “stm32f779xx_ITCM_flash.icf” used within EWARM Workspaces
            • +
          • STM32F768xx cmsis files are associated with STM32F767xx ones, as there is no difference between these devices on HAL side
            • +
          • STM32F778xx cmsis files are associated with STM32F777xx ones, as there is no difference between these devices on HAL side
            • +
          • +
        • All devices header files +
            +
          • Update Bit Definition names in DCMI_RISR / DCMI_IER registers
            • +
          • Update Bit Definition names in DMA2D_CR / DMA2D_FGPFCCR / DMA2D_BGPFCCR / DMA2D_OPFCCR registers
            • +
          • Update QUADSPI_CR_FTHRES Bit Definition in QUADSPI_CR register
            • +
          • Rename SAI_xFRCR_FSPO to SAI_xFRCR_FSPOL in SAI_xFRCR register
            • +
          • Rename ADC_CSR_DOVRx Bit Definition to ADC_CSR_OVRx in ADC_CSR register
            • +
          • Rename LTDC_GCR_DTEN Bit Definition to LTDC_GCR_DEN in LTDC_GCR register
            • +
          • Rename PWR_CSR1_UDSWRDY Bit Definition to PWR_CSR1_UDRDY in PWR_CSR1 register
            • +
          • Rename RTC_TAMPCR_TAMPx_TRG Bit Definition to RTC_TAMPCR_TAMPxTRG in RTC_TAMPCR register
            • +
          • Rename USART_ISR_LBD Bit Definition to USART_ISR_LBDF in USART_ISR register
            • +
          • Rename IS_SAI_BLOCK_PERIPH macro to IS_SAI_ALL_INSTANCE
            • +
          • Rename DCMI_ICR_OVF_ISC Bit Definition to DCMI_ICR_OVR_ISC
            • +
          • Rename DMA2D_IFSR register to DMA2D_IFCR
            • +
          • Rename EXTI_IMR_MRx Bit Definition to EXTI_IMR_IM0x
            • +
          • Rename EXTI_EMR_MRx Bit Definition to EXTI_EMR_EMx
            • +
          • Fix LPTIM_CR_SNGSTRT Bit Definition value in LPTIM_CR register
            • +
          • Fix mask incorrect naming in DBGMCU_APB2_FZ register
            • +
          • Fix Bits Definition for SYSCFG_EXTICR4_EXTI13_PI and SYSCFG_EXTICR4_EXTI13_PJ
            • +
          • Add DAC_CR_DMAUDRIEx Bit Definition in DAC_CR register
            • +
          • Add a new mask EXTI_IMR_IM in EXTI bits definition: Interrupt Mask All
            • +
          • Add UID_BASE define for Unique ID register base address
            • +
          • Add FLASHSIZE_BASE define for register base address
            • +
          • Add PACKAGESIZE_BASE define for register base address
            • +
          • Add FLASH_SECTOR_TOTAL define for total Flash sector number
            • +
          • Add Bits Definition for DCMI_ESCR, DCMI_ESUR, DCMI_CWSTRT, DCMI_CWSIZE and DCMI_DR registers
            • +
          • Add PWR_CSR1_EIWUP Bit Definition in PWR_CSR1 register
            • +
          • Add IP version define for QSPI: QSPI_V1_0
            • +
          • Add IS_UART_DRIVER_ENABLE_INSTANCE macro
            • +
          • Apply an ‘U’ suffix to all constants of ‘unsigned’ type (MISRA-C 2004 rule 10.6)
            • +
          • Remove uint32_t cast in all defines
            • +
          • Remove DMA_SxCR_ACK Bit Definition in DMA_SxCR register
            • +
          • Remove I2C_CR1_SWRST / I2C_CR1_WUPEN Bit Definitions in I2C_CR1 register
            • +
          • Keep the same DCMI register names (RISR, MISR, CWSTRTR and CWSIZER) as F4 family
            • +
          • +
        • system_stm32f7xx.c/.h files +
            +
          • Remove external memories configuration from the system_stm32f7xx.c common file (moved to Template Projects)
            • +
          • Add declaration of AHBPrescTable / APBPrescTable constant tables
            • +
          • +
        • stm32f7xx.h +
            +
          • Rename __STM32F7xx_CMSIS_DEVICE_VERSION_xx defines to __STM32F7_CMSIS_VERSION_xx (MISRA-C 2004 rule 5.1)
            • +
        -
      • Add IS_PCD_ALL_INSTANCE() and IS_HCD_ALL_INSTANCE() defines
        • -
      • Remove GADPCTL parameter from USB_OTG_GlobalTypeDef() structure
        • -
      • Remove GPWRDN parameter from USB_OTG_GlobalTypeDef5� STRUCTURE
        -
        • -
    • DFSDM
      • Align Bit naming for DFSDM_FLTICR register: DFSDM_FLTICR_CLRSCSDF--> DFSDM_FLTICR_CLRSCDF
      -
    • CEC
      • -
        -
      • Align Bit naming for CEC_RXDR register: CEC_TXDR_RXD--> CEC_RXDR_RXD
        • -
      -
    • QSPI
      • -
        -
      • Update FLEVEL field in QuadSPI Status register definition to be compliant with user manual
        -
        • -
      -
    -

    V1.2.3 -/ 29-June-2018

    -      Main -Changes
    • Add the support of STM32F730xx and  STM32F750xx  devices
      • Add "stm32f730xx.h" and "stm32f750xx.h" header files
      • Add startup files "startup_stm32f730xx.s" and "startup_stm32f750xx.s" for EWARM, MDK-ARM and SW4STM32 toolchains
      • Add Linker files "stm32f730xx_flash.icf", "stm32f730xx_sram.icf" and "stm32f730xx_ITCM_flash.icf" used within EWARM Workspaces
      • Add Linker files "stm32f750xx_flash.icf", "stm32f750xx_sram.icf" and "stm32f750xx_ITCM_flash.icf" used within EWARM Workspaces

    V1.2.2 -/ 26-December-2017

    Main -Changes

    -
    • Update bits definition for USBPHYC_PLL1 and USBPHYC_LDO registers to be inline with products documentation.

    V1.2.1 -/ 25-August-2017

    Main -Changes

    -
    • Update FLASHSIZE_BASE and UID_BASE defined values for STM32F72x and STM32F73x devices.
    • Update stm32f7xx.h to include stm32f7xx_hal.h file instead of stm32f7xx_hal_conf.h file
    • Remove Date and Version from header files

    V1.2.0 -/ 30-December-2016

    Main -Changes

    -
    • Add the support of STM32F722xx, STM32F723xx, STM32F732xx and STM32F733xx devices
      • Add "stm32f722xx.h", "stm32f723xx.h", "stm32f732xx.h" and "stm32f733xx.h" header files
      • Add startup files "startup_stm32f722xx.s", "startup_stm32f723xx.s", "startup_stm32f732xx.s" and "startup_stm32f733xx.s" for EWARM, MDK-ARM and SW4STM32 toolchains
      • Add Linker files "stm32f722xx_flash.icf", "stm32f722xx_sram.icf" and "stm32f722xx_ITCM_flash.icf" used within EWARM Workspaces
      • Add Linker files "stm32f723xx_flash.icf", "stm32f723xx_sram.icf" and "stm32f723xx_ITCM_flash.icf" used within EWARM Workspaces
      • Add Linker files "stm32f732xx_flash.icf", "stm32f732xx_sram.icf" and "stm32f732xx_ITCM_flash.icf" used within EWARM Workspaces
      • Add Linker files "stm32f733xx_flash.icf", "stm32f733xx_sram.icf" and "stm32f733xx_ITCM_flash.icf" used within EWARM Workspaces
    • All devices header files
      • Use _Pos and _Mask macro for all Bit Definitions
      • Use DAC1 instance instead of DAC
      • Add IS_SMBUS_ALL_INSTANCE macro
      • Add ADC123_COMMON instance
      • Add DMA_SxPAR_PA, DMA_SxM0AR_M0A and DMA_SxM1AR_M1A registers Bits Definition
      • Add DBGMCU_APB1_FZ_DBG_LPTIM1_STOP and DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT Bits Definition
      • Add FLASH_OTP_BASE and FLASH_OTP_END defines
      • Add MACDBGR register Bits Definition
      • Add GPIO_AFRL and GPIO_AFRH registers Bits Definition 
      • Add TIM2_OR, TIM5_OR and TIM11_OR registers Bits Definition
      • Add TIM1_AF1_BKINP Bit Definition for TIM1_AF1 register
      • Add -IS_TIM_32B_COUNTER_INSTANCE, IS_TIM_BREAK_INSTANCE, -IS_TIM_BREAKSOURCE_INSTANCE and IS_TIM_BKIN2_INSTANCE, -IS_TIM_CLOCK_DIVISION_INSTANCE, IS_TIM_REPETITION_COUNTER_INSTANCE, -IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE, -IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE, -IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE and -IS_TIM_COMMUTATION_EVENT_INSTANCE macros
      • Add IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE, IS_UART_HALFDUPLEX_INSTANCE and IS_UART_LIN_INSTANCE macros
      • Remove TIM_SMCR_OCCS Bit Definition for TIM_SMCR register
      • Remove USART_ISR_WUF and USART_ISR_REACK Bits Definition from USART_ISR register
      • Rename USART_CR1_M_0 / USART_CR1_M_1 defines to USART_CR1_M0 / USART_CR1_M1
      • Rename PACKAGESIZE_BASE define to PACKAGE_BASE
      • Rename RTC_OR_ALARMTYPE Bit Definition to RTC_OR_ALARMOUTTYPE
      • Rename RTC_CR_BCK Bit Definition to RTC_CR_BKP in RTC_CR register

    V1.1.1 -/ 01-July-2016

    Main -Changes

    -
    • stm32f7xx.h
      • update to respectively associate STM32F778xx and STM32F768xx devices to STM32F779xx and STM32F769xx devices

    V1.1.0 -/ 22-April-2016

    Main -Changes

    -
    • Add the support of STM32F765xx, STM32F767xx, STM32F768xx, STM32F769xx, STM32F777xx, STM32F778xx and STM32F779xx devices
      • Add "stm32f765xx.h", "stm32f767xx.h", "stm32f769xx.h", "stm32f777xx.h" and "stm32f779xx.h" header files
      • Add startup files "startup_stm32f765xx.s", "startup_stm32f767xx.s", "startup_stm32f769xx.s", "startup_stm32f777xx.s" and "startup_stm32f779xx.s" for EWARM, MDK-ARM and SW4STM32 toolchains
      • Add Linker files "stm32f765xx_flash.icf", "stm32f765xx_sram.icf" and "stm32f765xx_ITCM_flash.icf" used within EWARM Workspaces
      • Add Linker files "stm32f767xx_flash.icf", "stm32f767xx_sram.icf" and "stm32f767xx_ITCM_flash.icf" used within EWARM Workspaces
      • Add Linker files "stm32f769xx_flash.icf", "stm32f769xx_sram.icf" and "stm32f769xx_ITCM_flash.icf" used within EWARM Workspaces
      • Add Linker files "stm32f777xx_flash.icf", "stm32f777xx_sram.icf" and "stm32f777xx_ITCM_flash.icf" used within EWARM Workspaces
      • Add Linker files "stm32f779xx_flash.icf", "stm32f779xx_sram.icf" and "stm32f779xx_ITCM_flash.icf" used within EWARM Workspaces
      • STM32F768xx cmsis files are associated with STM32F767xx ones, as there is no difference between these devices on HAL side
      • STM32F778xx cmsis files are associated with STM32F777xx ones, as there is no difference between these devices on HAL side
    • All devices header files
      • Update Bit Definition names in DCMI_RISR / DCMI_IER registers
      • Update Bit Definition names in DMA2D_CR / DMA2D_FGPFCCR / DMA2D_BGPFCCR / DMA2D_OPFCCR registers
      • Update QUADSPI_CR_FTHRES Bit Definition in QUADSPI_CR register
      • Rename SAI_xFRCR_FSPO to SAI_xFRCR_FSPOL in SAI_xFRCR register
      • Rename ADC_CSR_DOVRx Bit Definition to ADC_CSR_OVRx in ADC_CSR register
      • Rename LTDC_GCR_DTEN Bit Definition to LTDC_GCR_DEN in LTDC_GCR register
      • Rename PWR_CSR1_UDSWRDY Bit Definition to PWR_CSR1_UDRDY in PWR_CSR1 register
      • Rename RTC_TAMPCR_TAMPx_TRG Bit Definition to RTC_TAMPCR_TAMPxTRG in RTC_TAMPCR register
      • Rename USART_ISR_LBD Bit Definition to USART_ISR_LBDF in USART_ISR register
      • Rename IS_SAI_BLOCK_PERIPH macro to IS_SAI_ALL_INSTANCE
      • Rename DCMI_ICR_OVF_ISC Bit Definition to DCMI_ICR_OVR_ISC
      • Rename DMA2D_IFSR register to DMA2D_IFCR
      • Rename EXTI_IMR_MRx Bit Definition to EXTI_IMR_IM0x
      • Rename EXTI_EMR_MRx Bit Definition to EXTI_EMR_EMx
      • Fix LPTIM_CR_SNGSTRT Bit Definition value in LPTIM_CR register
      • Fix mask incorrect naming in DBGMCU_APB2_FZ register
      • Fix Bits Definition for SYSCFG_EXTICR4_EXTI13_PI and SYSCFG_EXTICR4_EXTI13_PJ
      • Add DAC_CR_DMAUDRIEx Bit Definition in DAC_CR register
      • Add a new mask EXTI_IMR_IM in EXTI bits definition: Interrupt Mask All
      • Add UID_BASE define for Unique ID register base address
      • Add FLASHSIZE_BASE define for register base address
      • Add PACKAGESIZE_BASE define for register base address
      • Add FLASH_SECTOR_TOTAL define for total Flash sector number
      • Add Bits Definition for DCMI_ESCR, DCMI_ESUR, DCMI_CWSTRT, DCMI_CWSIZE and DCMI_DR registers
      • Add PWR_CSR1_EIWUP Bit Definition in PWR_CSR1 register
      • Add IP version define for QSPI: QSPI_V1_0
      • Add IS_UART_DRIVER_ENABLE_INSTANCE macro
      • Apply an 'U' suffix to all constants of 'unsigned' type (MISRA-C 2004 rule 10.6)
      • Remove uint32_t cast in all defines
      • Remove DMA_SxCR_ACK Bit Definition in DMA_SxCR register
      • Remove I2C_CR1_SWRST / I2C_CR1_WUPEN Bit Definitions in I2C_CR1 register
      • Keep the same DCMI register names (RISR, MISR, CWSTRTR and CWSIZER) as F4 family
    • system_stm32f7xx.c/.h files
      • Remove external memories configuration from the system_stm32f7xx.c common file (moved to Template Projects)
      • Add declaration of AHBPrescTable / APBPrescTable constant tables
    • stm32f7xx.h
      • Rename __STM32F7xx_CMSIS_DEVICE_VERSION_xx defines to __STM32F7_CMSIS_VERSION_xx (MISRA-C 2004 rule 5.1)

    V1.0.3 -/ 13-November-2015

    -

    Main -Changes

    -
    • stm32f745xx.h, stm32f746xx.h and stm32f756xx.h files
      • update __CM7_REV with proper Cortex M7 core revision
      • update SAI_xCR2_CPL bit definition
      • update WWDG bits naming to be aligned with reference manual
      • rename I2C_CR1_DFN bit to I2C_CR1_DNF
      • remove OR register definition from LPTIM_TypeDef structure
    • system_stm32f7xx.c
      • update SystemInit_ExtMemCtl() function implementation to allow simultaneous use of SDRAM and SRAM external memories

    V1.0.2 -/ 21-September-2015

    -

    Main -Changes

    -
    • stm32f745xx.h, stm32f746xx.h and stm32f756xx.h files
      • add new define USB_OTG_DOEPMSK_OTEPSPRM
      • add new define USB_OTG_DOEPINT_OTEPSPR

    V1.0.1 -/ 25-June-2015

    -

    Main -Changes

    -
    • stm32f745xx.h, stm32f746xx.h and stm32f756xx.h files
      • update IDR field declaration in CRC_TypeDef sructure
      • add I2C Own address 2 mask bits defininition in the I2C_OAR2 register
      • update SAI_xSR_FLVL_2 bit definition
    • stm32f756xx.h file
      • rename HASH_STR_NBWx bits definition to HASH_STR_NBLWx
      • rename HASH_IMR_DINIM bit definition to HASH_IMR_DINIE
      • rename HASH_IMR_DCIM bit definition to HASH_IMR_DCIE

    V1.0.0 -/ 28-April-2015

    -

    Main -Changes

    -
    • First -official release for STM32F756xx/746xx/745xx -devices
    -
      + + +
      + +
      +

      Main Changes

      +
        +
      • stm32f745xx.h, stm32f746xx.h and stm32f756xx.h files +
          +
        • update __CM7_REV with proper Cortex M7 core revision
          • +
        • update SAI_xCR2_CPL bit definition
          • +
        • update WWDG bits naming to be aligned with reference manual
          • +
        • rename I2C_CR1_DFN bit to I2C_CR1_DNF
          • +
        • remove OR register definition from LPTIM_TypeDef structure
          • +
        • +
      • system_stm32f7xx.c +
          +
        • update SystemInit_ExtMemCtl() function implementation to allow simultaneous use of SDRAM and SRAM external memories
          • +
        • +
      +
      +
      +
      + +
      +

      Main Changes

      +
        +
      • stm32f745xx.h, stm32f746xx.h and stm32f756xx.h files +
          +
        • add new define USB_OTG_DOEPMSK_OTEPSPRM
          • +
        • add new define USB_OTG_DOEPINT_OTEPSPR
          • +
      -

      License

      -

      -
      -
      -
      Redistribution -and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are -met:
      -       -
        -
      1. Redistributions -of source code must retain the above copyright notice, this list of -conditions and the following disclaimer.
        2. -
      2. Redistributions -in binary form must reproduce the above copyright notice, this list of -conditions and the following disclaimer in the -documentation and/or other materials provided with the distribution.
        3. -
      3. Neither the -name of STMicroelectronics nor the names of its contributors may be -used to endorse or promote products derived
        -
        4. -
      -       -from this software without specific prior written permission.
      -
      -THIS -SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, -INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -MERCHANTABILITY AND FITNESS FOR A PARTICULAR -PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR -CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF -THE POSSIBILITY OF SUCH DAMAGE.
      -
      -
      -

        

      - -
      -
      -

      For -complete documentation on STM32 Microcontrollers -visit www.st.com/STM32

      -
-

-
-
-

 

-
- \ No newline at end of file + + +
+ +
+

Main Changes

+
    +
  • stm32f745xx.h, stm32f746xx.h and stm32f756xx.h files +
      +
    • update IDR field declaration in CRC_TypeDef sructure
      • +
    • add I2C Own address 2 mask bits defininition in the I2C_OAR2 register
      • +
    • update SAI_xSR_FLVL_2 bit definition
      • +
    • +
  • stm32f756xx.h file +
      +
    • rename HASH_STR_NBWx bits definition to HASH_STR_NBLWx
      • +
    • rename HASH_IMR_DINIM bit definition to HASH_IMR_DINIE
      • +
    • rename HASH_IMR_DCIM bit definition to HASH_IMR_DCIE
      • +
    • +
+
+
+
+ +
+

Main Changes

+

First release

+

First official release for STM32F756xx/746xx/745xx devices

+
+
+ + +
+For complete documentation on STM32 Microcontrollers , visit: www.st.com/stm32 This release note uses up to date web standards and, for this reason, should not be opened with Internet Explorer but preferably with popular browsers such as Google Chrome, Mozilla Firefox, Opera or Microsoft Edge. +
+ + diff --git a/system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/startup_stm32f722xx.s b/system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/startup_stm32f722xx.s index 13e9e2904b..b6db501dbb 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/startup_stm32f722xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/startup_stm32f722xx.s @@ -14,29 +14,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT 2016 STMicroelectronics

+ *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/startup_stm32f723xx.s b/system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/startup_stm32f723xx.s index c52b1d7aec..7f13e36ec8 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/startup_stm32f723xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/startup_stm32f723xx.s @@ -14,29 +14,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT 2016 STMicroelectronics

+ *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/startup_stm32f730xx.s b/system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/startup_stm32f730xx.s index 6c34df2b77..3a7999d36c 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/startup_stm32f730xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/startup_stm32f730xx.s @@ -14,29 +14,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT 2016 STMicroelectronics

+ *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/startup_stm32f732xx.s b/system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/startup_stm32f732xx.s index 362da8bcd9..38f61df803 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/startup_stm32f732xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/startup_stm32f732xx.s @@ -14,29 +14,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT 2016 STMicroelectronics

+ *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/startup_stm32f733xx.s b/system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/startup_stm32f733xx.s index fce8ad0acc..ab332842e3 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/startup_stm32f733xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/startup_stm32f733xx.s @@ -14,29 +14,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT 2016 STMicroelectronics

+ *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/startup_stm32f745xx.s b/system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/startup_stm32f745xx.s index 22a5b1bb8e..2cd86f5ba1 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/startup_stm32f745xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/startup_stm32f745xx.s @@ -14,29 +14,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT 2016 STMicroelectronics

+ *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/startup_stm32f746xx.s b/system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/startup_stm32f746xx.s index 4fd5a9d971..d2445da4c8 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/startup_stm32f746xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/startup_stm32f746xx.s @@ -14,29 +14,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT 2016 STMicroelectronics

+ *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/startup_stm32f750xx.s b/system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/startup_stm32f750xx.s index e0858cc3ba..110e03276d 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/startup_stm32f750xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/startup_stm32f750xx.s @@ -14,29 +14,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT 2016 STMicroelectronics

+ *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/startup_stm32f756xx.s b/system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/startup_stm32f756xx.s index 2ee3ef35bc..9c3b8f3cb2 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/startup_stm32f756xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/startup_stm32f756xx.s @@ -14,29 +14,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT 2016 STMicroelectronics

+ *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/startup_stm32f765xx.s b/system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/startup_stm32f765xx.s index c843a88a21..3f74d74c58 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/startup_stm32f765xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/startup_stm32f765xx.s @@ -14,29 +14,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT 2016 STMicroelectronics

+ *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/startup_stm32f767xx.s b/system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/startup_stm32f767xx.s index 344526dac5..e61a208490 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/startup_stm32f767xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/startup_stm32f767xx.s @@ -14,29 +14,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT 2016 STMicroelectronics

+ *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/startup_stm32f769xx.s b/system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/startup_stm32f769xx.s index 64791b1854..88aa2f235f 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/startup_stm32f769xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/startup_stm32f769xx.s @@ -14,29 +14,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT 2016 STMicroelectronics

+ *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/startup_stm32f777xx.s b/system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/startup_stm32f777xx.s index dc476fc880..9a42ef90f9 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/startup_stm32f777xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/startup_stm32f777xx.s @@ -14,29 +14,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT 2016 STMicroelectronics

+ *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/startup_stm32f779xx.s b/system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/startup_stm32f779xx.s index f18c868d30..7aa112333f 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/startup_stm32f779xx.s +++ b/system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/startup_stm32f779xx.s @@ -14,29 +14,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT 2016 STMicroelectronics

+ *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/system_stm32f7xx.c b/system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/system_stm32f7xx.c index cb4e56623f..174364021b 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/system_stm32f7xx.c +++ b/system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/system_stm32f7xx.c @@ -22,29 +22,13 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT 2016 STMicroelectronics

+ *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

* - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -150,27 +134,9 @@ void SystemInit(void) { /* FPU settings ------------------------------------------------------------*/ - #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ - #endif - /* Reset the RCC clock configuration to the default reset state ------------*/ - /* Set HSION bit */ - RCC->CR |= (uint32_t)0x00000001; - - /* Reset CFGR register */ - RCC->CFGR = 0x00000000; - - /* Reset HSEON, CSSON and PLLON bits */ - RCC->CR &= (uint32_t)0xFEF6FFFF; - - /* Reset PLLCFGR register */ - RCC->PLLCFGR = 0x24003010; - - /* Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; - - /* Disable all interrupts */ - RCC->CIR = 0x00000000; +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ +#endif /* Configure the Vector Table location add offset address ------------------*/ #ifdef VECT_TAB_SRAM diff --git a/system/Drivers/CMSIS/Device/ST/STM32F7xx/_htmresc/mini-st.css b/system/Drivers/CMSIS/Device/ST/STM32F7xx/_htmresc/mini-st.css new file mode 100644 index 0000000000..3caf11c32e --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32F7xx/_htmresc/mini-st.css @@ -0,0 +1,1700 @@ +@charset "UTF-8"; +/* + Flavor name: Default (mini-default) + Author: Angelos Chalaris (chalarangelo@gmail.com) + Maintainers: Angelos Chalaris + mini.css version: v3.0.0-alpha.3 +*/ +/* + Browsers resets and base typography. +*/ +/* Core module CSS variable definitions */ +:root { + --fore-color: #111; + --secondary-fore-color: #444; + --back-color: #f8f8f8; + --secondary-back-color: #f0f0f0; + --blockquote-color: #f57c00; + --pre-color: #1565c0; + --border-color: #aaa; + --secondary-border-color: #ddd; + --heading-ratio: 1.19; + --universal-margin: 0.5rem; + --universal-padding: 0.125rem; + --universal-border-radius: 0.125rem; + --a-link-color: #0277bd; + --a-visited-color: #01579b; } + +html { + font-size: 14px; } + +a, b, del, em, i, ins, q, span, strong, u { + font-size: 1em; } + +html, * { + font-family: -apple-system, BlinkMacSystemFont, "Segoe UI", Roboto, Ubuntu, "Helvetica Neue", Helvetica, sans-serif; + line-height: 1.4; + -webkit-text-size-adjust: 100%; } + +* { + font-size: 1rem; } + +body { + margin: 0; + color: var(--fore-color); + background: var(--back-color); } + +details { + display: block; } + +summary { + display: list-item; } + +abbr[title] { + border-bottom: none; + text-decoration: underline dotted; } + +input { + overflow: visible; } + +img { + max-width: 100%; + height: auto; } + +h1, h2, h3, h4, h5, h6 { + line-height: 1.2; + margin: calc(1.5 * var(--universal-margin)) var(--universal-margin); + font-weight: 500; } + h1 small, h2 small, h3 small, h4 small, h5 small, h6 small { + color: var(--secondary-fore-color); + display: block; + margin-top: -0.25rem; } + +h1 { + font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio) * var(--heading-ratio)); } + +h2 { + font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio); ); + background: var(--mark-back-color); + font-weight: 600; + padding: 0.1em 0.5em 0.2em 0.5em; + color: var(--mark-fore-color); } + +h3 { + font-size: calc(1rem * var(--heading-ratio)); + padding-left: calc(2 * var(--universal-margin)); + /* background: var(--border-color); */ + } + +h4 { + font-size: 1rem;); + padding-left: calc(4 * var(--universal-margin)); } + +h5 { + font-size: 1rem; } + +h6 { + font-size: calc(1rem / var(--heading-ratio)); } + +p { + margin: var(--universal-margin); } + +ol, ul { + margin: var(--universal-margin); + padding-left: calc(6 * var(--universal-margin)); } + +b, strong { + font-weight: 700; } + +hr { + box-sizing: content-box; + border: 0; + line-height: 1.25em; + margin: var(--universal-margin); + height: 0.0625rem; + background: linear-gradient(to right, transparent, var(--border-color) 20%, var(--border-color) 80%, transparent); } + +blockquote { + display: block; + position: relative; + font-style: italic; + color: var(--secondary-fore-color); + margin: var(--universal-margin); + padding: calc(3 * var(--universal-padding)); + border: 0.0625rem solid var(--secondary-border-color); + border-left: 0.375rem solid var(--blockquote-color); + border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; } + blockquote:before { + position: absolute; + top: calc(0rem - var(--universal-padding)); + left: 0; + font-family: sans-serif; + font-size: 3rem; + font-weight: 700; + content: "\201c"; + color: var(--blockquote-color); } + blockquote[cite]:after { + font-style: normal; + font-size: 0.75em; + font-weight: 700; + content: "\a— " attr(cite); + white-space: pre; } + +code, kbd, pre, samp { + font-family: Menlo, Consolas, monospace; + font-size: 0.85em; } + +code { + background: var(--secondary-back-color); + border-radius: var(--universal-border-radius); + padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); } + +kbd { + background: var(--fore-color); + color: var(--back-color); + border-radius: var(--universal-border-radius); + padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); } + +pre { + overflow: auto; + background: var(--secondary-back-color); + padding: calc(1.5 * var(--universal-padding)); + margin: var(--universal-margin); + border: 0.0625rem solid var(--secondary-border-color); + border-left: 0.25rem solid var(--pre-color); + border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; } + +sup, sub, code, kbd { + line-height: 0; + position: relative; + vertical-align: baseline; } + +small, sup, sub, figcaption { + font-size: 0.75em; } + +sup { + top: -0.5em; } + +sub { + bottom: -0.25em; } + +figure { + margin: var(--universal-margin); } + +figcaption { + color: var(--secondary-fore-color); } + +a { + text-decoration: none; } + a:link { + color: var(--a-link-color); } + a:visited { + color: var(--a-visited-color); } + a:hover, a:focus { + text-decoration: underline; } + +/* + Definitions for the grid system, cards and containers. +*/ +.container { + margin: 0 auto; + padding: 0 calc(1.5 * var(--universal-padding)); } + +.row { + box-sizing: border-box; + display: flex; + flex: 0 1 auto; + flex-flow: row wrap; } + +.col-sm, +[class^='col-sm-'], +[class^='col-sm-offset-'], +.row[class*='cols-sm-'] > * { + box-sizing: border-box; + flex: 0 0 auto; + padding: 0 calc(var(--universal-padding) / 2); } + +.col-sm, +.row.cols-sm > * { + max-width: 100%; + flex-grow: 1; + flex-basis: 0; } + +.col-sm-1, +.row.cols-sm-1 > * { + max-width: 8.3333333333%; + flex-basis: 8.3333333333%; } + +.col-sm-offset-0 { + margin-left: 0; } + +.col-sm-2, +.row.cols-sm-2 > * { + max-width: 16.6666666667%; + flex-basis: 16.6666666667%; } + +.col-sm-offset-1 { + margin-left: 8.3333333333%; } + +.col-sm-3, +.row.cols-sm-3 > * { + max-width: 25%; + flex-basis: 25%; } + +.col-sm-offset-2 { + margin-left: 16.6666666667%; } + +.col-sm-4, +.row.cols-sm-4 > * { + max-width: 33.3333333333%; + flex-basis: 33.3333333333%; } + +.col-sm-offset-3 { + margin-left: 25%; } + +.col-sm-5, +.row.cols-sm-5 > * { + max-width: 41.6666666667%; + flex-basis: 41.6666666667%; } + +.col-sm-offset-4 { + margin-left: 33.3333333333%; } + +.col-sm-6, +.row.cols-sm-6 > * { + max-width: 50%; + flex-basis: 50%; } + +.col-sm-offset-5 { + margin-left: 41.6666666667%; } + +.col-sm-7, +.row.cols-sm-7 > * { + max-width: 58.3333333333%; + flex-basis: 58.3333333333%; } + +.col-sm-offset-6 { + margin-left: 50%; } + +.col-sm-8, +.row.cols-sm-8 > * { + max-width: 66.6666666667%; + flex-basis: 66.6666666667%; } + +.col-sm-offset-7 { + margin-left: 58.3333333333%; } + +.col-sm-9, +.row.cols-sm-9 > * { + max-width: 75%; + flex-basis: 75%; } + +.col-sm-offset-8 { + margin-left: 66.6666666667%; } + +.col-sm-10, +.row.cols-sm-10 > * { + max-width: 83.3333333333%; + flex-basis: 83.3333333333%; } + +.col-sm-offset-9 { + margin-left: 75%; } + +.col-sm-11, +.row.cols-sm-11 > * { + max-width: 91.6666666667%; + flex-basis: 91.6666666667%; } + +.col-sm-offset-10 { + margin-left: 83.3333333333%; } + +.col-sm-12, +.row.cols-sm-12 > * { + max-width: 100%; + flex-basis: 100%; } + +.col-sm-offset-11 { + margin-left: 91.6666666667%; } + +.col-sm-normal { + order: initial; } + +.col-sm-first { + order: -999; } + +.col-sm-last { + order: 999; } + +@media screen and (min-width: 500px) { + .col-md, + [class^='col-md-'], + [class^='col-md-offset-'], + .row[class*='cols-md-'] > * { + box-sizing: border-box; + flex: 0 0 auto; + padding: 0 calc(var(--universal-padding) / 2); } + + .col-md, + .row.cols-md > * { + max-width: 100%; + flex-grow: 1; + flex-basis: 0; } + + .col-md-1, + .row.cols-md-1 > * { + max-width: 8.3333333333%; + flex-basis: 8.3333333333%; } + + .col-md-offset-0 { + margin-left: 0; } + + .col-md-2, + .row.cols-md-2 > * { + max-width: 16.6666666667%; + flex-basis: 16.6666666667%; } + + .col-md-offset-1 { + margin-left: 8.3333333333%; } + + .col-md-3, + .row.cols-md-3 > * { + max-width: 25%; + flex-basis: 25%; } + + .col-md-offset-2 { + margin-left: 16.6666666667%; } + + .col-md-4, + .row.cols-md-4 > * { + max-width: 33.3333333333%; + flex-basis: 33.3333333333%; } + + .col-md-offset-3 { + margin-left: 25%; } + + .col-md-5, + .row.cols-md-5 > * { + max-width: 41.6666666667%; + flex-basis: 41.6666666667%; } + + .col-md-offset-4 { + margin-left: 33.3333333333%; } + + .col-md-6, + .row.cols-md-6 > * { + max-width: 50%; + flex-basis: 50%; } + + .col-md-offset-5 { + margin-left: 41.6666666667%; } + + .col-md-7, + .row.cols-md-7 > * { + max-width: 58.3333333333%; + flex-basis: 58.3333333333%; } + + .col-md-offset-6 { + margin-left: 50%; } + + .col-md-8, + .row.cols-md-8 > * { + max-width: 66.6666666667%; + flex-basis: 66.6666666667%; } + + .col-md-offset-7 { + margin-left: 58.3333333333%; } + + .col-md-9, + .row.cols-md-9 > * { + max-width: 75%; + flex-basis: 75%; } + + .col-md-offset-8 { + margin-left: 66.6666666667%; } + + .col-md-10, + .row.cols-md-10 > * { + max-width: 83.3333333333%; + flex-basis: 83.3333333333%; } + + .col-md-offset-9 { + margin-left: 75%; } + + .col-md-11, + .row.cols-md-11 > * { + max-width: 91.6666666667%; + flex-basis: 91.6666666667%; } + + .col-md-offset-10 { + margin-left: 83.3333333333%; } + + .col-md-12, + .row.cols-md-12 > * { + max-width: 100%; + flex-basis: 100%; } + + .col-md-offset-11 { + margin-left: 91.6666666667%; } + + .col-md-normal { + order: initial; } + + .col-md-first { + order: -999; } + + .col-md-last { + order: 999; } } +@media screen and (min-width: 1280px) { + .col-lg, + [class^='col-lg-'], + [class^='col-lg-offset-'], + .row[class*='cols-lg-'] > * { + box-sizing: border-box; + flex: 0 0 auto; + padding: 0 calc(var(--universal-padding) / 2); } + + .col-lg, + .row.cols-lg > * { + max-width: 100%; + flex-grow: 1; + flex-basis: 0; } + + .col-lg-1, + .row.cols-lg-1 > * { + max-width: 8.3333333333%; + flex-basis: 8.3333333333%; } + + .col-lg-offset-0 { + margin-left: 0; } + + .col-lg-2, + .row.cols-lg-2 > * { + max-width: 16.6666666667%; + flex-basis: 16.6666666667%; } + + .col-lg-offset-1 { + margin-left: 8.3333333333%; } + + .col-lg-3, + .row.cols-lg-3 > * { + max-width: 25%; + flex-basis: 25%; } + + .col-lg-offset-2 { + margin-left: 16.6666666667%; } + + .col-lg-4, + .row.cols-lg-4 > * { + max-width: 33.3333333333%; + flex-basis: 33.3333333333%; } + + .col-lg-offset-3 { + margin-left: 25%; } + + .col-lg-5, + .row.cols-lg-5 > * { + max-width: 41.6666666667%; + flex-basis: 41.6666666667%; } + + .col-lg-offset-4 { + margin-left: 33.3333333333%; } + + .col-lg-6, + .row.cols-lg-6 > * { + max-width: 50%; + flex-basis: 50%; } + + .col-lg-offset-5 { + margin-left: 41.6666666667%; } + + .col-lg-7, + .row.cols-lg-7 > * { + max-width: 58.3333333333%; + flex-basis: 58.3333333333%; } + + .col-lg-offset-6 { + margin-left: 50%; } + + .col-lg-8, + .row.cols-lg-8 > * { + max-width: 66.6666666667%; + flex-basis: 66.6666666667%; } + + .col-lg-offset-7 { + margin-left: 58.3333333333%; } + + .col-lg-9, + .row.cols-lg-9 > * { + max-width: 75%; + flex-basis: 75%; } + + .col-lg-offset-8 { + margin-left: 66.6666666667%; } + + .col-lg-10, + .row.cols-lg-10 > * { + max-width: 83.3333333333%; + flex-basis: 83.3333333333%; } + + .col-lg-offset-9 { + margin-left: 75%; } + + .col-lg-11, + .row.cols-lg-11 > * { + max-width: 91.6666666667%; + flex-basis: 91.6666666667%; } + + .col-lg-offset-10 { + margin-left: 83.3333333333%; } + + .col-lg-12, + .row.cols-lg-12 > * { + max-width: 100%; + flex-basis: 100%; } + + .col-lg-offset-11 { + margin-left: 91.6666666667%; } + + .col-lg-normal { + order: initial; } + + .col-lg-first { + order: -999; } + + .col-lg-last { + order: 999; } } +/* Card component CSS variable definitions */ +:root { + --card-back-color: #f8f8f8; + --card-fore-color: #111; + --card-border-color: #ddd; } + +.card { + display: flex; + flex-direction: column; + justify-content: space-between; + align-self: center; + position: relative; + width: 100%; + background: var(--card-back-color); + color: var(--card-fore-color); + border: 0.0625rem solid var(--card-border-color); + border-radius: var(--universal-border-radius); + margin: var(--universal-margin); + overflow: hidden; } + @media screen and (min-width: 320px) { + .card { + max-width: 320px; } } + .card > .sectione { + background: var(--card-back-color); + color: var(--card-fore-color); + box-sizing: border-box; + margin: 0; + border: 0; + border-radius: 0; + border-bottom: 0.0625rem solid var(--card-border-color); + padding: var(--universal-padding); + width: 100%; } + .card > .sectione.media { + height: 200px; + padding: 0; + -o-object-fit: cover; + object-fit: cover; } + .card > .sectione:last-child { + border-bottom: 0; } + +/* + Custom elements for card elements. +*/ +@media screen and (min-width: 240px) { + .card.small { + max-width: 240px; } } +@media screen and (min-width: 480px) { + .card.large { + max-width: 480px; } } +.card.fluid { + max-width: 100%; + width: auto; } + +.card.warning { +/* --card-back-color: #ffca28; */ + --card-back-color: #e5b8b7; + --card-border-color: #e8b825; } + +.card.error { + --card-back-color: #b71c1c; + --card-fore-color: #f8f8f8; + --card-border-color: #a71a1a; } + +.card > .sectione.dark { + --card-back-color: #e0e0e0; } + +.card > .sectione.double-padded { + padding: calc(1.5 * var(--universal-padding)); } + +/* + Definitions for forms and input elements. +*/ +/* Input_control module CSS variable definitions */ +:root { + --form-back-color: #f0f0f0; + --form-fore-color: #111; + --form-border-color: #ddd; + --input-back-color: #f8f8f8; + --input-fore-color: #111; + --input-border-color: #ddd; + --input-focus-color: #0288d1; + --input-invalid-color: #d32f2f; + --button-back-color: #e2e2e2; + --button-hover-back-color: #dcdcdc; + --button-fore-color: #212121; + --button-border-color: transparent; + --button-hover-border-color: transparent; + --button-group-border-color: rgba(124, 124, 124, 0.54); } + +form { + background: var(--form-back-color); + color: var(--form-fore-color); + border: 0.0625rem solid var(--form-border-color); + border-radius: var(--universal-border-radius); + margin: var(--universal-margin); + padding: calc(2 * var(--universal-padding)) var(--universal-padding); } + +fieldset { + border: 0.0625rem solid var(--form-border-color); + border-radius: var(--universal-border-radius); + margin: calc(var(--universal-margin) / 4); + padding: var(--universal-padding); } + +legend { + box-sizing: border-box; + display: table; + max-width: 100%; + white-space: normal; + font-weight: 700; + padding: calc(var(--universal-padding) / 2); } + +label { + padding: calc(var(--universal-padding) / 2) var(--universal-padding); } + +.input-group { + display: inline-block; } + .input-group.fluid { + display: flex; + align-items: center; + justify-content: center; } + .input-group.fluid > input { + max-width: 100%; + flex-grow: 1; + flex-basis: 0px; } + @media screen and (max-width: 499px) { + .input-group.fluid { + align-items: stretch; + flex-direction: column; } } + .input-group.vertical { + display: flex; + align-items: stretch; + flex-direction: column; } + .input-group.vertical > input { + max-width: 100%; + flex-grow: 1; + flex-basis: 0px; } + +[type="number"]::-webkit-inner-spin-button, [type="number"]::-webkit-outer-spin-button { + height: auto; } + +[type="search"] { + -webkit-appearance: textfield; + outline-offset: -2px; } + +[type="search"]::-webkit-search-cancel-button, +[type="search"]::-webkit-search-decoration { + -webkit-appearance: none; } + +input:not([type]), [type="text"], [type="email"], [type="number"], [type="search"], +[type="password"], [type="url"], [type="tel"], [type="checkbox"], [type="radio"], textarea, select { + box-sizing: border-box; + background: var(--input-back-color); + color: var(--input-fore-color); + border: 0.0625rem solid var(--input-border-color); + border-radius: var(--universal-border-radius); + margin: calc(var(--universal-margin) / 2); + padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); } + +input:not([type="button"]):not([type="submit"]):not([type="reset"]):hover, input:not([type="button"]):not([type="submit"]):not([type="reset"]):focus, textarea:hover, textarea:focus, select:hover, select:focus { + border-color: var(--input-focus-color); + box-shadow: none; } +input:not([type="button"]):not([type="submit"]):not([type="reset"]):invalid, input:not([type="button"]):not([type="submit"]):not([type="reset"]):focus:invalid, textarea:invalid, textarea:focus:invalid, select:invalid, select:focus:invalid { + border-color: var(--input-invalid-color); + box-shadow: none; } +input:not([type="button"]):not([type="submit"]):not([type="reset"])[readonly], textarea[readonly], select[readonly] { + background: var(--secondary-back-color); } + +select { + max-width: 100%; } + +option { + overflow: hidden; + text-overflow: ellipsis; } + +[type="checkbox"], [type="radio"] { + -webkit-appearance: none; + -moz-appearance: none; + appearance: none; + position: relative; + height: calc(1rem + var(--universal-padding) / 2); + width: calc(1rem + var(--universal-padding) / 2); + vertical-align: text-bottom; + padding: 0; + flex-basis: calc(1rem + var(--universal-padding) / 2) !important; + flex-grow: 0 !important; } + [type="checkbox"]:checked:before, [type="radio"]:checked:before { + position: absolute; } + +[type="checkbox"]:checked:before { + content: '\2713'; + font-family: sans-serif; + font-size: calc(1rem + var(--universal-padding) / 2); + top: calc(0rem - var(--universal-padding)); + left: calc(var(--universal-padding) / 4); } + +[type="radio"] { + border-radius: 100%; } + [type="radio"]:checked:before { + border-radius: 100%; + content: ''; + top: calc(0.0625rem + var(--universal-padding) / 2); + left: calc(0.0625rem + var(--universal-padding) / 2); + background: var(--input-fore-color); + width: 0.5rem; + height: 0.5rem; } + +:placeholder-shown { + color: var(--input-fore-color); } + +::-ms-placeholder { + color: var(--input-fore-color); + opacity: 0.54; } + +button::-moz-focus-inner, [type="button"]::-moz-focus-inner, [type="reset"]::-moz-focus-inner, [type="submit"]::-moz-focus-inner { + border-style: none; + padding: 0; } + +button, html [type="button"], [type="reset"], [type="submit"] { + -webkit-appearance: button; } + +button { + overflow: visible; + text-transform: none; } + +button, [type="button"], [type="submit"], [type="reset"], +a.button, label.button, .button, +a[role="button"], label[role="button"], [role="button"] { + display: inline-block; + background: var(--button-back-color); + color: var(--button-fore-color); + border: 0.0625rem solid var(--button-border-color); + border-radius: var(--universal-border-radius); + padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); + margin: var(--universal-margin); + text-decoration: none; + cursor: pointer; + transition: background 0.3s; } + button:hover, button:focus, [type="button"]:hover, [type="button"]:focus, [type="submit"]:hover, [type="submit"]:focus, [type="reset"]:hover, [type="reset"]:focus, + a.button:hover, + a.button:focus, label.button:hover, label.button:focus, .button:hover, .button:focus, + a[role="button"]:hover, + a[role="button"]:focus, label[role="button"]:hover, label[role="button"]:focus, [role="button"]:hover, [role="button"]:focus { + background: var(--button-hover-back-color); + border-color: var(--button-hover-border-color); } + +input:disabled, input[disabled], textarea:disabled, textarea[disabled], select:disabled, select[disabled], button:disabled, button[disabled], .button:disabled, .button[disabled], [role="button"]:disabled, [role="button"][disabled] { + cursor: not-allowed; + opacity: 0.75; } + +.button-group { + display: flex; + border: 0.0625rem solid var(--button-group-border-color); + border-radius: var(--universal-border-radius); + margin: var(--universal-margin); } + .button-group > button, .button-group [type="button"], .button-group > [type="submit"], .button-group > [type="reset"], .button-group > .button, .button-group > [role="button"] { + margin: 0; + max-width: 100%; + flex: 1 1 auto; + text-align: center; + border: 0; + border-radius: 0; + box-shadow: none; } + .button-group > :not(:first-child) { + border-left: 0.0625rem solid var(--button-group-border-color); } + @media screen and (max-width: 499px) { + .button-group { + flex-direction: column; } + .button-group > :not(:first-child) { + border: 0; + border-top: 0.0625rem solid var(--button-group-border-color); } } + +/* + Custom elements for forms and input elements. +*/ +button.primary, [type="button"].primary, [type="submit"].primary, [type="reset"].primary, .button.primary, [role="button"].primary { + --button-back-color: #1976d2; + --button-fore-color: #f8f8f8; } + button.primary:hover, button.primary:focus, [type="button"].primary:hover, [type="button"].primary:focus, [type="submit"].primary:hover, [type="submit"].primary:focus, [type="reset"].primary:hover, [type="reset"].primary:focus, .button.primary:hover, .button.primary:focus, [role="button"].primary:hover, [role="button"].primary:focus { + --button-hover-back-color: #1565c0; } + +button.secondary, [type="button"].secondary, [type="submit"].secondary, [type="reset"].secondary, .button.secondary, [role="button"].secondary { + --button-back-color: #d32f2f; + --button-fore-color: #f8f8f8; } + button.secondary:hover, button.secondary:focus, [type="button"].secondary:hover, [type="button"].secondary:focus, [type="submit"].secondary:hover, [type="submit"].secondary:focus, [type="reset"].secondary:hover, [type="reset"].secondary:focus, .button.secondary:hover, .button.secondary:focus, [role="button"].secondary:hover, [role="button"].secondary:focus { + --button-hover-back-color: #c62828; } + +button.tertiary, [type="button"].tertiary, [type="submit"].tertiary, [type="reset"].tertiary, .button.tertiary, [role="button"].tertiary { + --button-back-color: #308732; + --button-fore-color: #f8f8f8; } + button.tertiary:hover, button.tertiary:focus, [type="button"].tertiary:hover, [type="button"].tertiary:focus, [type="submit"].tertiary:hover, [type="submit"].tertiary:focus, [type="reset"].tertiary:hover, [type="reset"].tertiary:focus, .button.tertiary:hover, .button.tertiary:focus, [role="button"].tertiary:hover, [role="button"].tertiary:focus { + --button-hover-back-color: #277529; } + +button.inverse, [type="button"].inverse, [type="submit"].inverse, [type="reset"].inverse, .button.inverse, [role="button"].inverse { + --button-back-color: #212121; + --button-fore-color: #f8f8f8; } + button.inverse:hover, button.inverse:focus, [type="button"].inverse:hover, [type="button"].inverse:focus, [type="submit"].inverse:hover, [type="submit"].inverse:focus, [type="reset"].inverse:hover, [type="reset"].inverse:focus, .button.inverse:hover, .button.inverse:focus, [role="button"].inverse:hover, [role="button"].inverse:focus { + --button-hover-back-color: #111; } + +button.small, [type="button"].small, [type="submit"].small, [type="reset"].small, .button.small, [role="button"].small { + padding: calc(0.5 * var(--universal-padding)) calc(0.75 * var(--universal-padding)); + margin: var(--universal-margin); } + +button.large, [type="button"].large, [type="submit"].large, [type="reset"].large, .button.large, [role="button"].large { + padding: calc(1.5 * var(--universal-padding)) calc(2 * var(--universal-padding)); + margin: var(--universal-margin); } + +/* + Definitions for navigation elements. +*/ +/* Navigation module CSS variable definitions */ +:root { + --header-back-color: #f8f8f8; + --header-hover-back-color: #f0f0f0; + --header-fore-color: #444; + --header-border-color: #ddd; + --nav-back-color: #f8f8f8; + --nav-hover-back-color: #f0f0f0; + --nav-fore-color: #444; + --nav-border-color: #ddd; + --nav-link-color: #0277bd; + --footer-fore-color: #444; + --footer-back-color: #f8f8f8; + --footer-border-color: #ddd; + --footer-link-color: #0277bd; + --drawer-back-color: #f8f8f8; + --drawer-hover-back-color: #f0f0f0; + --drawer-border-color: #ddd; + --drawer-close-color: #444; } + +header { + height: 3.1875rem; + background: var(--header-back-color); + color: var(--header-fore-color); + border-bottom: 0.0625rem solid var(--header-border-color); + padding: calc(var(--universal-padding) / 4) 0; + white-space: nowrap; + overflow-x: auto; + overflow-y: hidden; } + header.row { + box-sizing: content-box; } + header .logo { + color: var(--header-fore-color); + font-size: 1.75rem; + padding: var(--universal-padding) calc(2 * var(--universal-padding)); + text-decoration: none; } + header button, header [type="button"], header .button, header [role="button"] { + box-sizing: border-box; + position: relative; + top: calc(0rem - var(--universal-padding) / 4); + height: calc(3.1875rem + var(--universal-padding) / 2); + background: var(--header-back-color); + line-height: calc(3.1875rem - var(--universal-padding) * 1.5); + text-align: center; + color: var(--header-fore-color); + border: 0; + border-radius: 0; + margin: 0; + text-transform: uppercase; } + header button:hover, header button:focus, header [type="button"]:hover, header [type="button"]:focus, header .button:hover, header .button:focus, header [role="button"]:hover, header [role="button"]:focus { + background: var(--header-hover-back-color); } + +nav { + background: var(--nav-back-color); + color: var(--nav-fore-color); + border: 0.0625rem solid var(--nav-border-color); + border-radius: var(--universal-border-radius); + margin: var(--universal-margin); } + nav * { + padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); } + nav a, nav a:visited { + display: block; + color: var(--nav-link-color); + border-radius: var(--universal-border-radius); + transition: background 0.3s; } + nav a:hover, nav a:focus, nav a:visited:hover, nav a:visited:focus { + text-decoration: none; + background: var(--nav-hover-back-color); } + nav .sublink-1 { + position: relative; + margin-left: calc(2 * var(--universal-padding)); } + nav .sublink-1:before { + position: absolute; + left: calc(var(--universal-padding) - 1 * var(--universal-padding)); + top: -0.0625rem; + content: ''; + height: 100%; + border: 0.0625rem solid var(--nav-border-color); + border-left: 0; } + nav .sublink-2 { + position: relative; + margin-left: calc(4 * var(--universal-padding)); } + nav .sublink-2:before { + position: absolute; + left: calc(var(--universal-padding) - 3 * var(--universal-padding)); + top: -0.0625rem; + content: ''; + height: 100%; + border: 0.0625rem solid var(--nav-border-color); + border-left: 0; } + +footer { + background: var(--footer-back-color); + color: var(--footer-fore-color); + border-top: 0.0625rem solid var(--footer-border-color); + padding: calc(2 * var(--universal-padding)) var(--universal-padding); + font-size: 0.875rem; } + footer a, footer a:visited { + color: var(--footer-link-color); } + +header.sticky { + position: -webkit-sticky; + position: sticky; + z-index: 1101; + top: 0; } + +footer.sticky { + position: -webkit-sticky; + position: sticky; + z-index: 1101; + bottom: 0; } + +.drawer-toggle:before { + display: inline-block; + position: relative; + vertical-align: bottom; + content: '\00a0\2261\00a0'; + font-family: sans-serif; + font-size: 1.5em; } +@media screen and (min-width: 500px) { + .drawer-toggle:not(.persistent) { + display: none; } } + +[type="checkbox"].drawer { + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); } + [type="checkbox"].drawer + * { + display: block; + box-sizing: border-box; + position: fixed; + top: 0; + width: 320px; + height: 100vh; + overflow-y: auto; + background: var(--drawer-back-color); + border: 0.0625rem solid var(--drawer-border-color); + border-radius: 0; + margin: 0; + z-index: 1110; + right: -320px; + transition: right 0.3s; } + [type="checkbox"].drawer + * .drawer-close { + position: absolute; + top: var(--universal-margin); + right: var(--universal-margin); + z-index: 1111; + width: 2rem; + height: 2rem; + border-radius: var(--universal-border-radius); + padding: var(--universal-padding); + margin: 0; + cursor: pointer; + transition: background 0.3s; } + [type="checkbox"].drawer + * .drawer-close:before { + display: block; + content: '\00D7'; + color: var(--drawer-close-color); + position: relative; + font-family: sans-serif; + font-size: 2rem; + line-height: 1; + text-align: center; } + [type="checkbox"].drawer + * .drawer-close:hover, [type="checkbox"].drawer + * .drawer-close:focus { + background: var(--drawer-hover-back-color); } + @media screen and (max-width: 320px) { + [type="checkbox"].drawer + * { + width: 100%; } } + [type="checkbox"].drawer:checked + * { + right: 0; } + @media screen and (min-width: 500px) { + [type="checkbox"].drawer:not(.persistent) + * { + position: static; + height: 100%; + z-index: 1100; } + [type="checkbox"].drawer:not(.persistent) + * .drawer-close { + display: none; } } + +/* + Definitions for the responsive table component. +*/ +/* Table module CSS variable definitions. */ +:root { + --table-border-color: #aaa; + --table-border-separator-color: #666; + --table-head-back-color: #e6e6e6; + --table-head-fore-color: #111; + --table-body-back-color: #f8f8f8; + --table-body-fore-color: #111; + --table-body-alt-back-color: #eee; } + +table { + border-collapse: separate; + border-spacing: 0; + : margin: calc(1.5 * var(--universal-margin)) var(--universal-margin); + display: flex; + flex: 0 1 auto; + flex-flow: row wrap; + padding: var(--universal-padding); + padding-top: 0; + margin: calc(1.5 * var(--universal-margin)) var(--universal-margin); } + table caption { + font-size: 1.25 * rem; + margin: calc(2 * var(--universal-margin)) 0; + max-width: 100%; + flex: 0 0 100%; + text-align: left;} + table thead, table tbody { + display: flex; + flex-flow: row wrap; + border: 0.0625rem solid var(--table-border-color); } + table thead { + z-index: 999; + border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0; + border-bottom: 0.0625rem solid var(--table-border-separator-color); } + table tbody { + border-top: 0; + margin-top: calc(0 - var(--universal-margin)); + border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); } + table tr { + display: flex; + padding: 0; } + table th, table td { + padding: calc(0.5 * var(--universal-padding)); + font-size: 0.9rem; } + table th { + text-align: left; + background: var(--table-head-back-color); + color: var(--table-head-fore-color); } + table td { + background: var(--table-body-back-color); + color: var(--table-body-fore-color); + border-top: 0.0625rem solid var(--table-border-color); } + +table:not(.horizontal) { + overflow: auto; + max-height: 850px; } + table:not(.horizontal) thead, table:not(.horizontal) tbody { + max-width: 100%; + flex: 0 0 100%; } + table:not(.horizontal) tr { + flex-flow: row wrap; + flex: 0 0 100%; } + table:not(.horizontal) th, table:not(.horizontal) td { + flex: 1 0 0%; + overflow: hidden; + text-overflow: ellipsis; } + table:not(.horizontal) thead { + position: sticky; + top: 0; } + table:not(.horizontal) tbody tr:first-child td { + border-top: 0; } + +table.horizontal { + border: 0; } + table.horizontal thead, table.horizontal tbody { + border: 0; + flex-flow: row nowrap; } + table.horizontal tbody { + overflow: auto; + justify-content: space-between; + flex: 1 0 0; + margin-left: calc( 4 * var(--universal-margin)); + padding-bottom: calc(var(--universal-padding) / 4); } + table.horizontal tr { + flex-direction: column; + flex: 1 0 auto; } + table.horizontal th, table.horizontal td { + width: 100%; + border: 0; + border-bottom: 0.0625rem solid var(--table-border-color); } + table.horizontal th:not(:first-child), table.horizontal td:not(:first-child) { + border-top: 0; } + table.horizontal th { + text-align: right; + border-left: 0.0625rem solid var(--table-border-color); + border-right: 0.0625rem solid var(--table-border-separator-color); } + table.horizontal thead tr:first-child { + padding-left: 0; } + table.horizontal th:first-child, table.horizontal td:first-child { + border-top: 0.0625rem solid var(--table-border-color); } + table.horizontal tbody tr:last-child td { + border-right: 0.0625rem solid var(--table-border-color); } + table.horizontal tbody tr:last-child td:first-child { + border-top-right-radius: 0.25rem; } + table.horizontal tbody tr:last-child td:last-child { + border-bottom-right-radius: 0.25rem; } + table.horizontal thead tr:first-child th:first-child { + border-top-left-radius: 0.25rem; } + table.horizontal thead tr:first-child th:last-child { + border-bottom-left-radius: 0.25rem; } + +@media screen and (max-width: 499px) { + table, table.horizontal { + border-collapse: collapse; + border: 0; + width: 100%; + display: table; } + table thead, table th, table.horizontal thead, table.horizontal th { + border: 0; + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + padding: 0; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); } + table tbody, table.horizontal tbody { + border: 0; + display: table-row-group; } + table tr, table.horizontal tr { + display: block; + border: 0.0625rem solid var(--table-border-color); + border-radius: var(--universal-border-radius); + background: #fafafa; + padding: var(--universal-padding); + margin: var(--universal-margin); + margin-bottom: calc(2 * var(--universal-margin)); } + table th, table td, table.horizontal th, table.horizontal td { + width: auto; } + table td, table.horizontal td { + display: block; + border: 0; + text-align: right; } + table td:before, table.horizontal td:before { + content: attr(data-label); + float: left; + font-weight: 600; } + table th:first-child, table td:first-child, table.horizontal th:first-child, table.horizontal td:first-child { + border-top: 0; } + table tbody tr:last-child td, table.horizontal tbody tr:last-child td { + border-right: 0; } } +:root { + --table-body-alt-back-color: #eee; } + +table tr:nth-of-type(2n) > td { + background: var(--table-body-alt-back-color); } + +@media screen and (max-width: 500px) { + table tr:nth-of-type(2n) { + background: var(--table-body-alt-back-color); } } +:root { + --table-body-hover-back-color: #90caf9; } + +table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focus, table.hoverable tr:focus > td { + background: var(--table-body-hover-back-color); } + +@media screen and (max-width: 500px) { + table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focus, table.hoverable tr:focus > td { + background: var(--table-body-hover-back-color); } } +/* + Definitions for contextual background elements, toasts and tooltips. +*/ +/* Contextual module CSS variable definitions */ +:root { + --mark-back-color: #0277bd; + --mark-fore-color: #fafafa; } + +mark { + background: var(--mark-back-color); + color: var(--mark-fore-color); + font-size: 0.95em; + line-height: 1em; + border-radius: var(--universal-border-radius); + padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); } + mark.inline-block { + display: inline-block; + font-size: 1em; + line-height: 1.5; + padding: calc(var(--universal-padding) / 2) var(--universal-padding); } + +:root { + --toast-back-color: #424242; + --toast-fore-color: #fafafa; } + +.toast { + position: fixed; + bottom: calc(var(--universal-margin) * 3); + left: 50%; + transform: translate(-50%, -50%); + z-index: 1111; + color: var(--toast-fore-color); + background: var(--toast-back-color); + border-radius: calc(var(--universal-border-radius) * 16); + padding: var(--universal-padding) calc(var(--universal-padding) * 3); } + +:root { + --tooltip-back-color: #212121; + --tooltip-fore-color: #fafafa; } + +.tooltip { + position: relative; + display: inline-block; } + .tooltip:before, .tooltip:after { + position: absolute; + opacity: 0; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); + transition: all 0.3s; + z-index: 1010; + left: 50%; } + .tooltip:not(.bottom):before, .tooltip:not(.bottom):after { + bottom: 75%; } + .tooltip.bottom:before, .tooltip.bottom:after { + top: 75%; } + .tooltip:hover:before, .tooltip:hover:after, .tooltip:focus:before, .tooltip:focus:after { + opacity: 1; + clip: auto; + -webkit-clip-path: inset(0%); + clip-path: inset(0%); } + .tooltip:before { + content: ''; + background: transparent; + border: var(--universal-margin) solid transparent; + left: calc(50% - var(--universal-margin)); } + .tooltip:not(.bottom):before { + border-top-color: #212121; } + .tooltip.bottom:before { + border-bottom-color: #212121; } + .tooltip:after { + content: attr(aria-label); + color: var(--tooltip-fore-color); + background: var(--tooltip-back-color); + border-radius: var(--universal-border-radius); + padding: var(--universal-padding); + white-space: nowrap; + transform: translateX(-50%); } + .tooltip:not(.bottom):after { + margin-bottom: calc(2 * var(--universal-margin)); } + .tooltip.bottom:after { + margin-top: calc(2 * var(--universal-margin)); } + +:root { + --modal-overlay-color: rgba(0, 0, 0, 0.45); + --modal-close-color: #444; + --modal-close-hover-color: #f0f0f0; } + +[type="checkbox"].modal { + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); } + [type="checkbox"].modal + div { + position: fixed; + top: 0; + left: 0; + display: none; + width: 100vw; + height: 100vh; + background: var(--modal-overlay-color); } + [type="checkbox"].modal + div .card { + margin: 0 auto; + max-height: 50vh; + overflow: auto; } + [type="checkbox"].modal + div .card .modal-close { + position: absolute; + top: 0; + right: 0; + width: 1.75rem; + height: 1.75rem; + border-radius: var(--universal-border-radius); + padding: var(--universal-padding); + margin: 0; + cursor: pointer; + transition: background 0.3s; } + [type="checkbox"].modal + div .card .modal-close:before { + display: block; + content: '\00D7'; + color: var(--modal-close-color); + position: relative; + font-family: sans-serif; + font-size: 1.75rem; + line-height: 1; + text-align: center; } + [type="checkbox"].modal + div .card .modal-close:hover, [type="checkbox"].modal + div .card .modal-close:focus { + background: var(--modal-close-hover-color); } + [type="checkbox"].modal:checked + div { + display: flex; + flex: 0 1 auto; + z-index: 1200; } + [type="checkbox"].modal:checked + div .card .modal-close { + z-index: 1211; } + +:root { + --collapse-label-back-color: #e8e8e8; + --collapse-label-fore-color: #212121; + --collapse-label-hover-back-color: #f0f0f0; + --collapse-selected-label-back-color: #ececec; + --collapse-border-color: #ddd; + --collapse-content-back-color: #fafafa; + --collapse-selected-label-border-color: #0277bd; } + +.collapse { + width: calc(100% - 2 * var(--universal-margin)); + opacity: 1; + display: flex; + flex-direction: column; + margin: var(--universal-margin); + border-radius: var(--universal-border-radius); } + .collapse > [type="radio"], .collapse > [type="checkbox"] { + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); } + .collapse > label { + flex-grow: 1; + display: inline-block; + height: 1.5rem; + cursor: pointer; + transition: background 0.3s; + color: var(--collapse-label-fore-color); + background: var(--collapse-label-back-color); + border: 0.0625rem solid var(--collapse-border-color); + padding: calc(1.5 * var(--universal-padding)); } + .collapse > label:hover, .collapse > label:focus { + background: var(--collapse-label-hover-back-color); } + .collapse > label + div { + flex-basis: auto; + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); + transition: max-height 0.3s; + max-height: 1px; } + .collapse > :checked + label { + background: var(--collapse-selected-label-back-color); + border-bottom-color: var(--collapse-selected-label-border-color); } + .collapse > :checked + label + div { + box-sizing: border-box; + position: relative; + width: 100%; + height: auto; + overflow: auto; + margin: 0; + background: var(--collapse-content-back-color); + border: 0.0625rem solid var(--collapse-border-color); + border-top: 0; + padding: var(--universal-padding); + clip: auto; + -webkit-clip-path: inset(0%); + clip-path: inset(0%); + max-height: 850px; } + .collapse > label:not(:first-of-type) { + border-top: 0; } + .collapse > label:first-of-type { + border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0; } + .collapse > label:last-of-type:not(:first-of-type) { + border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); } + .collapse > label:last-of-type:first-of-type { + border-radius: var(--universal-border-radius); } + .collapse > :checked:last-of-type:not(:first-of-type) + label { + border-radius: 0; } + .collapse > :checked:last-of-type + label + div { + border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); } + +/* + Custom elements for contextual background elements, toasts and tooltips. +*/ +mark.secondary { + --mark-back-color: #d32f2f; } + +mark.tertiary { + --mark-back-color: #308732; } + +mark.tag { + padding: calc(var(--universal-padding)/2) var(--universal-padding); + border-radius: 1em; } + +/* + Definitions for progress elements and spinners. +*/ +/* Progess module CSS variable definitions */ +:root { + --progress-back-color: #ddd; + --progress-fore-color: #555; } + +progress { + display: block; + vertical-align: baseline; + -webkit-appearance: none; + -moz-appearance: none; + appearance: none; + height: 0.75rem; + width: calc(100% - 2 * var(--universal-margin)); + margin: var(--universal-margin); + border: 0; + border-radius: calc(2 * var(--universal-border-radius)); + background: var(--progress-back-color); + color: var(--progress-fore-color); } + progress::-webkit-progress-value { + background: var(--progress-fore-color); + border-top-left-radius: calc(2 * var(--universal-border-radius)); + border-bottom-left-radius: calc(2 * var(--universal-border-radius)); } + progress::-webkit-progress-bar { + background: var(--progress-back-color); } + progress::-moz-progress-bar { + background: var(--progress-fore-color); + border-top-left-radius: calc(2 * var(--universal-border-radius)); + border-bottom-left-radius: calc(2 * var(--universal-border-radius)); } + progress[value="1000"]::-webkit-progress-value { + border-radius: calc(2 * var(--universal-border-radius)); } + progress[value="1000"]::-moz-progress-bar { + border-radius: calc(2 * var(--universal-border-radius)); } + progress.inline { + display: inline-block; + vertical-align: middle; + width: 60%; } + +:root { + --spinner-back-color: #ddd; + --spinner-fore-color: #555; } + +@keyframes spinner-donut-anim { + 0% { + transform: rotate(0deg); } + 100% { + transform: rotate(360deg); } } +.spinner { + display: inline-block; + margin: var(--universal-margin); + border: 0.25rem solid var(--spinner-back-color); + border-left: 0.25rem solid var(--spinner-fore-color); + border-radius: 50%; + width: 1.25rem; + height: 1.25rem; + animation: spinner-donut-anim 1.2s linear infinite; } + +/* + Custom elements for progress bars and spinners. +*/ +progress.primary { + --progress-fore-color: #1976d2; } + +progress.secondary { + --progress-fore-color: #d32f2f; } + +progress.tertiary { + --progress-fore-color: #308732; } + +.spinner.primary { + --spinner-fore-color: #1976d2; } + +.spinner.secondary { + --spinner-fore-color: #d32f2f; } + +.spinner.tertiary { + --spinner-fore-color: #308732; } + +/* + Definitions for icons - powered by Feather (https://feathericons.com/). +*/ +span[class^='icon-'] { + display: inline-block; + height: 1em; + width: 1em; + vertical-align: -0.125em; + background-size: contain; + margin: 0 calc(var(--universal-margin) / 4); } + span[class^='icon-'].secondary { + -webkit-filter: invert(25%); + filter: invert(25%); } + span[class^='icon-'].inverse { + -webkit-filter: invert(100%); + filter: invert(100%); } + +span.icon-alert { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='8' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='16' x2='12' y2='16'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-bookmark { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M19 21l-7-5-7 5V5a2 2 0 0 1 2-2h10a2 2 0 0 1 2 2z'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-calendar { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='4' width='18' height='18' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='16' y1='2' x2='16' y2='6'%3E%3C/line%3E%3Cline x1='8' y1='2' x2='8' y2='6'%3E%3C/line%3E%3Cline x1='3' y1='10' x2='21' y2='10'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-credit { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='1' y='4' width='22' height='16' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='1' y1='10' x2='23' y2='10'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-edit { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 14.66V20a2 2 0 0 1-2 2H4a2 2 0 0 1-2-2V6a2 2 0 0 1 2-2h5.34'%3E%3C/path%3E%3Cpolygon points='18 2 22 6 12 16 8 16 8 12 18 2'%3E%3C/polygon%3E%3C/svg%3E"); } +span.icon-link { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M18 13v6a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2V8a2 2 0 0 1 2-2h6'%3E%3C/path%3E%3Cpolyline points='15 3 21 3 21 9'%3E%3C/polyline%3E%3Cline x1='10' y1='14' x2='21' y2='3'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-help { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M9.09 9a3 3 0 0 1 5.83 1c0 2-3 3-3 3'%3E%3C/path%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='17' x2='12' y2='17'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-home { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M3 9l9-7 9 7v11a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2z'%3E%3C/path%3E%3Cpolyline points='9 22 9 12 15 12 15 22'%3E%3C/polyline%3E%3C/svg%3E"); } +span.icon-info { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='16' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='8' x2='12' y2='8'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-lock { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='11' width='18' height='11' rx='2' ry='2'%3E%3C/rect%3E%3Cpath d='M7 11V7a5 5 0 0 1 10 0v4'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-mail { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 4h16c1.1 0 2 .9 2 2v12c0 1.1-.9 2-2 2H4c-1.1 0-2-.9-2-2V6c0-1.1.9-2 2-2z'%3E%3C/path%3E%3Cpolyline points='22,6 12,13 2,6'%3E%3C/polyline%3E%3C/svg%3E"); } +span.icon-location { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 10c0 7-9 13-9 13s-9-6-9-13a9 9 0 0 1 18 0z'%3E%3C/path%3E%3Ccircle cx='12' cy='10' r='3'%3E%3C/circle%3E%3C/svg%3E"); } +span.icon-phone { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M22 16.92v3a2 2 0 0 1-2.18 2 19.79 19.79 0 0 1-8.63-3.07 19.5 19.5 0 0 1-6-6 19.79 19.79 0 0 1-3.07-8.67A2 2 0 0 1 4.11 2h3a2 2 0 0 1 2 1.72 12.84 12.84 0 0 0 .7 2.81 2 2 0 0 1-.45 2.11L8.09 9.91a16 16 0 0 0 6 6l1.27-1.27a2 2 0 0 1 2.11-.45 12.84 12.84 0 0 0 2.81.7A2 2 0 0 1 22 16.92z'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-rss { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 11a9 9 0 0 1 9 9'%3E%3C/path%3E%3Cpath d='M4 4a16 16 0 0 1 16 16'%3E%3C/path%3E%3Ccircle cx='5' cy='19' r='1'%3E%3C/circle%3E%3C/svg%3E"); } +span.icon-search { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='11' cy='11' r='8'%3E%3C/circle%3E%3Cline x1='21' y1='21' x2='16.65' y2='16.65'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-settings { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='3'%3E%3C/circle%3E%3Cpath d='M19.4 15a1.65 1.65 0 0 0 .33 1.82l.06.06a2 2 0 0 1 0 2.83 2 2 0 0 1-2.83 0l-.06-.06a1.65 1.65 0 0 0-1.82-.33 1.65 1.65 0 0 0-1 1.51V21a2 2 0 0 1-2 2 2 2 0 0 1-2-2v-.09A1.65 1.65 0 0 0 9 19.4a1.65 1.65 0 0 0-1.82.33l-.06.06a2 2 0 0 1-2.83 0 2 2 0 0 1 0-2.83l.06-.06a1.65 1.65 0 0 0 .33-1.82 1.65 1.65 0 0 0-1.51-1H3a2 2 0 0 1-2-2 2 2 0 0 1 2-2h.09A1.65 1.65 0 0 0 4.6 9a1.65 1.65 0 0 0-.33-1.82l-.06-.06a2 2 0 0 1 0-2.83 2 2 0 0 1 2.83 0l.06.06a1.65 1.65 0 0 0 1.82.33H9a1.65 1.65 0 0 0 1-1.51V3a2 2 0 0 1 2-2 2 2 0 0 1 2 2v.09a1.65 1.65 0 0 0 1 1.51 1.65 1.65 0 0 0 1.82-.33l.06-.06a2 2 0 0 1 2.83 0 2 2 0 0 1 0 2.83l-.06.06a1.65 1.65 0 0 0-.33 1.82V9a1.65 1.65 0 0 0 1.51 1H21a2 2 0 0 1 2 2 2 2 0 0 1-2 2h-.09a1.65 1.65 0 0 0-1.51 1z'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-share { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='18' cy='5' r='3'%3E%3C/circle%3E%3Ccircle cx='6' cy='12' r='3'%3E%3C/circle%3E%3Ccircle cx='18' cy='19' r='3'%3E%3C/circle%3E%3Cline x1='8.59' y1='13.51' x2='15.42' y2='17.49'%3E%3C/line%3E%3Cline x1='15.41' y1='6.51' x2='8.59' y2='10.49'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-cart { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='9' cy='21' r='1'%3E%3C/circle%3E%3Ccircle cx='20' cy='21' r='1'%3E%3C/circle%3E%3Cpath d='M1 1h4l2.68 13.39a2 2 0 0 0 2 1.61h9.72a2 2 0 0 0 2-1.61L23 6H6'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-upload { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 15v4a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2v-4'%3E%3C/path%3E%3Cpolyline points='17 8 12 3 7 8'%3E%3C/polyline%3E%3Cline x1='12' y1='3' x2='12' y2='15'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-user { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 21v-2a4 4 0 0 0-4-4H8a4 4 0 0 0-4 4v2'%3E%3C/path%3E%3Ccircle cx='12' cy='7' r='4'%3E%3C/circle%3E%3C/svg%3E"); } + +/* + Definitions for utilities and helper classes. +*/ +/* Utility module CSS variable definitions */ +:root { + --generic-border-color: rgba(0, 0, 0, 0.3); + --generic-box-shadow: 0 0.25rem 0.25rem 0 rgba(0, 0, 0, 0.125), 0 0.125rem 0.125rem -0.125rem rgba(0, 0, 0, 0.25); } + +.hidden { + display: none !important; } + +.visually-hidden { + position: absolute !important; + width: 1px !important; + height: 1px !important; + margin: -1px !important; + border: 0 !important; + padding: 0 !important; + clip: rect(0 0 0 0) !important; + -webkit-clip-path: inset(100%) !important; + clip-path: inset(100%) !important; + overflow: hidden !important; } + +.bordered { + border: 0.0625rem solid var(--generic-border-color) !important; } + +.rounded { + border-radius: var(--universal-border-radius) !important; } + +.circular { + border-radius: 50% !important; } + +.shadowed { + box-shadow: var(--generic-box-shadow) !important; } + +.responsive-margin { + margin: calc(var(--universal-margin) / 4) !important; } + @media screen and (min-width: 500px) { + .responsive-margin { + margin: calc(var(--universal-margin) / 2) !important; } } + @media screen and (min-width: 1280px) { + .responsive-margin { + margin: var(--universal-margin) !important; } } + +.responsive-padding { + padding: calc(var(--universal-padding) / 4) !important; } + @media screen and (min-width: 500px) { + .responsive-padding { + padding: calc(var(--universal-padding) / 2) !important; } } + @media screen and (min-width: 1280px) { + .responsive-padding { + padding: var(--universal-padding) !important; } } + +@media screen and (max-width: 499px) { + .hidden-sm { + display: none !important; } } +@media screen and (min-width: 500px) and (max-width: 1279px) { + .hidden-md { + display: none !important; } } +@media screen and (min-width: 1280px) { + .hidden-lg { + display: none !important; } } +@media screen and (max-width: 499px) { + .visually-hidden-sm { + position: absolute !important; + width: 1px !important; + height: 1px !important; + margin: -1px !important; + border: 0 !important; + padding: 0 !important; + clip: rect(0 0 0 0) !important; + -webkit-clip-path: inset(100%) !important; + clip-path: inset(100%) !important; + overflow: hidden !important; } } +@media screen and (min-width: 500px) and (max-width: 1279px) { + .visually-hidden-md { + position: absolute !important; + width: 1px !important; + height: 1px !important; + margin: -1px !important; + border: 0 !important; + padding: 0 !important; + clip: rect(0 0 0 0) !important; + -webkit-clip-path: inset(100%) !important; + clip-path: inset(100%) !important; + overflow: hidden !important; } } +@media screen and (min-width: 1280px) { + .visually-hidden-lg { + position: absolute !important; + width: 1px !important; + height: 1px !important; + margin: -1px !important; + border: 0 !important; + padding: 0 !important; + clip: rect(0 0 0 0) !important; + -webkit-clip-path: inset(100%) !important; + clip-path: inset(100%) !important; + overflow: hidden !important; } } + +/*# sourceMappingURL=mini-default.css.map */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32F7xx/_htmresc/st_logo.png b/system/Drivers/CMSIS/Device/ST/STM32F7xx/_htmresc/st_logo.png new file mode 100644 index 0000000000..8b80057fd3 Binary files /dev/null and b/system/Drivers/CMSIS/Device/ST/STM32F7xx/_htmresc/st_logo.png differ diff --git a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md index 4a1fb5935c..2c474f654d 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md +++ b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md @@ -4,8 +4,8 @@ * STM32F1: 4.3.1 * STM32F2: 2.2.3 * STM32F3: 2.3.4 - * STM32F4: 2.6.4 - * STM32F7: 1.2.4 + * STM32F4: 2.6.5 + * STM32F7: 1.2.5 * STM32G0: 1.3.0 * STM32G4: 1.1.1 * STM32H7: 1.8.0 diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h index f085e2db35..90767ed33b 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -241,7 +241,7 @@ #define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL #endif -#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32H7) || defined(STM32F4) +#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) #define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID #define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID #endif @@ -955,7 +955,7 @@ #define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 #define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 -#if defined(STM32L1) || defined(STM32L4) || defined(STM32H7) +#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) #define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID #define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID #endif @@ -1531,18 +1531,18 @@ #define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) -#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32G4) +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) #define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT #define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT #define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT #define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT -#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32G4 */ -#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32G4) +#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 */ +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) #define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA #define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA #define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA #define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA -#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32G4 */ +#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 */ #if defined(STM32F4) #define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT @@ -3245,7 +3245,7 @@ #if defined(STM32L4) #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE -#elif defined(STM32WB) || defined(STM32G0) || defined(STM32G4) +#elif defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) #else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK #endif @@ -3373,7 +3373,7 @@ /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose * @{ */ -#if defined (STM32G0) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32G4) +#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) #else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #endif @@ -3496,7 +3496,7 @@ #define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef #endif -#if defined(STM32H7) +#if defined(STM32H7) || defined(STM32L5) #define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback #define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback #define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback @@ -3751,9 +3751,9 @@ /** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose * @{ */ -#if defined (STM32L4) +#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) #define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE -#endif +#endif /* STM32L4 || STM32F4 || STM32F7 */ /** * @} */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cryp.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cryp.h index 835a8aec6f..a67d936bcb 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cryp.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cryp.h @@ -22,7 +22,7 @@ #define __STM32F4xx_HAL_CRYP_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif @@ -53,20 +53,23 @@ typedef struct This parameter can be a value of @ref CRYP_Data_Type */ uint32_t KeySize; /*!< Used only in AES mode : 128, 192 or 256 bit key length in CRYP1. 128 or 256 bit key length in TinyAES This parameter can be a value of @ref CRYP_Key_Size */ - uint32_t* pKey; /*!< The key used for encryption/decryption */ - uint32_t* pInitVect; /*!< The initialization vector used also as initialization + uint32_t *pKey; /*!< The key used for encryption/decryption */ + uint32_t *pInitVect; /*!< The initialization vector used also as initialization counter in CTR mode */ uint32_t Algorithm; /*!< DES/ TDES Algorithm ECB/CBC AES Algorithm ECB/CBC/CTR/GCM or CCM This parameter can be a value of @ref CRYP_Algorithm_Mode */ - uint32_t* Header; /*!< used only in AES GCM and CCM Algorithm for authentication, + uint32_t *Header; /*!< used only in AES GCM and CCM Algorithm for authentication, GCM : also known as Additional Authentication Data CCM : named B1 composed of the associated data length and Associated Data. */ uint32_t HeaderSize; /*!< The size of header buffer in word */ - uint32_t* B0; /*!< B0 is first authentication block used only in AES CCM mode */ + uint32_t *B0; /*!< B0 is first authentication block used only in AES CCM mode */ uint32_t DataWidthUnit; /*!< Data With Unit, this parameter can be value of @ref CRYP_Data_Width_Unit*/ + uint32_t KeyIVConfigSkip; /*!< CRYP peripheral Key and IV configuration skip, to config Key and Initialization + Vector only once and to skip configuration for consecutive processings. + This parameter can be a value of @ref CRYP_Configuration_Skip */ -}CRYP_ConfigTypeDef; +} CRYP_ConfigTypeDef; /** @@ -78,7 +81,7 @@ typedef enum HAL_CRYP_STATE_RESET = 0x00U, /*!< CRYP not yet initialized or disabled */ HAL_CRYP_STATE_READY = 0x01U, /*!< CRYP initialized and ready for use */ HAL_CRYP_STATE_BUSY = 0x02U /*!< CRYP BUSY, internal processing is ongoing */ -}HAL_CRYP_STATETypeDef; +} HAL_CRYP_STATETypeDef; /** @@ -88,50 +91,57 @@ typedef enum typedef struct __CRYP_HandleTypeDef { #if defined (CRYP) - CRYP_TypeDef *Instance; /*!< CRYP registers base address */ + CRYP_TypeDef *Instance; /*!< CRYP registers base address */ #else /* AES*/ - AES_TypeDef *Instance; /*!< AES Register base address */ + AES_TypeDef *Instance; /*!< AES Register base address */ #endif /* End AES or CRYP */ - CRYP_ConfigTypeDef Init; /*!< CRYP required parameters */ + CRYP_ConfigTypeDef Init; /*!< CRYP required parameters */ - FunctionalState AutoKeyDerivation; /*!< Used only in TinyAES to allows to bypass or not key write-up before decryption. + FunctionalState AutoKeyDerivation; /*!< Used only in TinyAES to allows to bypass or not key write-up before decryption. This parameter can be a value of ENABLE/DISABLE */ - uint32_t *pCrypInBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */ + uint32_t *pCrypInBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */ - uint32_t *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */ + uint32_t *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */ - __IO uint16_t CrypHeaderCount; /*!< Counter of header data */ + __IO uint16_t CrypHeaderCount; /*!< Counter of header data */ - __IO uint16_t CrypInCount; /*!< Counter of input data */ + __IO uint16_t CrypInCount; /*!< Counter of input data */ - __IO uint16_t CrypOutCount; /*!< Counter of output data */ + __IO uint16_t CrypOutCount; /*!< Counter of output data */ - uint16_t Size; /*!< length of input data in word */ + uint16_t Size; /*!< length of input data in word */ - uint32_t Phase; /*!< CRYP peripheral phase */ + uint32_t Phase; /*!< CRYP peripheral phase */ - DMA_HandleTypeDef *hdmain; /*!< CRYP In DMA handle parameters */ + DMA_HandleTypeDef *hdmain; /*!< CRYP In DMA handle parameters */ - DMA_HandleTypeDef *hdmaout; /*!< CRYP Out DMA handle parameters */ + DMA_HandleTypeDef *hdmaout; /*!< CRYP Out DMA handle parameters */ - HAL_LockTypeDef Lock; /*!< CRYP locking object */ + HAL_LockTypeDef Lock; /*!< CRYP locking object */ - __IO HAL_CRYP_STATETypeDef State; /*!< CRYP peripheral state */ + __IO HAL_CRYP_STATETypeDef State; /*!< CRYP peripheral state */ - __IO uint32_t ErrorCode; /*!< CRYP peripheral error code */ + __IO uint32_t ErrorCode; /*!< CRYP peripheral error code */ + + uint32_t KeyIVConfig; /*!< CRYP peripheral Key and IV configuration flag, used when + configuration can be skipped */ + + uint32_t SizesSum; /*!< Sum of successive payloads lengths (in bytes), stored + for a single signature computation after several + messages processing */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) - void (*InCpltCallback) (struct __CRYP_HandleTypeDef * hcryp); /*!< CRYP Input FIFO transfer completed callback */ - void (*OutCpltCallback) (struct __CRYP_HandleTypeDef * hcryp); /*!< CRYP Output FIFO transfer completed callback */ - void (*ErrorCallback) (struct __CRYP_HandleTypeDef * hcryp); /*!< CRYP Error callback */ + void (*InCpltCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Input FIFO transfer completed callback */ + void (*OutCpltCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Output FIFO transfer completed callback */ + void (*ErrorCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Error callback */ - void (* MspInitCallback) (struct __CRYP_HandleTypeDef * hcryp); /*!< CRYP Msp Init callback */ - void (* MspDeInitCallback)(struct __CRYP_HandleTypeDef * hcryp); /*!< CRYP Msp DeInit callback */ + void (* MspInitCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Msp Init callback */ + void (* MspDeInitCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Msp DeInit callback */ #endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */ -}CRYP_HandleTypeDef; +} CRYP_HandleTypeDef; /** @@ -152,7 +162,7 @@ typedef enum HAL_CRYP_MSPINIT_CB_ID = 0x04U, /*!< CRYP MspInit callback ID */ HAL_CRYP_MSPDEINIT_CB_ID = 0x05U /*!< CRYP MspDeInit callback ID */ -}HAL_CRYP_CallbackIDTypeDef; +} HAL_CRYP_CallbackIDTypeDef; /** * @} */ @@ -162,7 +172,7 @@ typedef enum * @{ */ -typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef * hcryp); /*!< pointer to a common CRYP callback function */ +typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp); /*!< pointer to a common CRYP callback function */ /** * @} @@ -309,6 +319,17 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef * hcryp); /*!< point #define CRYP_ERR_CLEAR AES_CR_ERRC /*!< Error Flag Clear */ #endif /* End AES or CRYP */ +/** + * @} + */ + +/** @defgroup CRYP_Configuration_Skip CRYP Key and IV Configuration Skip Mode + * @{ + */ + +#define CRYP_KEYIVCONFIG_ALWAYS 0x00000000U /*!< Peripheral Key and IV configuration to do systematically */ +#define CRYP_KEYIVCONFIG_ONCE 0x00000001U /*!< Peripheral Key and IV configuration to do only once */ + /** * @} */ @@ -366,12 +387,12 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef * hcryp); /*!< point * @arg CRYP_FLAG_OFNE: Output FIFO is not empty * @arg CRYP_FLAG_OFFU: Output FIFO is full * @arg CRYP_FLAG_OUTRIS: Input FIFO service raw interrupt is pending - * @retval The state of __FLAG__ (TRUE or FALSE). + * @retval The state of __FLAG__ (TRUE or FALSE). */ #define CRYP_FLAG_MASK 0x0000001FU #if defined(CRYP) #define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 24)) == 0x01U)?((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)): \ - ((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK))) + ((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK))) #else /* AES*/ #define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) #endif /* End AES or CRYP */ @@ -398,7 +419,8 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef * hcryp); /*!< point * @retval State of interruption (TRUE or FALSE). */ -#define __HAL_CRYP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__)) +#define __HAL_CRYP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR\ + & (__INTERRUPT__)) == (__INTERRUPT__)) #endif /* AES */ @@ -415,7 +437,8 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef * hcryp); /*!< point * @retval The state of __INTERRUPT__ (TRUE or FALSE). */ #if defined(CRYP) -#define __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->MISR & (__INTERRUPT__)) == (__INTERRUPT__)) +#define __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->MISR\ + & (__INTERRUPT__)) == (__INTERRUPT__)) #else /* AES*/ #define __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__)) #endif /* End AES or CRYP */ @@ -475,10 +498,11 @@ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp); HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp); void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp); void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp); -HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf ); -HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf ); +HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf); +HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf); #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID, pCRYP_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID, + pCRYP_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ /** @@ -490,8 +514,10 @@ HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRY */ /* encryption/decryption ***********************************/ -HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout); -HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout); +HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, + uint32_t Timeout); +HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, + uint32_t Timeout); HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output); HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output); HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output); @@ -532,32 +558,32 @@ uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp); #if defined(CRYP) #if defined (CRYP_CR_ALGOMODE_AES_GCM) #define IS_CRYP_ALGORITHM(ALGORITHM) (((ALGORITHM) == CRYP_DES_ECB) || \ - ((ALGORITHM) == CRYP_DES_CBC) || \ - ((ALGORITHM) == CRYP_TDES_ECB) || \ - ((ALGORITHM) == CRYP_TDES_CBC) || \ - ((ALGORITHM) == CRYP_AES_ECB) || \ - ((ALGORITHM) == CRYP_AES_CBC) || \ - ((ALGORITHM) == CRYP_AES_CTR) || \ - ((ALGORITHM) == CRYP_AES_GCM) || \ - ((ALGORITHM) == CRYP_AES_CCM)) + ((ALGORITHM) == CRYP_DES_CBC) || \ + ((ALGORITHM) == CRYP_TDES_ECB) || \ + ((ALGORITHM) == CRYP_TDES_CBC) || \ + ((ALGORITHM) == CRYP_AES_ECB) || \ + ((ALGORITHM) == CRYP_AES_CBC) || \ + ((ALGORITHM) == CRYP_AES_CTR) || \ + ((ALGORITHM) == CRYP_AES_GCM) || \ + ((ALGORITHM) == CRYP_AES_CCM)) #else /*NO GCM CCM */ #define IS_CRYP_ALGORITHM(ALGORITHM) (((ALGORITHM) == CRYP_DES_ECB) || \ - ((ALGORITHM) == CRYP_DES_CBC) || \ - ((ALGORITHM) == CRYP_TDES_ECB) || \ - ((ALGORITHM) == CRYP_TDES_CBC) || \ - ((ALGORITHM) == CRYP_AES_ECB) || \ - ((ALGORITHM) == CRYP_AES_CBC) || \ - ((ALGORITHM) == CRYP_AES_CTR)) + ((ALGORITHM) == CRYP_DES_CBC) || \ + ((ALGORITHM) == CRYP_TDES_ECB) || \ + ((ALGORITHM) == CRYP_TDES_CBC) || \ + ((ALGORITHM) == CRYP_AES_ECB) || \ + ((ALGORITHM) == CRYP_AES_CBC) || \ + ((ALGORITHM) == CRYP_AES_CTR)) #endif /* GCM CCM defined*/ #define IS_CRYP_KEYSIZE(KEYSIZE)(((KEYSIZE) == CRYP_KEYSIZE_128B) || \ ((KEYSIZE) == CRYP_KEYSIZE_192B) || \ ((KEYSIZE) == CRYP_KEYSIZE_256B)) #else /* AES*/ #define IS_CRYP_ALGORITHM(ALGORITHM) (((ALGORITHM) == CRYP_AES_ECB) || \ - ((ALGORITHM) == CRYP_AES_CBC) || \ - ((ALGORITHM) == CRYP_AES_CTR) || \ - ((ALGORITHM) == CRYP_AES_GCM_GMAC)|| \ - ((ALGORITHM) == CRYP_AES_CCM)) + ((ALGORITHM) == CRYP_AES_CBC) || \ + ((ALGORITHM) == CRYP_AES_CTR) || \ + ((ALGORITHM) == CRYP_AES_GCM_GMAC)|| \ + ((ALGORITHM) == CRYP_AES_CCM)) #define IS_CRYP_KEYSIZE(KEYSIZE)(((KEYSIZE) == CRYP_KEYSIZE_128B) || \ @@ -569,6 +595,8 @@ uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp); ((DATATYPE) == CRYP_DATATYPE_8B) || \ ((DATATYPE) == CRYP_DATATYPE_1B)) +#define IS_CRYP_INIT(CONFIG)(((CONFIG) == CRYP_KEYIVCONFIG_ALWAYS) || \ + ((CONFIG) == CRYP_KEYIVCONFIG_ONCE)) /** * @} */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cryp_ex.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cryp_ex.h index 8f9fc9ddae..251e94b1da 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cryp_ex.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cryp_ex.h @@ -22,7 +22,7 @@ #define __STM32F4xx_HAL_CRYP_EX_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -84,9 +84,9 @@ * @{ */ - /** +/** * @} - */ + */ /* Private functions ---------------------------------------------------------*/ /** @defgroup CRYPEx_Private_Functions CRYPEx Private Functions diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h index 8bb516cf2f..ff74222eb6 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h @@ -253,9 +253,7 @@ typedef struct #define IS_EXTI_TRIGGER(__LINE__) (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u) -#define IS_EXTI_PENDING_EDGE(__LINE__) (((__LINE__) == EXTI_TRIGGER_FALLING) || \ - ((__LINE__) == EXTI_TRIGGER_RISING) || \ - ((__LINE__) == EXTI_TRIGGER_RISING_FALLING)) +#define IS_EXTI_PENDING_EDGE(__LINE__) ((__LINE__) == EXTI_TRIGGER_RISING_FALLING) #define IS_EXTI_CONFIG_LINE(__LINE__) (((__LINE__) & EXTI_CONFIG) != 0x00u) diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpsmbus.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpsmbus.h new file mode 100644 index 0000000000..04531d920d --- /dev/null +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpsmbus.h @@ -0,0 +1,745 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_fmpsmbus.h + * @author MCD Application Team + * @brief Header file of FMPSMBUS HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F4xx_HAL_FMPSMBUS_H +#define STM32F4xx_HAL_FMPSMBUS_H + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(FMPI2C_CR1_PE) +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup FMPSMBUS + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup FMPSMBUS_Exported_Types FMPSMBUS Exported Types + * @{ + */ + +/** @defgroup FMPSMBUS_Configuration_Structure_definition FMPSMBUS Configuration Structure definition + * @brief FMPSMBUS Configuration Structure definition + * @{ + */ +typedef struct +{ + uint32_t Timing; /*!< Specifies the FMPSMBUS_TIMINGR_register value. + This parameter calculated by referring to FMPSMBUS initialization + section in Reference manual */ + uint32_t AnalogFilter; /*!< Specifies if Analog Filter is enable or not. + This parameter can be a value of @ref FMPSMBUS_Analog_Filter */ + + uint32_t OwnAddress1; /*!< Specifies the first device own address. + This parameter can be a 7-bit or 10-bit address. */ + + uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode for master is selected. + This parameter can be a value of @ref FMPSMBUS_addressing_mode */ + + uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. + This parameter can be a value of @ref FMPSMBUS_dual_addressing_mode */ + + uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected + This parameter can be a 7-bit address. */ + + uint32_t OwnAddress2Masks; /*!< Specifies the acknoledge mask address second device own address if dual addressing mode is selected + This parameter can be a value of @ref FMPSMBUS_own_address2_masks. */ + + uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. + This parameter can be a value of @ref FMPSMBUS_general_call_addressing_mode. */ + + uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. + This parameter can be a value of @ref FMPSMBUS_nostretch_mode */ + + uint32_t PacketErrorCheckMode; /*!< Specifies if Packet Error Check mode is selected. + This parameter can be a value of @ref FMPSMBUS_packet_error_check_mode */ + + uint32_t PeripheralMode; /*!< Specifies which mode of Periphal is selected. + This parameter can be a value of @ref FMPSMBUS_peripheral_mode */ + + uint32_t SMBusTimeout; /*!< Specifies the content of the 32 Bits FMPSMBUS_TIMEOUT_register value. + (Enable bits and different timeout values) + This parameter calculated by referring to FMPSMBUS initialization + section in Reference manual */ +} FMPSMBUS_InitTypeDef; +/** + * @} + */ + +/** @defgroup HAL_state_definition HAL state definition + * @brief HAL State definition + * @{ + */ +#define HAL_FMPSMBUS_STATE_RESET (0x00000000U) /*!< FMPSMBUS not yet initialized or disabled */ +#define HAL_FMPSMBUS_STATE_READY (0x00000001U) /*!< FMPSMBUS initialized and ready for use */ +#define HAL_FMPSMBUS_STATE_BUSY (0x00000002U) /*!< FMPSMBUS internal process is ongoing */ +#define HAL_FMPSMBUS_STATE_MASTER_BUSY_TX (0x00000012U) /*!< Master Data Transmission process is ongoing */ +#define HAL_FMPSMBUS_STATE_MASTER_BUSY_RX (0x00000022U) /*!< Master Data Reception process is ongoing */ +#define HAL_FMPSMBUS_STATE_SLAVE_BUSY_TX (0x00000032U) /*!< Slave Data Transmission process is ongoing */ +#define HAL_FMPSMBUS_STATE_SLAVE_BUSY_RX (0x00000042U) /*!< Slave Data Reception process is ongoing */ +#define HAL_FMPSMBUS_STATE_TIMEOUT (0x00000003U) /*!< Timeout state */ +#define HAL_FMPSMBUS_STATE_ERROR (0x00000004U) /*!< Reception process is ongoing */ +#define HAL_FMPSMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */ +/** + * @} + */ + +/** @defgroup FMPSMBUS_Error_Code_definition FMPSMBUS Error Code definition + * @brief FMPSMBUS Error Code definition + * @{ + */ +#define HAL_FMPSMBUS_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_FMPSMBUS_ERROR_BERR (0x00000001U) /*!< BERR error */ +#define HAL_FMPSMBUS_ERROR_ARLO (0x00000002U) /*!< ARLO error */ +#define HAL_FMPSMBUS_ERROR_ACKF (0x00000004U) /*!< ACKF error */ +#define HAL_FMPSMBUS_ERROR_OVR (0x00000008U) /*!< OVR error */ +#define HAL_FMPSMBUS_ERROR_HALTIMEOUT (0x00000010U) /*!< Timeout error */ +#define HAL_FMPSMBUS_ERROR_BUSTIMEOUT (0x00000020U) /*!< Bus Timeout error */ +#define HAL_FMPSMBUS_ERROR_ALERT (0x00000040U) /*!< Alert error */ +#define HAL_FMPSMBUS_ERROR_PECERR (0x00000080U) /*!< PEC error */ +#if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1) +#define HAL_FMPSMBUS_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */ +#endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */ +#define HAL_FMPSMBUS_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */ +/** + * @} + */ + +/** @defgroup FMPSMBUS_handle_Structure_definition FMPSMBUS handle Structure definition + * @brief FMPSMBUS handle Structure definition + * @{ + */ +typedef struct __FMPSMBUS_HandleTypeDef +{ + FMPI2C_TypeDef *Instance; /*!< FMPSMBUS registers base address */ + + FMPSMBUS_InitTypeDef Init; /*!< FMPSMBUS communication parameters */ + + uint8_t *pBuffPtr; /*!< Pointer to FMPSMBUS transfer buffer */ + + uint16_t XferSize; /*!< FMPSMBUS transfer size */ + + __IO uint16_t XferCount; /*!< FMPSMBUS transfer counter */ + + __IO uint32_t XferOptions; /*!< FMPSMBUS transfer options */ + + __IO uint32_t PreviousState; /*!< FMPSMBUS communication Previous state */ + + HAL_LockTypeDef Lock; /*!< FMPSMBUS locking object */ + + __IO uint32_t State; /*!< FMPSMBUS communication state */ + + __IO uint32_t ErrorCode; /*!< FMPSMBUS Error code */ + +#if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1) + void (* MasterTxCpltCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); /*!< FMPSMBUS Master Tx Transfer completed callback */ + void (* MasterRxCpltCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); /*!< FMPSMBUS Master Rx Transfer completed callback */ + void (* SlaveTxCpltCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); /*!< FMPSMBUS Slave Tx Transfer completed callback */ + void (* SlaveRxCpltCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); /*!< FMPSMBUS Slave Rx Transfer completed callback */ + void (* ListenCpltCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); /*!< FMPSMBUS Listen Complete callback */ + void (* ErrorCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); /*!< FMPSMBUS Error callback */ + + void (* AddrCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< FMPSMBUS Slave Address Match callback */ + + void (* MspInitCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); /*!< FMPSMBUS Msp Init callback */ + void (* MspDeInitCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); /*!< FMPSMBUS Msp DeInit callback */ + +#endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */ +} FMPSMBUS_HandleTypeDef; + +#if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1) +/** + * @brief HAL FMPSMBUS Callback ID enumeration definition + */ +typedef enum +{ + HAL_FMPSMBUS_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< FMPSMBUS Master Tx Transfer completed callback ID */ + HAL_FMPSMBUS_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< FMPSMBUS Master Rx Transfer completed callback ID */ + HAL_FMPSMBUS_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< FMPSMBUS Slave Tx Transfer completed callback ID */ + HAL_FMPSMBUS_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< FMPSMBUS Slave Rx Transfer completed callback ID */ + HAL_FMPSMBUS_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< FMPSMBUS Listen Complete callback ID */ + HAL_FMPSMBUS_ERROR_CB_ID = 0x05U, /*!< FMPSMBUS Error callback ID */ + + HAL_FMPSMBUS_MSPINIT_CB_ID = 0x06U, /*!< FMPSMBUS Msp Init callback ID */ + HAL_FMPSMBUS_MSPDEINIT_CB_ID = 0x07U /*!< FMPSMBUS Msp DeInit callback ID */ + +} HAL_FMPSMBUS_CallbackIDTypeDef; + +/** + * @brief HAL FMPSMBUS Callback pointer definition + */ +typedef void (*pFMPSMBUS_CallbackTypeDef)(FMPSMBUS_HandleTypeDef *hfmpsmbus); /*!< pointer to an FMPSMBUS callback function */ +typedef void (*pFMPSMBUS_AddrCallbackTypeDef)(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an FMPSMBUS Address Match callback function */ + +#endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** + * @} + */ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup FMPSMBUS_Exported_Constants FMPSMBUS Exported Constants + * @{ + */ + +/** @defgroup FMPSMBUS_Analog_Filter FMPSMBUS Analog Filter + * @{ + */ +#define FMPSMBUS_ANALOGFILTER_ENABLE (0x00000000U) +#define FMPSMBUS_ANALOGFILTER_DISABLE FMPI2C_CR1_ANFOFF +/** + * @} + */ + +/** @defgroup FMPSMBUS_addressing_mode FMPSMBUS addressing mode + * @{ + */ +#define FMPSMBUS_ADDRESSINGMODE_7BIT (0x00000001U) +#define FMPSMBUS_ADDRESSINGMODE_10BIT (0x00000002U) +/** + * @} + */ + +/** @defgroup FMPSMBUS_dual_addressing_mode FMPSMBUS dual addressing mode + * @{ + */ + +#define FMPSMBUS_DUALADDRESS_DISABLE (0x00000000U) +#define FMPSMBUS_DUALADDRESS_ENABLE FMPI2C_OAR2_OA2EN +/** + * @} + */ + +/** @defgroup FMPSMBUS_own_address2_masks FMPSMBUS ownaddress2 masks + * @{ + */ + +#define FMPSMBUS_OA2_NOMASK ((uint8_t)0x00U) +#define FMPSMBUS_OA2_MASK01 ((uint8_t)0x01U) +#define FMPSMBUS_OA2_MASK02 ((uint8_t)0x02U) +#define FMPSMBUS_OA2_MASK03 ((uint8_t)0x03U) +#define FMPSMBUS_OA2_MASK04 ((uint8_t)0x04U) +#define FMPSMBUS_OA2_MASK05 ((uint8_t)0x05U) +#define FMPSMBUS_OA2_MASK06 ((uint8_t)0x06U) +#define FMPSMBUS_OA2_MASK07 ((uint8_t)0x07U) +/** + * @} + */ + + +/** @defgroup FMPSMBUS_general_call_addressing_mode FMPSMBUS general call addressing mode + * @{ + */ +#define FMPSMBUS_GENERALCALL_DISABLE (0x00000000U) +#define FMPSMBUS_GENERALCALL_ENABLE FMPI2C_CR1_GCEN +/** + * @} + */ + +/** @defgroup FMPSMBUS_nostretch_mode FMPSMBUS nostretch mode + * @{ + */ +#define FMPSMBUS_NOSTRETCH_DISABLE (0x00000000U) +#define FMPSMBUS_NOSTRETCH_ENABLE FMPI2C_CR1_NOSTRETCH +/** + * @} + */ + +/** @defgroup FMPSMBUS_packet_error_check_mode FMPSMBUS packet error check mode + * @{ + */ +#define FMPSMBUS_PEC_DISABLE (0x00000000U) +#define FMPSMBUS_PEC_ENABLE FMPI2C_CR1_PECEN +/** + * @} + */ + +/** @defgroup FMPSMBUS_peripheral_mode FMPSMBUS peripheral mode + * @{ + */ +#define FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_HOST FMPI2C_CR1_SMBHEN +#define FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_SLAVE (0x00000000U) +#define FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_SLAVE_ARP FMPI2C_CR1_SMBDEN +/** + * @} + */ + +/** @defgroup FMPSMBUS_ReloadEndMode_definition FMPSMBUS ReloadEndMode definition + * @{ + */ + +#define FMPSMBUS_SOFTEND_MODE (0x00000000U) +#define FMPSMBUS_RELOAD_MODE FMPI2C_CR2_RELOAD +#define FMPSMBUS_AUTOEND_MODE FMPI2C_CR2_AUTOEND +#define FMPSMBUS_SENDPEC_MODE FMPI2C_CR2_PECBYTE +/** + * @} + */ + +/** @defgroup FMPSMBUS_StartStopMode_definition FMPSMBUS StartStopMode definition + * @{ + */ + +#define FMPSMBUS_NO_STARTSTOP (0x00000000U) +#define FMPSMBUS_GENERATE_STOP (uint32_t)(0x80000000U | FMPI2C_CR2_STOP) +#define FMPSMBUS_GENERATE_START_READ (uint32_t)(0x80000000U | FMPI2C_CR2_START | FMPI2C_CR2_RD_WRN) +#define FMPSMBUS_GENERATE_START_WRITE (uint32_t)(0x80000000U | FMPI2C_CR2_START) +/** + * @} + */ + +/** @defgroup FMPSMBUS_XferOptions_definition FMPSMBUS XferOptions definition + * @{ + */ + +/* List of XferOptions in usage of : + * 1- Restart condition when direction change + * 2- No Restart condition in other use cases + */ +#define FMPSMBUS_FIRST_FRAME FMPSMBUS_SOFTEND_MODE +#define FMPSMBUS_NEXT_FRAME ((uint32_t)(FMPSMBUS_RELOAD_MODE | FMPSMBUS_SOFTEND_MODE)) +#define FMPSMBUS_FIRST_AND_LAST_FRAME_NO_PEC FMPSMBUS_AUTOEND_MODE +#define FMPSMBUS_LAST_FRAME_NO_PEC FMPSMBUS_AUTOEND_MODE +#define FMPSMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(FMPSMBUS_AUTOEND_MODE | FMPSMBUS_SENDPEC_MODE)) +#define FMPSMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(FMPSMBUS_AUTOEND_MODE | FMPSMBUS_SENDPEC_MODE)) + +/* List of XferOptions in usage of : + * 1- Restart condition in all use cases (direction change or not) + */ +#define FMPSMBUS_OTHER_FRAME_NO_PEC (0x000000AAU) +#define FMPSMBUS_OTHER_FRAME_WITH_PEC (0x0000AA00U) +#define FMPSMBUS_OTHER_AND_LAST_FRAME_NO_PEC (0x00AA0000U) +#define FMPSMBUS_OTHER_AND_LAST_FRAME_WITH_PEC (0xAA000000U) +/** + * @} + */ + +/** @defgroup FMPSMBUS_Interrupt_configuration_definition FMPSMBUS Interrupt configuration definition + * @brief FMPSMBUS Interrupt definition + * Elements values convention: 0xXXXXXXXX + * - XXXXXXXX : Interrupt control mask + * @{ + */ +#define FMPSMBUS_IT_ERRI FMPI2C_CR1_ERRIE +#define FMPSMBUS_IT_TCI FMPI2C_CR1_TCIE +#define FMPSMBUS_IT_STOPI FMPI2C_CR1_STOPIE +#define FMPSMBUS_IT_NACKI FMPI2C_CR1_NACKIE +#define FMPSMBUS_IT_ADDRI FMPI2C_CR1_ADDRIE +#define FMPSMBUS_IT_RXI FMPI2C_CR1_RXIE +#define FMPSMBUS_IT_TXI FMPI2C_CR1_TXIE +#define FMPSMBUS_IT_TX (FMPSMBUS_IT_ERRI | FMPSMBUS_IT_TCI | FMPSMBUS_IT_STOPI | FMPSMBUS_IT_NACKI | FMPSMBUS_IT_TXI) +#define FMPSMBUS_IT_RX (FMPSMBUS_IT_ERRI | FMPSMBUS_IT_TCI | FMPSMBUS_IT_NACKI | FMPSMBUS_IT_RXI) +#define FMPSMBUS_IT_ALERT (FMPSMBUS_IT_ERRI) +#define FMPSMBUS_IT_ADDR (FMPSMBUS_IT_ADDRI | FMPSMBUS_IT_STOPI | FMPSMBUS_IT_NACKI) +/** + * @} + */ + +/** @defgroup FMPSMBUS_Flag_definition FMPSMBUS Flag definition + * @brief Flag definition + * Elements values convention: 0xXXXXYYYY + * - XXXXXXXX : Flag mask + * @{ + */ + +#define FMPSMBUS_FLAG_TXE FMPI2C_ISR_TXE +#define FMPSMBUS_FLAG_TXIS FMPI2C_ISR_TXIS +#define FMPSMBUS_FLAG_RXNE FMPI2C_ISR_RXNE +#define FMPSMBUS_FLAG_ADDR FMPI2C_ISR_ADDR +#define FMPSMBUS_FLAG_AF FMPI2C_ISR_NACKF +#define FMPSMBUS_FLAG_STOPF FMPI2C_ISR_STOPF +#define FMPSMBUS_FLAG_TC FMPI2C_ISR_TC +#define FMPSMBUS_FLAG_TCR FMPI2C_ISR_TCR +#define FMPSMBUS_FLAG_BERR FMPI2C_ISR_BERR +#define FMPSMBUS_FLAG_ARLO FMPI2C_ISR_ARLO +#define FMPSMBUS_FLAG_OVR FMPI2C_ISR_OVR +#define FMPSMBUS_FLAG_PECERR FMPI2C_ISR_PECERR +#define FMPSMBUS_FLAG_TIMEOUT FMPI2C_ISR_TIMEOUT +#define FMPSMBUS_FLAG_ALERT FMPI2C_ISR_ALERT +#define FMPSMBUS_FLAG_BUSY FMPI2C_ISR_BUSY +#define FMPSMBUS_FLAG_DIR FMPI2C_ISR_DIR +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros ------------------------------------------------------------*/ +/** @defgroup FMPSMBUS_Exported_Macros FMPSMBUS Exported Macros + * @{ + */ + +/** @brief Reset FMPSMBUS handle state. + * @param __HANDLE__ specifies the FMPSMBUS Handle. + * @retval None + */ +#if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1) +#define __HAL_FMPSMBUS_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_FMPSMBUS_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_FMPSMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_FMPSMBUS_STATE_RESET) +#endif + +/** @brief Enable the specified FMPSMBUS interrupts. + * @param __HANDLE__ specifies the FMPSMBUS Handle. + * @param __INTERRUPT__ specifies the interrupt source to enable. + * This parameter can be one of the following values: + * @arg @ref FMPSMBUS_IT_ERRI Errors interrupt enable + * @arg @ref FMPSMBUS_IT_TCI Transfer complete interrupt enable + * @arg @ref FMPSMBUS_IT_STOPI STOP detection interrupt enable + * @arg @ref FMPSMBUS_IT_NACKI NACK received interrupt enable + * @arg @ref FMPSMBUS_IT_ADDRI Address match interrupt enable + * @arg @ref FMPSMBUS_IT_RXI RX interrupt enable + * @arg @ref FMPSMBUS_IT_TXI TX interrupt enable + * + * @retval None + */ +#define __HAL_FMPSMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__)) + +/** @brief Disable the specified FMPSMBUS interrupts. + * @param __HANDLE__ specifies the FMPSMBUS Handle. + * @param __INTERRUPT__ specifies the interrupt source to disable. + * This parameter can be one of the following values: + * @arg @ref FMPSMBUS_IT_ERRI Errors interrupt enable + * @arg @ref FMPSMBUS_IT_TCI Transfer complete interrupt enable + * @arg @ref FMPSMBUS_IT_STOPI STOP detection interrupt enable + * @arg @ref FMPSMBUS_IT_NACKI NACK received interrupt enable + * @arg @ref FMPSMBUS_IT_ADDRI Address match interrupt enable + * @arg @ref FMPSMBUS_IT_RXI RX interrupt enable + * @arg @ref FMPSMBUS_IT_TXI TX interrupt enable + * + * @retval None + */ +#define __HAL_FMPSMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__))) + +/** @brief Check whether the specified FMPSMBUS interrupt source is enabled or not. + * @param __HANDLE__ specifies the FMPSMBUS Handle. + * @param __INTERRUPT__ specifies the FMPSMBUS interrupt source to check. + * This parameter can be one of the following values: + * @arg @ref FMPSMBUS_IT_ERRI Errors interrupt enable + * @arg @ref FMPSMBUS_IT_TCI Transfer complete interrupt enable + * @arg @ref FMPSMBUS_IT_STOPI STOP detection interrupt enable + * @arg @ref FMPSMBUS_IT_NACKI NACK received interrupt enable + * @arg @ref FMPSMBUS_IT_ADDRI Address match interrupt enable + * @arg @ref FMPSMBUS_IT_RXI RX interrupt enable + * @arg @ref FMPSMBUS_IT_TXI TX interrupt enable + * + * @retval The new state of __IT__ (SET or RESET). + */ +#define __HAL_FMPSMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Check whether the specified FMPSMBUS flag is set or not. + * @param __HANDLE__ specifies the FMPSMBUS Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref FMPSMBUS_FLAG_TXE Transmit data register empty + * @arg @ref FMPSMBUS_FLAG_TXIS Transmit interrupt status + * @arg @ref FMPSMBUS_FLAG_RXNE Receive data register not empty + * @arg @ref FMPSMBUS_FLAG_ADDR Address matched (slave mode) + * @arg @ref FMPSMBUS_FLAG_AF NACK received flag + * @arg @ref FMPSMBUS_FLAG_STOPF STOP detection flag + * @arg @ref FMPSMBUS_FLAG_TC Transfer complete (master mode) + * @arg @ref FMPSMBUS_FLAG_TCR Transfer complete reload + * @arg @ref FMPSMBUS_FLAG_BERR Bus error + * @arg @ref FMPSMBUS_FLAG_ARLO Arbitration lost + * @arg @ref FMPSMBUS_FLAG_OVR Overrun/Underrun + * @arg @ref FMPSMBUS_FLAG_PECERR PEC error in reception + * @arg @ref FMPSMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag + * @arg @ref FMPSMBUS_FLAG_ALERT SMBus alert + * @arg @ref FMPSMBUS_FLAG_BUSY Bus busy + * @arg @ref FMPSMBUS_FLAG_DIR Transfer direction (slave mode) + * + * @retval The new state of __FLAG__ (SET or RESET). + */ +#define FMPSMBUS_FLAG_MASK (0x0001FFFFU) +#define __HAL_FMPSMBUS_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & FMPSMBUS_FLAG_MASK)) == ((__FLAG__) & FMPSMBUS_FLAG_MASK)) ? SET : RESET) + +/** @brief Clear the FMPSMBUS pending flags which are cleared by writing 1 in a specific bit. + * @param __HANDLE__ specifies the FMPSMBUS Handle. + * @param __FLAG__ specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg @ref FMPSMBUS_FLAG_ADDR Address matched (slave mode) + * @arg @ref FMPSMBUS_FLAG_AF NACK received flag + * @arg @ref FMPSMBUS_FLAG_STOPF STOP detection flag + * @arg @ref FMPSMBUS_FLAG_BERR Bus error + * @arg @ref FMPSMBUS_FLAG_ARLO Arbitration lost + * @arg @ref FMPSMBUS_FLAG_OVR Overrun/Underrun + * @arg @ref FMPSMBUS_FLAG_PECERR PEC error in reception + * @arg @ref FMPSMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag + * @arg @ref FMPSMBUS_FLAG_ALERT SMBus alert + * + * @retval None + */ +#define __HAL_FMPSMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) + +/** @brief Enable the specified FMPSMBUS peripheral. + * @param __HANDLE__ specifies the FMPSMBUS Handle. + * @retval None + */ +#define __HAL_FMPSMBUS_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, FMPI2C_CR1_PE)) + +/** @brief Disable the specified FMPSMBUS peripheral. + * @param __HANDLE__ specifies the FMPSMBUS Handle. + * @retval None + */ +#define __HAL_FMPSMBUS_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, FMPI2C_CR1_PE)) + +/** @brief Generate a Non-Acknowledge FMPSMBUS peripheral in Slave mode. + * @param __HANDLE__ specifies the FMPSMBUS Handle. + * @retval None + */ +#define __HAL_FMPSMBUS_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, FMPI2C_CR2_NACK)) + +/** + * @} + */ + + +/* Private constants ---------------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup FMPSMBUS_Private_Macro FMPSMBUS Private Macros + * @{ + */ + +#define IS_FMPSMBUS_ANALOG_FILTER(FILTER) (((FILTER) == FMPSMBUS_ANALOGFILTER_ENABLE) || \ + ((FILTER) == FMPSMBUS_ANALOGFILTER_DISABLE)) + +#define IS_FMPSMBUS_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) + +#define IS_FMPSMBUS_ADDRESSING_MODE(MODE) (((MODE) == FMPSMBUS_ADDRESSINGMODE_7BIT) || \ + ((MODE) == FMPSMBUS_ADDRESSINGMODE_10BIT)) + +#define IS_FMPSMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == FMPSMBUS_DUALADDRESS_DISABLE) || \ + ((ADDRESS) == FMPSMBUS_DUALADDRESS_ENABLE)) + +#define IS_FMPSMBUS_OWN_ADDRESS2_MASK(MASK) (((MASK) == FMPSMBUS_OA2_NOMASK) || \ + ((MASK) == FMPSMBUS_OA2_MASK01) || \ + ((MASK) == FMPSMBUS_OA2_MASK02) || \ + ((MASK) == FMPSMBUS_OA2_MASK03) || \ + ((MASK) == FMPSMBUS_OA2_MASK04) || \ + ((MASK) == FMPSMBUS_OA2_MASK05) || \ + ((MASK) == FMPSMBUS_OA2_MASK06) || \ + ((MASK) == FMPSMBUS_OA2_MASK07)) + +#define IS_FMPSMBUS_GENERAL_CALL(CALL) (((CALL) == FMPSMBUS_GENERALCALL_DISABLE) || \ + ((CALL) == FMPSMBUS_GENERALCALL_ENABLE)) + +#define IS_FMPSMBUS_NO_STRETCH(STRETCH) (((STRETCH) == FMPSMBUS_NOSTRETCH_DISABLE) || \ + ((STRETCH) == FMPSMBUS_NOSTRETCH_ENABLE)) + +#define IS_FMPSMBUS_PEC(PEC) (((PEC) == FMPSMBUS_PEC_DISABLE) || \ + ((PEC) == FMPSMBUS_PEC_ENABLE)) + +#define IS_FMPSMBUS_PERIPHERAL_MODE(MODE) (((MODE) == FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_HOST) || \ + ((MODE) == FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_SLAVE) || \ + ((MODE) == FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_SLAVE_ARP)) + +#define IS_FMPSMBUS_TRANSFER_MODE(MODE) (((MODE) == FMPSMBUS_RELOAD_MODE) || \ + ((MODE) == FMPSMBUS_AUTOEND_MODE) || \ + ((MODE) == FMPSMBUS_SOFTEND_MODE) || \ + ((MODE) == FMPSMBUS_SENDPEC_MODE) || \ + ((MODE) == (FMPSMBUS_RELOAD_MODE | FMPSMBUS_SENDPEC_MODE)) || \ + ((MODE) == (FMPSMBUS_AUTOEND_MODE | FMPSMBUS_SENDPEC_MODE)) || \ + ((MODE) == (FMPSMBUS_AUTOEND_MODE | FMPSMBUS_RELOAD_MODE)) || \ + ((MODE) == (FMPSMBUS_AUTOEND_MODE | FMPSMBUS_SENDPEC_MODE | FMPSMBUS_RELOAD_MODE ))) + + +#define IS_FMPSMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == FMPSMBUS_GENERATE_STOP) || \ + ((REQUEST) == FMPSMBUS_GENERATE_START_READ) || \ + ((REQUEST) == FMPSMBUS_GENERATE_START_WRITE) || \ + ((REQUEST) == FMPSMBUS_NO_STARTSTOP)) + + +#define IS_FMPSMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_FMPSMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \ + ((REQUEST) == FMPSMBUS_FIRST_FRAME) || \ + ((REQUEST) == FMPSMBUS_NEXT_FRAME) || \ + ((REQUEST) == FMPSMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \ + ((REQUEST) == FMPSMBUS_LAST_FRAME_NO_PEC) || \ + ((REQUEST) == FMPSMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \ + ((REQUEST) == FMPSMBUS_LAST_FRAME_WITH_PEC)) + +#define IS_FMPSMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == FMPSMBUS_OTHER_FRAME_NO_PEC) || \ + ((REQUEST) == FMPSMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \ + ((REQUEST) == FMPSMBUS_OTHER_FRAME_WITH_PEC) || \ + ((REQUEST) == FMPSMBUS_OTHER_AND_LAST_FRAME_WITH_PEC)) + +#define FMPSMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(FMPI2C_CR1_SMBHEN | FMPI2C_CR1_SMBDEN | FMPI2C_CR1_PECEN))) +#define FMPSMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(FMPI2C_CR2_SADD | FMPI2C_CR2_HEAD10R | FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | FMPI2C_CR2_RD_WRN))) + +#define FMPSMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == FMPSMBUS_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | (FMPI2C_CR2_START) | (FMPI2C_CR2_AUTOEND)) & (~FMPI2C_CR2_RD_WRN)) : \ + (uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | (FMPI2C_CR2_ADD10) | (FMPI2C_CR2_START)) & (~FMPI2C_CR2_RD_WRN))) + +#define FMPSMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & FMPI2C_ISR_ADDCODE) >> 17U) +#define FMPSMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & FMPI2C_ISR_DIR) >> 16U) +#define FMPSMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & FMPI2C_CR2_AUTOEND) +#define FMPSMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & FMPI2C_CR2_PECBYTE) +#define FMPSMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & FMPI2C_CR1_ALERTEN) + +#define FMPSMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & FMPSMBUS_FLAG_MASK)) == ((__FLAG__) & FMPSMBUS_FLAG_MASK)) ? SET : RESET) +#define FMPSMBUS_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET) + +#define IS_FMPSMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU) +#define IS_FMPSMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup FMPSMBUS_Exported_Functions FMPSMBUS Exported Functions + * @{ + */ + +/** @addtogroup FMPSMBUS_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ + +/* Initialization and de-initialization functions ****************************/ +HAL_StatusTypeDef HAL_FMPSMBUS_Init(FMPSMBUS_HandleTypeDef *hfmpsmbus); +HAL_StatusTypeDef HAL_FMPSMBUS_DeInit(FMPSMBUS_HandleTypeDef *hfmpsmbus); +void HAL_FMPSMBUS_MspInit(FMPSMBUS_HandleTypeDef *hfmpsmbus); +void HAL_FMPSMBUS_MspDeInit(FMPSMBUS_HandleTypeDef *hfmpsmbus); +HAL_StatusTypeDef HAL_FMPSMBUS_ConfigAnalogFilter(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t AnalogFilter); +HAL_StatusTypeDef HAL_FMPSMBUS_ConfigDigitalFilter(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t DigitalFilter); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_FMPSMBUS_RegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, HAL_FMPSMBUS_CallbackIDTypeDef CallbackID, pFMPSMBUS_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_FMPSMBUS_UnRegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, HAL_FMPSMBUS_CallbackIDTypeDef CallbackID); + +HAL_StatusTypeDef HAL_FMPSMBUS_RegisterAddrCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, pFMPSMBUS_AddrCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_FMPSMBUS_UnRegisterAddrCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus); +#endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @addtogroup FMPSMBUS_Exported_Functions_Group2 Input and Output operation functions + * @{ + */ + +/* IO operation functions *****************************************************/ +/** @addtogroup Blocking_mode_Polling Blocking mode Polling + * @{ + */ +/******* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_FMPSMBUS_IsDeviceReady(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout); +/** + * @} + */ + +/** @addtogroup Non-Blocking_mode_Interrupt Non-Blocking mode Interrupt + * @{ + */ +/******* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_FMPSMBUS_Master_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_FMPSMBUS_Master_Receive_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_FMPSMBUS_Master_Abort_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress); +HAL_StatusTypeDef HAL_FMPSMBUS_Slave_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_FMPSMBUS_Slave_Receive_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions); + +HAL_StatusTypeDef HAL_FMPSMBUS_EnableAlert_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus); +HAL_StatusTypeDef HAL_FMPSMBUS_DisableAlert_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus); +HAL_StatusTypeDef HAL_FMPSMBUS_EnableListen_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus); +HAL_StatusTypeDef HAL_FMPSMBUS_DisableListen_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus); +/** + * @} + */ + +/** @addtogroup FMPSMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks + * @{ + */ +/******* FMPSMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */ +void HAL_FMPSMBUS_EV_IRQHandler(FMPSMBUS_HandleTypeDef *hfmpsmbus); +void HAL_FMPSMBUS_ER_IRQHandler(FMPSMBUS_HandleTypeDef *hfmpsmbus); +void HAL_FMPSMBUS_MasterTxCpltCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus); +void HAL_FMPSMBUS_MasterRxCpltCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus); +void HAL_FMPSMBUS_SlaveTxCpltCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus); +void HAL_FMPSMBUS_SlaveRxCpltCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus); +void HAL_FMPSMBUS_AddrCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); +void HAL_FMPSMBUS_ListenCpltCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus); +void HAL_FMPSMBUS_ErrorCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus); + +/** + * @} + */ + +/** @addtogroup FMPSMBUS_Exported_Functions_Group3 Peripheral State and Errors functions + * @{ + */ + +/* Peripheral State and Errors functions **************************************************/ +uint32_t HAL_FMPSMBUS_GetState(FMPSMBUS_HandleTypeDef *hfmpsmbus); +uint32_t HAL_FMPSMBUS_GetError(FMPSMBUS_HandleTypeDef *hfmpsmbus); + +/** + * @} + */ + +/** + * @} + */ + +/* Private Functions ---------------------------------------------------------*/ +/** @defgroup FMPSMBUS_Private_Functions FMPSMBUS Private Functions + * @{ + */ +/* Private functions are defined in stm32f4xx_hal_fmpsmbus.c file */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* FMPI2C_CR1_PE */ +#ifdef __cplusplus +} +#endif + + +#endif /* STM32F4xx_HAL_FMPSMBUS_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_hcd.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_hcd.h index 5f4cccdc5b..4e76af480d 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_hcd.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_hcd.h @@ -109,8 +109,8 @@ typedef struct * @{ */ #define HCD_SPEED_HIGH USBH_HS_SPEED -#define HCD_SPEED_FULL USBH_FS_SPEED -#define HCD_SPEED_LOW USBH_LS_SPEED +#define HCD_SPEED_FULL USBH_FSLS_SPEED +#define HCD_SPEED_LOW USBH_FSLS_SPEED /** * @} @@ -170,19 +170,15 @@ typedef struct /** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions * @{ */ -HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd); -HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd); -HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, - uint8_t ch_num, - uint8_t epnum, - uint8_t dev_address, - uint8_t speed, - uint8_t ep_type, - uint16_t mps); +HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd); +HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd); +HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num, + uint8_t epnum, uint8_t dev_address, + uint8_t speed, uint8_t ep_type, uint16_t mps); -HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num); -void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd); -void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd); +HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num); +void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd); +void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd); #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) /** @defgroup HAL_HCD_Callback_ID_enumeration_definition HAL USB OTG HCD Callback ID enumeration definition @@ -191,14 +187,14 @@ void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd); */ typedef enum { - HAL_HCD_SOF_CB_ID = 0x01, /*!< USB HCD SOF callback ID */ - HAL_HCD_CONNECT_CB_ID = 0x02, /*!< USB HCD Connect callback ID */ - HAL_HCD_DISCONNECT_CB_ID = 0x03, /*!< USB HCD Disconnect callback ID */ - HAL_HCD_PORT_ENABLED_CB_ID = 0x04, /*!< USB HCD Port Enable callback ID */ - HAL_HCD_PORT_DISABLED_CB_ID = 0x05, /*!< USB HCD Port Disable callback ID */ + HAL_HCD_SOF_CB_ID = 0x01, /*!< USB HCD SOF callback ID */ + HAL_HCD_CONNECT_CB_ID = 0x02, /*!< USB HCD Connect callback ID */ + HAL_HCD_DISCONNECT_CB_ID = 0x03, /*!< USB HCD Disconnect callback ID */ + HAL_HCD_PORT_ENABLED_CB_ID = 0x04, /*!< USB HCD Port Enable callback ID */ + HAL_HCD_PORT_DISABLED_CB_ID = 0x05, /*!< USB HCD Port Disable callback ID */ - HAL_HCD_MSPINIT_CB_ID = 0x06, /*!< USB HCD MspInit callback ID */ - HAL_HCD_MSPDEINIT_CB_ID = 0x07 /*!< USB HCD MspDeInit callback ID */ + HAL_HCD_MSPINIT_CB_ID = 0x06, /*!< USB HCD MspInit callback ID */ + HAL_HCD_MSPDEINIT_CB_ID = 0x07 /*!< USB HCD MspDeInit callback ID */ } HAL_HCD_CallbackIDTypeDef; /** @@ -232,25 +228,20 @@ HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef /** @addtogroup HCD_Exported_Functions_Group2 Input and Output operation functions * @{ */ -HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, - uint8_t ch_num, - uint8_t direction, - uint8_t ep_type, - uint8_t token, - uint8_t *pbuff, - uint16_t length, - uint8_t do_ping); +HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, uint8_t ch_num, + uint8_t direction, uint8_t ep_type, + uint8_t token, uint8_t *pbuff, + uint16_t length, uint8_t do_ping); /* Non-Blocking mode: Interrupt */ -void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd); -void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd); -void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd); -void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd); -void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd); -void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd); -void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, - uint8_t chnum, - HCD_URBStateTypeDef urb_state); +void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd); +void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd); +void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd); +void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd); +void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd); +void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd); +void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum, + HCD_URBStateTypeDef urb_state); /** * @} */ @@ -259,9 +250,9 @@ void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, /** @addtogroup HCD_Exported_Functions_Group3 Peripheral Control functions * @{ */ -HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd); -HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd); -HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd); +HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd); +HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd); +HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd); /** * @} */ @@ -272,8 +263,8 @@ HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd); */ HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd); HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum); -uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum); HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum); +uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum); uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd); uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd); /** diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2s.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2s.h index 2d96315146..203ffc1b53 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2s.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2s.h @@ -181,6 +181,7 @@ typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) #define HAL_I2S_ERROR_INVALID_CALLBACK (0x00000020U) /*!< Invalid Callback error */ #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ +#define HAL_I2S_ERROR_BUSY_LINE_RX (0x00000040U) /*!< Busy Rx Line error */ /** * @} */ @@ -421,6 +422,15 @@ typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to tmpreg_udr = ((__HANDLE__)->Instance->SR);\ UNUSED(tmpreg_udr); \ }while(0U) +/** @brief Flush the I2S DR Register. + * @param __HANDLE__ specifies the I2S Handle. + * @retval None + */ +#define __HAL_I2S_FLUSH_RX_DR(__HANDLE__) do{\ + __IO uint32_t tmpreg_dr = 0x00U;\ + tmpreg_dr = ((__HANDLE__)->Instance->DR);\ + UNUSED(tmpreg_dr); \ + }while(0U) /** * @} */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2s_ex.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2s_ex.h index 872283bff4..10335f49f4 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2s_ex.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2s_ex.h @@ -111,6 +111,16 @@ extern "C" { tmpreg_udr = I2SxEXT((__HANDLE__)->Instance)->SR;\ UNUSED(tmpreg_udr); \ }while(0U) +/** @brief Flush the I2S and I2SExt DR Registers. + * @param __HANDLE__ specifies the I2S Handle. + * @retval None + */ +#define __HAL_I2SEXT_FLUSH_RX_DR(__HANDLE__) do{ \ + __IO uint32_t tmpreg_dr = 0x00U; \ + tmpreg_dr = I2SxEXT((__HANDLE__)->Instance)->DR; \ + tmpreg_dr = ((__HANDLE__)->Instance->DR); \ + UNUSED(tmpreg_dr); \ + }while(0U) /** * @} */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h index 2db595c44c..edbb7c6170 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h @@ -96,16 +96,16 @@ typedef struct __PCD_HandleTypeDef typedef struct #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { - PCD_TypeDef *Instance; /*!< Register base address */ - PCD_InitTypeDef Init; /*!< PCD required parameters */ - __IO uint8_t USB_Address; /*!< USB Address */ - PCD_EPTypeDef IN_ep[16]; /*!< IN endpoint parameters */ - PCD_EPTypeDef OUT_ep[16]; /*!< OUT endpoint parameters */ - HAL_LockTypeDef Lock; /*!< PCD peripheral status */ - __IO PCD_StateTypeDef State; /*!< PCD communication state */ - __IO uint32_t ErrorCode; /*!< PCD Error code */ - uint32_t Setup[12]; /*!< Setup packet buffer */ - PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */ + PCD_TypeDef *Instance; /*!< Register base address */ + PCD_InitTypeDef Init; /*!< PCD required parameters */ + __IO uint8_t USB_Address; /*!< USB Address */ + PCD_EPTypeDef IN_ep[16]; /*!< IN endpoint parameters */ + PCD_EPTypeDef OUT_ep[16]; /*!< OUT endpoint parameters */ + HAL_LockTypeDef Lock; /*!< PCD peripheral status */ + __IO PCD_StateTypeDef State; /*!< PCD communication state */ + __IO uint32_t ErrorCode; /*!< PCD Error code */ + uint32_t Setup[12]; /*!< Setup packet buffer */ + PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */ uint32_t BESL; @@ -260,7 +260,7 @@ typedef enum HAL_PCD_SUSPEND_CB_ID = 0x04, /*!< USB PCD Suspend callback ID */ HAL_PCD_RESUME_CB_ID = 0x05, /*!< USB PCD Resume callback ID */ HAL_PCD_CONNECT_CB_ID = 0x06, /*!< USB PCD Connect callback ID */ - HAL_PCD_DISCONNECT_CB_ID = 0x07, /*!< USB PCD Disconnect callback ID */ + HAL_PCD_DISCONNECT_CB_ID = 0x07, /*!< USB PCD Disconnect callback ID */ HAL_PCD_MSPINIT_CB_ID = 0x08, /*!< USB PCD MspInit callback ID */ HAL_PCD_MSPDEINIT_CB_ID = 0x09 /*!< USB PCD MspDeInit callback ID */ @@ -379,14 +379,6 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @{ */ #if defined (USB_OTG_FS) || defined (USB_OTG_HS) -#define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE 0x08U -#define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE 0x0CU -#define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE 0x10U - -#define USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE 0x08U -#define USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE 0x0CU -#define USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE 0x10U - #define USB_OTG_FS_WAKEUP_EXTI_LINE (0x1U << 18) /*!< USB FS EXTI Line WakeUp Interrupt */ #define USB_OTG_HS_WAKEUP_EXTI_LINE (0x1U << 20) /*!< USB HS EXTI Line WakeUp Interrupt */ #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_qspi.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_qspi.h index 039558aa04..97e9324f34 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_qspi.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_qspi.h @@ -6,30 +6,30 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. + *

© Copyright (c) 2016 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_HAL_QSPI_H -#define __STM32F4xx_HAL_QSPI_H +#ifndef STM32F4xx_HAL_QSPI_H +#define STM32F4xx_HAL_QSPI_H #ifdef __cplusplus extern "C" { #endif -#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ - defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hal_def.h" +#if defined(QUADSPI) + /** @addtogroup STM32F4xx_HAL_Driver * @{ */ @@ -46,35 +46,27 @@ /** * @brief QSPI Init structure definition */ - typedef struct { uint32_t ClockPrescaler; /* Specifies the prescaler factor for generating clock based on the AHB clock. This parameter can be a number between 0 and 255 */ - uint32_t FifoThreshold; /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode) This parameter can be a value between 1 and 32 */ - uint32_t SampleShifting; /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode) This parameter can be a value of @ref QSPI_SampleShifting */ - uint32_t FlashSize; /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits required to address the flash memory. The flash capacity can be up to 4GB (addressed using 32 bits) in indirect mode, but the addressable space in memory-mapped mode is limited to 256MB This parameter can be a number between 0 and 31 */ - uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number of clock cycles which the chip select must remain high between commands. This parameter can be a value of @ref QSPI_ChipSelectHighTime */ - uint32_t ClockMode; /* Specifies the Clock Mode. It indicates the level that clock takes between commands. This parameter can be a value of @ref QSPI_ClockMode */ - uint32_t FlashID; /* Specifies the Flash which will be used, This parameter can be a value of @ref QSPI_Flash_Select */ - uint32_t DualFlash; /* Specifies the Dual Flash Mode State This parameter can be a value of @ref QSPI_DualFlash_Mode */ }QSPI_InitTypeDef; @@ -142,9 +134,9 @@ typedef struct uint32_t Instruction; /* Specifies the Instruction to be sent This parameter can be a value (8-bit) between 0x00 and 0xFF */ uint32_t Address; /* Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize) - This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFFU */ + This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */ uint32_t AlternateBytes; /* Specifies the Alternate Bytes to be sent (Size from 1 to 4 bytes according AlternateBytesSize) - This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFFU */ + This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */ uint32_t AddressSize; /* Specifies the Address Size This parameter can be a value of @ref QSPI_AddressSize */ uint32_t AlternateBytesSize; /* Specifies the Alternate Bytes Size @@ -159,15 +151,15 @@ typedef struct This parameter can be a value of @ref QSPI_AlternateBytesMode */ uint32_t DataMode; /* Specifies the Data Mode (used for dummy cycles and data phases) This parameter can be a value of @ref QSPI_DataMode */ - uint32_t NbData; /* Specifies the number of data to transfer. - This parameter can be any value between 0 and 0xFFFFFFFFU (0 means undefined length + uint32_t NbData; /* Specifies the number of data to transfer. (This is the number of bytes) + This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length until end of memory)*/ uint32_t DdrMode; /* Specifies the double data rate mode for address, alternate byte and data phase This parameter can be a value of @ref QSPI_DdrMode */ - uint32_t DdrHoldHalfCycle; /* Specifies the DDR hold half cycle. It delays the data output by one half of - system clock in DDR mode. + uint32_t DdrHoldHalfCycle; /* Specifies if the DDR hold is enabled. When enabled it delays the data + output by one half of system clock in DDR mode. This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */ - uint32_t SIOOMode; /* Specifies the send instruction only once mode + uint32_t SIOOMode; /* Specifies the send instruction only once mode This parameter can be a value of @ref QSPI_SIOOMode */ }QSPI_CommandTypeDef; @@ -177,11 +169,11 @@ typedef struct typedef struct { uint32_t Match; /* Specifies the value to be compared with the masked status register to get a match. - This parameter can be any value between 0 and 0xFFFFFFFFU */ + This parameter can be any value between 0 and 0xFFFFFFFF */ uint32_t Mask; /* Specifies the mask to be applied to the status bytes received. - This parameter can be any value between 0 and 0xFFFFFFFFU */ + This parameter can be any value between 0 and 0xFFFFFFFF */ uint32_t Interval; /* Specifies the number of clock cycles between two read during automatic polling phases. - This parameter can be any value between 0 and 0xFFFFU */ + This parameter can be any value between 0 and 0xFFFF */ uint32_t StatusBytesSize; /* Specifies the size of the status bytes received. This parameter can be any value between 1 and 4 */ uint32_t MatchMode; /* Specifies the method used for determining a match. @@ -196,8 +188,8 @@ typedef struct typedef struct { uint32_t TimeOutPeriod; /* Specifies the number of clock to wait when the FIFO is full before to release the chip select. - This parameter can be any value between 0 and 0xFFFFU */ - uint32_t TimeOutActivation; /* Specifies if the time out counter is enabled to release the chip select. + This parameter can be any value between 0 and 0xFFFF */ + uint32_t TimeOutActivation; /* Specifies if the timeout counter is enabled to release the chip select. This parameter can be a value of @ref QSPI_TimeOutActivation */ }QSPI_MemoryMappedTypeDef; @@ -235,14 +227,15 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi); /** @defgroup QSPI_Exported_Constants QSPI Exported Constants * @{ */ + /** @defgroup QSPI_ErrorCode QSPI Error Code * @{ */ -#define HAL_QSPI_ERROR_NONE 0x00000000U /*!< No error */ -#define HAL_QSPI_ERROR_TIMEOUT 0x00000001U /*!< Timeout error */ -#define HAL_QSPI_ERROR_TRANSFER 0x00000002U /*!< Transfer error */ -#define HAL_QSPI_ERROR_DMA 0x00000004U /*!< DMA transfer error */ -#define HAL_QSPI_ERROR_INVALID_PARAM 0x00000008U /*!< Invalid parameters error */ +#define HAL_QSPI_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_QSPI_ERROR_TIMEOUT 0x00000001U /*!< Timeout error */ +#define HAL_QSPI_ERROR_TRANSFER 0x00000002U /*!< Transfer error */ +#define HAL_QSPI_ERROR_DMA 0x00000004U /*!< DMA transfer error */ +#define HAL_QSPI_ERROR_INVALID_PARAM 0x00000008U /*!< Invalid parameters error */ #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) #define HAL_QSPI_ERROR_INVALID_CALLBACK 0x00000010U /*!< Invalid callback error */ #endif @@ -253,23 +246,23 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi); /** @defgroup QSPI_SampleShifting QSPI Sample Shifting * @{ */ -#define QSPI_SAMPLE_SHIFTING_NONE 0x00000000U /*!State = HAL_QSPI_STATE_RESET) #endif -/** @brief Enable QSPI - * @param __HANDLE__ specifies the QSPI Handle. +/** @brief Enable the QSPI peripheral. + * @param __HANDLE__ : specifies the QSPI Handle. * @retval None */ #define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) -/** @brief Disable QSPI - * @param __HANDLE__ specifies the QSPI Handle. +/** @brief Disable the QSPI peripheral. + * @param __HANDLE__ : specifies the QSPI Handle. * @retval None */ #define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) -/** @brief Enables the specified QSPI interrupt. - * @param __HANDLE__ specifies the QSPI Handle. - * @param __INTERRUPT__ specifies the QSPI interrupt source to enable. +/** @brief Enable the specified QSPI interrupt. + * @param __HANDLE__ : specifies the QSPI Handle. + * @param __INTERRUPT__ : specifies the QSPI interrupt source to enable. * This parameter can be one of the following values: - * @arg QSPI_IT_TO: QSPI Time out interrupt + * @arg QSPI_IT_TO: QSPI Timeout interrupt * @arg QSPI_IT_SM: QSPI Status match interrupt * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt * @arg QSPI_IT_TC: QSPI Transfer complete interrupt @@ -503,9 +496,9 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi); #define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) -/** @brief Disables the specified QSPI interrupt. - * @param __HANDLE__ specifies the QSPI Handle. - * @param __INTERRUPT__ specifies the QSPI interrupt source to disable. +/** @brief Disable the specified QSPI interrupt. + * @param __HANDLE__ : specifies the QSPI Handle. + * @param __INTERRUPT__ : specifies the QSPI interrupt source to disable. * This parameter can be one of the following values: * @arg QSPI_IT_TO: QSPI Timeout interrupt * @arg QSPI_IT_SM: QSPI Status match interrupt @@ -516,11 +509,11 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi); */ #define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) -/** @brief Checks whether the specified QSPI interrupt source is enabled. - * @param __HANDLE__ specifies the QSPI Handle. - * @param __INTERRUPT__ specifies the QSPI interrupt source to check. +/** @brief Check whether the specified QSPI interrupt source is enabled or not. + * @param __HANDLE__ : specifies the QSPI Handle. + * @param __INTERRUPT__ : specifies the QSPI interrupt source to check. * This parameter can be one of the following values: - * @arg QSPI_IT_TO: QSPI Time out interrupt + * @arg QSPI_IT_TO: QSPI Timeout interrupt * @arg QSPI_IT_SM: QSPI Status match interrupt * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt * @arg QSPI_IT_TC: QSPI Transfer complete interrupt @@ -530,25 +523,25 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi); #define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__)) /** - * @brief Get the selected QSPI's flag status. - * @param __HANDLE__ specifies the QSPI Handle. - * @param __FLAG__ specifies the QSPI flag to check. + * @brief Check whether the selected QSPI flag is set or not. + * @param __HANDLE__ : specifies the QSPI Handle. + * @param __FLAG__ : specifies the QSPI flag to check. * This parameter can be one of the following values: * @arg QSPI_FLAG_BUSY: QSPI Busy flag - * @arg QSPI_FLAG_TO: QSPI Time out flag + * @arg QSPI_FLAG_TO: QSPI Timeout flag * @arg QSPI_FLAG_SM: QSPI Status match flag * @arg QSPI_FLAG_FT: QSPI FIFO threshold flag * @arg QSPI_FLAG_TC: QSPI Transfer complete flag * @arg QSPI_FLAG_TE: QSPI Transfer error flag * @retval None */ -#define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) (READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) +#define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? SET : RESET) /** @brief Clears the specified QSPI's flag status. - * @param __HANDLE__ specifies the QSPI Handle. - * @param __FLAG__ specifies the QSPI clear register flag that needs to be set + * @param __HANDLE__ : specifies the QSPI Handle. + * @param __FLAG__ : specifies the QSPI clear register flag that needs to be set * This parameter can be one of the following values: - * @arg QSPI_FLAG_TO: QSPI Time out flag + * @arg QSPI_FLAG_TO: QSPI Timeout flag * @arg QSPI_FLAG_SM: QSPI Status match flag * @arg QSPI_FLAG_TC: QSPI Transfer complete flag * @arg QSPI_FLAG_TE: QSPI Transfer error flag @@ -599,13 +592,7 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_Co /* QSPI memory-mapped mode */ HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg); -/** - * @} - */ -/** @addtogroup QSPI_Exported_Functions_Group3 - * @{ - */ /* Callback functions in non-blocking modes ***********************************/ void HAL_QSPI_ErrorCallback (QSPI_HandleTypeDef *hqspi); void HAL_QSPI_AbortCpltCallback (QSPI_HandleTypeDef *hqspi); @@ -633,7 +620,7 @@ HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, * @} */ -/** @addtogroup QSPI_Exported_Functions_Group4 +/** @addtogroup QSPI_Exported_Functions_Group3 * @{ */ /* Peripheral Control and State functions ************************************/ @@ -644,168 +631,108 @@ HAL_StatusTypeDef HAL_QSPI_Abort_IT (QSPI_HandleTypeDef *hqspi); void HAL_QSPI_SetTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Timeout); HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold); uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi); +HAL_StatusTypeDef HAL_QSPI_SetFlashID (QSPI_HandleTypeDef *hqspi, uint32_t FlashID); /** * @} */ -/* Private macros ------------------------------------------------------------*/ -/** @defgroup QSPI_Private_Macros QSPI Private Macros - * @{ - */ -/** @defgroup QSPI_ClockPrescaler QSPI Clock Prescaler - * @{ - */ -#define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFU) /** * @} */ +/* End of exported functions -------------------------------------------------*/ -/** @defgroup QSPI_FifoThreshold QSPI Fifo Threshold - * @{ - */ -#define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0U) && ((THR) <= 32U)) -/** - * @} - */ - -#define IS_QSPI_SSHIFT(SSHIFT) (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \ - ((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE)) - -/** @defgroup QSPI_FlashSize QSPI Flash Size +/* Private macros ------------------------------------------------------------*/ +/** @defgroup QSPI_Private_Macros QSPI Private Macros * @{ */ -#define IS_QSPI_FLASH_SIZE(FSIZE) (((FSIZE) <= 31U)) -/** - * @} - */ +#define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFU) -#define IS_QSPI_CS_HIGH_TIME(CSHTIME) (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \ - ((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \ - ((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \ - ((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \ - ((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \ - ((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \ - ((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \ - ((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE)) +#define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0U) && ((THR) <= 32U)) -#define IS_QSPI_CLOCK_MODE(CLKMODE) (((CLKMODE) == QSPI_CLOCK_MODE_0) || \ - ((CLKMODE) == QSPI_CLOCK_MODE_3)) +#define IS_QSPI_SSHIFT(SSHIFT) (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \ + ((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE)) -#define IS_QSPI_FLASH_ID(FLA) (((FLA) == QSPI_FLASH_ID_1) || \ - ((FLA) == QSPI_FLASH_ID_2)) +#define IS_QSPI_FLASH_SIZE(FSIZE) (((FSIZE) <= 31U)) -#define IS_QSPI_DUAL_FLASH_MODE(MODE) (((MODE) == QSPI_DUALFLASH_ENABLE) || \ - ((MODE) == QSPI_DUALFLASH_DISABLE)) +#define IS_QSPI_CS_HIGH_TIME(CSHTIME) (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \ + ((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \ + ((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \ + ((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \ + ((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \ + ((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \ + ((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \ + ((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE)) +#define IS_QSPI_CLOCK_MODE(CLKMODE) (((CLKMODE) == QSPI_CLOCK_MODE_0) || \ + ((CLKMODE) == QSPI_CLOCK_MODE_3)) -/** @defgroup QSPI_Instruction QSPI Instruction - * @{ - */ -#define IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFFU) -/** - * @} - */ +#define IS_QSPI_FLASH_ID(FLASH_ID) (((FLASH_ID) == QSPI_FLASH_ID_1) || \ + ((FLASH_ID) == QSPI_FLASH_ID_2)) -#define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE) (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS) || \ - ((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \ - ((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \ - ((ADDR_SIZE) == QSPI_ADDRESS_32_BITS)) +#define IS_QSPI_DUAL_FLASH_MODE(MODE) (((MODE) == QSPI_DUALFLASH_ENABLE) || \ + ((MODE) == QSPI_DUALFLASH_DISABLE)) -#define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS) || \ - ((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \ - ((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \ - ((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS)) +#define IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFFU) +#define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE) (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS) || \ + ((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \ + ((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \ + ((ADDR_SIZE) == QSPI_ADDRESS_32_BITS)) -/** @defgroup QSPI_DummyCycles QSPI Dummy Cycles - * @{ - */ -#define IS_QSPI_DUMMY_CYCLES(DCY) ((DCY) <= 31U) -/** - * @} - */ +#define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS) || \ + ((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \ + ((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \ + ((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS)) -#define IS_QSPI_INSTRUCTION_MODE(MODE) (((MODE) == QSPI_INSTRUCTION_NONE) || \ - ((MODE) == QSPI_INSTRUCTION_1_LINE) || \ - ((MODE) == QSPI_INSTRUCTION_2_LINES) || \ - ((MODE) == QSPI_INSTRUCTION_4_LINES)) +#define IS_QSPI_DUMMY_CYCLES(DCY) ((DCY) <= 31U) -#define IS_QSPI_ADDRESS_MODE(MODE) (((MODE) == QSPI_ADDRESS_NONE) || \ - ((MODE) == QSPI_ADDRESS_1_LINE) || \ - ((MODE) == QSPI_ADDRESS_2_LINES) || \ - ((MODE) == QSPI_ADDRESS_4_LINES)) +#define IS_QSPI_INSTRUCTION_MODE(MODE) (((MODE) == QSPI_INSTRUCTION_NONE) || \ + ((MODE) == QSPI_INSTRUCTION_1_LINE) || \ + ((MODE) == QSPI_INSTRUCTION_2_LINES) || \ + ((MODE) == QSPI_INSTRUCTION_4_LINES)) -#define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE) || \ - ((MODE) == QSPI_ALTERNATE_BYTES_1_LINE) || \ - ((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \ - ((MODE) == QSPI_ALTERNATE_BYTES_4_LINES)) +#define IS_QSPI_ADDRESS_MODE(MODE) (((MODE) == QSPI_ADDRESS_NONE) || \ + ((MODE) == QSPI_ADDRESS_1_LINE) || \ + ((MODE) == QSPI_ADDRESS_2_LINES) || \ + ((MODE) == QSPI_ADDRESS_4_LINES)) -#define IS_QSPI_DATA_MODE(MODE) (((MODE) == QSPI_DATA_NONE) || \ - ((MODE) == QSPI_DATA_1_LINE) || \ - ((MODE) == QSPI_DATA_2_LINES) || \ - ((MODE) == QSPI_DATA_4_LINES)) +#define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE) || \ + ((MODE) == QSPI_ALTERNATE_BYTES_1_LINE) || \ + ((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \ + ((MODE) == QSPI_ALTERNATE_BYTES_4_LINES)) -#define IS_QSPI_DDR_MODE(DDR_MODE) (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \ - ((DDR_MODE) == QSPI_DDR_MODE_ENABLE)) +#define IS_QSPI_DATA_MODE(MODE) (((MODE) == QSPI_DATA_NONE) || \ + ((MODE) == QSPI_DATA_1_LINE) || \ + ((MODE) == QSPI_DATA_2_LINES) || \ + ((MODE) == QSPI_DATA_4_LINES)) -#define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \ - ((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY)) +#define IS_QSPI_DDR_MODE(DDR_MODE) (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \ + ((DDR_MODE) == QSPI_DDR_MODE_ENABLE)) -#define IS_QSPI_SIOO_MODE(SIOO_MODE) (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \ - ((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD)) - -/** @defgroup QSPI_Interval QSPI Interval - * @{ - */ -#define IS_QSPI_INTERVAL(INTERVAL) ((INTERVAL) <= QUADSPI_PIR_INTERVAL) -/** - * @} - */ - -/** @defgroup QSPI_StatusBytesSize QSPI Status Bytes Size - * @{ - */ -#define IS_QSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 4U)) -/** - * @} - */ -#define IS_QSPI_MATCH_MODE(MODE) (((MODE) == QSPI_MATCH_MODE_AND) || \ - ((MODE) == QSPI_MATCH_MODE_OR)) +#define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \ + ((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY)) -#define IS_QSPI_AUTOMATIC_STOP(APMS) (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \ - ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE)) +#define IS_QSPI_SIOO_MODE(SIOO_MODE) (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \ + ((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD)) -#define IS_QSPI_TIMEOUT_ACTIVATION(TCEN) (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \ - ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE)) +#define IS_QSPI_INTERVAL(INTERVAL) ((INTERVAL) <= QUADSPI_PIR_INTERVAL) -/** @defgroup QSPI_TimeOutPeriod QSPI TimeOut Period - * @{ - */ -#define IS_QSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFFU) -/** - * @} - */ +#define IS_QSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 4U)) -#define IS_QSPI_GET_FLAG(FLAG) (((FLAG) == QSPI_FLAG_BUSY) || \ - ((FLAG) == QSPI_FLAG_TO) || \ - ((FLAG) == QSPI_FLAG_SM) || \ - ((FLAG) == QSPI_FLAG_FT) || \ - ((FLAG) == QSPI_FLAG_TC) || \ - ((FLAG) == QSPI_FLAG_TE)) +#define IS_QSPI_MATCH_MODE(MODE) (((MODE) == QSPI_MATCH_MODE_AND) || \ + ((MODE) == QSPI_MATCH_MODE_OR)) -#define IS_QSPI_IT(IT) ((((IT) & 0xFFE0FFFFU) == 0x00000000U) && ((IT) != 0x00000000U)) -/** - * @} - */ +#define IS_QSPI_AUTOMATIC_STOP(APMS) (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \ + ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE)) -/* Private functions ---------------------------------------------------------*/ -/** @defgroup QSPI_Private_Functions QSPI Private Functions - * @{ - */ +#define IS_QSPI_TIMEOUT_ACTIVATION(TCEN) (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \ + ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE)) +#define IS_QSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFFU) /** - * @} - */ +* @} +*/ +/* End of private macros -----------------------------------------------------*/ /** * @} @@ -815,16 +742,12 @@ uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi); * @} */ -/** - * @} - */ -#endif /* STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || - STM32F413xx || STM32F423xx */ +#endif /* defined(QUADSPI) || defined(QUADSPI1) || defined(QUADSPI2) */ #ifdef __cplusplus } #endif -#endif /* __STM32F4xx_HAL_QSPI_H */ +#endif /* STM32F4xx_HAL_QSPI_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fmpi2c.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fmpi2c.h new file mode 100644 index 0000000000..b3779a4851 --- /dev/null +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fmpi2c.h @@ -0,0 +1,2191 @@ +/** + ****************************************************************************** + * @file stm32f4xx_ll_fmpi2c.h + * @author MCD Application Team + * @brief Header file of FMPI2C LL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F4xx_LL_FMPI2C_H +#define STM32F4xx_LL_FMPI2C_H + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(FMPI2C_CR1_PE) +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx.h" + +/** @addtogroup STM32F4xx_LL_Driver + * @{ + */ + +#if defined (FMPI2C1) + +/** @defgroup FMPI2C_LL FMPI2C + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup FMPI2C_LL_Private_Constants FMPI2C Private Constants + * @{ + */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup FMPI2C_LL_Private_Macros FMPI2C Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup FMPI2C_LL_ES_INIT FMPI2C Exported Init structure + * @{ + */ +typedef struct +{ + uint32_t PeripheralMode; /*!< Specifies the peripheral mode. + This parameter can be a value of @ref FMPI2C_LL_EC_PERIPHERAL_MODE + + This feature can be modified afterwards using unitary function @ref LL_FMPI2C_SetMode(). */ + + uint32_t Timing; /*!< Specifies the SDA setup, hold time and the SCL high, low period values. + This parameter must be set by referring to the STM32CubeMX Tool and + the helper macro @ref __LL_FMPI2C_CONVERT_TIMINGS() + + This feature can be modified afterwards using unitary function @ref LL_FMPI2C_SetTiming(). */ + + uint32_t AnalogFilter; /*!< Enables or disables analog noise filter. + This parameter can be a value of @ref FMPI2C_LL_EC_ANALOGFILTER_SELECTION + + This feature can be modified afterwards using unitary functions @ref LL_FMPI2C_EnableAnalogFilter() or LL_FMPI2C_DisableAnalogFilter(). */ + + uint32_t DigitalFilter; /*!< Configures the digital noise filter. + This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F + + This feature can be modified afterwards using unitary function @ref LL_FMPI2C_SetDigitalFilter(). */ + + uint32_t OwnAddress1; /*!< Specifies the device own address 1. + This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF + + This feature can be modified afterwards using unitary function @ref LL_FMPI2C_SetOwnAddress1(). */ + + uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte. + This parameter can be a value of @ref FMPI2C_LL_EC_I2C_ACKNOWLEDGE + + This feature can be modified afterwards using unitary function @ref LL_FMPI2C_AcknowledgeNextData(). */ + + uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit). + This parameter can be a value of @ref FMPI2C_LL_EC_OWNADDRESS1 + + This feature can be modified afterwards using unitary function @ref LL_FMPI2C_SetOwnAddress1(). */ +} LL_FMPI2C_InitTypeDef; +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup FMPI2C_LL_Exported_Constants FMPI2C Exported Constants + * @{ + */ + +/** @defgroup FMPI2C_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_FMPI2C_WriteReg function + * @{ + */ +#define LL_FMPI2C_ICR_ADDRCF FMPI2C_ICR_ADDRCF /*!< Address Matched flag */ +#define LL_FMPI2C_ICR_NACKCF FMPI2C_ICR_NACKCF /*!< Not Acknowledge flag */ +#define LL_FMPI2C_ICR_STOPCF FMPI2C_ICR_STOPCF /*!< Stop detection flag */ +#define LL_FMPI2C_ICR_BERRCF FMPI2C_ICR_BERRCF /*!< Bus error flag */ +#define LL_FMPI2C_ICR_ARLOCF FMPI2C_ICR_ARLOCF /*!< Arbitration Lost flag */ +#define LL_FMPI2C_ICR_OVRCF FMPI2C_ICR_OVRCF /*!< Overrun/Underrun flag */ +#define LL_FMPI2C_ICR_PECCF FMPI2C_ICR_PECCF /*!< PEC error flag */ +#define LL_FMPI2C_ICR_TIMOUTCF FMPI2C_ICR_TIMOUTCF /*!< Timeout detection flag */ +#define LL_FMPI2C_ICR_ALERTCF FMPI2C_ICR_ALERTCF /*!< Alert flag */ +/** + * @} + */ + +/** @defgroup FMPI2C_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_FMPI2C_ReadReg function + * @{ + */ +#define LL_FMPI2C_ISR_TXE FMPI2C_ISR_TXE /*!< Transmit data register empty */ +#define LL_FMPI2C_ISR_TXIS FMPI2C_ISR_TXIS /*!< Transmit interrupt status */ +#define LL_FMPI2C_ISR_RXNE FMPI2C_ISR_RXNE /*!< Receive data register not empty */ +#define LL_FMPI2C_ISR_ADDR FMPI2C_ISR_ADDR /*!< Address matched (slave mode) */ +#define LL_FMPI2C_ISR_NACKF FMPI2C_ISR_NACKF /*!< Not Acknowledge received flag */ +#define LL_FMPI2C_ISR_STOPF FMPI2C_ISR_STOPF /*!< Stop detection flag */ +#define LL_FMPI2C_ISR_TC FMPI2C_ISR_TC /*!< Transfer Complete (master mode) */ +#define LL_FMPI2C_ISR_TCR FMPI2C_ISR_TCR /*!< Transfer Complete Reload */ +#define LL_FMPI2C_ISR_BERR FMPI2C_ISR_BERR /*!< Bus error */ +#define LL_FMPI2C_ISR_ARLO FMPI2C_ISR_ARLO /*!< Arbitration lost */ +#define LL_FMPI2C_ISR_OVR FMPI2C_ISR_OVR /*!< Overrun/Underrun (slave mode) */ +#define LL_FMPI2C_ISR_PECERR FMPI2C_ISR_PECERR /*!< PEC Error in reception (SMBus mode) */ +#define LL_FMPI2C_ISR_TIMEOUT FMPI2C_ISR_TIMEOUT /*!< Timeout detection flag (SMBus mode) */ +#define LL_FMPI2C_ISR_ALERT FMPI2C_ISR_ALERT /*!< SMBus alert (SMBus mode) */ +#define LL_FMPI2C_ISR_BUSY FMPI2C_ISR_BUSY /*!< Bus busy */ +/** + * @} + */ + +/** @defgroup FMPI2C_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_FMPI2C_ReadReg and LL_FMPI2C_WriteReg functions + * @{ + */ +#define LL_FMPI2C_CR1_TXIE FMPI2C_CR1_TXIE /*!< TX Interrupt enable */ +#define LL_FMPI2C_CR1_RXIE FMPI2C_CR1_RXIE /*!< RX Interrupt enable */ +#define LL_FMPI2C_CR1_ADDRIE FMPI2C_CR1_ADDRIE /*!< Address match Interrupt enable (slave only) */ +#define LL_FMPI2C_CR1_NACKIE FMPI2C_CR1_NACKIE /*!< Not acknowledge received Interrupt enable */ +#define LL_FMPI2C_CR1_STOPIE FMPI2C_CR1_STOPIE /*!< STOP detection Interrupt enable */ +#define LL_FMPI2C_CR1_TCIE FMPI2C_CR1_TCIE /*!< Transfer Complete interrupt enable */ +#define LL_FMPI2C_CR1_ERRIE FMPI2C_CR1_ERRIE /*!< Error interrupts enable */ +/** + * @} + */ + +/** @defgroup FMPI2C_LL_EC_PERIPHERAL_MODE Peripheral Mode + * @{ + */ +#define LL_FMPI2C_MODE_I2C 0x00000000U /*!< FMPI2C Master or Slave mode */ +#define LL_FMPI2C_MODE_SMBUS_HOST FMPI2C_CR1_SMBHEN /*!< SMBus Host address acknowledge */ +#define LL_FMPI2C_MODE_SMBUS_DEVICE 0x00000000U /*!< SMBus Device default mode (Default address not acknowledge) */ +#define LL_FMPI2C_MODE_SMBUS_DEVICE_ARP FMPI2C_CR1_SMBDEN /*!< SMBus Device Default address acknowledge */ +/** + * @} + */ + +/** @defgroup FMPI2C_LL_EC_ANALOGFILTER_SELECTION Analog Filter Selection + * @{ + */ +#define LL_FMPI2C_ANALOGFILTER_ENABLE 0x00000000U /*!< Analog filter is enabled. */ +#define LL_FMPI2C_ANALOGFILTER_DISABLE FMPI2C_CR1_ANFOFF /*!< Analog filter is disabled. */ +/** + * @} + */ + +/** @defgroup FMPI2C_LL_EC_ADDRESSING_MODE Master Addressing Mode + * @{ + */ +#define LL_FMPI2C_ADDRESSING_MODE_7BIT 0x00000000U /*!< Master operates in 7-bit addressing mode. */ +#define LL_FMPI2C_ADDRESSING_MODE_10BIT FMPI2C_CR2_ADD10 /*!< Master operates in 10-bit addressing mode.*/ +/** + * @} + */ + +/** @defgroup FMPI2C_LL_EC_OWNADDRESS1 Own Address 1 Length + * @{ + */ +#define LL_FMPI2C_OWNADDRESS1_7BIT 0x00000000U /*!< Own address 1 is a 7-bit address. */ +#define LL_FMPI2C_OWNADDRESS1_10BIT FMPI2C_OAR1_OA1MODE /*!< Own address 1 is a 10-bit address.*/ +/** + * @} + */ + +/** @defgroup FMPI2C_LL_EC_OWNADDRESS2 Own Address 2 Masks + * @{ + */ +#define LL_FMPI2C_OWNADDRESS2_NOMASK FMPI2C_OAR2_OA2NOMASK /*!< Own Address2 No mask. */ +#define LL_FMPI2C_OWNADDRESS2_MASK01 FMPI2C_OAR2_OA2MASK01 /*!< Only Address2 bits[7:2] are compared. */ +#define LL_FMPI2C_OWNADDRESS2_MASK02 FMPI2C_OAR2_OA2MASK02 /*!< Only Address2 bits[7:3] are compared. */ +#define LL_FMPI2C_OWNADDRESS2_MASK03 FMPI2C_OAR2_OA2MASK03 /*!< Only Address2 bits[7:4] are compared. */ +#define LL_FMPI2C_OWNADDRESS2_MASK04 FMPI2C_OAR2_OA2MASK04 /*!< Only Address2 bits[7:5] are compared. */ +#define LL_FMPI2C_OWNADDRESS2_MASK05 FMPI2C_OAR2_OA2MASK05 /*!< Only Address2 bits[7:6] are compared. */ +#define LL_FMPI2C_OWNADDRESS2_MASK06 FMPI2C_OAR2_OA2MASK06 /*!< Only Address2 bits[7] are compared. */ +#define LL_FMPI2C_OWNADDRESS2_MASK07 FMPI2C_OAR2_OA2MASK07 /*!< No comparison is done. All Address2 are acknowledged.*/ +/** + * @} + */ + +/** @defgroup FMPI2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation + * @{ + */ +#define LL_FMPI2C_ACK 0x00000000U /*!< ACK is sent after current received byte. */ +#define LL_FMPI2C_NACK FMPI2C_CR2_NACK /*!< NACK is sent after current received byte.*/ +/** + * @} + */ + +/** @defgroup FMPI2C_LL_EC_ADDRSLAVE Slave Address Length + * @{ + */ +#define LL_FMPI2C_ADDRSLAVE_7BIT 0x00000000U /*!< Slave Address in 7-bit. */ +#define LL_FMPI2C_ADDRSLAVE_10BIT FMPI2C_CR2_ADD10 /*!< Slave Address in 10-bit.*/ +/** + * @} + */ + +/** @defgroup FMPI2C_LL_EC_REQUEST Transfer Request Direction + * @{ + */ +#define LL_FMPI2C_REQUEST_WRITE 0x00000000U /*!< Master request a write transfer. */ +#define LL_FMPI2C_REQUEST_READ FMPI2C_CR2_RD_WRN /*!< Master request a read transfer. */ +/** + * @} + */ + +/** @defgroup FMPI2C_LL_EC_MODE Transfer End Mode + * @{ + */ +#define LL_FMPI2C_MODE_RELOAD FMPI2C_CR2_RELOAD /*!< Enable FMPI2C Reload mode. */ +#define LL_FMPI2C_MODE_AUTOEND FMPI2C_CR2_AUTOEND /*!< Enable FMPI2C Automatic end mode with no HW PEC comparison. */ +#define LL_FMPI2C_MODE_SOFTEND 0x00000000U /*!< Enable FMPI2C Software end mode with no HW PEC comparison. */ +#define LL_FMPI2C_MODE_SMBUS_RELOAD LL_FMPI2C_MODE_RELOAD /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */ +#define LL_FMPI2C_MODE_SMBUS_AUTOEND_NO_PEC LL_FMPI2C_MODE_AUTOEND /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */ +#define LL_FMPI2C_MODE_SMBUS_SOFTEND_NO_PEC LL_FMPI2C_MODE_SOFTEND /*!< Enable SMBUS Software end mode with HW PEC comparison. */ +#define LL_FMPI2C_MODE_SMBUS_AUTOEND_WITH_PEC (uint32_t)(LL_FMPI2C_MODE_AUTOEND | FMPI2C_CR2_PECBYTE) /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */ +#define LL_FMPI2C_MODE_SMBUS_SOFTEND_WITH_PEC (uint32_t)(LL_FMPI2C_MODE_SOFTEND | FMPI2C_CR2_PECBYTE) /*!< Enable SMBUS Software end mode with HW PEC comparison. */ +/** + * @} + */ + +/** @defgroup FMPI2C_LL_EC_GENERATE Start And Stop Generation + * @{ + */ +#define LL_FMPI2C_GENERATE_NOSTARTSTOP 0x00000000U /*!< Don't Generate Stop and Start condition. */ +#define LL_FMPI2C_GENERATE_STOP (uint32_t)(0x80000000U | FMPI2C_CR2_STOP) /*!< Generate Stop condition (Size should be set to 0). */ +#define LL_FMPI2C_GENERATE_START_READ (uint32_t)(0x80000000U | FMPI2C_CR2_START | FMPI2C_CR2_RD_WRN) /*!< Generate Start for read request. */ +#define LL_FMPI2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | FMPI2C_CR2_START) /*!< Generate Start for write request. */ +#define LL_FMPI2C_GENERATE_RESTART_7BIT_READ (uint32_t)(0x80000000U | FMPI2C_CR2_START | FMPI2C_CR2_RD_WRN) /*!< Generate Restart for read request, slave 7Bit address. */ +#define LL_FMPI2C_GENERATE_RESTART_7BIT_WRITE (uint32_t)(0x80000000U | FMPI2C_CR2_START) /*!< Generate Restart for write request, slave 7Bit address. */ +#define LL_FMPI2C_GENERATE_RESTART_10BIT_READ (uint32_t)(0x80000000U | FMPI2C_CR2_START | FMPI2C_CR2_RD_WRN | FMPI2C_CR2_HEAD10R) /*!< Generate Restart for read request, slave 10Bit address. */ +#define LL_FMPI2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | FMPI2C_CR2_START) /*!< Generate Restart for write request, slave 10Bit address.*/ +/** + * @} + */ + +/** @defgroup FMPI2C_LL_EC_DIRECTION Read Write Direction + * @{ + */ +#define LL_FMPI2C_DIRECTION_WRITE 0x00000000U /*!< Write transfer request by master, slave enters receiver mode. */ +#define LL_FMPI2C_DIRECTION_READ FMPI2C_ISR_DIR /*!< Read transfer request by master, slave enters transmitter mode.*/ +/** + * @} + */ + +/** @defgroup FMPI2C_LL_EC_DMA_REG_DATA DMA Register Data + * @{ + */ +#define LL_FMPI2C_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */ +#define LL_FMPI2C_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */ +/** + * @} + */ + +/** @defgroup FMPI2C_LL_EC_SMBUS_TIMEOUTA_MODE SMBus TimeoutA Mode SCL SDA Timeout + * @{ + */ +#define LL_FMPI2C_SMBUS_TIMEOUTA_MODE_SCL_LOW 0x00000000U /*!< TimeoutA is used to detect SCL low level timeout. */ +#define LL_FMPI2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH FMPI2C_TIMEOUTR_TIDLE /*!< TimeoutA is used to detect both SCL and SDA high level timeout.*/ +/** + * @} + */ + +/** @defgroup FMPI2C_LL_EC_SMBUS_TIMEOUT_SELECTION SMBus Timeout Selection + * @{ + */ +#define LL_FMPI2C_SMBUS_TIMEOUTA FMPI2C_TIMEOUTR_TIMOUTEN /*!< TimeoutA enable bit */ +#define LL_FMPI2C_SMBUS_TIMEOUTB FMPI2C_TIMEOUTR_TEXTEN /*!< TimeoutB (extended clock) enable bit */ +#define LL_FMPI2C_SMBUS_ALL_TIMEOUT (uint32_t)(FMPI2C_TIMEOUTR_TIMOUTEN | FMPI2C_TIMEOUTR_TEXTEN) /*!< TimeoutA and TimeoutB (extended clock) enable bits */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup FMPI2C_LL_Exported_Macros FMPI2C Exported Macros + * @{ + */ + +/** @defgroup FMPI2C_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in FMPI2C register + * @param __INSTANCE__ FMPI2C Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_FMPI2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in FMPI2C register + * @param __INSTANCE__ FMPI2C Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_FMPI2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup FMPI2C_LL_EM_CONVERT_TIMINGS Convert SDA SCL timings + * @{ + */ +/** + * @brief Configure the SDA setup, hold time and the SCL high, low period. + * @param __PRESCALER__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. + * @param __DATA_SETUP_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tscldel = (SCLDEL+1)xtpresc) + * @param __DATA_HOLD_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tsdadel = SDADELxtpresc) + * @param __CLOCK_HIGH_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. (tsclh = (SCLH+1)xtpresc) + * @param __CLOCK_LOW_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. (tscll = (SCLL+1)xtpresc) + * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF + */ +#define __LL_FMPI2C_CONVERT_TIMINGS(__PRESCALER__, __DATA_SETUP_TIME__, __DATA_HOLD_TIME__, __CLOCK_HIGH_PERIOD__, __CLOCK_LOW_PERIOD__) \ + ((((uint32_t)(__PRESCALER__) << FMPI2C_TIMINGR_PRESC_Pos) & FMPI2C_TIMINGR_PRESC) | \ + (((uint32_t)(__DATA_SETUP_TIME__) << FMPI2C_TIMINGR_SCLDEL_Pos) & FMPI2C_TIMINGR_SCLDEL) | \ + (((uint32_t)(__DATA_HOLD_TIME__) << FMPI2C_TIMINGR_SDADEL_Pos) & FMPI2C_TIMINGR_SDADEL) | \ + (((uint32_t)(__CLOCK_HIGH_PERIOD__) << FMPI2C_TIMINGR_SCLH_Pos) & FMPI2C_TIMINGR_SCLH) | \ + (((uint32_t)(__CLOCK_LOW_PERIOD__) << FMPI2C_TIMINGR_SCLL_Pos) & FMPI2C_TIMINGR_SCLL)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup FMPI2C_LL_Exported_Functions FMPI2C Exported Functions + * @{ + */ + +/** @defgroup FMPI2C_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Enable FMPI2C peripheral (PE = 1). + * @rmtoll CR1 PE LL_FMPI2C_Enable + * @param FMPI2Cx FMPI2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_FMPI2C_Enable(FMPI2C_TypeDef *FMPI2Cx) +{ + SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_PE); +} + +/** + * @brief Disable FMPI2C peripheral (PE = 0). + * @note When PE = 0, the FMPI2C SCL and SDA lines are released. + * Internal state machines and status bits are put back to their reset value. + * When cleared, PE must be kept low for at least 3 APB clock cycles. + * @rmtoll CR1 PE LL_FMPI2C_Disable + * @param FMPI2Cx FMPI2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_FMPI2C_Disable(FMPI2C_TypeDef *FMPI2Cx) +{ + CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_PE); +} + +/** + * @brief Check if the FMPI2C peripheral is enabled or disabled. + * @rmtoll CR1 PE LL_FMPI2C_IsEnabled + * @param FMPI2Cx FMPI2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabled(FMPI2C_TypeDef *FMPI2Cx) +{ + return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_PE) == (FMPI2C_CR1_PE)) ? 1UL : 0UL); +} + +/** + * @brief Configure Noise Filters (Analog and Digital). + * @note If the analog filter is also enabled, the digital filter is added to analog filter. + * The filters can only be programmed when the FMPI2C is disabled (PE = 0). + * @rmtoll CR1 ANFOFF LL_FMPI2C_ConfigFilters\n + * CR1 DNF LL_FMPI2C_ConfigFilters + * @param FMPI2Cx FMPI2C Instance. + * @param AnalogFilter This parameter can be one of the following values: + * @arg @ref LL_FMPI2C_ANALOGFILTER_ENABLE + * @arg @ref LL_FMPI2C_ANALOGFILTER_DISABLE + * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*tfmpi2cclk). + * This parameter is used to configure the digital noise filter on SDA and SCL input. + * The digital filter will filter spikes with a length of up to DNF[3:0]*tfmpi2cclk. + * @retval None + */ +__STATIC_INLINE void LL_FMPI2C_ConfigFilters(FMPI2C_TypeDef *FMPI2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter) +{ + MODIFY_REG(FMPI2Cx->CR1, FMPI2C_CR1_ANFOFF | FMPI2C_CR1_DNF, AnalogFilter | (DigitalFilter << FMPI2C_CR1_DNF_Pos)); +} + +/** + * @brief Configure Digital Noise Filter. + * @note If the analog filter is also enabled, the digital filter is added to analog filter. + * This filter can only be programmed when the FMPI2C is disabled (PE = 0). + * @rmtoll CR1 DNF LL_FMPI2C_SetDigitalFilter + * @param FMPI2Cx FMPI2C Instance. + * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*tfmpi2cclk). + * This parameter is used to configure the digital noise filter on SDA and SCL input. + * The digital filter will filter spikes with a length of up to DNF[3:0]*tfmpi2cclk. + * @retval None + */ +__STATIC_INLINE void LL_FMPI2C_SetDigitalFilter(FMPI2C_TypeDef *FMPI2Cx, uint32_t DigitalFilter) +{ + MODIFY_REG(FMPI2Cx->CR1, FMPI2C_CR1_DNF, DigitalFilter << FMPI2C_CR1_DNF_Pos); +} + +/** + * @brief Get the current Digital Noise Filter configuration. + * @rmtoll CR1 DNF LL_FMPI2C_GetDigitalFilter + * @param FMPI2Cx FMPI2C Instance. + * @retval Value between Min_Data=0x0 and Max_Data=0xF + */ +__STATIC_INLINE uint32_t LL_FMPI2C_GetDigitalFilter(FMPI2C_TypeDef *FMPI2Cx) +{ + return (uint32_t)(READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_DNF) >> FMPI2C_CR1_DNF_Pos); +} + +/** + * @brief Enable Analog Noise Filter. + * @note This filter can only be programmed when the FMPI2C is disabled (PE = 0). + * @rmtoll CR1 ANFOFF LL_FMPI2C_EnableAnalogFilter + * @param FMPI2Cx FMPI2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_FMPI2C_EnableAnalogFilter(FMPI2C_TypeDef *FMPI2Cx) +{ + CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_ANFOFF); +} + +/** + * @brief Disable Analog Noise Filter. + * @note This filter can only be programmed when the FMPI2C is disabled (PE = 0). + * @rmtoll CR1 ANFOFF LL_FMPI2C_DisableAnalogFilter + * @param FMPI2Cx FMPI2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_FMPI2C_DisableAnalogFilter(FMPI2C_TypeDef *FMPI2Cx) +{ + SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_ANFOFF); +} + +/** + * @brief Check if Analog Noise Filter is enabled or disabled. + * @rmtoll CR1 ANFOFF LL_FMPI2C_IsEnabledAnalogFilter + * @param FMPI2Cx FMPI2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledAnalogFilter(FMPI2C_TypeDef *FMPI2Cx) +{ + return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_ANFOFF) != (FMPI2C_CR1_ANFOFF)) ? 1UL : 0UL); +} + +/** + * @brief Enable DMA transmission requests. + * @rmtoll CR1 TXDMAEN LL_FMPI2C_EnableDMAReq_TX + * @param FMPI2Cx FMPI2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_FMPI2C_EnableDMAReq_TX(FMPI2C_TypeDef *FMPI2Cx) +{ + SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_TXDMAEN); +} + +/** + * @brief Disable DMA transmission requests. + * @rmtoll CR1 TXDMAEN LL_FMPI2C_DisableDMAReq_TX + * @param FMPI2Cx FMPI2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_FMPI2C_DisableDMAReq_TX(FMPI2C_TypeDef *FMPI2Cx) +{ + CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_TXDMAEN); +} + +/** + * @brief Check if DMA transmission requests are enabled or disabled. + * @rmtoll CR1 TXDMAEN LL_FMPI2C_IsEnabledDMAReq_TX + * @param FMPI2Cx FMPI2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledDMAReq_TX(FMPI2C_TypeDef *FMPI2Cx) +{ + return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_TXDMAEN) == (FMPI2C_CR1_TXDMAEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable DMA reception requests. + * @rmtoll CR1 RXDMAEN LL_FMPI2C_EnableDMAReq_RX + * @param FMPI2Cx FMPI2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_FMPI2C_EnableDMAReq_RX(FMPI2C_TypeDef *FMPI2Cx) +{ + SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_RXDMAEN); +} + +/** + * @brief Disable DMA reception requests. + * @rmtoll CR1 RXDMAEN LL_FMPI2C_DisableDMAReq_RX + * @param FMPI2Cx FMPI2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_FMPI2C_DisableDMAReq_RX(FMPI2C_TypeDef *FMPI2Cx) +{ + CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_RXDMAEN); +} + +/** + * @brief Check if DMA reception requests are enabled or disabled. + * @rmtoll CR1 RXDMAEN LL_FMPI2C_IsEnabledDMAReq_RX + * @param FMPI2Cx FMPI2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledDMAReq_RX(FMPI2C_TypeDef *FMPI2Cx) +{ + return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_RXDMAEN) == (FMPI2C_CR1_RXDMAEN)) ? 1UL : 0UL); +} + +/** + * @brief Get the data register address used for DMA transfer + * @rmtoll TXDR TXDATA LL_FMPI2C_DMA_GetRegAddr\n + * RXDR RXDATA LL_FMPI2C_DMA_GetRegAddr + * @param FMPI2Cx FMPI2C Instance + * @param Direction This parameter can be one of the following values: + * @arg @ref LL_FMPI2C_DMA_REG_DATA_TRANSMIT + * @arg @ref LL_FMPI2C_DMA_REG_DATA_RECEIVE + * @retval Address of data register + */ +__STATIC_INLINE uint32_t LL_FMPI2C_DMA_GetRegAddr(FMPI2C_TypeDef *FMPI2Cx, uint32_t Direction) +{ + register uint32_t data_reg_addr; + + if (Direction == LL_FMPI2C_DMA_REG_DATA_TRANSMIT) + { + /* return address of TXDR register */ + data_reg_addr = (uint32_t) & (FMPI2Cx->TXDR); + } + else + { + /* return address of RXDR register */ + data_reg_addr = (uint32_t) & (FMPI2Cx->RXDR); + } + + return data_reg_addr; +} + +/** + * @brief Enable Clock stretching. + * @note This bit can only be programmed when the FMPI2C is disabled (PE = 0). + * @rmtoll CR1 NOSTRETCH LL_FMPI2C_EnableClockStretching + * @param FMPI2Cx FMPI2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_FMPI2C_EnableClockStretching(FMPI2C_TypeDef *FMPI2Cx) +{ + CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_NOSTRETCH); +} + +/** + * @brief Disable Clock stretching. + * @note This bit can only be programmed when the FMPI2C is disabled (PE = 0). + * @rmtoll CR1 NOSTRETCH LL_FMPI2C_DisableClockStretching + * @param FMPI2Cx FMPI2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_FMPI2C_DisableClockStretching(FMPI2C_TypeDef *FMPI2Cx) +{ + SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_NOSTRETCH); +} + +/** + * @brief Check if Clock stretching is enabled or disabled. + * @rmtoll CR1 NOSTRETCH LL_FMPI2C_IsEnabledClockStretching + * @param FMPI2Cx FMPI2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledClockStretching(FMPI2C_TypeDef *FMPI2Cx) +{ + return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_NOSTRETCH) != (FMPI2C_CR1_NOSTRETCH)) ? 1UL : 0UL); +} + +/** + * @brief Enable hardware byte control in slave mode. + * @rmtoll CR1 SBC LL_FMPI2C_EnableSlaveByteControl + * @param FMPI2Cx FMPI2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_FMPI2C_EnableSlaveByteControl(FMPI2C_TypeDef *FMPI2Cx) +{ + SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_SBC); +} + +/** + * @brief Disable hardware byte control in slave mode. + * @rmtoll CR1 SBC LL_FMPI2C_DisableSlaveByteControl + * @param FMPI2Cx FMPI2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_FMPI2C_DisableSlaveByteControl(FMPI2C_TypeDef *FMPI2Cx) +{ + CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_SBC); +} + +/** + * @brief Check if hardware byte control in slave mode is enabled or disabled. + * @rmtoll CR1 SBC LL_FMPI2C_IsEnabledSlaveByteControl + * @param FMPI2Cx FMPI2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledSlaveByteControl(FMPI2C_TypeDef *FMPI2Cx) +{ + return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_SBC) == (FMPI2C_CR1_SBC)) ? 1UL : 0UL); +} + + +/** + * @brief Enable General Call. + * @note When enabled the Address 0x00 is ACKed. + * @rmtoll CR1 GCEN LL_FMPI2C_EnableGeneralCall + * @param FMPI2Cx FMPI2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_FMPI2C_EnableGeneralCall(FMPI2C_TypeDef *FMPI2Cx) +{ + SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_GCEN); +} + +/** + * @brief Disable General Call. + * @note When disabled the Address 0x00 is NACKed. + * @rmtoll CR1 GCEN LL_FMPI2C_DisableGeneralCall + * @param FMPI2Cx FMPI2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_FMPI2C_DisableGeneralCall(FMPI2C_TypeDef *FMPI2Cx) +{ + CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_GCEN); +} + +/** + * @brief Check if General Call is enabled or disabled. + * @rmtoll CR1 GCEN LL_FMPI2C_IsEnabledGeneralCall + * @param FMPI2Cx FMPI2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledGeneralCall(FMPI2C_TypeDef *FMPI2Cx) +{ + return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_GCEN) == (FMPI2C_CR1_GCEN)) ? 1UL : 0UL); +} + +/** + * @brief Configure the Master to operate in 7-bit or 10-bit addressing mode. + * @note Changing this bit is not allowed, when the START bit is set. + * @rmtoll CR2 ADD10 LL_FMPI2C_SetMasterAddressingMode + * @param FMPI2Cx FMPI2C Instance. + * @param AddressingMode This parameter can be one of the following values: + * @arg @ref LL_FMPI2C_ADDRESSING_MODE_7BIT + * @arg @ref LL_FMPI2C_ADDRESSING_MODE_10BIT + * @retval None + */ +__STATIC_INLINE void LL_FMPI2C_SetMasterAddressingMode(FMPI2C_TypeDef *FMPI2Cx, uint32_t AddressingMode) +{ + MODIFY_REG(FMPI2Cx->CR2, FMPI2C_CR2_ADD10, AddressingMode); +} + +/** + * @brief Get the Master addressing mode. + * @rmtoll CR2 ADD10 LL_FMPI2C_GetMasterAddressingMode + * @param FMPI2Cx FMPI2C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_FMPI2C_ADDRESSING_MODE_7BIT + * @arg @ref LL_FMPI2C_ADDRESSING_MODE_10BIT + */ +__STATIC_INLINE uint32_t LL_FMPI2C_GetMasterAddressingMode(FMPI2C_TypeDef *FMPI2Cx) +{ + return (uint32_t)(READ_BIT(FMPI2Cx->CR2, FMPI2C_CR2_ADD10)); +} + +/** + * @brief Set the Own Address1. + * @rmtoll OAR1 OA1 LL_FMPI2C_SetOwnAddress1\n + * OAR1 OA1MODE LL_FMPI2C_SetOwnAddress1 + * @param FMPI2Cx FMPI2C Instance. + * @param OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF. + * @param OwnAddrSize This parameter can be one of the following values: + * @arg @ref LL_FMPI2C_OWNADDRESS1_7BIT + * @arg @ref LL_FMPI2C_OWNADDRESS1_10BIT + * @retval None + */ +__STATIC_INLINE void LL_FMPI2C_SetOwnAddress1(FMPI2C_TypeDef *FMPI2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize) +{ + MODIFY_REG(FMPI2Cx->OAR1, FMPI2C_OAR1_OA1 | FMPI2C_OAR1_OA1MODE, OwnAddress1 | OwnAddrSize); +} + +/** + * @brief Enable acknowledge on Own Address1 match address. + * @rmtoll OAR1 OA1EN LL_FMPI2C_EnableOwnAddress1 + * @param FMPI2Cx FMPI2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_FMPI2C_EnableOwnAddress1(FMPI2C_TypeDef *FMPI2Cx) +{ + SET_BIT(FMPI2Cx->OAR1, FMPI2C_OAR1_OA1EN); +} + +/** + * @brief Disable acknowledge on Own Address1 match address. + * @rmtoll OAR1 OA1EN LL_FMPI2C_DisableOwnAddress1 + * @param FMPI2Cx FMPI2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_FMPI2C_DisableOwnAddress1(FMPI2C_TypeDef *FMPI2Cx) +{ + CLEAR_BIT(FMPI2Cx->OAR1, FMPI2C_OAR1_OA1EN); +} + +/** + * @brief Check if Own Address1 acknowledge is enabled or disabled. + * @rmtoll OAR1 OA1EN LL_FMPI2C_IsEnabledOwnAddress1 + * @param FMPI2Cx FMPI2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledOwnAddress1(FMPI2C_TypeDef *FMPI2Cx) +{ + return ((READ_BIT(FMPI2Cx->OAR1, FMPI2C_OAR1_OA1EN) == (FMPI2C_OAR1_OA1EN)) ? 1UL : 0UL); +} + +/** + * @brief Set the 7bits Own Address2. + * @note This action has no effect if own address2 is enabled. + * @rmtoll OAR2 OA2 LL_FMPI2C_SetOwnAddress2\n + * OAR2 OA2MSK LL_FMPI2C_SetOwnAddress2 + * @param FMPI2Cx FMPI2C Instance. + * @param OwnAddress2 Value between Min_Data=0 and Max_Data=0x7F. + * @param OwnAddrMask This parameter can be one of the following values: + * @arg @ref LL_FMPI2C_OWNADDRESS2_NOMASK + * @arg @ref LL_FMPI2C_OWNADDRESS2_MASK01 + * @arg @ref LL_FMPI2C_OWNADDRESS2_MASK02 + * @arg @ref LL_FMPI2C_OWNADDRESS2_MASK03 + * @arg @ref LL_FMPI2C_OWNADDRESS2_MASK04 + * @arg @ref LL_FMPI2C_OWNADDRESS2_MASK05 + * @arg @ref LL_FMPI2C_OWNADDRESS2_MASK06 + * @arg @ref LL_FMPI2C_OWNADDRESS2_MASK07 + * @retval None + */ +__STATIC_INLINE void LL_FMPI2C_SetOwnAddress2(FMPI2C_TypeDef *FMPI2Cx, uint32_t OwnAddress2, uint32_t OwnAddrMask) +{ + MODIFY_REG(FMPI2Cx->OAR2, FMPI2C_OAR2_OA2 | FMPI2C_OAR2_OA2MSK, OwnAddress2 | OwnAddrMask); +} + +/** + * @brief Enable acknowledge on Own Address2 match address. + * @rmtoll OAR2 OA2EN LL_FMPI2C_EnableOwnAddress2 + * @param FMPI2Cx FMPI2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_FMPI2C_EnableOwnAddress2(FMPI2C_TypeDef *FMPI2Cx) +{ + SET_BIT(FMPI2Cx->OAR2, FMPI2C_OAR2_OA2EN); +} + +/** + * @brief Disable acknowledge on Own Address2 match address. + * @rmtoll OAR2 OA2EN LL_FMPI2C_DisableOwnAddress2 + * @param FMPI2Cx FMPI2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_FMPI2C_DisableOwnAddress2(FMPI2C_TypeDef *FMPI2Cx) +{ + CLEAR_BIT(FMPI2Cx->OAR2, FMPI2C_OAR2_OA2EN); +} + +/** + * @brief Check if Own Address1 acknowledge is enabled or disabled. + * @rmtoll OAR2 OA2EN LL_FMPI2C_IsEnabledOwnAddress2 + * @param FMPI2Cx FMPI2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledOwnAddress2(FMPI2C_TypeDef *FMPI2Cx) +{ + return ((READ_BIT(FMPI2Cx->OAR2, FMPI2C_OAR2_OA2EN) == (FMPI2C_OAR2_OA2EN)) ? 1UL : 0UL); +} + +/** + * @brief Configure the SDA setup, hold time and the SCL high, low period. + * @note This bit can only be programmed when the FMPI2C is disabled (PE = 0). + * @rmtoll TIMINGR TIMINGR LL_FMPI2C_SetTiming + * @param FMPI2Cx FMPI2C Instance. + * @param Timing This parameter must be a value between Min_Data=0 and Max_Data=0xFFFFFFFF. + * @note This parameter is computed with the STM32CubeMX Tool. + * @retval None + */ +__STATIC_INLINE void LL_FMPI2C_SetTiming(FMPI2C_TypeDef *FMPI2Cx, uint32_t Timing) +{ + WRITE_REG(FMPI2Cx->TIMINGR, Timing); +} + +/** + * @brief Get the Timing Prescaler setting. + * @rmtoll TIMINGR PRESC LL_FMPI2C_GetTimingPrescaler + * @param FMPI2Cx FMPI2C Instance. + * @retval Value between Min_Data=0x0 and Max_Data=0xF + */ +__STATIC_INLINE uint32_t LL_FMPI2C_GetTimingPrescaler(FMPI2C_TypeDef *FMPI2Cx) +{ + return (uint32_t)(READ_BIT(FMPI2Cx->TIMINGR, FMPI2C_TIMINGR_PRESC) >> FMPI2C_TIMINGR_PRESC_Pos); +} + +/** + * @brief Get the SCL low period setting. + * @rmtoll TIMINGR SCLL LL_FMPI2C_GetClockLowPeriod + * @param FMPI2Cx FMPI2C Instance. + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_FMPI2C_GetClockLowPeriod(FMPI2C_TypeDef *FMPI2Cx) +{ + return (uint32_t)(READ_BIT(FMPI2Cx->TIMINGR, FMPI2C_TIMINGR_SCLL) >> FMPI2C_TIMINGR_SCLL_Pos); +} + +/** + * @brief Get the SCL high period setting. + * @rmtoll TIMINGR SCLH LL_FMPI2C_GetClockHighPeriod + * @param FMPI2Cx FMPI2C Instance. + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_FMPI2C_GetClockHighPeriod(FMPI2C_TypeDef *FMPI2Cx) +{ + return (uint32_t)(READ_BIT(FMPI2Cx->TIMINGR, FMPI2C_TIMINGR_SCLH) >> FMPI2C_TIMINGR_SCLH_Pos); +} + +/** + * @brief Get the SDA hold time. + * @rmtoll TIMINGR SDADEL LL_FMPI2C_GetDataHoldTime + * @param FMPI2Cx FMPI2C Instance. + * @retval Value between Min_Data=0x0 and Max_Data=0xF + */ +__STATIC_INLINE uint32_t LL_FMPI2C_GetDataHoldTime(FMPI2C_TypeDef *FMPI2Cx) +{ + return (uint32_t)(READ_BIT(FMPI2Cx->TIMINGR, FMPI2C_TIMINGR_SDADEL) >> FMPI2C_TIMINGR_SDADEL_Pos); +} + +/** + * @brief Get the SDA setup time. + * @rmtoll TIMINGR SCLDEL LL_FMPI2C_GetDataSetupTime + * @param FMPI2Cx FMPI2C Instance. + * @retval Value between Min_Data=0x0 and Max_Data=0xF + */ +__STATIC_INLINE uint32_t LL_FMPI2C_GetDataSetupTime(FMPI2C_TypeDef *FMPI2Cx) +{ + return (uint32_t)(READ_BIT(FMPI2Cx->TIMINGR, FMPI2C_TIMINGR_SCLDEL) >> FMPI2C_TIMINGR_SCLDEL_Pos); +} + +/** + * @brief Configure peripheral mode. + * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * SMBus feature is supported by the FMPI2Cx Instance. + * @rmtoll CR1 SMBHEN LL_FMPI2C_SetMode\n + * CR1 SMBDEN LL_FMPI2C_SetMode + * @param FMPI2Cx FMPI2C Instance. + * @param PeripheralMode This parameter can be one of the following values: + * @arg @ref LL_FMPI2C_MODE_I2C + * @arg @ref LL_FMPI2C_MODE_SMBUS_HOST + * @arg @ref LL_FMPI2C_MODE_SMBUS_DEVICE + * @arg @ref LL_FMPI2C_MODE_SMBUS_DEVICE_ARP + * @retval None + */ +__STATIC_INLINE void LL_FMPI2C_SetMode(FMPI2C_TypeDef *FMPI2Cx, uint32_t PeripheralMode) +{ + MODIFY_REG(FMPI2Cx->CR1, FMPI2C_CR1_SMBHEN | FMPI2C_CR1_SMBDEN, PeripheralMode); +} + +/** + * @brief Get peripheral mode. + * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * SMBus feature is supported by the FMPI2Cx Instance. + * @rmtoll CR1 SMBHEN LL_FMPI2C_GetMode\n + * CR1 SMBDEN LL_FMPI2C_GetMode + * @param FMPI2Cx FMPI2C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_FMPI2C_MODE_I2C + * @arg @ref LL_FMPI2C_MODE_SMBUS_HOST + * @arg @ref LL_FMPI2C_MODE_SMBUS_DEVICE + * @arg @ref LL_FMPI2C_MODE_SMBUS_DEVICE_ARP + */ +__STATIC_INLINE uint32_t LL_FMPI2C_GetMode(FMPI2C_TypeDef *FMPI2Cx) +{ + return (uint32_t)(READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_SMBHEN | FMPI2C_CR1_SMBDEN)); +} + +/** + * @brief Enable SMBus alert (Host or Device mode) + * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * SMBus feature is supported by the FMPI2Cx Instance. + * @note SMBus Device mode: + * - SMBus Alert pin is drived low and + * Alert Response Address Header acknowledge is enabled. + * SMBus Host mode: + * - SMBus Alert pin management is supported. + * @rmtoll CR1 ALERTEN LL_FMPI2C_EnableSMBusAlert + * @param FMPI2Cx FMPI2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_FMPI2C_EnableSMBusAlert(FMPI2C_TypeDef *FMPI2Cx) +{ + SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_ALERTEN); +} + +/** + * @brief Disable SMBus alert (Host or Device mode) + * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * SMBus feature is supported by the FMPI2Cx Instance. + * @note SMBus Device mode: + * - SMBus Alert pin is not drived (can be used as a standard GPIO) and + * Alert Response Address Header acknowledge is disabled. + * SMBus Host mode: + * - SMBus Alert pin management is not supported. + * @rmtoll CR1 ALERTEN LL_FMPI2C_DisableSMBusAlert + * @param FMPI2Cx FMPI2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_FMPI2C_DisableSMBusAlert(FMPI2C_TypeDef *FMPI2Cx) +{ + CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_ALERTEN); +} + +/** + * @brief Check if SMBus alert (Host or Device mode) is enabled or disabled. + * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * SMBus feature is supported by the FMPI2Cx Instance. + * @rmtoll CR1 ALERTEN LL_FMPI2C_IsEnabledSMBusAlert + * @param FMPI2Cx FMPI2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledSMBusAlert(FMPI2C_TypeDef *FMPI2Cx) +{ + return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_ALERTEN) == (FMPI2C_CR1_ALERTEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable SMBus Packet Error Calculation (PEC). + * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * SMBus feature is supported by the FMPI2Cx Instance. + * @rmtoll CR1 PECEN LL_FMPI2C_EnableSMBusPEC + * @param FMPI2Cx FMPI2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_FMPI2C_EnableSMBusPEC(FMPI2C_TypeDef *FMPI2Cx) +{ + SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_PECEN); +} + +/** + * @brief Disable SMBus Packet Error Calculation (PEC). + * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * SMBus feature is supported by the FMPI2Cx Instance. + * @rmtoll CR1 PECEN LL_FMPI2C_DisableSMBusPEC + * @param FMPI2Cx FMPI2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_FMPI2C_DisableSMBusPEC(FMPI2C_TypeDef *FMPI2Cx) +{ + CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_PECEN); +} + +/** + * @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled. + * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * SMBus feature is supported by the FMPI2Cx Instance. + * @rmtoll CR1 PECEN LL_FMPI2C_IsEnabledSMBusPEC + * @param FMPI2Cx FMPI2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledSMBusPEC(FMPI2C_TypeDef *FMPI2Cx) +{ + return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_PECEN) == (FMPI2C_CR1_PECEN)) ? 1UL : 0UL); +} + +/** + * @brief Configure the SMBus Clock Timeout. + * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * SMBus feature is supported by the FMPI2Cx Instance. + * @note This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB). + * @rmtoll TIMEOUTR TIMEOUTA LL_FMPI2C_ConfigSMBusTimeout\n + * TIMEOUTR TIDLE LL_FMPI2C_ConfigSMBusTimeout\n + * TIMEOUTR TIMEOUTB LL_FMPI2C_ConfigSMBusTimeout + * @param FMPI2Cx FMPI2C Instance. + * @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF. + * @param TimeoutAMode This parameter can be one of the following values: + * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTA_MODE_SCL_LOW + * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH + * @param TimeoutB + * @retval None + */ +__STATIC_INLINE void LL_FMPI2C_ConfigSMBusTimeout(FMPI2C_TypeDef *FMPI2Cx, uint32_t TimeoutA, uint32_t TimeoutAMode, + uint32_t TimeoutB) +{ + MODIFY_REG(FMPI2Cx->TIMEOUTR, FMPI2C_TIMEOUTR_TIMEOUTA | FMPI2C_TIMEOUTR_TIDLE | FMPI2C_TIMEOUTR_TIMEOUTB, + TimeoutA | TimeoutAMode | (TimeoutB << FMPI2C_TIMEOUTR_TIMEOUTB_Pos)); +} + +/** + * @brief Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode). + * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * SMBus feature is supported by the FMPI2Cx Instance. + * @note These bits can only be programmed when TimeoutA is disabled. + * @rmtoll TIMEOUTR TIMEOUTA LL_FMPI2C_SetSMBusTimeoutA + * @param FMPI2Cx FMPI2C Instance. + * @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF. + * @retval None + */ +__STATIC_INLINE void LL_FMPI2C_SetSMBusTimeoutA(FMPI2C_TypeDef *FMPI2Cx, uint32_t TimeoutA) +{ + WRITE_REG(FMPI2Cx->TIMEOUTR, TimeoutA); +} + +/** + * @brief Get the SMBus Clock TimeoutA setting. + * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * SMBus feature is supported by the FMPI2Cx Instance. + * @rmtoll TIMEOUTR TIMEOUTA LL_FMPI2C_GetSMBusTimeoutA + * @param FMPI2Cx FMPI2C Instance. + * @retval Value between Min_Data=0 and Max_Data=0xFFF + */ +__STATIC_INLINE uint32_t LL_FMPI2C_GetSMBusTimeoutA(FMPI2C_TypeDef *FMPI2Cx) +{ + return (uint32_t)(READ_BIT(FMPI2Cx->TIMEOUTR, FMPI2C_TIMEOUTR_TIMEOUTA)); +} + +/** + * @brief Set the SMBus Clock TimeoutA mode. + * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * SMBus feature is supported by the FMPI2Cx Instance. + * @note This bit can only be programmed when TimeoutA is disabled. + * @rmtoll TIMEOUTR TIDLE LL_FMPI2C_SetSMBusTimeoutAMode + * @param FMPI2Cx FMPI2C Instance. + * @param TimeoutAMode This parameter can be one of the following values: + * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTA_MODE_SCL_LOW + * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH + * @retval None + */ +__STATIC_INLINE void LL_FMPI2C_SetSMBusTimeoutAMode(FMPI2C_TypeDef *FMPI2Cx, uint32_t TimeoutAMode) +{ + WRITE_REG(FMPI2Cx->TIMEOUTR, TimeoutAMode); +} + +/** + * @brief Get the SMBus Clock TimeoutA mode. + * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * SMBus feature is supported by the FMPI2Cx Instance. + * @rmtoll TIMEOUTR TIDLE LL_FMPI2C_GetSMBusTimeoutAMode + * @param FMPI2Cx FMPI2C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTA_MODE_SCL_LOW + * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH + */ +__STATIC_INLINE uint32_t LL_FMPI2C_GetSMBusTimeoutAMode(FMPI2C_TypeDef *FMPI2Cx) +{ + return (uint32_t)(READ_BIT(FMPI2Cx->TIMEOUTR, FMPI2C_TIMEOUTR_TIDLE)); +} + +/** + * @brief Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode). + * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * SMBus feature is supported by the FMPI2Cx Instance. + * @note These bits can only be programmed when TimeoutB is disabled. + * @rmtoll TIMEOUTR TIMEOUTB LL_FMPI2C_SetSMBusTimeoutB + * @param FMPI2Cx FMPI2C Instance. + * @param TimeoutB This parameter must be a value between Min_Data=0 and Max_Data=0xFFF. + * @retval None + */ +__STATIC_INLINE void LL_FMPI2C_SetSMBusTimeoutB(FMPI2C_TypeDef *FMPI2Cx, uint32_t TimeoutB) +{ + WRITE_REG(FMPI2Cx->TIMEOUTR, TimeoutB << FMPI2C_TIMEOUTR_TIMEOUTB_Pos); +} + +/** + * @brief Get the SMBus Extented Cumulative Clock TimeoutB setting. + * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * SMBus feature is supported by the FMPI2Cx Instance. + * @rmtoll TIMEOUTR TIMEOUTB LL_FMPI2C_GetSMBusTimeoutB + * @param FMPI2Cx FMPI2C Instance. + * @retval Value between Min_Data=0 and Max_Data=0xFFF + */ +__STATIC_INLINE uint32_t LL_FMPI2C_GetSMBusTimeoutB(FMPI2C_TypeDef *FMPI2Cx) +{ + return (uint32_t)(READ_BIT(FMPI2Cx->TIMEOUTR, FMPI2C_TIMEOUTR_TIMEOUTB) >> FMPI2C_TIMEOUTR_TIMEOUTB_Pos); +} + +/** + * @brief Enable the SMBus Clock Timeout. + * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * SMBus feature is supported by the FMPI2Cx Instance. + * @rmtoll TIMEOUTR TIMOUTEN LL_FMPI2C_EnableSMBusTimeout\n + * TIMEOUTR TEXTEN LL_FMPI2C_EnableSMBusTimeout + * @param FMPI2Cx FMPI2C Instance. + * @param ClockTimeout This parameter can be one of the following values: + * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTA + * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTB + * @arg @ref LL_FMPI2C_SMBUS_ALL_TIMEOUT + * @retval None + */ +__STATIC_INLINE void LL_FMPI2C_EnableSMBusTimeout(FMPI2C_TypeDef *FMPI2Cx, uint32_t ClockTimeout) +{ + SET_BIT(FMPI2Cx->TIMEOUTR, ClockTimeout); +} + +/** + * @brief Disable the SMBus Clock Timeout. + * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * SMBus feature is supported by the FMPI2Cx Instance. + * @rmtoll TIMEOUTR TIMOUTEN LL_FMPI2C_DisableSMBusTimeout\n + * TIMEOUTR TEXTEN LL_FMPI2C_DisableSMBusTimeout + * @param FMPI2Cx FMPI2C Instance. + * @param ClockTimeout This parameter can be one of the following values: + * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTA + * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTB + * @arg @ref LL_FMPI2C_SMBUS_ALL_TIMEOUT + * @retval None + */ +__STATIC_INLINE void LL_FMPI2C_DisableSMBusTimeout(FMPI2C_TypeDef *FMPI2Cx, uint32_t ClockTimeout) +{ + CLEAR_BIT(FMPI2Cx->TIMEOUTR, ClockTimeout); +} + +/** + * @brief Check if the SMBus Clock Timeout is enabled or disabled. + * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * SMBus feature is supported by the FMPI2Cx Instance. + * @rmtoll TIMEOUTR TIMOUTEN LL_FMPI2C_IsEnabledSMBusTimeout\n + * TIMEOUTR TEXTEN LL_FMPI2C_IsEnabledSMBusTimeout + * @param FMPI2Cx FMPI2C Instance. + * @param ClockTimeout This parameter can be one of the following values: + * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTA + * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTB + * @arg @ref LL_FMPI2C_SMBUS_ALL_TIMEOUT + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledSMBusTimeout(FMPI2C_TypeDef *FMPI2Cx, uint32_t ClockTimeout) +{ + return ((READ_BIT(FMPI2Cx->TIMEOUTR, (FMPI2C_TIMEOUTR_TIMOUTEN | FMPI2C_TIMEOUTR_TEXTEN)) == (ClockTimeout)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup FMPI2C_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable TXIS interrupt. + * @rmtoll CR1 TXIE LL_FMPI2C_EnableIT_TX + * @param FMPI2Cx FMPI2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_FMPI2C_EnableIT_TX(FMPI2C_TypeDef *FMPI2Cx) +{ + SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_TXIE); +} + +/** + * @brief Disable TXIS interrupt. + * @rmtoll CR1 TXIE LL_FMPI2C_DisableIT_TX + * @param FMPI2Cx FMPI2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_FMPI2C_DisableIT_TX(FMPI2C_TypeDef *FMPI2Cx) +{ + CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_TXIE); +} + +/** + * @brief Check if the TXIS Interrupt is enabled or disabled. + * @rmtoll CR1 TXIE LL_FMPI2C_IsEnabledIT_TX + * @param FMPI2Cx FMPI2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledIT_TX(FMPI2C_TypeDef *FMPI2Cx) +{ + return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_TXIE) == (FMPI2C_CR1_TXIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable RXNE interrupt. + * @rmtoll CR1 RXIE LL_FMPI2C_EnableIT_RX + * @param FMPI2Cx FMPI2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_FMPI2C_EnableIT_RX(FMPI2C_TypeDef *FMPI2Cx) +{ + SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_RXIE); +} + +/** + * @brief Disable RXNE interrupt. + * @rmtoll CR1 RXIE LL_FMPI2C_DisableIT_RX + * @param FMPI2Cx FMPI2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_FMPI2C_DisableIT_RX(FMPI2C_TypeDef *FMPI2Cx) +{ + CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_RXIE); +} + +/** + * @brief Check if the RXNE Interrupt is enabled or disabled. + * @rmtoll CR1 RXIE LL_FMPI2C_IsEnabledIT_RX + * @param FMPI2Cx FMPI2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledIT_RX(FMPI2C_TypeDef *FMPI2Cx) +{ + return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_RXIE) == (FMPI2C_CR1_RXIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable Address match interrupt (slave mode only). + * @rmtoll CR1 ADDRIE LL_FMPI2C_EnableIT_ADDR + * @param FMPI2Cx FMPI2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_FMPI2C_EnableIT_ADDR(FMPI2C_TypeDef *FMPI2Cx) +{ + SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_ADDRIE); +} + +/** + * @brief Disable Address match interrupt (slave mode only). + * @rmtoll CR1 ADDRIE LL_FMPI2C_DisableIT_ADDR + * @param FMPI2Cx FMPI2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_FMPI2C_DisableIT_ADDR(FMPI2C_TypeDef *FMPI2Cx) +{ + CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_ADDRIE); +} + +/** + * @brief Check if Address match interrupt is enabled or disabled. + * @rmtoll CR1 ADDRIE LL_FMPI2C_IsEnabledIT_ADDR + * @param FMPI2Cx FMPI2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledIT_ADDR(FMPI2C_TypeDef *FMPI2Cx) +{ + return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_ADDRIE) == (FMPI2C_CR1_ADDRIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable Not acknowledge received interrupt. + * @rmtoll CR1 NACKIE LL_FMPI2C_EnableIT_NACK + * @param FMPI2Cx FMPI2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_FMPI2C_EnableIT_NACK(FMPI2C_TypeDef *FMPI2Cx) +{ + SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_NACKIE); +} + +/** + * @brief Disable Not acknowledge received interrupt. + * @rmtoll CR1 NACKIE LL_FMPI2C_DisableIT_NACK + * @param FMPI2Cx FMPI2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_FMPI2C_DisableIT_NACK(FMPI2C_TypeDef *FMPI2Cx) +{ + CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_NACKIE); +} + +/** + * @brief Check if Not acknowledge received interrupt is enabled or disabled. + * @rmtoll CR1 NACKIE LL_FMPI2C_IsEnabledIT_NACK + * @param FMPI2Cx FMPI2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledIT_NACK(FMPI2C_TypeDef *FMPI2Cx) +{ + return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_NACKIE) == (FMPI2C_CR1_NACKIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable STOP detection interrupt. + * @rmtoll CR1 STOPIE LL_FMPI2C_EnableIT_STOP + * @param FMPI2Cx FMPI2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_FMPI2C_EnableIT_STOP(FMPI2C_TypeDef *FMPI2Cx) +{ + SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_STOPIE); +} + +/** + * @brief Disable STOP detection interrupt. + * @rmtoll CR1 STOPIE LL_FMPI2C_DisableIT_STOP + * @param FMPI2Cx FMPI2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_FMPI2C_DisableIT_STOP(FMPI2C_TypeDef *FMPI2Cx) +{ + CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_STOPIE); +} + +/** + * @brief Check if STOP detection interrupt is enabled or disabled. + * @rmtoll CR1 STOPIE LL_FMPI2C_IsEnabledIT_STOP + * @param FMPI2Cx FMPI2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledIT_STOP(FMPI2C_TypeDef *FMPI2Cx) +{ + return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_STOPIE) == (FMPI2C_CR1_STOPIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable Transfer Complete interrupt. + * @note Any of these events will generate interrupt : + * Transfer Complete (TC) + * Transfer Complete Reload (TCR) + * @rmtoll CR1 TCIE LL_FMPI2C_EnableIT_TC + * @param FMPI2Cx FMPI2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_FMPI2C_EnableIT_TC(FMPI2C_TypeDef *FMPI2Cx) +{ + SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_TCIE); +} + +/** + * @brief Disable Transfer Complete interrupt. + * @note Any of these events will generate interrupt : + * Transfer Complete (TC) + * Transfer Complete Reload (TCR) + * @rmtoll CR1 TCIE LL_FMPI2C_DisableIT_TC + * @param FMPI2Cx FMPI2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_FMPI2C_DisableIT_TC(FMPI2C_TypeDef *FMPI2Cx) +{ + CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_TCIE); +} + +/** + * @brief Check if Transfer Complete interrupt is enabled or disabled. + * @rmtoll CR1 TCIE LL_FMPI2C_IsEnabledIT_TC + * @param FMPI2Cx FMPI2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledIT_TC(FMPI2C_TypeDef *FMPI2Cx) +{ + return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_TCIE) == (FMPI2C_CR1_TCIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable Error interrupts. + * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * SMBus feature is supported by the FMPI2Cx Instance. + * @note Any of these errors will generate interrupt : + * Arbitration Loss (ARLO) + * Bus Error detection (BERR) + * Overrun/Underrun (OVR) + * SMBus Timeout detection (TIMEOUT) + * SMBus PEC error detection (PECERR) + * SMBus Alert pin event detection (ALERT) + * @rmtoll CR1 ERRIE LL_FMPI2C_EnableIT_ERR + * @param FMPI2Cx FMPI2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_FMPI2C_EnableIT_ERR(FMPI2C_TypeDef *FMPI2Cx) +{ + SET_BIT(FMPI2Cx->CR1, FMPI2C_CR1_ERRIE); +} + +/** + * @brief Disable Error interrupts. + * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * SMBus feature is supported by the FMPI2Cx Instance. + * @note Any of these errors will generate interrupt : + * Arbitration Loss (ARLO) + * Bus Error detection (BERR) + * Overrun/Underrun (OVR) + * SMBus Timeout detection (TIMEOUT) + * SMBus PEC error detection (PECERR) + * SMBus Alert pin event detection (ALERT) + * @rmtoll CR1 ERRIE LL_FMPI2C_DisableIT_ERR + * @param FMPI2Cx FMPI2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_FMPI2C_DisableIT_ERR(FMPI2C_TypeDef *FMPI2Cx) +{ + CLEAR_BIT(FMPI2Cx->CR1, FMPI2C_CR1_ERRIE); +} + +/** + * @brief Check if Error interrupts are enabled or disabled. + * @rmtoll CR1 ERRIE LL_FMPI2C_IsEnabledIT_ERR + * @param FMPI2Cx FMPI2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledIT_ERR(FMPI2C_TypeDef *FMPI2Cx) +{ + return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_ERRIE) == (FMPI2C_CR1_ERRIE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup FMPI2C_LL_EF_FLAG_management FLAG_management + * @{ + */ + +/** + * @brief Indicate the status of Transmit data register empty flag. + * @note RESET: When next data is written in Transmit data register. + * SET: When Transmit data register is empty. + * @rmtoll ISR TXE LL_FMPI2C_IsActiveFlag_TXE + * @param FMPI2Cx FMPI2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_TXE(FMPI2C_TypeDef *FMPI2Cx) +{ + return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_TXE) == (FMPI2C_ISR_TXE)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Transmit interrupt flag. + * @note RESET: When next data is written in Transmit data register. + * SET: When Transmit data register is empty. + * @rmtoll ISR TXIS LL_FMPI2C_IsActiveFlag_TXIS + * @param FMPI2Cx FMPI2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_TXIS(FMPI2C_TypeDef *FMPI2Cx) +{ + return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_TXIS) == (FMPI2C_ISR_TXIS)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Receive data register not empty flag. + * @note RESET: When Receive data register is read. + * SET: When the received data is copied in Receive data register. + * @rmtoll ISR RXNE LL_FMPI2C_IsActiveFlag_RXNE + * @param FMPI2Cx FMPI2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_RXNE(FMPI2C_TypeDef *FMPI2Cx) +{ + return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_RXNE) == (FMPI2C_ISR_RXNE)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Address matched flag (slave mode). + * @note RESET: Clear default value. + * SET: When the received slave address matched with one of the enabled slave address. + * @rmtoll ISR ADDR LL_FMPI2C_IsActiveFlag_ADDR + * @param FMPI2Cx FMPI2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_ADDR(FMPI2C_TypeDef *FMPI2Cx) +{ + return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_ADDR) == (FMPI2C_ISR_ADDR)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Not Acknowledge received flag. + * @note RESET: Clear default value. + * SET: When a NACK is received after a byte transmission. + * @rmtoll ISR NACKF LL_FMPI2C_IsActiveFlag_NACK + * @param FMPI2Cx FMPI2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_NACK(FMPI2C_TypeDef *FMPI2Cx) +{ + return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_NACKF) == (FMPI2C_ISR_NACKF)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Stop detection flag. + * @note RESET: Clear default value. + * SET: When a Stop condition is detected. + * @rmtoll ISR STOPF LL_FMPI2C_IsActiveFlag_STOP + * @param FMPI2Cx FMPI2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_STOP(FMPI2C_TypeDef *FMPI2Cx) +{ + return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_STOPF) == (FMPI2C_ISR_STOPF)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Transfer complete flag (master mode). + * @note RESET: Clear default value. + * SET: When RELOAD=0, AUTOEND=0 and NBYTES date have been transferred. + * @rmtoll ISR TC LL_FMPI2C_IsActiveFlag_TC + * @param FMPI2Cx FMPI2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_TC(FMPI2C_TypeDef *FMPI2Cx) +{ + return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_TC) == (FMPI2C_ISR_TC)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Transfer complete flag (master mode). + * @note RESET: Clear default value. + * SET: When RELOAD=1 and NBYTES date have been transferred. + * @rmtoll ISR TCR LL_FMPI2C_IsActiveFlag_TCR + * @param FMPI2Cx FMPI2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_TCR(FMPI2C_TypeDef *FMPI2Cx) +{ + return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_TCR) == (FMPI2C_ISR_TCR)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Bus error flag. + * @note RESET: Clear default value. + * SET: When a misplaced Start or Stop condition is detected. + * @rmtoll ISR BERR LL_FMPI2C_IsActiveFlag_BERR + * @param FMPI2Cx FMPI2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_BERR(FMPI2C_TypeDef *FMPI2Cx) +{ + return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_BERR) == (FMPI2C_ISR_BERR)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Arbitration lost flag. + * @note RESET: Clear default value. + * SET: When arbitration lost. + * @rmtoll ISR ARLO LL_FMPI2C_IsActiveFlag_ARLO + * @param FMPI2Cx FMPI2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_ARLO(FMPI2C_TypeDef *FMPI2Cx) +{ + return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_ARLO) == (FMPI2C_ISR_ARLO)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Overrun/Underrun flag (slave mode). + * @note RESET: Clear default value. + * SET: When an overrun/underrun error occurs (Clock Stretching Disabled). + * @rmtoll ISR OVR LL_FMPI2C_IsActiveFlag_OVR + * @param FMPI2Cx FMPI2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_OVR(FMPI2C_TypeDef *FMPI2Cx) +{ + return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_OVR) == (FMPI2C_ISR_OVR)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of SMBus PEC error flag in reception. + * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * SMBus feature is supported by the FMPI2Cx Instance. + * @note RESET: Clear default value. + * SET: When the received PEC does not match with the PEC register content. + * @rmtoll ISR PECERR LL_FMPI2C_IsActiveSMBusFlag_PECERR + * @param FMPI2Cx FMPI2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveSMBusFlag_PECERR(FMPI2C_TypeDef *FMPI2Cx) +{ + return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_PECERR) == (FMPI2C_ISR_PECERR)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of SMBus Timeout detection flag. + * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * SMBus feature is supported by the FMPI2Cx Instance. + * @note RESET: Clear default value. + * SET: When a timeout or extended clock timeout occurs. + * @rmtoll ISR TIMEOUT LL_FMPI2C_IsActiveSMBusFlag_TIMEOUT + * @param FMPI2Cx FMPI2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveSMBusFlag_TIMEOUT(FMPI2C_TypeDef *FMPI2Cx) +{ + return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_TIMEOUT) == (FMPI2C_ISR_TIMEOUT)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of SMBus alert flag. + * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * SMBus feature is supported by the FMPI2Cx Instance. + * @note RESET: Clear default value. + * SET: When SMBus host configuration, SMBus alert enabled and + * a falling edge event occurs on SMBA pin. + * @rmtoll ISR ALERT LL_FMPI2C_IsActiveSMBusFlag_ALERT + * @param FMPI2Cx FMPI2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveSMBusFlag_ALERT(FMPI2C_TypeDef *FMPI2Cx) +{ + return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_ALERT) == (FMPI2C_ISR_ALERT)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Bus Busy flag. + * @note RESET: Clear default value. + * SET: When a Start condition is detected. + * @rmtoll ISR BUSY LL_FMPI2C_IsActiveFlag_BUSY + * @param FMPI2Cx FMPI2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_BUSY(FMPI2C_TypeDef *FMPI2Cx) +{ + return ((READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_BUSY) == (FMPI2C_ISR_BUSY)) ? 1UL : 0UL); +} + +/** + * @brief Clear Address Matched flag. + * @rmtoll ICR ADDRCF LL_FMPI2C_ClearFlag_ADDR + * @param FMPI2Cx FMPI2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_FMPI2C_ClearFlag_ADDR(FMPI2C_TypeDef *FMPI2Cx) +{ + SET_BIT(FMPI2Cx->ICR, FMPI2C_ICR_ADDRCF); +} + +/** + * @brief Clear Not Acknowledge flag. + * @rmtoll ICR NACKCF LL_FMPI2C_ClearFlag_NACK + * @param FMPI2Cx FMPI2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_FMPI2C_ClearFlag_NACK(FMPI2C_TypeDef *FMPI2Cx) +{ + SET_BIT(FMPI2Cx->ICR, FMPI2C_ICR_NACKCF); +} + +/** + * @brief Clear Stop detection flag. + * @rmtoll ICR STOPCF LL_FMPI2C_ClearFlag_STOP + * @param FMPI2Cx FMPI2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_FMPI2C_ClearFlag_STOP(FMPI2C_TypeDef *FMPI2Cx) +{ + SET_BIT(FMPI2Cx->ICR, FMPI2C_ICR_STOPCF); +} + +/** + * @brief Clear Transmit data register empty flag (TXE). + * @note This bit can be clear by software in order to flush the transmit data register (TXDR). + * @rmtoll ISR TXE LL_FMPI2C_ClearFlag_TXE + * @param FMPI2Cx FMPI2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_FMPI2C_ClearFlag_TXE(FMPI2C_TypeDef *FMPI2Cx) +{ + WRITE_REG(FMPI2Cx->ISR, FMPI2C_ISR_TXE); +} + +/** + * @brief Clear Bus error flag. + * @rmtoll ICR BERRCF LL_FMPI2C_ClearFlag_BERR + * @param FMPI2Cx FMPI2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_FMPI2C_ClearFlag_BERR(FMPI2C_TypeDef *FMPI2Cx) +{ + SET_BIT(FMPI2Cx->ICR, FMPI2C_ICR_BERRCF); +} + +/** + * @brief Clear Arbitration lost flag. + * @rmtoll ICR ARLOCF LL_FMPI2C_ClearFlag_ARLO + * @param FMPI2Cx FMPI2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_FMPI2C_ClearFlag_ARLO(FMPI2C_TypeDef *FMPI2Cx) +{ + SET_BIT(FMPI2Cx->ICR, FMPI2C_ICR_ARLOCF); +} + +/** + * @brief Clear Overrun/Underrun flag. + * @rmtoll ICR OVRCF LL_FMPI2C_ClearFlag_OVR + * @param FMPI2Cx FMPI2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_FMPI2C_ClearFlag_OVR(FMPI2C_TypeDef *FMPI2Cx) +{ + SET_BIT(FMPI2Cx->ICR, FMPI2C_ICR_OVRCF); +} + +/** + * @brief Clear SMBus PEC error flag. + * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * SMBus feature is supported by the FMPI2Cx Instance. + * @rmtoll ICR PECCF LL_FMPI2C_ClearSMBusFlag_PECERR + * @param FMPI2Cx FMPI2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_FMPI2C_ClearSMBusFlag_PECERR(FMPI2C_TypeDef *FMPI2Cx) +{ + SET_BIT(FMPI2Cx->ICR, FMPI2C_ICR_PECCF); +} + +/** + * @brief Clear SMBus Timeout detection flag. + * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * SMBus feature is supported by the FMPI2Cx Instance. + * @rmtoll ICR TIMOUTCF LL_FMPI2C_ClearSMBusFlag_TIMEOUT + * @param FMPI2Cx FMPI2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_FMPI2C_ClearSMBusFlag_TIMEOUT(FMPI2C_TypeDef *FMPI2Cx) +{ + SET_BIT(FMPI2Cx->ICR, FMPI2C_ICR_TIMOUTCF); +} + +/** + * @brief Clear SMBus Alert flag. + * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * SMBus feature is supported by the FMPI2Cx Instance. + * @rmtoll ICR ALERTCF LL_FMPI2C_ClearSMBusFlag_ALERT + * @param FMPI2Cx FMPI2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_FMPI2C_ClearSMBusFlag_ALERT(FMPI2C_TypeDef *FMPI2Cx) +{ + SET_BIT(FMPI2Cx->ICR, FMPI2C_ICR_ALERTCF); +} + +/** + * @} + */ + +/** @defgroup FMPI2C_LL_EF_Data_Management Data_Management + * @{ + */ + +/** + * @brief Enable automatic STOP condition generation (master mode). + * @note Automatic end mode : a STOP condition is automatically sent when NBYTES data are transferred. + * This bit has no effect in slave mode or when RELOAD bit is set. + * @rmtoll CR2 AUTOEND LL_FMPI2C_EnableAutoEndMode + * @param FMPI2Cx FMPI2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_FMPI2C_EnableAutoEndMode(FMPI2C_TypeDef *FMPI2Cx) +{ + SET_BIT(FMPI2Cx->CR2, FMPI2C_CR2_AUTOEND); +} + +/** + * @brief Disable automatic STOP condition generation (master mode). + * @note Software end mode : TC flag is set when NBYTES data are transferre, stretching SCL low. + * @rmtoll CR2 AUTOEND LL_FMPI2C_DisableAutoEndMode + * @param FMPI2Cx FMPI2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_FMPI2C_DisableAutoEndMode(FMPI2C_TypeDef *FMPI2Cx) +{ + CLEAR_BIT(FMPI2Cx->CR2, FMPI2C_CR2_AUTOEND); +} + +/** + * @brief Check if automatic STOP condition is enabled or disabled. + * @rmtoll CR2 AUTOEND LL_FMPI2C_IsEnabledAutoEndMode + * @param FMPI2Cx FMPI2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledAutoEndMode(FMPI2C_TypeDef *FMPI2Cx) +{ + return ((READ_BIT(FMPI2Cx->CR2, FMPI2C_CR2_AUTOEND) == (FMPI2C_CR2_AUTOEND)) ? 1UL : 0UL); +} + +/** + * @brief Enable reload mode (master mode). + * @note The transfer is not completed after the NBYTES data transfer, NBYTES will be reloaded when TCR flag is set. + * @rmtoll CR2 RELOAD LL_FMPI2C_EnableReloadMode + * @param FMPI2Cx FMPI2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_FMPI2C_EnableReloadMode(FMPI2C_TypeDef *FMPI2Cx) +{ + SET_BIT(FMPI2Cx->CR2, FMPI2C_CR2_RELOAD); +} + +/** + * @brief Disable reload mode (master mode). + * @note The transfer is completed after the NBYTES data transfer(STOP or RESTART will follow). + * @rmtoll CR2 RELOAD LL_FMPI2C_DisableReloadMode + * @param FMPI2Cx FMPI2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_FMPI2C_DisableReloadMode(FMPI2C_TypeDef *FMPI2Cx) +{ + CLEAR_BIT(FMPI2Cx->CR2, FMPI2C_CR2_RELOAD); +} + +/** + * @brief Check if reload mode is enabled or disabled. + * @rmtoll CR2 RELOAD LL_FMPI2C_IsEnabledReloadMode + * @param FMPI2Cx FMPI2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledReloadMode(FMPI2C_TypeDef *FMPI2Cx) +{ + return ((READ_BIT(FMPI2Cx->CR2, FMPI2C_CR2_RELOAD) == (FMPI2C_CR2_RELOAD)) ? 1UL : 0UL); +} + +/** + * @brief Configure the number of bytes for transfer. + * @note Changing these bits when START bit is set is not allowed. + * @rmtoll CR2 NBYTES LL_FMPI2C_SetTransferSize + * @param FMPI2Cx FMPI2C Instance. + * @param TransferSize This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF. + * @retval None + */ +__STATIC_INLINE void LL_FMPI2C_SetTransferSize(FMPI2C_TypeDef *FMPI2Cx, uint32_t TransferSize) +{ + MODIFY_REG(FMPI2Cx->CR2, FMPI2C_CR2_NBYTES, TransferSize << FMPI2C_CR2_NBYTES_Pos); +} + +/** + * @brief Get the number of bytes configured for transfer. + * @rmtoll CR2 NBYTES LL_FMPI2C_GetTransferSize + * @param FMPI2Cx FMPI2C Instance. + * @retval Value between Min_Data=0x0 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_FMPI2C_GetTransferSize(FMPI2C_TypeDef *FMPI2Cx) +{ + return (uint32_t)(READ_BIT(FMPI2Cx->CR2, FMPI2C_CR2_NBYTES) >> FMPI2C_CR2_NBYTES_Pos); +} + +/** + * @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte. + * @note Usage in Slave mode only. + * @rmtoll CR2 NACK LL_FMPI2C_AcknowledgeNextData + * @param FMPI2Cx FMPI2C Instance. + * @param TypeAcknowledge This parameter can be one of the following values: + * @arg @ref LL_FMPI2C_ACK + * @arg @ref LL_FMPI2C_NACK + * @retval None + */ +__STATIC_INLINE void LL_FMPI2C_AcknowledgeNextData(FMPI2C_TypeDef *FMPI2Cx, uint32_t TypeAcknowledge) +{ + MODIFY_REG(FMPI2Cx->CR2, FMPI2C_CR2_NACK, TypeAcknowledge); +} + +/** + * @brief Generate a START or RESTART condition + * @note The START bit can be set even if bus is BUSY or FMPI2C is in slave mode. + * This action has no effect when RELOAD is set. + * @rmtoll CR2 START LL_FMPI2C_GenerateStartCondition + * @param FMPI2Cx FMPI2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_FMPI2C_GenerateStartCondition(FMPI2C_TypeDef *FMPI2Cx) +{ + SET_BIT(FMPI2Cx->CR2, FMPI2C_CR2_START); +} + +/** + * @brief Generate a STOP condition after the current byte transfer (master mode). + * @rmtoll CR2 STOP LL_FMPI2C_GenerateStopCondition + * @param FMPI2Cx FMPI2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_FMPI2C_GenerateStopCondition(FMPI2C_TypeDef *FMPI2Cx) +{ + SET_BIT(FMPI2Cx->CR2, FMPI2C_CR2_STOP); +} + +/** + * @brief Enable automatic RESTART Read request condition for 10bit address header (master mode). + * @note The master sends the complete 10bit slave address read sequence : + * Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address in Read direction. + * @rmtoll CR2 HEAD10R LL_FMPI2C_EnableAuto10BitRead + * @param FMPI2Cx FMPI2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_FMPI2C_EnableAuto10BitRead(FMPI2C_TypeDef *FMPI2Cx) +{ + CLEAR_BIT(FMPI2Cx->CR2, FMPI2C_CR2_HEAD10R); +} + +/** + * @brief Disable automatic RESTART Read request condition for 10bit address header (master mode). + * @note The master only sends the first 7 bits of 10bit address in Read direction. + * @rmtoll CR2 HEAD10R LL_FMPI2C_DisableAuto10BitRead + * @param FMPI2Cx FMPI2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_FMPI2C_DisableAuto10BitRead(FMPI2C_TypeDef *FMPI2Cx) +{ + SET_BIT(FMPI2Cx->CR2, FMPI2C_CR2_HEAD10R); +} + +/** + * @brief Check if automatic RESTART Read request condition for 10bit address header is enabled or disabled. + * @rmtoll CR2 HEAD10R LL_FMPI2C_IsEnabledAuto10BitRead + * @param FMPI2Cx FMPI2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledAuto10BitRead(FMPI2C_TypeDef *FMPI2Cx) +{ + return ((READ_BIT(FMPI2Cx->CR2, FMPI2C_CR2_HEAD10R) != (FMPI2C_CR2_HEAD10R)) ? 1UL : 0UL); +} + +/** + * @brief Configure the transfer direction (master mode). + * @note Changing these bits when START bit is set is not allowed. + * @rmtoll CR2 RD_WRN LL_FMPI2C_SetTransferRequest + * @param FMPI2Cx FMPI2C Instance. + * @param TransferRequest This parameter can be one of the following values: + * @arg @ref LL_FMPI2C_REQUEST_WRITE + * @arg @ref LL_FMPI2C_REQUEST_READ + * @retval None + */ +__STATIC_INLINE void LL_FMPI2C_SetTransferRequest(FMPI2C_TypeDef *FMPI2Cx, uint32_t TransferRequest) +{ + MODIFY_REG(FMPI2Cx->CR2, FMPI2C_CR2_RD_WRN, TransferRequest); +} + +/** + * @brief Get the transfer direction requested (master mode). + * @rmtoll CR2 RD_WRN LL_FMPI2C_GetTransferRequest + * @param FMPI2Cx FMPI2C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_FMPI2C_REQUEST_WRITE + * @arg @ref LL_FMPI2C_REQUEST_READ + */ +__STATIC_INLINE uint32_t LL_FMPI2C_GetTransferRequest(FMPI2C_TypeDef *FMPI2Cx) +{ + return (uint32_t)(READ_BIT(FMPI2Cx->CR2, FMPI2C_CR2_RD_WRN)); +} + +/** + * @brief Configure the slave address for transfer (master mode). + * @note Changing these bits when START bit is set is not allowed. + * @rmtoll CR2 SADD LL_FMPI2C_SetSlaveAddr + * @param FMPI2Cx FMPI2C Instance. + * @param SlaveAddr This parameter must be a value between Min_Data=0x00 and Max_Data=0x3F. + * @retval None + */ +__STATIC_INLINE void LL_FMPI2C_SetSlaveAddr(FMPI2C_TypeDef *FMPI2Cx, uint32_t SlaveAddr) +{ + MODIFY_REG(FMPI2Cx->CR2, FMPI2C_CR2_SADD, SlaveAddr); +} + +/** + * @brief Get the slave address programmed for transfer. + * @rmtoll CR2 SADD LL_FMPI2C_GetSlaveAddr + * @param FMPI2Cx FMPI2C Instance. + * @retval Value between Min_Data=0x0 and Max_Data=0x3F + */ +__STATIC_INLINE uint32_t LL_FMPI2C_GetSlaveAddr(FMPI2C_TypeDef *FMPI2Cx) +{ + return (uint32_t)(READ_BIT(FMPI2Cx->CR2, FMPI2C_CR2_SADD)); +} + +/** + * @brief Handles FMPI2Cx communication when starting transfer or during transfer (TC or TCR flag are set). + * @rmtoll CR2 SADD LL_FMPI2C_HandleTransfer\n + * CR2 ADD10 LL_FMPI2C_HandleTransfer\n + * CR2 RD_WRN LL_FMPI2C_HandleTransfer\n + * CR2 START LL_FMPI2C_HandleTransfer\n + * CR2 STOP LL_FMPI2C_HandleTransfer\n + * CR2 RELOAD LL_FMPI2C_HandleTransfer\n + * CR2 NBYTES LL_FMPI2C_HandleTransfer\n + * CR2 AUTOEND LL_FMPI2C_HandleTransfer\n + * CR2 HEAD10R LL_FMPI2C_HandleTransfer + * @param FMPI2Cx FMPI2C Instance. + * @param SlaveAddr Specifies the slave address to be programmed. + * @param SlaveAddrSize This parameter can be one of the following values: + * @arg @ref LL_FMPI2C_ADDRSLAVE_7BIT + * @arg @ref LL_FMPI2C_ADDRSLAVE_10BIT + * @param TransferSize Specifies the number of bytes to be programmed. + * This parameter must be a value between Min_Data=0 and Max_Data=255. + * @param EndMode This parameter can be one of the following values: + * @arg @ref LL_FMPI2C_MODE_RELOAD + * @arg @ref LL_FMPI2C_MODE_AUTOEND + * @arg @ref LL_FMPI2C_MODE_SOFTEND + * @arg @ref LL_FMPI2C_MODE_SMBUS_RELOAD + * @arg @ref LL_FMPI2C_MODE_SMBUS_AUTOEND_NO_PEC + * @arg @ref LL_FMPI2C_MODE_SMBUS_SOFTEND_NO_PEC + * @arg @ref LL_FMPI2C_MODE_SMBUS_AUTOEND_WITH_PEC + * @arg @ref LL_FMPI2C_MODE_SMBUS_SOFTEND_WITH_PEC + * @param Request This parameter can be one of the following values: + * @arg @ref LL_FMPI2C_GENERATE_NOSTARTSTOP + * @arg @ref LL_FMPI2C_GENERATE_STOP + * @arg @ref LL_FMPI2C_GENERATE_START_READ + * @arg @ref LL_FMPI2C_GENERATE_START_WRITE + * @arg @ref LL_FMPI2C_GENERATE_RESTART_7BIT_READ + * @arg @ref LL_FMPI2C_GENERATE_RESTART_7BIT_WRITE + * @arg @ref LL_FMPI2C_GENERATE_RESTART_10BIT_READ + * @arg @ref LL_FMPI2C_GENERATE_RESTART_10BIT_WRITE + * @retval None + */ +__STATIC_INLINE void LL_FMPI2C_HandleTransfer(FMPI2C_TypeDef *FMPI2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize, + uint32_t TransferSize, uint32_t EndMode, uint32_t Request) +{ + MODIFY_REG(FMPI2Cx->CR2, FMPI2C_CR2_SADD | FMPI2C_CR2_ADD10 | (FMPI2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - FMPI2C_CR2_RD_WRN_Pos))) | FMPI2C_CR2_START | FMPI2C_CR2_STOP | FMPI2C_CR2_RELOAD | + FMPI2C_CR2_NBYTES | FMPI2C_CR2_AUTOEND | FMPI2C_CR2_HEAD10R, + SlaveAddr | SlaveAddrSize | (TransferSize << FMPI2C_CR2_NBYTES_Pos) | EndMode | Request); +} + +/** + * @brief Indicate the value of transfer direction (slave mode). + * @note RESET: Write transfer, Slave enters in receiver mode. + * SET: Read transfer, Slave enters in transmitter mode. + * @rmtoll ISR DIR LL_FMPI2C_GetTransferDirection + * @param FMPI2Cx FMPI2C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_FMPI2C_DIRECTION_WRITE + * @arg @ref LL_FMPI2C_DIRECTION_READ + */ +__STATIC_INLINE uint32_t LL_FMPI2C_GetTransferDirection(FMPI2C_TypeDef *FMPI2Cx) +{ + return (uint32_t)(READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_DIR)); +} + +/** + * @brief Return the slave matched address. + * @rmtoll ISR ADDCODE LL_FMPI2C_GetAddressMatchCode + * @param FMPI2Cx FMPI2C Instance. + * @retval Value between Min_Data=0x00 and Max_Data=0x3F + */ +__STATIC_INLINE uint32_t LL_FMPI2C_GetAddressMatchCode(FMPI2C_TypeDef *FMPI2Cx) +{ + return (uint32_t)(READ_BIT(FMPI2Cx->ISR, FMPI2C_ISR_ADDCODE) >> FMPI2C_ISR_ADDCODE_Pos << 1); +} + +/** + * @brief Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode). + * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * SMBus feature is supported by the FMPI2Cx Instance. + * @note This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition or an Address Matched is received. + * This bit has no effect when RELOAD bit is set. + * This bit has no effect in device mode when SBC bit is not set. + * @rmtoll CR2 PECBYTE LL_FMPI2C_EnableSMBusPECCompare + * @param FMPI2Cx FMPI2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_FMPI2C_EnableSMBusPECCompare(FMPI2C_TypeDef *FMPI2Cx) +{ + SET_BIT(FMPI2Cx->CR2, FMPI2C_CR2_PECBYTE); +} + +/** + * @brief Check if the SMBus Packet Error byte internal comparison is requested or not. + * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * SMBus feature is supported by the FMPI2Cx Instance. + * @rmtoll CR2 PECBYTE LL_FMPI2C_IsEnabledSMBusPECCompare + * @param FMPI2Cx FMPI2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledSMBusPECCompare(FMPI2C_TypeDef *FMPI2Cx) +{ + return ((READ_BIT(FMPI2Cx->CR2, FMPI2C_CR2_PECBYTE) == (FMPI2C_CR2_PECBYTE)) ? 1UL : 0UL); +} + +/** + * @brief Get the SMBus Packet Error byte calculated. + * @note Macro @ref IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * SMBus feature is supported by the FMPI2Cx Instance. + * @rmtoll PECR PEC LL_FMPI2C_GetSMBusPEC + * @param FMPI2Cx FMPI2C Instance. + * @retval Value between Min_Data=0x00 and Max_Data=0xFF +*/ +__STATIC_INLINE uint32_t LL_FMPI2C_GetSMBusPEC(FMPI2C_TypeDef *FMPI2Cx) +{ + return (uint32_t)(READ_BIT(FMPI2Cx->PECR, FMPI2C_PECR_PEC)); +} + +/** + * @brief Read Receive Data register. + * @rmtoll RXDR RXDATA LL_FMPI2C_ReceiveData8 + * @param FMPI2Cx FMPI2C Instance. + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint8_t LL_FMPI2C_ReceiveData8(FMPI2C_TypeDef *FMPI2Cx) +{ + return (uint8_t)(READ_BIT(FMPI2Cx->RXDR, FMPI2C_RXDR_RXDATA)); +} + +/** + * @brief Write in Transmit Data Register . + * @rmtoll TXDR TXDATA LL_FMPI2C_TransmitData8 + * @param FMPI2Cx FMPI2C Instance. + * @param Data Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_FMPI2C_TransmitData8(FMPI2C_TypeDef *FMPI2Cx, uint8_t Data) +{ + WRITE_REG(FMPI2Cx->TXDR, Data); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup FMPI2C_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_FMPI2C_Init(FMPI2C_TypeDef *FMPI2Cx, LL_FMPI2C_InitTypeDef *FMPI2C_InitStruct); +ErrorStatus LL_FMPI2C_DeInit(FMPI2C_TypeDef *FMPI2Cx); +void LL_FMPI2C_StructInit(LL_FMPI2C_InitTypeDef *FMPI2C_InitStruct); + + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* FMPI2C1 */ + +/** + * @} + */ + +#endif /* FMPI2C_CR1_PE */ +#ifdef __cplusplus +} +#endif + +#endif /* STM32F4xx_LL_FMPI2C_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_gpio.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_gpio.h index 5cb04c5486..3f1b3a1d6e 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_gpio.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_gpio.h @@ -340,12 +340,11 @@ __STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin) * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN * @retval None */ -__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t OutputType) +__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType) { - MODIFY_REG(GPIOx->OTYPER, (GPIO_OTYPER_OT_0 << POSITION_VAL(Pin)), (OutputType << POSITION_VAL(Pin))); + MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType)); } - /** * @brief Return gpio output type for several pins on dedicated port. * @note Output type as to be set when gpio pin is in output or diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h index a1f31b3a64..2f1907fa49 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h +++ b/system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h @@ -155,7 +155,7 @@ typedef struct typedef struct { - uint8_t dev_addr ; /*!< USB device address. + uint8_t dev_addr; /*!< USB device address. This parameter must be a number between Min_Data = 1 and Max_Data = 255 */ uint8_t ch_num; /*!< Host channel number. @@ -199,10 +199,10 @@ typedef struct uint32_t ErrCnt; /*!< Host channel error count.*/ - USB_OTG_URBStateTypeDef urb_state; /*!< URB state. + USB_OTG_URBStateTypeDef urb_state; /*!< URB state. This parameter can be any value of @ref USB_OTG_URBStateTypeDef */ - USB_OTG_HCStateTypeDef state; /*!< Host Channel state. + USB_OTG_HCStateTypeDef state; /*!< Host Channel state. This parameter can be any value of @ref USB_OTG_HCStateTypeDef */ } USB_OTG_HCTypeDef; #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ @@ -237,11 +237,11 @@ typedef struct /** @defgroup USB_LL Device Speed * @{ */ -#define USBD_HS_SPEED 0U -#define USBD_HSINFS_SPEED 1U -#define USBH_HS_SPEED 0U -#define USBD_FS_SPEED 2U -#define USBH_FS_SPEED 1U +#define USBD_HS_SPEED 0U +#define USBD_HSINFS_SPEED 1U +#define USBH_HS_SPEED 0U +#define USBD_FS_SPEED 2U +#define USBH_FSLS_SPEED 1U /** * @} */ @@ -269,11 +269,11 @@ typedef struct * @{ */ #ifndef USBD_HS_TRDT_VALUE -#define USBD_HS_TRDT_VALUE 9U +#define USBD_HS_TRDT_VALUE 9U #endif /* USBD_HS_TRDT_VALUE */ #ifndef USBD_FS_TRDT_VALUE -#define USBD_FS_TRDT_VALUE 5U -#define USBD_DEFAULT_TRDT_VALUE 9U +#define USBD_FS_TRDT_VALUE 5U +#define USBD_DEFAULT_TRDT_VALUE 9U #endif /* USBD_HS_TRDT_VALUE */ /** * @} @@ -282,9 +282,9 @@ typedef struct /** @defgroup USB_LL_Core_MPS USB Low Layer Core MPS * @{ */ -#define USB_OTG_HS_MAX_PACKET_SIZE 512U -#define USB_OTG_FS_MAX_PACKET_SIZE 64U -#define USB_OTG_MAX_EP0_SIZE 64U +#define USB_OTG_HS_MAX_PACKET_SIZE 512U +#define USB_OTG_FS_MAX_PACKET_SIZE 64U +#define USB_OTG_MAX_EP0_SIZE 64U /** * @} */ @@ -294,7 +294,6 @@ typedef struct */ #define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ (0U << 1) #define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ (1U << 1) -#define DSTS_ENUMSPD_LS_PHY_6MHZ (2U << 1) #define DSTS_ENUMSPD_FS_PHY_48MHZ (3U << 1) /** * @} @@ -403,7 +402,7 @@ typedef struct #define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)(USBx_BASE + USB_OTG_HOST_CHANNEL_BASE + ((i) * USB_OTG_HOST_CHANNEL_SIZE))) #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ -#define EP_ADDR_MSK 0xFU +#define EP_ADDR_MSK 0xFU /** * @} */ @@ -468,13 +467,9 @@ HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx); HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state); uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef *USBx); uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, - uint8_t ch_num, - uint8_t epnum, - uint8_t dev_address, - uint8_t speed, - uint8_t ep_type, - uint16_t mps); +HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, + uint8_t epnum, uint8_t dev_address, uint8_t speed, + uint8_t ep_type, uint16_t mps); HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma); uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx); HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num); diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Release_Notes.html b/system/Drivers/STM32F4xx_HAL_Driver/Release_Notes.html index 83e7e4ddfe..ff1f1d4dac 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Release_Notes.html +++ b/system/Drivers/STM32F4xx_HAL_Driver/Release_Notes.html @@ -23,6 +23,11 @@ + + + + + @@ -907,8 +912,7 @@ - - +
@@ -940,8 +944,61 @@

@@ -688,8 +689,138 @@

-

Update History

-

V1.7.7 / 06-December-2019

+

Update History

+ +

V1.7.8 / 12-February-2020

+ + +

Main +Changes

+ + + + + +
    +
  • Add new HAL FMPSMBUS and LL FMPI2C drivers
    • +
  • General updates to fix known defects and + enhancements implementation
    • +
+
    +
  • Update HAL CRYP driver to support block by block decryption without reinitializes the IV and KEY for each call.
    • +
  • Improve code quality by fixing MisraC-2012 violations
    +
    +
    • +
  • HAL/LL USB update
      • +
    •  Add handling USB host babble error interrupt
      • +
    •  Fix Enabling ULPI interface for platforms that integrates USB HS PHY
      • +
    •  Fix Host data toggling for IN Iso transfers
      • +
    •  Ensure to disable USB EP during endpoint deactivation
      +
      • +
  • HAL CRYP update
      • +
    •  Update HAL CRYP driver to support block by block decryption without initializing the IV and KEY at each call.
      +
      • +
        +
      • Add new CRYP Handler parameters: "KeyIVConfig" and "SizesSum"
        • +
      • Add new CRYP init parameter: "KeyIVConfigSkip"
        +
        • +
      +
  • HAL I2S update
    • +
      +
    • Update HAL_I2S_DMAStop() API to be more safe
      • +
        +
      • Add a check on BSY, TXE and RXNE flags before disabling the I2S
        • +
      +
    • Update HAL_I2S_DMAStop() API to fix multi-call transfer issue(to avoid re-initializing the I2S for the next transfer).
      +
      • +
        +
      • Add __HAL_I2SEXT_FLUSH_RX_DR() and __HAL_I2S_FLUSH_RX_DR() macros to flush the remaining data inside DR registers.
        • +
      • Add new ErrorCode define: HAL_I2S_ERROR_BUSY_LINE_RX
        +
        • +
      +
    + +
+ +

V1.7.7 / 06-December-2019

+

Main Changes

@@ -1019,7 +1076,7 @@

HAL NAND update
  • Update HAL_NAND_Write_Page_8b(), HAL_NAND_Write_Page_16b() and  HAL_NAND_Write_SpareArea_16b() to manage correctly the time out -condition.
  • HAL SAI update
    • Optimize SAI_DMATxCplt() and SAI_DMARxCplt() APIs to check on "Mode" parameter instead of CIRC bit in the CR register.
    • Remove unused SAI_FIFO_SIZE define
    • Update HAL_SAI_Receive_DMA() programming sequence to be inline with reference manual

    V1.7.6 / 12-April-2019

    +condition.
  • HAL SAI update
    • Optimize SAI_DMATxCplt() and SAI_DMARxCplt() APIs to check on "Mode" parameter instead of CIRC bit in the CR register.
    • Remove unused SAI_FIFO_SIZE define
    • Update HAL_SAI_Receive_DMA() programming sequence to be inline with reference manual

    V1.7.6 / 12-April-2019

    Main Changes

    @@ -1044,7 +1101,7 @@

    V1.7.5 / 08-February-2019

    +

    V1.7.5 / 08-February-2019

    Main Changes

    @@ -1436,9 +1493,9 @@

    -

    V1.7.4 / 02-February-2018

    Main +

    V1.7.4 / 02-February-2018

    Main Changes

    • General updates -to fix known defects and enhancements implementation
    • HAL update
      • Update UNUSED() macro implementation to avoid GCC warning
        • The warning is detected when the UNUSED() macro is called from C++ file
      • Update to make RAMFUNC define as generic type instead of HAL_StatusTypdef type.
    • HAL FLASH update
      • Update the prototypes of the following APIs after change on RAMFUNC defines 
        • HAL_FLASHEx_StopFlashInterfaceClk()
        • HAL_FLASHEx_StartFlashInterfaceClk()
        • HAL_FLASHEx_EnableFlashSleepMode()
        • HAL_FLASHEx_DisableFlashSleepMode()
    • HAL SAI update
      • Update HAL_SAI_DMAStop() and HAL_SAI_Abort() process to fix the lock/unlock audio issue

    V1.7.3 / 22-December-2017

    Main +to fix known defects and enhancements implementation

  • HAL update
    • Update UNUSED() macro implementation to avoid GCC warning
      • The warning is detected when the UNUSED() macro is called from C++ file
    • Update to make RAMFUNC define as generic type instead of HAL_StatusTypdef type.
  • HAL FLASH update
    • Update the prototypes of the following APIs after change on RAMFUNC defines 
      • HAL_FLASHEx_StopFlashInterfaceClk()
      • HAL_FLASHEx_StartFlashInterfaceClk()
      • HAL_FLASHEx_EnableFlashSleepMode()
      • HAL_FLASHEx_DisableFlashSleepMode()
  • HAL SAI update
    • Update HAL_SAI_DMAStop() and HAL_SAI_Abort() process to fix the lock/unlock audio issue

    V1.7.3 / 22-December-2017

    Main Changes

    • General updates to fix known defects and enhancements implementation
    • The following changes done on the HAL drivers require an update on the application code based on older HAL versions
      • Rework of HAL CAN driver (compatibility break) 
        • A new HAL CAN driver has been redesigned with new APIs, to bypass @@ -1470,7 +1527,7 @@

          Ensure reset of CIR and CSR registers when issuing HAL_RCC_DeInit()/LL_RCC_DeInit functions

        • Update HAL_RCC_OscConfig() to keep backup domain enabled when configuring respectively LSE and RTC clock source
        • Add new HAL interfaces allowing to control the activation or deactivation of PLLI2S and PLLSAI:
          • HAL_RCCEx_EnablePLLI2S()
          • HAL_RCCEx_DisablePLLI2S()
          • HAL_RCCEx_EnablePLLSAI()
          • HAL_RCCEx_DisablePLLSAI()
      • LL RCC update 
        • Add new LL RCC macro
          • LL_RCC_PLL_SetMainSource() allowing to configure PLL main clock source
      • LL FMC / LL FSMC update
        • Add clear of the PTYP bit to select the PCARD mode in FMC_PCCARD_Init() / FSMC_PCCARD_Init()
      -

      V1.7.2 / 06-October-2017

      Main +

      V1.7.2 / 06-October-2017

      Main Changes

      • General updates to fix known defects and enhancements implementation
      • Fix compilation warning with GCC compiler
      • Remove Date and version from header files
      • Update HAL drivers to refer to the new CMSIS bit position defines instead of usage the POSITION_VAL() macro
      • HAL Generic update
        • stm32f4xx_hal_def.h file changes: 
          • Update __weak and __packed defined values for ARM compiler
          • Update __ALIGN_BEGIN and __ALIGN_END defined values for ARM compiler
        • stm32f4xx_ll_system.h file: add LL_SYSCFG_REMAP_SDRAM define
      • HAL ADC update
        • Fix wrong definition of ADC channel temperature sensor for STM32F413xx and STM32F423xx devices.
      • HAL DMA update
        • Update values for the following defines: DMA_FLAG_FEIF0_4 and DMA_FLAG_DMEIF0_4 
      • HAL DSI update
        • Fix Extra warning with SW4STM32 compiler
        • Fix DSI display issue when using EWARM w/ high level optimization 
        • Fix MISRAC errors
      • HAL FLASH update
        • HAL_FLASH_Unlock() update to return state error when the FLASH is already unlocked
      • HAL FMPI2C update
        • Update Interface APIs headers to remove confusing message about device address
        • Update @@ -1501,7 +1558,7 @@

          • HAL RNG update
            • HAL_RNG_Init() remove Lock()/Unlock()
          • HAL MMC update
            • HAL_MMC_Erase() API: add missing () to fix compilation warning detected with SW4STM32 when extra feature is enabled.
          • HAL RTC update
            • HAL_RTC_Init() API: update to force the wait for synchro before setting TAFCR register when BYPSHAD bit in CR register is 0.
          • HAL SAI update
            • Update HAL_SAI_DMAStop() API to flush fifo after disabling SAI
          • HAL I2S update
            • Update I2S DMA fullduplex process to handle I2S Rx and Tx DMA Half transfer complete callback
          • HAL TIM update
            • Update HAL_TIMEx_OCN_xxxx() and HAL_TIMEx_PWMN_xxx() API description to remove support of TIM_CHANNEL_4
          • LL DMA update
            • Update to clear DMA flags using WRITE_REG() instead SET_REG() API to avoid read access to the IFCR register that is write only.
          • LL RTC update
            • Fix warning with static analyzer
          • LL USART update
            • Add assert macros to check USART BaudRate register
          • LL I2C update
            • Rename IS_I2C_CLOCK_SPEED() and IS_I2C_DUTY_CYCLE() respectively to IS_LL_I2C_CLOCK_SPEED() and - IS_LL_I2C_DUTY_CYCLE() to avoid incompatible macros redefinition.
          • LL TIM update
            • Update LL_TIM_EnableUpdateEvent() API to clear UDIS bit in TIM CR1 register instead of setting it.
            • Update LL_TIM_DisableUpdateEvent() API to set UDIS bit in TIM CR1 register instead of clearing it.
          • LL USART update
            • Fix MISRA error w/ IS_LL_USART_BRR() macro
            • Fix wrong check when UART10 instance is used

          V1.7.1 / 14-April-2017

          Main + IS_LL_I2C_DUTY_CYCLE() to avoid incompatible macros redefinition.

      • LL TIM update
        • Update LL_TIM_EnableUpdateEvent() API to clear UDIS bit in TIM CR1 register instead of setting it.
        • Update LL_TIM_DisableUpdateEvent() API to set UDIS bit in TIM CR1 register instead of clearing it.
      • LL USART update
        • Fix MISRA error w/ IS_LL_USART_BRR() macro
        • Fix wrong check when UART10 instance is used

      V1.7.1 / 14-April-2017

      Main Changes

      • Update CHM UserManuals to support LL drivers
      • General updates @@ -1515,7 +1572,7 @@

      • HAL PWR update
        • HAL_PWREx_EnterUnderDriveSTOPMode() API: remove check on UDRDY flag

      • LL ADC update
        • Fix wrong ADC group injected sequence configuration
          • LL_ADC_INJ_SetSequencerRanks() and LL_ADC_INJ_GetSequencerRanks() API's update to take in -consideration the ADC number of conversions
          • Update the defined values for ADC group injected seqencer ranks 

      V1.7.0 / 17-February-2017

      Main +consideration the ADC number of conversions

      • Update the defined values for ADC group injected seqencer ranks 

    V1.7.0 / 17-February-2017

    Main Changes

    • Add Low Layer drivers allowing performance and footprint optimization
      • Low @@ -1541,10 +1598,10 @@

        I2S clock input frequency calculation to HAL RCC driver.

      • Update the HAL I2SEx driver to keep only full duplex feature.
      • HAL_I2S_Init() API updated to
        • Fix wrong I2S clock calculation when PCM mode is used.
        • Return state HAL_I2S_ERROR_PRESCALER when the I2S clock is wrongly configured
    -
    • HAL LTDC update
      • Optimize HAL_LTDC_IRQHandler() function by using direct register read
      • Rename the following API's
        • HAL_LTDC_Relaod() by HAL_LTDC_Reload() 
        • HAL_LTDC_StructInitFromVideoConfig() by HAL_LTDCEx_StructInitFromVideoConfig()
        • HAL_LTDC_StructInitFromAdaptedCommandConfig() by HAL_LTDCEx_StructInitFromAdaptedCommandConfig()
      • Add new defines for LTDC layers (LTDC_LAYER_1 / LTDC_LAYER_2)
      • Remove unused asserts
    • HAL USB PCD update
      • Flush all TX FIFOs on USB Reset
      • Remove Lock mechanism from HAL_PCD_EP_Transmit() and HAL_PCD_EP_Receive() API's
    • LL USB update
      • Enable DMA Burst mode for USB OTG HS
      • Fix SD card detection issue
    • LL SDMMC update
      • Add new SDMMC_CmdSDEraseStartAdd, SDMMC_CmdSDEraseEndAdd, SDMMC_CmdOpCondition and SDMMC_CmdSwitch functions

    V1.6.0 / 04-November-2016

    Main +

    • HAL LTDC update
      • Optimize HAL_LTDC_IRQHandler() function by using direct register read
      • Rename the following API's
        • HAL_LTDC_Relaod() by HAL_LTDC_Reload() 
        • HAL_LTDC_StructInitFromVideoConfig() by HAL_LTDCEx_StructInitFromVideoConfig()
        • HAL_LTDC_StructInitFromAdaptedCommandConfig() by HAL_LTDCEx_StructInitFromAdaptedCommandConfig()
      • Add new defines for LTDC layers (LTDC_LAYER_1 / LTDC_LAYER_2)
      • Remove unused asserts
    • HAL USB PCD update
      • Flush all TX FIFOs on USB Reset
      • Remove Lock mechanism from HAL_PCD_EP_Transmit() and HAL_PCD_EP_Receive() API's
    • LL USB update
      • Enable DMA Burst mode for USB OTG HS
      • Fix SD card detection issue
    • LL SDMMC update
      • Add new SDMMC_CmdSDEraseStartAdd, SDMMC_CmdSDEraseEndAdd, SDMMC_CmdOpCondition and SDMMC_CmdSwitch functions

    V1.6.0 / 04-November-2016

    Main Changes

    -
    • Add support of STM32F413xx and STM32F423xx devices
    • General updates to fix known defects and enhancements implementation
    • HAL CAN update
      • Update to add the support of 3 CAN management
    • HAL CRYP update
      • Update to add the support of AES features
    • HAL DFSDM update
      • Add definitions for new external trigger filters
      • Add definition for new Channels 4, 5, 6 and 7
      • Add functions and API for Filter state configuration and management
      • Add new functions: 
        • HAL_DFSDM_BitstreamClock_Start()
        • HAL_DFSDM_BitstreamClock_Stop()
        • HAL_DFSDM_BitStreamClkDistribution_Config() 
    • HAL DMA
      • Add the support of DMA Channels from 8 to 15
      • Update HAL_DMA_DeInit() function with the check on DMA stream instance
    • HAL DSI update
      • Update HAL_DSI_ConfigHostTimeouts() and HAL_DSI_Init() functions to avoid scratch in DSI_CCR register
    • HAL FLASH update
      • Enhance FLASH_WaitForLastOperation() function implementation
      • Update __HAL_FLASH_GET_FLAG() macro implementation
    • HAL GPIO update
      • Add specific alternate functions definitions
    • HAL I2C update
      • Update I2C_DMAError() function implementation to ignore DMA FIFO error
    • HAL I2S update
      • Enhance HAL_I2S_Init() implementation to test on PCM_SHORT and PCM_LONG standards
    • HAL IRDA update
      • Add new functions and call backs for Transfer Abort
        • HAL_IRDA_Abort()
        • HAL_IRDA_AbortTransmit()
        • HAL_IRDA_AbortReceive()
        • HAL_IRDA_Abort_IT()
        • HAL_IRDA_AbortTransmit_IT()
        • HAL_IRDA_AbortReceive_IT()
        • HAL_IRDA_AbortCpltCallback()
        • HAL_IRDA_AbortTransmitCpltCallback()
        • HAL_IRDA_AbortReceiveCpltCallback()
    • HAL PCD update
      • Update HAL_PCD_GetRxCount()  function implementation
    • HAL RCC update
      • Update __HAL_RCC_HSE_CONFIG() macro implementation
      • Update __HAL_RCC_LSE_CONFIG() macro implementation
    • HAL SMARTCARD update
      • Add new functions and call backs for Transfer Abort
        • HAL_ SMARTCARD_Abort()
        • HAL_ SMARTCARD_AbortTransmit()
        • HAL_ SMARTCARD_AbortReceive()
        • HAL_ SMARTCARD_Abort_IT()
        • HAL_ SMARTCARD_AbortTransmit_IT()
        • HAL_ SMARTCARD_AbortReceive_IT()
        • HAL_ SMARTCARD_AbortCpltCallback()
        • HAL_ SMARTCARD_AbortTransmitCpltCallback()
        • HAL_ SMARTCARD_AbortReceiveCpltCallback()
    • HAL TIM update
      • Update HAL_TIMEx_RemapConfig() function to manage TIM internal trigger remap: LPTIM or TIM3_TRGO
    • HAL UART update
      • Add Transfer abort functions and callbacks
    • HAL USART update
      • Add Transfer abort functions and callbacks

    V1.5.2 / 22-September-2016

    Main +

    • Add support of STM32F413xx and STM32F423xx devices
    • General updates to fix known defects and enhancements implementation
    • HAL CAN update
      • Update to add the support of 3 CAN management
    • HAL CRYP update
      • Update to add the support of AES features
    • HAL DFSDM update
      • Add definitions for new external trigger filters
      • Add definition for new Channels 4, 5, 6 and 7
      • Add functions and API for Filter state configuration and management
      • Add new functions: 
        • HAL_DFSDM_BitstreamClock_Start()
        • HAL_DFSDM_BitstreamClock_Stop()
        • HAL_DFSDM_BitStreamClkDistribution_Config() 
    • HAL DMA
      • Add the support of DMA Channels from 8 to 15
      • Update HAL_DMA_DeInit() function with the check on DMA stream instance
    • HAL DSI update
      • Update HAL_DSI_ConfigHostTimeouts() and HAL_DSI_Init() functions to avoid scratch in DSI_CCR register
    • HAL FLASH update
      • Enhance FLASH_WaitForLastOperation() function implementation
      • Update __HAL_FLASH_GET_FLAG() macro implementation
    • HAL GPIO update
      • Add specific alternate functions definitions
    • HAL I2C update
      • Update I2C_DMAError() function implementation to ignore DMA FIFO error
    • HAL I2S update
      • Enhance HAL_I2S_Init() implementation to test on PCM_SHORT and PCM_LONG standards
    • HAL IRDA update
      • Add new functions and call backs for Transfer Abort
        • HAL_IRDA_Abort()
        • HAL_IRDA_AbortTransmit()
        • HAL_IRDA_AbortReceive()
        • HAL_IRDA_Abort_IT()
        • HAL_IRDA_AbortTransmit_IT()
        • HAL_IRDA_AbortReceive_IT()
        • HAL_IRDA_AbortCpltCallback()
        • HAL_IRDA_AbortTransmitCpltCallback()
        • HAL_IRDA_AbortReceiveCpltCallback()
    • HAL PCD update
      • Update HAL_PCD_GetRxCount()  function implementation
    • HAL RCC update
      • Update __HAL_RCC_HSE_CONFIG() macro implementation
      • Update __HAL_RCC_LSE_CONFIG() macro implementation
    • HAL SMARTCARD update
      • Add new functions and call backs for Transfer Abort
        • HAL_ SMARTCARD_Abort()
        • HAL_ SMARTCARD_AbortTransmit()
        • HAL_ SMARTCARD_AbortReceive()
        • HAL_ SMARTCARD_Abort_IT()
        • HAL_ SMARTCARD_AbortTransmit_IT()
        • HAL_ SMARTCARD_AbortReceive_IT()
        • HAL_ SMARTCARD_AbortCpltCallback()
        • HAL_ SMARTCARD_AbortTransmitCpltCallback()
        • HAL_ SMARTCARD_AbortReceiveCpltCallback()
    • HAL TIM update
      • Update HAL_TIMEx_RemapConfig() function to manage TIM internal trigger remap: LPTIM or TIM3_TRGO
    • HAL UART update
      • Add Transfer abort functions and callbacks
    • HAL USART update
      • Add Transfer abort functions and callbacks

    V1.5.2 / 22-September-2016

    Main Changes

    • HAL I2C update
      • Fix wrong @@ -1553,7 +1610,7 @@

        Update I2C API's (Polling, IT and DMA interfaces) to manage I2C XferSize and XferCount handle parameters instead of API size parameter to help user to get information of counter in case of error. 

      • Update Abort functionality to manage DMA use -case

    • HAL FMPI2C update
      • Update to disable Own Address before setting the new Own Address configuration:
        • Update HAL_FMPI2C_Init() to disable FMPI2C_OARx_EN bit before any configuration in OARx registers
    • HAL CAN update
      • Update CAN receive processes to set CAN RxMsg FIFONumber parameter
    • HAL UART update
      • Update UART handle TxXferCount and RxXferCount parameters as volatile to avoid eventual issue with High Speed optimization  

    V1.5.1 / 01-July-2016

    Main +case

  • HAL FMPI2C update
    • Update to disable Own Address before setting the new Own Address configuration:
      • Update HAL_FMPI2C_Init() to disable FMPI2C_OARx_EN bit before any configuration in OARx registers
  • HAL CAN update
    • Update CAN receive processes to set CAN RxMsg FIFONumber parameter
  • HAL UART update
    • Update UART handle TxXferCount and RxXferCount parameters as volatile to avoid eventual issue with High Speed optimization  

    V1.5.1 / 01-July-2016

    Main Changes

    • HAL GPIO update
      • HAL_GPIO_Init()/HAL_GPIO_DeInit() API's: update GPIO_GET_INDEX() macro implementation to support all GPIO's
    • HAL SPI update
      • Fix regression issue: retore HAL_SPI_DMAPause() and HAL_SPI_DMAResume() API's
    • HAL RCC update
      • Fix FSMC macros compilation warnings with STM32F412Rx devices
    • HAL DMA update
      • HAL_DMA_PollFortransfer() API clean up
    • HAL PPP update(PPP refers to IRDA, UART, USART and SMARTCARD)
      • Update HAL_PPP_IRQHandler() to add a check on interrupt source before managing the error 
    @@ -1562,7 +1619,7 @@

  • HAL QSPI update
    • Implement workaround to fix the limitation pronounced in the Errata sheet 2.1.8 section: In some specific cases, DMA2 data corruption -occurs when managing AHB and APB2 peripherals in a concurrent way

    V1.5.0 / 06-May-2016

    +occurs when managing AHB and APB2 peripherals in a concurrent way

    V1.5.0 / 06-May-2016

    Main Changes

    @@ -1613,7 +1670,7 @@

    to provide the possibility to convert VrefInt channel when both VrefInt and Vbat channels are selected.
  • HAL SPDIFRX update
    • Overall driver update for wait on flag management optimization 
  • HAL WWDG update 
    • Overall rework of the driver for more efficient implementation
      • Remove the following APIs:
        • HAL_WWDG_Start()
        • HAL_WWDG_Start_IT()
        • HAL_WWDG_MspDeInit()
        • HAL_WWDG_GetState()
      • Update implementation:
        • HAL_WWDG_Init()
          • A new parameter in the Init Structure: EWIMode
        • HAL_WWDG_MspInit()
        • HAL_WWDG_Refresh() 
          • This function insures the reload of the counter
          • The "counter" parameter has been removed
        • HAL_WWDG_IRQHandler()
        • HAL_WWDG_EarlyWakeupCallback() is the new prototype of HAL_WWDG_WakeUpCallback()
    • Refer to the following example to identify the changes: WWDG_Example
    -

    V1.4.4 / 22-January-2016

    +

    V1.4.4 / 22-January-2016

    Main Changes

    • @@ -1825,11 +1882,11 @@

      Update the FSMC_NORSRAM_Init() function to use -BurstAccessMode field properly


    V1.4.4 / 11-December-2015

    Main +BurstAccessMode field properly

    V1.4.4 / 11-December-2015

    Main Changes
    • HAL Generic update
      • Update HAL weak empty callbacks to prevent unused argument compilation warnings with some compilers by calling the following line: -
        • UNUSED(hppp);
      • STM32Fxxx_User_Manual.chm files regenerated for HAL V1.4.3
    • HAL ETH update 
      • Update HAL_ETH_Init() function to add timeout on the Software reset management

    V1.4.2 / 10-November-2015

    +
    • UNUSED(hppp);
  • STM32Fxxx_User_Manual.chm files regenerated for HAL V1.4.3
  • HAL ETH update 
    • Update HAL_ETH_Init() function to add timeout on the Software reset management

    V1.4.2 / 10-November-2015

    Main Changes

    @@ -1842,7 +1899,7 @@

    UNUSED(hppp);
    • HAL CORTEX update
      • Remove duplication for __HAL_CORTEX_SYSTICKCLK_CONFIG() macro
    • HAL HASH update
      • Rename HAL_HASH_STATETypeDef to HAL_HASH_StateTypeDef
      • Rename HAL_HASH_PhaseTypeDef to HAL_HASH_PhaseTypeDef
    • HAL RCC update
      • Add new macros __HAL_RCC_PPP_IS_CLK_ENABLED() to check on Clock enable/disable status
      • Update __HAL_RCC_USB_OTG_FS_CLK_DISABLE() macro to remove the disable for the SYSCFG
      • Update HAL_RCC_MCOConfig() API to use new defines for the GPIO Speed
      • Generic update to improve the PLL VCO min value(100MHz): PLLN, PLLI2S and PLLSAI min value is 50 instead of 192
    • HAL FLASH update
      • __HAL_FLASH_INSTRUCTION_CACHE_RESET() macro: update to reset  ICRST bit in the ACR register after setting it.
      • Update to support until 15 FLASH wait state (FLASH_LATENCY_15) for STM32F446xx devices
    • -

      HAL CRYP update

      • Update HAL_CRYP_DESECB_Decrypt() API to fix the inverted pPlainData and pCypherData parameters issue
    • HAL I2S update
      • Update HAL_I2S_Init() API to call __HAL_RCC_I2S_CONFIG() macro when external I2S clock is selected
    • HAL LTDC update
      • Update HAL_LTDC_SetWindowPosition() API to configure Immediate reload register instead of vertical blanking reload register.
    • HAL TIM update
      • Update HAL_TIM_ConfigClockSource() API to check only the required parameters
    • HAL NAND update
      • Update HAL_NAND_Read_Page()/HAL_NAND_Write_Page()/HAL_NAND_Read_SpareArea() APIs to manage correctly the NAND Page access
    • HAL CAN update
      • Update to use "=" instead of "|=" to clear flags in the MSR, TSR, RF0R and RF1R registers
    • HAL HCD update
      • Fix typo in __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() macro implementation
    • HAL PCD update
      • Update HAL_PCD_IRQHandler() API to avoid issue when DMA mode enabled for Status Phase IN stage
    • LL FMC update
      • Update the FMC_NORSRAM_Extended_Timing_Init() API to remove the check on CLKDIvison and DataLatency parameters
      • Update the FMC_NORSRAM_Init() API to add a check on the PageSize parameter for STM32F42/43xx devices
    • LL FSMC update
      • Update the FSMC_NORSRAM_Extended_Timing_Init() API to remove the check on CLKDIvison and DataLatency parameters

    V1.4.1 / 09-October-2015

    +

    HAL CRYP update

    • Update HAL_CRYP_DESECB_Decrypt() API to fix the inverted pPlainData and pCypherData parameters issue
  • HAL I2S update
    • Update HAL_I2S_Init() API to call __HAL_RCC_I2S_CONFIG() macro when external I2S clock is selected
  • HAL LTDC update
    • Update HAL_LTDC_SetWindowPosition() API to configure Immediate reload register instead of vertical blanking reload register.
  • HAL TIM update
    • Update HAL_TIM_ConfigClockSource() API to check only the required parameters
  • HAL NAND update
    • Update HAL_NAND_Read_Page()/HAL_NAND_Write_Page()/HAL_NAND_Read_SpareArea() APIs to manage correctly the NAND Page access
  • HAL CAN update
    • Update to use "=" instead of "|=" to clear flags in the MSR, TSR, RF0R and RF1R registers
  • HAL HCD update
    • Fix typo in __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() macro implementation
  • HAL PCD update
    • Update HAL_PCD_IRQHandler() API to avoid issue when DMA mode enabled for Status Phase IN stage
  • LL FMC update
    • Update the FMC_NORSRAM_Extended_Timing_Init() API to remove the check on CLKDIvison and DataLatency parameters
    • Update the FMC_NORSRAM_Init() API to add a check on the PageSize parameter for STM32F42/43xx devices
  • LL FSMC update
    • Update the FSMC_NORSRAM_Extended_Timing_Init() API to remove the check on CLKDIvison and DataLatency parameters

    V1.4.1 / 09-October-2015

    Main Changes

    @@ -1859,7 +1916,7 @@

    Update DSI_HS_PM_ENABLE define value
  • Implement workaround for the hardware limitation: �The time to activate the clock -between HS transmissions is not calculated correctly�

    • V1.4.0 / 14-August-2015

    +between HS transmissions is not calculated correctly�

    V1.4.0 / 14-August-2015

    Main Changes

    @@ -1876,7 +1933,7 @@

    STM32F469xx and STM32F479xx devices
    • HAL RTC update
      • Update HAL_RTCEx_SetWakeUpTimer() and HAL_RTCEx_SetWakeUpTimer_IT() functions to properly check on the WUTWF flag
    • HAL TIM update
      • add new defines TIM_SYSTEMBREAKINPUT_HARDFAULT,  TIM_SYSTEMBREAKINPUT_PVD and TIM_SYSTEMBREAKINPUT_HARDFAULT_PVD, -applicable only to STM32F410xx devices

    V1.3.2 / 26-June-2015

    +applicable only to STM32F410xx devices

    V1.3.2 / 26-June-2015

    Main Changes

    @@ -1897,7 +1954,7 @@

    HAL FLASH update
    • FLASH_OB_GetRDP() API update to return uint8_t instead of FlagStatus
    •  __HAL_FLASH_GET_LATENCY() new macro add to get the flash latency
  • HAL SPI update
    • Fix the wrong definition of HAL_SPI_ERROR_FLAG literal
  • HAL I2S update
    • HAL_I2S_Transmit() API update to check on busy flag only for I2S slave mode
  • HAL CRC update
    • __HAL_CRC_SET_IDR() macro implementation change to use WRITE_REG() instead of MODIFY_REG()
  • HAL DMA2D update
    • HAL_DMA2D_ConfigLayer() API update to use "=" instead of "|=" to erase BGCOLR and FGCOLR registers before setting the new configuration
  • HAL HASH update
    • HAL_HASH_MODE_Start_IT() (MODE stands for MD5, SHA1, SHA224 and SHA36) updates:
      • Fix processing fail for small input buffers
      • Update to unlock the process and call return HAL_OK at the end of HASH -processing to avoid incorrectly repeating software
      • Update to properly manage the HashITCounter
      • Update to call the HAL_HASH_InCpltCallback() at the end of the complete buffer instead of every each 512 bits
    • __HAL_HASH_GET_FLAG() update to  check the right register when the DINNE flag  is selected
    • HAL_HASH_SHA1_Accumulate() updates:
      • Add a call to the new IS_HASH_SHA1_BUFFER_SIZE() macro to check the size parameter. 
      • Add the following note in API description
     * @note  Input buffer size in bytes must be a multiple of 4 otherwise the digest computation is corrupted.
    • HAL RTC update
      • Update to define hardware independent literals names:
        • Rename RTC_TAMPERPIN_PC13 by  RTC_TAMPERPIN_DEFAULT
        • Rename RTC_TAMPERPIN_PA0 by RTC_TAMPERPIN_POS1
        • Rename RTC_TAMPERPIN_PI8 by RTC_TAMPERPIN_POS1
        • Rename RTC_TIMESTAMPPIN_PC13 by RTC_TIMESTAMPPIN_DEFAULT
        • Rename RTC_TIMESTAMPPIN_PA0 by RTC_TIMESTAMPPIN_POS1
        • Rename RTC_TIMESTAMPPIN_PI8 by RTC_TIMESTAMPPIN_POS1
    • HAL ETH update
      • Remove duplicated IS_ETH_DUPLEX_MODE() and IS_ETH_RX_MODE() macros
      • Remove illegal space ETH_MAC_READCONTROLLER_FLUSHING macro
      • Update ETH_MAC_READCONTROLLER_XXX defined values (XXX can be IDLE, READING_DATA and READING_STATUS)
    • HAL PCD update
      • HAL_PCD_IRQHandler API: fix the bad Configuration of Turnaround Time
    • HAL HCD update
      • Update to use local variable in USB Host channel re-activation
    • LL FMC update
      • FMC_SDRAM_SendCommand() API: remove the following line: return HAL_ERROR;
    • LL USB update
      • USB_FlushTxFifo API: update to flush all Tx FIFO
      • Update to use local variable in USB Host channel re-activation

    V1.3.1 / 25-Mars-2015

    +processing to avoid incorrectly repeating software
  • Update to properly manage the HashITCounter
  • Update to call the HAL_HASH_InCpltCallback() at the end of the complete buffer instead of every each 512 bits
  • __HAL_HASH_GET_FLAG() update to  check the right register when the DINNE flag  is selected
  • HAL_HASH_SHA1_Accumulate() updates:
    • Add a call to the new IS_HASH_SHA1_BUFFER_SIZE() macro to check the size parameter. 
    • Add the following note in API description
     * @note  Input buffer size in bytes must be a multiple of 4 otherwise the digest computation is corrupted.
    • HAL RTC update
      • Update to define hardware independent literals names:
        • Rename RTC_TAMPERPIN_PC13 by  RTC_TAMPERPIN_DEFAULT
        • Rename RTC_TAMPERPIN_PA0 by RTC_TAMPERPIN_POS1
        • Rename RTC_TAMPERPIN_PI8 by RTC_TAMPERPIN_POS1
        • Rename RTC_TIMESTAMPPIN_PC13 by RTC_TIMESTAMPPIN_DEFAULT
        • Rename RTC_TIMESTAMPPIN_PA0 by RTC_TIMESTAMPPIN_POS1
        • Rename RTC_TIMESTAMPPIN_PI8 by RTC_TIMESTAMPPIN_POS1
    • HAL ETH update
      • Remove duplicated IS_ETH_DUPLEX_MODE() and IS_ETH_RX_MODE() macros
      • Remove illegal space ETH_MAC_READCONTROLLER_FLUSHING macro
      • Update ETH_MAC_READCONTROLLER_XXX defined values (XXX can be IDLE, READING_DATA and READING_STATUS)
    • HAL PCD update
      • HAL_PCD_IRQHandler API: fix the bad Configuration of Turnaround Time
    • HAL HCD update
      • Update to use local variable in USB Host channel re-activation
    • LL FMC update
      • FMC_SDRAM_SendCommand() API: remove the following line: return HAL_ERROR;
    • LL USB update
      • USB_FlushTxFifo API: update to flush all Tx FIFO
      • Update to use local variable in USB Host channel re-activation

    V1.3.1 / 25-Mars-2015

    Main Changes

    @@ -1907,7 +1964,7 @@

  • HAL PWR update
    • Fix compilation issue with STM32F417xx product: update STM32F17xx by STM32F417xx
  • HAL SPI update
    • Remove unused variable to avoid warning with TrueSTUDIO 
  • HAL I2C update
    • I2C Polling/IT/DMA processes: move the wait loop on busy flag at the top of the processes, to ensure that software not perform any write access to I2C_CR1 register before hardware clearing STOP bit and to avoid also the waiting loop on BUSY flag under I2C/DMA ISR.
    • Update busy flag Timeout value
    • I2C Master Receive Processes update to disable ACK before generate the STOP 
  • HAL DAC update
    • Fix -V1.3.0 regression issue with DAC software trigger configuration

    V1.3.0 / 09-Mars-2015

    +V1.3.0 regression issue with DAC software trigger configuration

    V1.3.0 / 09-Mars-2015

    Main Changes

    @@ -1964,7 +2021,7 @@

      * @note   Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
      *         User should request a transition to LSE Off first and then LSE On or LSE Bypass.
      • Add the -following new macros for PLL source and PLLM selection :
        • __HAL_RCC_PLL_PLLSOURCE_CONFIG()
        • __HAL_RCC_PLL_PLLM_CONFIG()
      • Macros rename:
        • HAL_RCC_OTGHS_FORCE_RESET() by HAL_RCC_USB_OTG_HS_FORCE_RESET()
        • HAL_RCC_OTGHS_RELEASE_RESET() by HAL_RCC_USB_OTG_HS_RELEASE_RESET()
        • HAL_RCC_OTGHS_CLK_SLEEP_ENABLE() by HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE()
        • HAL_RCC_OTGHS_CLK_SLEEP_DISABLE() by HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE()
        • HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE() by HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE()
        • HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE() by HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE()
      • Add __HAL_RCC_SYSCLK_CONFIG() new macro to configure the system clock source (SYSCLK)
      • __HAL_RCC_GET_SYSCLK_SOURCE() updates:
        • Add new RCC Literals:
          • RCC_SYSCLKSOURCE_STATUS_HSI
          • RCC_SYSCLKSOURCE_STATUS_HSE
          • RCC_SYSCLKSOURCE_STATUS_PLLCLK
          • RCC_SYSCLKSOURCE_STATUS_PLLRCLK
        •  Update macro description to refer to the literals above
    • HAL PWR update
      • Add new define PWR_WAKEUP_PIN2
      • Add new API to Control/Get VOS bits of CR register
        • HAL_PWR_HAL_PWREx_ControlVoltageScaling()
        • HAL_PWREx_GetVoltageRange()
      • __HAL_PWR_ VOLTAGESCALING_CONFIG(): Implement workaround to cover VOS limitation delay when PLL is enabled after setting the VOS configuration
    • HAL GPIO update
      • Add the +following new macros for PLL source and PLLM selection :
        • __HAL_RCC_PLL_PLLSOURCE_CONFIG()
        • __HAL_RCC_PLL_PLLM_CONFIG()
      • Macros rename:
        • HAL_RCC_OTGHS_FORCE_RESET() by HAL_RCC_USB_OTG_HS_FORCE_RESET()
        • HAL_RCC_OTGHS_RELEASE_RESET() by HAL_RCC_USB_OTG_HS_RELEASE_RESET()
        • HAL_RCC_OTGHS_CLK_SLEEP_ENABLE() by HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE()
        • HAL_RCC_OTGHS_CLK_SLEEP_DISABLE() by HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE()
        • HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE() by HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE()
        • HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE() by HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE()
      • Add __HAL_RCC_SYSCLK_CONFIG() new macro to configure the system clock source (SYSCLK)
      • __HAL_RCC_GET_SYSCLK_SOURCE() updates:
        • Add new RCC Literals:
          • RCC_SYSCLKSOURCE_STATUS_HSI
          • RCC_SYSCLKSOURCE_STATUS_HSE
          • RCC_SYSCLKSOURCE_STATUS_PLLCLK
          • RCC_SYSCLKSOURCE_STATUS_PLLRCLK
        •  Update macro description to refer to the literals above
    • HAL PWR update
      • Add new define PWR_WAKEUP_PIN2
      • Add new API to Control/Get VOS bits of CR register
        • HAL_PWR_HAL_PWREx_ControlVoltageScaling()
        • HAL_PWREx_GetVoltageRange()
      • __HAL_PWR_ VOLTAGESCALING_CONFIG(): Implement workaround to cover VOS limitation delay when PLL is enabled after setting the VOS configuration
    • HAL GPIO update
      • Add the new Alternate functions literals related to remap for SPI, USART, I2C, SPDIFRX, CEC and QSPI
      • HAL_GPIO_DeInit(): Update to check if GPIO Pin x is already used in EXTI mode on @@ -2013,7 +2070,7 @@

        HAL_I2S_Init(), HAL_I2S_DMAPause(), HAL_I2S_DMAStop(), HAL_I2S_DMAResume(), HAL_I2S_IRQHandle()

    • Move the following static functions from generic to extension driver
      •  I2S_DMARxCplt() and I2S_DMATxCplt()
    • Remove static attribute from I2S_Transmit_IT() and I2S_Receive_IT() functions
    • Move I2SxEXT() macro to extension file
    • Add I2S_CLOCK_PLLR and I2S_CLOCK_PLLSRC defines for I2S clock source
    • Add new function I2S_GetInputClock()
  • HAL LL FMC update
    • Add WriteFifo and PageSize fields in the FMC_NORSRAM_InitTypeDef structure
    • Add FMC_PAGE_SIZE_NONE, FMC_PAGE_SIZE_128, FMC_PAGE_SIZE_256, FMC_PAGE_SIZE_1024, FMC_WRITE_FIFO_DISABLE, FMC_WRITE_FIFO_ENABLE -defines
    • Update FMC_NORSRAM_Init(), FMC_NORSRAM_DeInit() and FMC_NORSRAM_Extended_Timing_Init() functions
  • HAL LL USB update
    • Update USB_OTG_CfgTypeDef structure to support LPM, lpm_enable field added
    • Update USB_HostInit() and USB_DevInit() functions to support the VBUS Sensing B activation

    V1.2.0 / 26-December-2014

    +defines
  • Update FMC_NORSRAM_Init(), FMC_NORSRAM_DeInit() and FMC_NORSRAM_Extended_Timing_Init() functions
  • HAL LL USB update
    • Update USB_OTG_CfgTypeDef structure to support LPM, lpm_enable field added
    • Update USB_HostInit() and USB_DevInit() functions to support the VBUS Sensing B activation

    V1.2.0 / 26-December-2014

    @@ -2232,7 +2289,7 @@

    V1.1.0 / 19-June-2014

    +

    V1.1.0 / 19-June-2014

    Main Changes

    @@ -2737,7 +2794,7 @@

    V1.0.0 / 18-February-2014

    +

    V1.0.0 / 18-February-2014

    Main Changes

    @@ -2747,7 +2804,7 @@

    -
  • First official release

    • License

    +
  • First official release

    • License

    Redistribution and use in source and binary forms, with or without diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c index f64ecb7442..4dd969682c 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c @@ -50,11 +50,11 @@ * @{ */ /** - * @brief STM32F4xx HAL Driver version number V1.7.7 + * @brief STM32F4xx HAL Driver version number V1.7.8 */ #define __STM32F4xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ #define __STM32F4xx_HAL_VERSION_SUB1 (0x07U) /*!< [23:16] sub1 version */ -#define __STM32F4xx_HAL_VERSION_SUB2 (0x07U) /*!< [15:8] sub2 version */ +#define __STM32F4xx_HAL_VERSION_SUB2 (0x08U) /*!< [15:8] sub2 version */ #define __STM32F4xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32F4xx_HAL_VERSION ((__STM32F4xx_HAL_VERSION_MAIN << 24U)\ |(__STM32F4xx_HAL_VERSION_SUB1 << 16U)\ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c index 009a4473fd..0fbc723a7f 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c @@ -537,19 +537,19 @@ __weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan) * the configuration information for CAN module * @param CallbackID ID of the callback to be registered * This parameter can be one of the following values: - * @arg @ref HAL_CAN_TX_MAILBOX0_COMPLETE_CALLBACK_CB_ID Tx Mailbox 0 Complete callback ID - * @arg @ref HAL_CAN_TX_MAILBOX1_COMPLETE_CALLBACK_CB_ID Tx Mailbox 1 Complete callback ID - * @arg @ref HAL_CAN_TX_MAILBOX2_COMPLETE_CALLBACK_CB_ID Tx Mailbox 2 Complete callback ID - * @arg @ref HAL_CAN_TX_MAILBOX0_ABORT_CALLBACK_CB_ID Tx Mailbox 0 Abort callback ID - * @arg @ref HAL_CAN_TX_MAILBOX1_ABORT_CALLBACK_CB_ID Tx Mailbox 1 Abort callback ID - * @arg @ref HAL_CAN_TX_MAILBOX2_ABORT_CALLBACK_CB_ID Tx Mailbox 2 Abort callback ID - * @arg @ref HAL_CAN_RX_FIFO0_MSG_PENDING_CALLBACK_CB_ID Rx Fifo 0 message pending callback ID - * @arg @ref HAL_CAN_RX_FIFO0_FULL_CALLBACK_CB_ID Rx Fifo 0 full callback ID - * @arg @ref HAL_CAN_RX_FIFO1_MSGPENDING_CALLBACK_CB_ID Rx Fifo 1 message pending callback ID - * @arg @ref HAL_CAN_RX_FIFO1_FULL_CALLBACK_CB_ID Rx Fifo 1 full callback ID - * @arg @ref HAL_CAN_SLEEP_CALLBACK_CB_ID Sleep callback ID - * @arg @ref HAL_CAN_WAKEUP_FROM_RX_MSG_CALLBACK_CB_ID Wake Up from Rx message callback ID - * @arg @ref HAL_CAN_ERROR_CALLBACK_CB_ID Error callback ID + * @arg @ref HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID Tx Mailbox 0 Complete callback ID + * @arg @ref HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID Tx Mailbox 1 Complete callback ID + * @arg @ref HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID Tx Mailbox 2 Complete callback ID + * @arg @ref HAL_CAN_TX_MAILBOX0_ABORT_CB_ID Tx Mailbox 0 Abort callback ID + * @arg @ref HAL_CAN_TX_MAILBOX1_ABORT_CB_ID Tx Mailbox 1 Abort callback ID + * @arg @ref HAL_CAN_TX_MAILBOX2_ABORT_CB_ID Tx Mailbox 2 Abort callback ID + * @arg @ref HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID Rx Fifo 0 message pending callback ID + * @arg @ref HAL_CAN_RX_FIFO0_FULL_CB_ID Rx Fifo 0 full callback ID + * @arg @ref HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID Rx Fifo 1 message pending callback ID + * @arg @ref HAL_CAN_RX_FIFO1_FULL_CB_ID Rx Fifo 1 full callback ID + * @arg @ref HAL_CAN_SLEEP_CB_ID Sleep callback ID + * @arg @ref HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID Wake Up from Rx message callback ID + * @arg @ref HAL_CAN_ERROR_CB_ID Error callback ID * @arg @ref HAL_CAN_MSPINIT_CB_ID MspInit callback ID * @arg @ref HAL_CAN_MSPDEINIT_CB_ID MspDeInit callback ID * @param pCallback pointer to the Callback function @@ -680,19 +680,19 @@ HAL_StatusTypeDef HAL_CAN_RegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_Call * the configuration information for CAN module * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: - * @arg @ref HAL_CAN_TX_MAILBOX0_COMPLETE_CALLBACK_CB_ID Tx Mailbox 0 Complete callback ID - * @arg @ref HAL_CAN_TX_MAILBOX1_COMPLETE_CALLBACK_CB_ID Tx Mailbox 1 Complete callback ID - * @arg @ref HAL_CAN_TX_MAILBOX2_COMPLETE_CALLBACK_CB_ID Tx Mailbox 2 Complete callback ID - * @arg @ref HAL_CAN_TX_MAILBOX0_ABORT_CALLBACK_CB_ID Tx Mailbox 0 Abort callback ID - * @arg @ref HAL_CAN_TX_MAILBOX1_ABORT_CALLBACK_CB_ID Tx Mailbox 1 Abort callback ID - * @arg @ref HAL_CAN_TX_MAILBOX2_ABORT_CALLBACK_CB_ID Tx Mailbox 2 Abort callback ID - * @arg @ref HAL_CAN_RX_FIFO0_MSG_PENDING_CALLBACK_CB_ID Rx Fifo 0 message pending callback ID - * @arg @ref HAL_CAN_RX_FIFO0_FULL_CALLBACK_CB_ID Rx Fifo 0 full callback ID - * @arg @ref HAL_CAN_RX_FIFO1_MSGPENDING_CALLBACK_CB_ID Rx Fifo 1 message pending callback ID - * @arg @ref HAL_CAN_RX_FIFO1_FULL_CALLBACK_CB_ID Rx Fifo 1 full callback ID - * @arg @ref HAL_CAN_SLEEP_CALLBACK_CB_ID Sleep callback ID - * @arg @ref HAL_CAN_WAKEUP_FROM_RX_MSG_CALLBACK_CB_ID Wake Up from Rx message callback ID - * @arg @ref HAL_CAN_ERROR_CALLBACK_CB_ID Error callback ID + * @arg @ref HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID Tx Mailbox 0 Complete callback ID + * @arg @ref HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID Tx Mailbox 1 Complete callback ID + * @arg @ref HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID Tx Mailbox 2 Complete callback ID + * @arg @ref HAL_CAN_TX_MAILBOX0_ABORT_CB_ID Tx Mailbox 0 Abort callback ID + * @arg @ref HAL_CAN_TX_MAILBOX1_ABORT_CB_ID Tx Mailbox 1 Abort callback ID + * @arg @ref HAL_CAN_TX_MAILBOX2_ABORT_CB_ID Tx Mailbox 2 Abort callback ID + * @arg @ref HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID Rx Fifo 0 message pending callback ID + * @arg @ref HAL_CAN_RX_FIFO0_FULL_CB_ID Rx Fifo 0 full callback ID + * @arg @ref HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID Rx Fifo 1 message pending callback ID + * @arg @ref HAL_CAN_RX_FIFO1_FULL_CB_ID Rx Fifo 1 full callback ID + * @arg @ref HAL_CAN_SLEEP_CB_ID Sleep callback ID + * @arg @ref HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID Wake Up from Rx message callback ID + * @arg @ref HAL_CAN_ERROR_CB_ID Error callback ID * @arg @ref HAL_CAN_MSPINIT_CB_ID MspInit callback ID * @arg @ref HAL_CAN_MSPDEINIT_CB_ID MspDeInit callback ID * @retval HAL status diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cryp.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cryp.c index e56cf85806..97f8bd74de 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cryp.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cryp.c @@ -64,6 +64,12 @@ (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral. + (#)To process a single message with consecutive calls to HAL_CRYP_Encrypt() or HAL_CRYP_Decrypt() + without having to configure again the Key or the Initialization Vector between each API call, + the field KeyIVConfigSkip of the initialization structure must be set to CRYP_KEYIVCONFIG_ONCE. + Same is true for consecutive calls of HAL_CRYP_Encrypt_IT(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt_DMA() + or HAL_CRYP_Decrypt_DMA(). + [..] The cryptographic processor supports following standards: (#) The data encryption standard (DES) and Triple-DES (TDES) supported only by CRYP1 IP: @@ -295,7 +301,7 @@ #define CRYP_OPERATINGMODE_DECRYPT CRYP_CR_ALGODIR /*!< Decryption */ #endif /* End CRYP or AES */ - /* CTR1 information to use in CCM algorithm */ +/* CTR1 information to use in CCM algorithm */ #define CRYP_CCM_CTR1_0 0x07FFFFFFU #define CRYP_CCM_CTR1_1 0xFFFFFF00U #define CRYP_CCM_CTR1_2 0x00000001U @@ -350,7 +356,7 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp); static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcryp); static void CRYP_Workaround(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp); -static HAL_StatusTypeDef CRYP_AESGCM_Process_IT (CRYP_HandleTypeDef *hcryp); +static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp); static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp); @@ -386,8 +392,8 @@ static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t T /** @defgroup CRYP_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions. - * + * @brief Initialization and Configuration functions. + * @verbatim ======================================================================================== ##### Initialization, de-initialization and Set and Get configuration functions ##### @@ -424,7 +430,7 @@ static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t T HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp) { /* Check the CRYP handle allocation */ - if(hcryp == NULL) + if (hcryp == NULL) { return HAL_ERROR; } @@ -433,9 +439,10 @@ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp) assert_param(IS_CRYP_KEYSIZE(hcryp->Init.KeySize)); assert_param(IS_CRYP_DATATYPE(hcryp->Init.DataType)); assert_param(IS_CRYP_ALGORITHM(hcryp->Init.Algorithm)); + assert_param(IS_CRYP_INIT(hcryp->Init.KeyIVConfigSkip)); - #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) - if(hcryp->State == HAL_CRYP_STATE_RESET) +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) + if (hcryp->State == HAL_CRYP_STATE_RESET) { /* Allocate lock resource and initialize it */ hcryp->Lock = HAL_UNLOCKED; @@ -444,7 +451,7 @@ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp) hcryp->OutCpltCallback = HAL_CRYP_OutCpltCallback; /* Legacy weak OutCpltCallback */ hcryp->ErrorCallback = HAL_CRYP_ErrorCallback; /* Legacy weak ErrorCallback */ - if(hcryp->MspInitCallback == NULL) + if (hcryp->MspInitCallback == NULL) { hcryp->MspInitCallback = HAL_CRYP_MspInit; /* Legacy weak MspInit */ } @@ -453,7 +460,7 @@ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp) hcryp->MspInitCallback(hcryp); } #else - if(hcryp->State == HAL_CRYP_STATE_RESET) + if (hcryp->State == HAL_CRYP_STATE_RESET) { /* Allocate lock resource and initialize it */ hcryp->Lock = HAL_UNLOCKED; @@ -461,16 +468,18 @@ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp) /* Init the low level hardware */ HAL_CRYP_MspInit(hcryp); } - #endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */ +#endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */ /* Set the key size(This bit field is don�t care in the DES or TDES modes) data type and Algorithm */ #if defined (CRYP) - MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE|CRYP_CR_KEYSIZE|CRYP_CR_ALGOMODE, hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm); + MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE | CRYP_CR_KEYSIZE | CRYP_CR_ALGOMODE, + hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm); #else /*AES*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE|AES_CR_KEYSIZE|AES_CR_CHMOD, hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm); + MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD, + hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm); #endif /* End AES or CRYP*/ @@ -492,11 +501,11 @@ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp) * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp) { /* Check the CRYP handle allocation */ - if(hcryp == NULL) + if (hcryp == NULL) { return HAL_ERROR; } @@ -507,14 +516,14 @@ HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp) /* Reset CrypInCount and CrypOutCount */ hcryp->CrypInCount = 0; hcryp->CrypOutCount = 0; - hcryp->CrypHeaderCount =0; + hcryp->CrypHeaderCount = 0; /* Disable the CRYP peripheral clock */ __HAL_CRYP_DISABLE(hcryp); #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) - if(hcryp->MspDeInitCallback == NULL) + if (hcryp->MspDeInitCallback == NULL) { hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit; /* Legacy weak MspDeInit */ } @@ -546,10 +555,10 @@ HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp) * the configuration information for CRYP module * @retval HAL status */ -HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf ) +HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf) { /* Check the CRYP handle allocation */ - if((hcryp == NULL)|| (pConf == NULL) ) + if ((hcryp == NULL) || (pConf == NULL)) { return HAL_ERROR; } @@ -559,7 +568,7 @@ HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeD assert_param(IS_CRYP_DATATYPE(pConf->DataType)); assert_param(IS_CRYP_ALGORITHM(pConf->Algorithm)); - if(hcryp->State == HAL_CRYP_STATE_READY) + if (hcryp->State == HAL_CRYP_STATE_READY) { /* Change the CRYP state */ hcryp->State = HAL_CRYP_STATE_BUSY; @@ -581,13 +590,15 @@ HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeD /* Set the key size(This bit field is don�t care in the DES or TDES modes) data type, AlgoMode and operating mode*/ #if defined (CRYP) - MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE|CRYP_CR_KEYSIZE|CRYP_CR_ALGOMODE, hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm); + MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE | CRYP_CR_KEYSIZE | CRYP_CR_ALGOMODE, + hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm); #else /*AES*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE|AES_CR_KEYSIZE|AES_CR_CHMOD, hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm); + MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD, + hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm); /*clear error flags*/ - __HAL_CRYP_CLEAR_FLAG(hcryp,CRYP_ERR_CLEAR); + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_ERR_CLEAR); #endif /* End AES or CRYP */ @@ -624,15 +635,15 @@ HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeD * the configuration information for CRYP module * @retval HAL status */ -HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf ) +HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf) { /* Check the CRYP handle allocation */ - if((hcryp == NULL)|| (pConf == NULL) ) + if ((hcryp == NULL) || (pConf == NULL)) { return HAL_ERROR; } - if(hcryp->State == HAL_CRYP_STATE_READY) + if (hcryp->State == HAL_CRYP_STATE_READY) { /* Change the CRYP state */ hcryp->State = HAL_CRYP_STATE_BUSY; @@ -717,11 +728,12 @@ __weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp) * @param pCallback pointer to the Callback function * @retval status */ -HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID, pCRYP_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID, + pCRYP_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; - if(pCallback == NULL) + if (pCallback == NULL) { /* Update the error code */ hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK; @@ -731,56 +743,56 @@ HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_ /* Process locked */ __HAL_LOCK(hcryp); - if(hcryp->State == HAL_CRYP_STATE_READY) + if (hcryp->State == HAL_CRYP_STATE_READY) { switch (CallbackID) { - case HAL_CRYP_INPUT_COMPLETE_CB_ID : - hcryp->InCpltCallback = pCallback; - break; + case HAL_CRYP_INPUT_COMPLETE_CB_ID : + hcryp->InCpltCallback = pCallback; + break; - case HAL_CRYP_OUTPUT_COMPLETE_CB_ID : - hcryp->OutCpltCallback = pCallback; - break; + case HAL_CRYP_OUTPUT_COMPLETE_CB_ID : + hcryp->OutCpltCallback = pCallback; + break; - case HAL_CRYP_ERROR_CB_ID : - hcryp->ErrorCallback = pCallback; - break; + case HAL_CRYP_ERROR_CB_ID : + hcryp->ErrorCallback = pCallback; + break; - case HAL_CRYP_MSPINIT_CB_ID : - hcryp->MspInitCallback = pCallback; - break; + case HAL_CRYP_MSPINIT_CB_ID : + hcryp->MspInitCallback = pCallback; + break; - case HAL_CRYP_MSPDEINIT_CB_ID : - hcryp->MspDeInitCallback = pCallback; - break; + case HAL_CRYP_MSPDEINIT_CB_ID : + hcryp->MspDeInitCallback = pCallback; + break; - default : - /* Update the error code */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - break; + default : + /* Update the error code */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; } } - else if(hcryp->State == HAL_CRYP_STATE_RESET) + else if (hcryp->State == HAL_CRYP_STATE_RESET) { switch (CallbackID) { - case HAL_CRYP_MSPINIT_CB_ID : - hcryp->MspInitCallback = pCallback; - break; + case HAL_CRYP_MSPINIT_CB_ID : + hcryp->MspInitCallback = pCallback; + break; - case HAL_CRYP_MSPDEINIT_CB_ID : - hcryp->MspDeInitCallback = pCallback; - break; + case HAL_CRYP_MSPDEINIT_CB_ID : + hcryp->MspDeInitCallback = pCallback; + break; - default : - /* Update the error code */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - break; + default : + /* Update the error code */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; } } else @@ -817,56 +829,56 @@ HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRY /* Process locked */ __HAL_LOCK(hcryp); - if(hcryp->State == HAL_CRYP_STATE_READY) + if (hcryp->State == HAL_CRYP_STATE_READY) { switch (CallbackID) { - case HAL_CRYP_INPUT_COMPLETE_CB_ID : - hcryp->InCpltCallback = HAL_CRYP_InCpltCallback; /* Legacy weak InCpltCallback */ - break; + case HAL_CRYP_INPUT_COMPLETE_CB_ID : + hcryp->InCpltCallback = HAL_CRYP_InCpltCallback; /* Legacy weak InCpltCallback */ + break; - case HAL_CRYP_OUTPUT_COMPLETE_CB_ID : - hcryp->OutCpltCallback = HAL_CRYP_OutCpltCallback; /* Legacy weak OutCpltCallback */ - break; + case HAL_CRYP_OUTPUT_COMPLETE_CB_ID : + hcryp->OutCpltCallback = HAL_CRYP_OutCpltCallback; /* Legacy weak OutCpltCallback */ + break; - case HAL_CRYP_ERROR_CB_ID : - hcryp->ErrorCallback = HAL_CRYP_ErrorCallback; /* Legacy weak ErrorCallback */ - break; + case HAL_CRYP_ERROR_CB_ID : + hcryp->ErrorCallback = HAL_CRYP_ErrorCallback; /* Legacy weak ErrorCallback */ + break; - case HAL_CRYP_MSPINIT_CB_ID : - hcryp->MspInitCallback = HAL_CRYP_MspInit; - break; + case HAL_CRYP_MSPINIT_CB_ID : + hcryp->MspInitCallback = HAL_CRYP_MspInit; + break; - case HAL_CRYP_MSPDEINIT_CB_ID : - hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit; - break; + case HAL_CRYP_MSPDEINIT_CB_ID : + hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit; + break; - default : - /* Update the error code */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - break; + default : + /* Update the error code */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; } } - else if(hcryp->State == HAL_CRYP_STATE_RESET) + else if (hcryp->State == HAL_CRYP_STATE_RESET) { switch (CallbackID) { - case HAL_CRYP_MSPINIT_CB_ID : - hcryp->MspInitCallback = HAL_CRYP_MspInit; - break; + case HAL_CRYP_MSPINIT_CB_ID : + hcryp->MspInitCallback = HAL_CRYP_MspInit; + break; - case HAL_CRYP_MSPDEINIT_CB_ID : - hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit; - break; + case HAL_CRYP_MSPDEINIT_CB_ID : + hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit; + break; - default : - /* Update the error code */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - break; + default : + /* Update the error code */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; } } else @@ -888,8 +900,8 @@ HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRY */ /** @defgroup CRYP_Exported_Functions_Group2 Encrypt Decrypt functions - * @brief processing functions. - * + * @brief processing functions. + * @verbatim ============================================================================== ##### Encrypt Decrypt functions ##### @@ -927,12 +939,13 @@ HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRY * @param Timeout: Specify Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout) +HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, + uint32_t Timeout) { uint32_t algo; HAL_StatusTypeDef status; - if(hcryp->State == HAL_CRYP_STATE_READY) + if (hcryp->State == HAL_CRYP_STATE_READY) { /* Change state Busy */ hcryp->State = HAL_CRYP_STATE_BUSY; @@ -963,65 +976,69 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, u /* algo get algorithm selected */ algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE; - switch(algo) + switch (algo) { - case CRYP_DES_ECB: - case CRYP_DES_CBC: - case CRYP_TDES_ECB: - case CRYP_TDES_CBC: + case CRYP_DES_ECB: + case CRYP_DES_CBC: + case CRYP_TDES_ECB: + case CRYP_TDES_CBC: - /*Set Key */ - hcryp->Instance->K1LR = *(uint32_t*)(hcryp->Init.pKey); - hcryp->Instance->K1RR = *(uint32_t*)(hcryp->Init.pKey+1); - if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC)) - { - hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey+2); - hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+3); - hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+4); - hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+5); - } + /*Set Key */ + hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey); + hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1); + if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC)) + { + hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2); + hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3); + hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4); + hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5); + } - /*Set Initialization Vector (IV)*/ - if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC)) - { - hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect); - hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1); - } + /*Set Initialization Vector (IV)*/ + if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC)) + { + hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect); + hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1); + } - /* Flush FIFO */ - HAL_CRYP_FIFO_FLUSH(hcryp); + /* Flush FIFO */ + HAL_CRYP_FIFO_FLUSH(hcryp); - /* Set the phase */ - hcryp->Phase = CRYP_PHASE_PROCESS; + /* Set the phase */ + hcryp->Phase = CRYP_PHASE_PROCESS; - /* Statrt DES/TDES encryption process */ - status = CRYP_TDES_Process(hcryp,Timeout); - break; + /* Statrt DES/TDES encryption process */ + status = CRYP_TDES_Process(hcryp, Timeout); + break; - case CRYP_AES_ECB: - case CRYP_AES_CBC: - case CRYP_AES_CTR: + case CRYP_AES_ECB: + case CRYP_AES_CBC: + case CRYP_AES_CTR: - /* AES encryption */ - status = CRYP_AES_Encrypt(hcryp, Timeout); - break; -#if defined (CRYP_CR_ALGOMODE_AES_GCM) - case CRYP_AES_GCM: + /* AES encryption */ + status = CRYP_AES_Encrypt(hcryp, Timeout); + break; + #if defined (CRYP_CR_ALGOMODE_AES_GCM) + case CRYP_AES_GCM: - /* AES GCM encryption */ - status = CRYP_AESGCM_Process(hcryp, Timeout); + /* AES GCM encryption */ + status = CRYP_AESGCM_Process(hcryp, Timeout); - break; + break; - case CRYP_AES_CCM: + case CRYP_AES_CCM: - /* AES CCM encryption */ - status = CRYP_AESCCM_Process(hcryp,Timeout); - break; -#endif /* GCM CCM defined*/ - default: - hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; - return HAL_ERROR; + /* AES CCM encryption */ + status = CRYP_AESCCM_Process(hcryp, Timeout); + break; + #endif /* GCM CCM defined*/ + default: + hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; + /* Change the CRYP peripheral state */ + hcryp->State = HAL_CRYP_STATE_READY; + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; } #else /*AES*/ @@ -1032,32 +1049,36 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, u /* algo get algorithm selected */ algo = hcryp->Instance->CR & AES_CR_CHMOD; - switch(algo) + switch (algo) { - case CRYP_AES_ECB: - case CRYP_AES_CBC: - case CRYP_AES_CTR: + case CRYP_AES_ECB: + case CRYP_AES_CBC: + case CRYP_AES_CTR: - /* AES encryption */ - status = CRYP_AES_Encrypt(hcryp, Timeout); - break; + /* AES encryption */ + status = CRYP_AES_Encrypt(hcryp, Timeout); + break; - case CRYP_AES_GCM_GMAC: + case CRYP_AES_GCM_GMAC: - /* AES GCM encryption */ - status = CRYP_AESGCM_Process (hcryp,Timeout) ; - break; + /* AES GCM encryption */ + status = CRYP_AESGCM_Process(hcryp, Timeout) ; + break; - case CRYP_AES_CCM: + case CRYP_AES_CCM: - /* AES CCM encryption */ - status = CRYP_AESCCM_Process(hcryp,Timeout); - break; + /* AES CCM encryption */ + status = CRYP_AESCCM_Process(hcryp, Timeout); + break; - default: - hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; - return HAL_ERROR; + default: + hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; + /* Change the CRYP peripheral state */ + hcryp->State = HAL_CRYP_STATE_READY; + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; } #endif /*end AES or CRYP */ @@ -1091,12 +1112,13 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, u * @param Timeout: Specify Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout) +HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, + uint32_t Timeout) { HAL_StatusTypeDef status; uint32_t algo; - if(hcryp->State == HAL_CRYP_STATE_READY) + if (hcryp->State == HAL_CRYP_STATE_READY) { /* Change state Busy */ hcryp->State = HAL_CRYP_STATE_BUSY; @@ -1128,65 +1150,69 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, u /* algo get algorithm selected */ algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE; - switch(algo) + switch (algo) { - case CRYP_DES_ECB: - case CRYP_DES_CBC: - case CRYP_TDES_ECB: - case CRYP_TDES_CBC: + case CRYP_DES_ECB: + case CRYP_DES_CBC: + case CRYP_TDES_ECB: + case CRYP_TDES_CBC: - /*Set Key */ - hcryp->Instance->K1LR = *(uint32_t*)(hcryp->Init.pKey); - hcryp->Instance->K1RR = *(uint32_t*)(hcryp->Init.pKey+1); - if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC)) - { - hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey+2); - hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+3); - hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+4); - hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+5); - } + /*Set Key */ + hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey); + hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1); + if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC)) + { + hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2); + hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3); + hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4); + hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5); + } - /*Set Initialization Vector (IV)*/ - if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC)) - { - hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect); - hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1); - } + /*Set Initialization Vector (IV)*/ + if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC)) + { + hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect); + hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1); + } - /* Flush FIFO */ - HAL_CRYP_FIFO_FLUSH(hcryp); + /* Flush FIFO */ + HAL_CRYP_FIFO_FLUSH(hcryp); - /* Set the phase */ - hcryp->Phase = CRYP_PHASE_PROCESS; + /* Set the phase */ + hcryp->Phase = CRYP_PHASE_PROCESS; - /* Start DES/TDES decryption process */ - status = CRYP_TDES_Process(hcryp, Timeout); + /* Start DES/TDES decryption process */ + status = CRYP_TDES_Process(hcryp, Timeout); - break; + break; - case CRYP_AES_ECB: - case CRYP_AES_CBC: - case CRYP_AES_CTR: + case CRYP_AES_ECB: + case CRYP_AES_CBC: + case CRYP_AES_CTR: - /* AES decryption */ - status = CRYP_AES_Decrypt(hcryp, Timeout); - break; -#if defined (CRYP_CR_ALGOMODE_AES_GCM) - case CRYP_AES_GCM: + /* AES decryption */ + status = CRYP_AES_Decrypt(hcryp, Timeout); + break; + #if defined (CRYP_CR_ALGOMODE_AES_GCM) + case CRYP_AES_GCM: - /* AES GCM decryption */ - status = CRYP_AESGCM_Process (hcryp, Timeout) ; - break; + /* AES GCM decryption */ + status = CRYP_AESGCM_Process(hcryp, Timeout) ; + break; - case CRYP_AES_CCM: + case CRYP_AES_CCM: - /* AES CCM decryption */ - status = CRYP_AESCCM_Process(hcryp, Timeout); - break; -#endif /* GCM CCM defined*/ - default: - hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; - return HAL_ERROR; + /* AES CCM decryption */ + status = CRYP_AESCCM_Process(hcryp, Timeout); + break; + #endif /* GCM CCM defined*/ + default: + hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; + /* Change the CRYP peripheral state */ + hcryp->State = HAL_CRYP_STATE_READY; + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; } #else /*AES*/ @@ -1197,32 +1223,36 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, u /* algo get algorithm selected */ algo = hcryp->Instance->CR & AES_CR_CHMOD; - switch(algo) + switch (algo) { - case CRYP_AES_ECB: - case CRYP_AES_CBC: - case CRYP_AES_CTR: + case CRYP_AES_ECB: + case CRYP_AES_CBC: + case CRYP_AES_CTR: - /* AES decryption */ - status = CRYP_AES_Decrypt(hcryp, Timeout); - break; + /* AES decryption */ + status = CRYP_AES_Decrypt(hcryp, Timeout); + break; - case CRYP_AES_GCM_GMAC: + case CRYP_AES_GCM_GMAC: - /* AES GCM decryption */ - status = CRYP_AESGCM_Process (hcryp, Timeout) ; - break; + /* AES GCM decryption */ + status = CRYP_AESGCM_Process(hcryp, Timeout) ; + break; - case CRYP_AES_CCM: + case CRYP_AES_CCM: - /* AES CCM decryption */ - status = CRYP_AESCCM_Process(hcryp, Timeout); - break; + /* AES CCM decryption */ + status = CRYP_AESCCM_Process(hcryp, Timeout); + break; - default: - hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; - return HAL_ERROR; + default: + hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; + /* Change the CRYP peripheral state */ + hcryp->State = HAL_CRYP_STATE_READY; + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; } #endif /* End AES or CRYP */ @@ -1260,7 +1290,7 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input uint32_t algo; HAL_StatusTypeDef status = HAL_OK; - if(hcryp->State == HAL_CRYP_STATE_READY) + if (hcryp->State == HAL_CRYP_STATE_READY) { /* Change state Busy */ hcryp->State = HAL_CRYP_STATE_BUSY; @@ -1292,64 +1322,68 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input /* algo get algorithm selected */ algo = (hcryp->Instance->CR & CRYP_CR_ALGOMODE); - switch(algo) + switch (algo) { - case CRYP_DES_ECB: - case CRYP_DES_CBC: - case CRYP_TDES_ECB: - case CRYP_TDES_CBC: + case CRYP_DES_ECB: + case CRYP_DES_CBC: + case CRYP_TDES_ECB: + case CRYP_TDES_CBC: - /*Set Key */ - hcryp->Instance->K1LR = *(uint32_t*)(hcryp->Init.pKey); - hcryp->Instance->K1RR = *(uint32_t*)(hcryp->Init.pKey+1); - if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC)) - { - hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey+2); - hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+3); - hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+4); - hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+5); - } - /* Set the Initialization Vector*/ - if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC)) - { - hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect); - hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1); - } + /*Set Key */ + hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey); + hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1); + if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC)) + { + hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2); + hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3); + hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4); + hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5); + } + /* Set the Initialization Vector*/ + if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC)) + { + hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect); + hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1); + } - /* Flush FIFO */ - HAL_CRYP_FIFO_FLUSH(hcryp); + /* Flush FIFO */ + HAL_CRYP_FIFO_FLUSH(hcryp); - /* Set the phase */ - hcryp->Phase = CRYP_PHASE_PROCESS; + /* Set the phase */ + hcryp->Phase = CRYP_PHASE_PROCESS; - /* Enable interrupts */ - __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI); + /* Enable interrupts */ + __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI); - /* Enable CRYP to start DES/TDES process*/ - __HAL_CRYP_ENABLE(hcryp); - break; + /* Enable CRYP to start DES/TDES process*/ + __HAL_CRYP_ENABLE(hcryp); + break; - case CRYP_AES_ECB: - case CRYP_AES_CBC: - case CRYP_AES_CTR: + case CRYP_AES_ECB: + case CRYP_AES_CBC: + case CRYP_AES_CTR: - status = CRYP_AES_Encrypt_IT(hcryp); - break; -#if defined (CRYP_CR_ALGOMODE_AES_GCM) - case CRYP_AES_GCM: + status = CRYP_AES_Encrypt_IT(hcryp); + break; + #if defined (CRYP_CR_ALGOMODE_AES_GCM) + case CRYP_AES_GCM: - status = CRYP_AESGCM_Process_IT (hcryp) ; - break; + status = CRYP_AESGCM_Process_IT(hcryp) ; + break; - case CRYP_AES_CCM: + case CRYP_AES_CCM: - status = CRYP_AESCCM_Process_IT(hcryp); - break; -#endif /* GCM CCM defined*/ - default: - hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; - status = HAL_ERROR; - break; + status = CRYP_AESCCM_Process_IT(hcryp); + break; + #endif /* GCM CCM defined*/ + default: + hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; + /* Change the CRYP peripheral state */ + hcryp->State = HAL_CRYP_STATE_READY; + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + status = HAL_ERROR; + break; } #else /* AES */ @@ -1360,32 +1394,36 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input /* algo get algorithm selected */ algo = hcryp->Instance->CR & AES_CR_CHMOD; - switch(algo) + switch (algo) { - case CRYP_AES_ECB: - case CRYP_AES_CBC: - case CRYP_AES_CTR: + case CRYP_AES_ECB: + case CRYP_AES_CBC: + case CRYP_AES_CTR: - /* AES encryption */ - status = CRYP_AES_Encrypt_IT(hcryp); - break; + /* AES encryption */ + status = CRYP_AES_Encrypt_IT(hcryp); + break; - case CRYP_AES_GCM_GMAC: + case CRYP_AES_GCM_GMAC: - /* AES GCM encryption */ - status = CRYP_AESGCM_Process_IT (hcryp) ; - break; + /* AES GCM encryption */ + status = CRYP_AESGCM_Process_IT(hcryp) ; + break; - case CRYP_AES_CCM: + case CRYP_AES_CCM: - /* AES CCM encryption */ - status = CRYP_AESCCM_Process_IT(hcryp); - break; + /* AES CCM encryption */ + status = CRYP_AESCCM_Process_IT(hcryp); + break; - default: - hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; - status = HAL_ERROR; - break; + default: + hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; + /* Change the CRYP peripheral state */ + hcryp->State = HAL_CRYP_STATE_READY; + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + status = HAL_ERROR; + break; } #endif /*end AES or CRYP*/ @@ -1415,7 +1453,7 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input uint32_t algo; HAL_StatusTypeDef status = HAL_OK; - if(hcryp->State == HAL_CRYP_STATE_READY) + if (hcryp->State == HAL_CRYP_STATE_READY) { /* Change state Busy */ hcryp->State = HAL_CRYP_STATE_BUSY; @@ -1442,73 +1480,77 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input #if defined (CRYP) /* Set decryption operating mode*/ - MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR,CRYP_OPERATINGMODE_DECRYPT); + MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_DECRYPT); /* algo get algorithm selected */ algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE; - switch(algo) + switch (algo) { - case CRYP_DES_ECB: - case CRYP_DES_CBC: - case CRYP_TDES_ECB: - case CRYP_TDES_CBC: + case CRYP_DES_ECB: + case CRYP_DES_CBC: + case CRYP_TDES_ECB: + case CRYP_TDES_CBC: - /*Set Key */ - hcryp->Instance->K1LR = *(uint32_t*)(hcryp->Init.pKey); - hcryp->Instance->K1RR = *(uint32_t*)(hcryp->Init.pKey+1); - if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC)) - { - hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey+2); - hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+3); - hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+4); - hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+5); - } + /*Set Key */ + hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey); + hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1); + if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC)) + { + hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2); + hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3); + hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4); + hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5); + } - /* Set the Initialization Vector*/ - if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC)) - { - hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect); - hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1); - } - /* Flush FIFO */ - HAL_CRYP_FIFO_FLUSH(hcryp); + /* Set the Initialization Vector*/ + if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC)) + { + hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect); + hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1); + } + /* Flush FIFO */ + HAL_CRYP_FIFO_FLUSH(hcryp); - /* Set the phase */ - hcryp->Phase = CRYP_PHASE_PROCESS; + /* Set the phase */ + hcryp->Phase = CRYP_PHASE_PROCESS; - /* Enable interrupts */ - __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI); + /* Enable interrupts */ + __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI); - /* Enable CRYP and start DES/TDES process*/ - __HAL_CRYP_ENABLE(hcryp); + /* Enable CRYP and start DES/TDES process*/ + __HAL_CRYP_ENABLE(hcryp); - break; + break; - case CRYP_AES_ECB: - case CRYP_AES_CBC: - case CRYP_AES_CTR: + case CRYP_AES_ECB: + case CRYP_AES_CBC: + case CRYP_AES_CTR: - /* AES decryption */ - status = CRYP_AES_Decrypt_IT(hcryp); - break; -#if defined (CRYP_CR_ALGOMODE_AES_GCM) - case CRYP_AES_GCM: + /* AES decryption */ + status = CRYP_AES_Decrypt_IT(hcryp); + break; + #if defined (CRYP_CR_ALGOMODE_AES_GCM) + case CRYP_AES_GCM: - /* AES GCM decryption */ - status = CRYP_AESGCM_Process_IT (hcryp) ; - break; + /* AES GCM decryption */ + status = CRYP_AESGCM_Process_IT(hcryp) ; + break; - case CRYP_AES_CCM: + case CRYP_AES_CCM: - /* AES CCMdecryption */ - status = CRYP_AESCCM_Process_IT(hcryp); - break; -#endif /* GCM CCM defined*/ - default: - hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; - status = HAL_ERROR; - break; + /* AES CCMdecryption */ + status = CRYP_AESCCM_Process_IT(hcryp); + break; + #endif /* GCM CCM defined*/ + default: + hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; + /* Change the CRYP peripheral state */ + hcryp->State = HAL_CRYP_STATE_READY; + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + status = HAL_ERROR; + break; } #else /*AES*/ @@ -1519,32 +1561,36 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input /* algo get algorithm selected */ algo = hcryp->Instance->CR & AES_CR_CHMOD; - switch(algo) + switch (algo) { - case CRYP_AES_ECB: - case CRYP_AES_CBC: - case CRYP_AES_CTR: + case CRYP_AES_ECB: + case CRYP_AES_CBC: + case CRYP_AES_CTR: - /* AES decryption */ - status = CRYP_AES_Decrypt_IT(hcryp); - break; + /* AES decryption */ + status = CRYP_AES_Decrypt_IT(hcryp); + break; - case CRYP_AES_GCM_GMAC: + case CRYP_AES_GCM_GMAC: - /* AES GCM decryption */ - status = CRYP_AESGCM_Process_IT (hcryp) ; - break; + /* AES GCM decryption */ + status = CRYP_AESGCM_Process_IT(hcryp) ; + break; - case CRYP_AES_CCM: + case CRYP_AES_CCM: - /* AES CCM decryption */ - status = CRYP_AESCCM_Process_IT(hcryp); - break; + /* AES CCM decryption */ + status = CRYP_AESCCM_Process_IT(hcryp); + break; - default: - hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; - status = HAL_ERROR; - break; + default: + hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; + /* Change the CRYP peripheral state */ + hcryp->State = HAL_CRYP_STATE_READY; + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + status = HAL_ERROR; + break; } #endif /* End AES or CRYP */ @@ -1573,8 +1619,9 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Inpu { uint32_t algo; HAL_StatusTypeDef status = HAL_OK; + uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ - if(hcryp->State == HAL_CRYP_STATE_READY) + if (hcryp->State == HAL_CRYP_STATE_READY) { /* Change state Busy */ hcryp->State = HAL_CRYP_STATE_BUSY; @@ -1606,77 +1653,104 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Inpu /* algo get algorithm selected */ algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE; - switch(algo) + switch (algo) { - case CRYP_DES_ECB: - case CRYP_DES_CBC: - case CRYP_TDES_ECB: - case CRYP_TDES_CBC: + case CRYP_DES_ECB: + case CRYP_DES_CBC: + case CRYP_TDES_ECB: + case CRYP_TDES_CBC: - /*Set Key */ - hcryp->Instance->K1LR = *(uint32_t*)(hcryp->Init.pKey); - hcryp->Instance->K1RR = *(uint32_t*)(hcryp->Init.pKey+1); - if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC)) - { - hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey+2); - hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+3); - hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+4); - hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+5); - } - - /* Set the Initialization Vector*/ - if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC)) - { - hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect); - hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1); - } + /*Set Key */ + hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey); + hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1); + if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC)) + { + hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2); + hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3); + hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4); + hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5); + } - /* Flush FIFO */ - HAL_CRYP_FIFO_FLUSH(hcryp); + /* Set the Initialization Vector*/ + if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC)) + { + hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect); + hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1); + } - /* Set the phase */ - hcryp->Phase = CRYP_PHASE_PROCESS; + /* Flush FIFO */ + HAL_CRYP_FIFO_FLUSH(hcryp); - /* Start DMA process transfer for DES/TDES */ - CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), ((uint16_t)(hcryp->Size)/4U), (uint32_t)(hcryp->pCrypOutBuffPtr)); - break; + /* Set the phase */ + hcryp->Phase = CRYP_PHASE_PROCESS; - case CRYP_AES_ECB: - case CRYP_AES_CBC: - case CRYP_AES_CTR: + /* Start DMA process transfer for DES/TDES */ + CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), ((uint16_t)(hcryp->Size) / 4U), + (uint32_t)(hcryp->pCrypOutBuffPtr)); + break; - /* Set the Key*/ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); + case CRYP_AES_ECB: + case CRYP_AES_CBC: + case CRYP_AES_CTR: - /* Set the Initialization Vector IV */ - if (hcryp->Init.Algorithm != CRYP_AES_ECB) - { - hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect); - hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1); - hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2); - hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3); - } - /* Set the phase */ - hcryp->Phase = CRYP_PHASE_PROCESS; + if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) + { + if (hcryp->KeyIVConfig == 1U) + { + /* If the Key and IV configuration has to be done only once + and if it has already been done, skip it */ + DoKeyIVConfig = 0U; + } + else + { + /* If the Key and IV configuration has to be done only once + and if it has not been done already, do it and set KeyIVConfig + to keep track it won't have to be done again next time */ + hcryp->KeyIVConfig = 1U; + } + } - /* Start DMA process transfer for AES */ - CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), ((uint16_t)(hcryp->Size)/4U), (uint32_t)(hcryp->pCrypOutBuffPtr)); - break; -#if defined (CRYP_CR_ALGOMODE_AES_GCM) - case CRYP_AES_GCM: - /* AES GCM encryption */ - status = CRYP_AESGCM_Process_DMA (hcryp) ; - break; + if (DoKeyIVConfig == 1U) + { + /* Set the Key*/ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); - case CRYP_AES_CCM: - /* AES CCM encryption */ - status = CRYP_AESCCM_Process_DMA(hcryp); - break; -#endif /* GCM CCM defined*/ - default: - hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; - status = HAL_ERROR; - break; + /* Set the Initialization Vector*/ + if (hcryp->Init.Algorithm != CRYP_AES_ECB) + { + hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect); + hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1U); + hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2U); + hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3U); + } + } /* if (DoKeyIVConfig == 1U) */ + + /* Set the phase */ + hcryp->Phase = CRYP_PHASE_PROCESS; + + /* Start DMA process transfer for AES */ + CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), ((uint16_t)(hcryp->Size) / 4U), + (uint32_t)(hcryp->pCrypOutBuffPtr)); + break; + #if defined (CRYP_CR_ALGOMODE_AES_GCM) + case CRYP_AES_GCM: + /* AES GCM encryption */ + status = CRYP_AESGCM_Process_DMA(hcryp) ; + break; + + case CRYP_AES_CCM: + /* AES CCM encryption */ + status = CRYP_AESCCM_Process_DMA(hcryp); + break; + #endif /* GCM CCM defined*/ + default: + hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; + /* Change the CRYP peripheral state */ + hcryp->State = HAL_CRYP_STATE_READY; + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + status = HAL_ERROR; + break; } #else /*AES*/ @@ -1686,46 +1760,69 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Inpu /* algo get algorithm selected */ algo = hcryp->Instance->CR & AES_CR_CHMOD; - switch(algo) + switch (algo) { - case CRYP_AES_ECB: - case CRYP_AES_CBC: - case CRYP_AES_CTR: - - /* Set the Key*/ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); - - /* Set the Initialization Vector*/ - if (hcryp->Init.Algorithm != CRYP_AES_ECB) - { - hcryp->Instance->IVR3 = *(uint32_t*)(hcryp->Init.pInitVect); - hcryp->Instance->IVR2 = *(uint32_t*)(hcryp->Init.pInitVect+1); - hcryp->Instance->IVR1 = *(uint32_t*)(hcryp->Init.pInitVect+2); - hcryp->Instance->IVR0 = *(uint32_t*)(hcryp->Init.pInitVect+3); - } - - /* Set the phase */ - hcryp->Phase = CRYP_PHASE_PROCESS; - - /* Start DMA process transfer for AES */ - CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), (hcryp->Size/4U), (uint32_t)(hcryp->pCrypOutBuffPtr)); - break; + case CRYP_AES_ECB: + case CRYP_AES_CBC: + case CRYP_AES_CTR: - case CRYP_AES_GCM_GMAC: - /* AES GCM encryption */ - status = CRYP_AESGCM_Process_DMA (hcryp) ; - break; + if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) + { + if (hcryp->KeyIVConfig == 1U) + { + /* If the Key and IV configuration has to be done only once + and if it has already been done, skip it */ + DoKeyIVConfig = 0U; + } + else + { + /* If the Key and IV configuration has to be done only once + and if it has not been done already, do it and set KeyIVConfig + to keep track it won't have to be done again next time */ + hcryp->KeyIVConfig = 1U; + } + } - case CRYP_AES_CCM: - /* AES CCM encryption */ - status = CRYP_AESCCM_Process_DMA(hcryp); - break; + if (DoKeyIVConfig == 1U) + { + /* Set the Key*/ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); - default: - hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; - status = HAL_ERROR; - break; + /* Set the Initialization Vector*/ + if (hcryp->Init.Algorithm != CRYP_AES_ECB) + { + hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect); + hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1); + hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2); + hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3); + } + } /* if (DoKeyIVConfig == 1U) */ + /* Set the phase */ + hcryp->Phase = CRYP_PHASE_PROCESS; + + /* Start DMA process transfer for AES */ + CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), (uint32_t)(hcryp->pCrypOutBuffPtr)); + break; + + case CRYP_AES_GCM_GMAC: + /* AES GCM encryption */ + status = CRYP_AESGCM_Process_DMA(hcryp) ; + break; + + case CRYP_AES_CCM: + /* AES CCM encryption */ + status = CRYP_AESCCM_Process_DMA(hcryp); + break; + + default: + hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; + /* Change the CRYP peripheral state */ + hcryp->State = HAL_CRYP_STATE_READY; + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + status = HAL_ERROR; + break; } #endif /* End AES or CRYP */ @@ -1755,7 +1852,7 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Inpu uint32_t algo; HAL_StatusTypeDef status = HAL_OK; - if(hcryp->State == HAL_CRYP_STATE_READY) + if (hcryp->State == HAL_CRYP_STATE_READY) { /* Change state Busy */ @@ -1788,63 +1885,68 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Inpu /* algo get algorithm selected */ algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE; - switch(algo) + switch (algo) { - case CRYP_DES_ECB: - case CRYP_DES_CBC: - case CRYP_TDES_ECB: - case CRYP_TDES_CBC: - - /*Set Key */ - hcryp->Instance->K1LR = *(uint32_t*)(hcryp->Init.pKey); - hcryp->Instance->K1RR = *(uint32_t*)(hcryp->Init.pKey+1); - if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC)) - { - hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey+2); - hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+3); - hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+4); - hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+5); - } - - /* Set the Initialization Vector*/ - if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC)) - { - hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect); - hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1); - } - - /* Flush FIFO */ - HAL_CRYP_FIFO_FLUSH(hcryp); - - /* Set the phase */ - hcryp->Phase = CRYP_PHASE_PROCESS; - - /* Start DMA process transfer for DES/TDES */ - CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), ((uint16_t)(hcryp->Size)/4U), (uint32_t)(hcryp->pCrypOutBuffPtr)); - break; + case CRYP_DES_ECB: + case CRYP_DES_CBC: + case CRYP_TDES_ECB: + case CRYP_TDES_CBC: - case CRYP_AES_ECB: - case CRYP_AES_CBC: - case CRYP_AES_CTR: + /*Set Key */ + hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey); + hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1); + if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC)) + { + hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2); + hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3); + hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4); + hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5); + } - /* AES decryption */ - status = CRYP_AES_Decrypt_DMA(hcryp); - break; -#if defined (CRYP_CR_ALGOMODE_AES_GCM) - case CRYP_AES_GCM: - /* AES GCM decryption */ - status = CRYP_AESGCM_Process_DMA (hcryp) ; - break; + /* Set the Initialization Vector*/ + if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC)) + { + hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect); + hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1); + } - case CRYP_AES_CCM: - /* AES CCM decryption */ - status = CRYP_AESCCM_Process_DMA(hcryp); - break; -#endif /* GCM CCM defined*/ - default: - hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; - status = HAL_ERROR; - break; + /* Flush FIFO */ + HAL_CRYP_FIFO_FLUSH(hcryp); + + /* Set the phase */ + hcryp->Phase = CRYP_PHASE_PROCESS; + + /* Start DMA process transfer for DES/TDES */ + CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), ((uint16_t)(hcryp->Size) / 4U), + (uint32_t)(hcryp->pCrypOutBuffPtr)); + break; + + case CRYP_AES_ECB: + case CRYP_AES_CBC: + case CRYP_AES_CTR: + + /* AES decryption */ + status = CRYP_AES_Decrypt_DMA(hcryp); + break; + #if defined (CRYP_CR_ALGOMODE_AES_GCM) + case CRYP_AES_GCM: + /* AES GCM decryption */ + status = CRYP_AESGCM_Process_DMA(hcryp) ; + break; + + case CRYP_AES_CCM: + /* AES CCM decryption */ + status = CRYP_AESCCM_Process_DMA(hcryp); + break; + #endif /* GCM CCM defined*/ + default: + hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; + /* Change the CRYP peripheral state */ + hcryp->State = HAL_CRYP_STATE_READY; + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + status = HAL_ERROR; + break; } #else /*AES*/ @@ -1855,31 +1957,35 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Inpu /* algo get algorithm selected */ algo = hcryp->Instance->CR & AES_CR_CHMOD; - switch(algo) + switch (algo) { - case CRYP_AES_ECB: - case CRYP_AES_CBC: - case CRYP_AES_CTR: + case CRYP_AES_ECB: + case CRYP_AES_CBC: + case CRYP_AES_CTR: - /* AES decryption */ - status = CRYP_AES_Decrypt_DMA(hcryp); - break; + /* AES decryption */ + status = CRYP_AES_Decrypt_DMA(hcryp); + break; - case CRYP_AES_GCM_GMAC: - /* AES GCM decryption */ - status = CRYP_AESGCM_Process_DMA (hcryp) ; - break; + case CRYP_AES_GCM_GMAC: + /* AES GCM decryption */ + status = CRYP_AESGCM_Process_DMA(hcryp) ; + break; - case CRYP_AES_CCM: - /* AES CCM decryption */ - status = CRYP_AESCCM_Process_DMA(hcryp); - break; + case CRYP_AES_CCM: + /* AES CCM decryption */ + status = CRYP_AESCCM_Process_DMA(hcryp); + break; - default: - hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; - status = HAL_ERROR; - break; + default: + hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; + /* Change the CRYP peripheral state */ + hcryp->State = HAL_CRYP_STATE_READY; + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + status = HAL_ERROR; + break; } #endif /* End AES or CRYP */ } @@ -1899,8 +2005,8 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Inpu */ /** @defgroup CRYP_Exported_Functions_Group3 CRYP IRQ handler management - * @brief CRYP IRQ handler. - * + * @brief CRYP IRQ handler. + * @verbatim ============================================================================== ##### CRYP IRQ handler management ##### @@ -1927,21 +2033,25 @@ void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp) #if defined (CRYP) - if((__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI) != 0x0U) || (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI) != 0x0U)) + uint32_t itstatus = hcryp->Instance->MISR; + + if ((itstatus & (CRYP_IT_INI | CRYP_IT_OUTI)) != 0U) { - if ((hcryp->Init.Algorithm == CRYP_DES_ECB)|| (hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC)) + if ((hcryp->Init.Algorithm == CRYP_DES_ECB) || (hcryp->Init.Algorithm == CRYP_DES_CBC) + || (hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC)) { CRYP_TDES_IT(hcryp); /* DES or TDES*/ } - else if((hcryp->Init.Algorithm == CRYP_AES_ECB) || (hcryp->Init.Algorithm == CRYP_AES_CBC) || (hcryp->Init.Algorithm == CRYP_AES_CTR)) + else if ((hcryp->Init.Algorithm == CRYP_AES_ECB) || (hcryp->Init.Algorithm == CRYP_AES_CBC) + || (hcryp->Init.Algorithm == CRYP_AES_CTR)) { CRYP_AES_IT(hcryp); /*AES*/ } -#if defined (CRYP_CR_ALGOMODE_AES_GCM) - else if((hcryp->Init.Algorithm == CRYP_AES_GCM) ||(hcryp->Init.Algorithm == CRYP_CR_ALGOMODE_AES_CCM) ) + #if defined (CRYP_CR_ALGOMODE_AES_GCM) + else if ((hcryp->Init.Algorithm == CRYP_AES_GCM) || (hcryp->Init.Algorithm == CRYP_CR_ALGOMODE_AES_CCM)) { /* if header phase */ - if ((hcryp->Instance->CR & CRYP_PHASE_HEADER) == CRYP_PHASE_HEADER ) + if ((hcryp->Instance->CR & CRYP_PHASE_HEADER) == CRYP_PHASE_HEADER) { CRYP_GCMCCM_SetHeaderPhase_IT(hcryp); } @@ -1950,7 +2060,7 @@ void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp) CRYP_GCMCCM_SetPayloadPhase_IT(hcryp); } } -#endif /* GCM CCM defined*/ + #endif /* GCM CCM defined*/ else { /* Nothing to do */ @@ -1958,52 +2068,55 @@ void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp) } #else /*AES*/ - if((__HAL_CRYP_GET_FLAG(hcryp,CRYP_IT_CCF) != 0x0U) && (__HAL_CRYP_GET_IT_SOURCE(hcryp,CRYP_IT_CCFIE) != 0x0U)) + if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_IT_CCF) != RESET) { - - /* Clear computation complete flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp,CRYP_CCF_CLEAR); - - if(hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC) + if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_CCFIE) != RESET) { - /* if header phase */ - if ((hcryp->Instance->CR & CRYP_PHASE_HEADER) == CRYP_PHASE_HEADER ) - { - CRYP_GCMCCM_SetHeaderPhase_IT(hcryp); - } - else /* if payload phase */ + /* Clear computation complete flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); + + if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC) { - CRYP_GCMCCM_SetPayloadPhase_IT(hcryp); + + /* if header phase */ + if ((hcryp->Instance->CR & CRYP_PHASE_HEADER) == CRYP_PHASE_HEADER) + { + CRYP_GCMCCM_SetHeaderPhase_IT(hcryp); + } + else /* if payload phase */ + { + CRYP_GCMCCM_SetPayloadPhase_IT(hcryp); + } } - } - else if(hcryp->Init.Algorithm == CRYP_AES_CCM) - { - /* if header phase */ - if (hcryp->Init.HeaderSize >= hcryp->CrypHeaderCount ) + else if (hcryp->Init.Algorithm == CRYP_AES_CCM) { - CRYP_GCMCCM_SetHeaderPhase_IT(hcryp); + /* if header phase */ + if (hcryp->Init.HeaderSize >= hcryp->CrypHeaderCount) + { + CRYP_GCMCCM_SetHeaderPhase_IT(hcryp); + } + else /* if payload phase */ + { + CRYP_GCMCCM_SetPayloadPhase_IT(hcryp); + } } - else /* if payload phase */ + else /* AES Algorithm ECB,CBC or CTR*/ { - CRYP_GCMCCM_SetPayloadPhase_IT(hcryp); + CRYP_AES_IT(hcryp); } } - else /* AES Algorithm ECB,CBC or CTR*/ - { - CRYP_AES_IT(hcryp); - } } /* Check if error occurred */ - if (__HAL_CRYP_GET_IT_SOURCE(hcryp,CRYP_IT_ERRIE) != RESET) + if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_ERRIE) != RESET) { /* If write Error occurred */ - if (__HAL_CRYP_GET_FLAG(hcryp,CRYP_IT_WRERR) != RESET) + if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_IT_WRERR) != RESET) { hcryp->ErrorCode |= HAL_CRYP_ERROR_WRITE; } /* If read Error occurred */ - if (__HAL_CRYP_GET_FLAG(hcryp,CRYP_IT_RDERR) != RESET) + if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_IT_RDERR) != RESET) { hcryp->ErrorCode |= HAL_CRYP_ERROR_READ; } @@ -2071,7 +2184,7 @@ __weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp) * the configuration information for CRYP module. * @retval None */ - __weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp) +__weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp) { /* Prevent unused argument(s) compilation warning */ UNUSED(hcryp); @@ -2089,7 +2202,7 @@ __weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp) * @{ */ - #if defined (CRYP) +#if defined (CRYP) /** * @brief Encryption in ECB/CBC Algorithm with DES/TDES standard. @@ -2100,9 +2213,10 @@ __weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp) */ static HAL_StatusTypeDef CRYP_TDES_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) { - uint32_t temp; /* Temporary CrypOutBuff */ + uint32_t temp[2]; /* Temporary CrypOutBuff */ uint16_t incount; /* Temporary CrypInCount Value */ uint16_t outcount; /* Temporary CrypOutCount Value */ + uint32_t i; /* Enable CRYP */ __HAL_CRYP_ENABLE(hcryp); @@ -2110,22 +2224,22 @@ static HAL_StatusTypeDef CRYP_TDES_Process(CRYP_HandleTypeDef *hcryp, uint32_t T outcount = hcryp->CrypOutCount; /*Start processing*/ - while((hcryp->CrypInCount < (hcryp->Size/4U)) && (outcount < (hcryp->Size/4U))) + while ((hcryp->CrypInCount < (hcryp->Size / 4U)) && (outcount < (hcryp->Size / 4U))) { /* Temporary CrypInCount Value */ incount = hcryp->CrypInCount; /* Write plain data and get cipher data */ - if(((hcryp->Instance->SR & CRYP_FLAG_IFNF ) != 0x0U) && (incount < (hcryp->Size/4U))) + if (((hcryp->Instance->SR & CRYP_FLAG_IFNF) != 0x0U) && (incount < (hcryp->Size / 4U))) { /* Write the input block in the IN FIFO */ - hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; } /* Wait for OFNE flag to be raised */ - if(CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK) + if (CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK) { /* Disable the CRYP peripheral clock */ __HAL_CRYP_DISABLE(hcryp); @@ -2148,15 +2262,20 @@ static HAL_StatusTypeDef CRYP_TDES_Process(CRYP_HandleTypeDef *hcryp, uint32_t T /*Temporary CrypOutCount Value*/ outcount = hcryp->CrypOutCount; - if(((hcryp->Instance->SR & CRYP_FLAG_OFNE ) != 0x0U) && (outcount < (hcryp->Size/4U))) + if (((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U) && (outcount < (hcryp->Size / 4U))) { /* Read the output block from the Output FIFO and put them in temporary Buffer then get CrypOutBuff from temporary buffer */ - temp = hcryp->Instance->DOUT; - *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp; - hcryp->CrypOutCount++; - temp = hcryp->Instance->DOUT; - *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp; - hcryp->CrypOutCount++; + for (i = 0U; i < 2U; i++) + { + temp[i] = hcryp->Instance->DOUT; + } + i = 0U; + while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 2U)) + { + *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i]; + hcryp->CrypOutCount++; + i++; + } } /*Temporary CrypOutCount Value*/ outcount = hcryp->CrypOutCount; @@ -2180,63 +2299,74 @@ static HAL_StatusTypeDef CRYP_TDES_Process(CRYP_HandleTypeDef *hcryp, uint32_t T */ static void CRYP_TDES_IT(CRYP_HandleTypeDef *hcryp) { - uint32_t temp; /* Temporary CrypOutBuff */ + uint32_t temp[2]; /* Temporary CrypOutBuff */ + uint32_t i; - if(hcryp->State == HAL_CRYP_STATE_BUSY) + if (hcryp->State == HAL_CRYP_STATE_BUSY) { - if((__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI) != 0x0U) && (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_INRIS) != 0x0U)) - + if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI) != 0x0U) { - /* Write input block in the IN FIFO */ - hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); - hcryp->CrypInCount++; - hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); - hcryp->CrypInCount++; - - if(hcryp->CrypInCount == ((uint16_t)(hcryp->Size)/4U)) + if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_INRIS) != 0x0U) { - /* Disable interruption */ - __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI); - /* Call the input data transfer complete callback */ + /* Write input block in the IN FIFO */ + hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + + if (hcryp->CrypInCount == ((uint16_t)(hcryp->Size) / 4U)) + { + /* Disable interruption */ + __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI); + /* Call the input data transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) - /*Call registered Input complete callback*/ - hcryp->InCpltCallback(hcryp); + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); #else - /*Call legacy weak Input complete callback*/ - HAL_CRYP_InCpltCallback(hcryp); + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } } } - if((__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI) != 0x0U)&& (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_OUTRIS) != 0x0U)) + if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI) != 0x0U) { - /* Read the output block from the Output FIFO and put them in temporary Buffer then get CrypOutBuff from temporary buffer */ - temp = hcryp->Instance->DOUT; - *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp; - hcryp->CrypOutCount++; - temp = hcryp->Instance->DOUT; - *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp; - hcryp->CrypOutCount++; - if(hcryp->CrypOutCount == ((uint16_t)(hcryp->Size)/4U)) + if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_OUTRIS) != 0x0U) { - /* Disable interruption */ - __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI); + /* Read the output block from the Output FIFO and put them in temporary Buffer then get CrypOutBuff from temporary buffer */ + for (i = 0U; i < 2U; i++) + { + temp[i] = hcryp->Instance->DOUT; + } + i = 0U; + while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 2U)) + { + *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i]; + hcryp->CrypOutCount++; + i++; + } + if (hcryp->CrypOutCount == ((uint16_t)(hcryp->Size) / 4U)) + { + /* Disable interruption */ + __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI); - /* Disable CRYP */ - __HAL_CRYP_DISABLE(hcryp); + /* Disable CRYP */ + __HAL_CRYP_DISABLE(hcryp); - /* Process unlocked */ - __HAL_UNLOCK(hcryp); + /* Process unlocked */ + __HAL_UNLOCK(hcryp); - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_READY; - /* Call output transfer complete callback */ + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_READY; + /* Call output transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) - /*Call registered Output complete callback*/ - hcryp->OutCpltCallback(hcryp); + /*Call registered Output complete callback*/ + hcryp->OutCpltCallback(hcryp); #else - /*Call legacy weak Output complete callback*/ - HAL_CRYP_OutCpltCallback(hcryp); + /*Call legacy weak Output complete callback*/ + HAL_CRYP_OutCpltCallback(hcryp); #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } } } } @@ -2267,25 +2397,47 @@ static void CRYP_TDES_IT(CRYP_HandleTypeDef *hcryp) static HAL_StatusTypeDef CRYP_AES_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) { uint16_t outcount; /* Temporary CrypOutCount Value */ + uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ - /* Set the Key*/ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); + if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) + { + if (hcryp->KeyIVConfig == 1U) + { + /* If the Key and IV configuration has to be done only once + and if it has already been done, skip it */ + DoKeyIVConfig = 0U; + } + else + { + /* If the Key and IV configuration has to be done only once + and if it has not been done already, do it and set KeyIVConfig + to keep track it won't have to be done again next time */ + hcryp->KeyIVConfig = 1U; + } + } - if (hcryp->Init.Algorithm != CRYP_AES_ECB) + if (DoKeyIVConfig == 1U) { - /* Set the Initialization Vector*/ + + /* Set the Key*/ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + + if (hcryp->Init.Algorithm != CRYP_AES_ECB) + { + /* Set the Initialization Vector*/ #if defined (AES) - hcryp->Instance->IVR3 = *(uint32_t*)(hcryp->Init.pInitVect); - hcryp->Instance->IVR2 = *(uint32_t*)(hcryp->Init.pInitVect+1); - hcryp->Instance->IVR1 = *(uint32_t*)(hcryp->Init.pInitVect+2); - hcryp->Instance->IVR0 = *(uint32_t*)(hcryp->Init.pInitVect+3); + hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect); + hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1); + hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2); + hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3); #else /* CRYP */ - hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect); - hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1); - hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2); - hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3); + hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect); + hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1); + hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2); + hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3); #endif /* End AES or CRYP */ - } + } + } /* if (DoKeyIVConfig == 1U) */ /* Set the phase */ hcryp->Phase = CRYP_PHASE_PROCESS; @@ -2296,10 +2448,10 @@ static HAL_StatusTypeDef CRYP_AES_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t Ti /*Temporary CrypOutCount Value*/ outcount = hcryp->CrypOutCount; - while((hcryp->CrypInCount < (hcryp->Size/4U)) && (outcount < (hcryp->Size/4U))) + while ((hcryp->CrypInCount < (hcryp->Size / 4U)) && (outcount < (hcryp->Size / 4U))) { /* Write plain Ddta and get cipher data */ - CRYP_AES_ProcessData(hcryp,Timeout); + CRYP_AES_ProcessData(hcryp, Timeout); /*Temporary CrypOutCount Value*/ outcount = hcryp->CrypOutCount; } @@ -2322,47 +2474,69 @@ static HAL_StatusTypeDef CRYP_AES_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t Ti */ static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp) { + uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ - /* Set the Key*/ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); + if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) + { + if (hcryp->KeyIVConfig == 1U) + { + /* If the Key and IV configuration has to be done only once + and if it has already been done, skip it */ + DoKeyIVConfig = 0U; + } + else + { + /* If the Key and IV configuration has to be done only once + and if it has not been done already, do it and set KeyIVConfig + to keep track it won't have to be done again next time */ + hcryp->KeyIVConfig = 1U; + } + } - if (hcryp->Init.Algorithm != CRYP_AES_ECB) + if (DoKeyIVConfig == 1U) { - /* Set the Initialization Vector*/ + /* Set the Key*/ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + + if (hcryp->Init.Algorithm != CRYP_AES_ECB) + { + /* Set the Initialization Vector*/ #if defined (AES) - hcryp->Instance->IVR3 = *(uint32_t*)(hcryp->Init.pInitVect); - hcryp->Instance->IVR2 = *(uint32_t*)(hcryp->Init.pInitVect+1); - hcryp->Instance->IVR1 = *(uint32_t*)(hcryp->Init.pInitVect+2); - hcryp->Instance->IVR0 = *(uint32_t*)(hcryp->Init.pInitVect+3); + hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect); + hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1); + hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2); + hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3); #else /* CRYP */ - hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect); - hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1); - hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2); - hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3); + hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect); + hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1); + hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2); + hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3); #endif /* End AES or CRYP */ - } + } + } /* if (DoKeyIVConfig == 1U) */ + /* Set the phase */ hcryp->Phase = CRYP_PHASE_PROCESS; - if(hcryp->Size != 0U) + if (hcryp->Size != 0U) { #if defined (AES) /* Enable computation complete flag and error interrupts */ - __HAL_CRYP_ENABLE_IT(hcryp,CRYP_IT_CCFIE | CRYP_IT_ERRIE); + __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE); /* Enable CRYP */ __HAL_CRYP_ENABLE(hcryp); /* Write the input block in the IN FIFO */ - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; #else /* CRYP */ @@ -2394,18 +2568,76 @@ static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp) * @param Timeout: Specify Timeout value * @retval HAL status */ -static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout ) +static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) { uint16_t outcount; /* Temporary CrypOutCount Value */ + uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ - /* Key preparation for ECB/CBC */ - if (hcryp->Init.Algorithm != CRYP_AES_CTR) + if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) { -#if defined (AES) - if (hcryp->AutoKeyDerivation == DISABLE)/*Mode 2 Key preparation*/ + if (hcryp->KeyIVConfig == 1U) + { + /* If the Key and IV configuration has to be done only once + and if it has already been done, skip it */ + DoKeyIVConfig = 0U; + } + else + { + /* If the Key and IV configuration has to be done only once + and if it has not been done already, do it and set KeyIVConfig + to keep track it won't have to be done again next time */ + hcryp->KeyIVConfig = 1U; + } + } + + if (DoKeyIVConfig == 1U) + { + /* Key preparation for ECB/CBC */ + if (hcryp->Init.Algorithm != CRYP_AES_CTR) { - /* Set key preparation for decryption operating mode*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION); +#if defined (AES) + if (hcryp->AutoKeyDerivation == DISABLE)/*Mode 2 Key preparation*/ + { + /* Set key preparation for decryption operating mode*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION); + + /* Set the Key*/ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + + /* Enable CRYP */ + __HAL_CRYP_ENABLE(hcryp); + + /* Wait for CCF flag to be raised */ + if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state & error code*/ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + /* Clear CCF Flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); + + /* Return to decryption operating mode(Mode 3)*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); + } + else /*Mode 4 : decryption & Key preparation*/ + { + /* Set the Key*/ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + + /* Set decryption & Key preparation operating mode*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT); + } +#else /* CRYP */ + /* change ALGOMODE to key preparation for decryption*/ + MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_CR_ALGOMODE_AES_KEY); /* Set the Key*/ CRYP_SetKey(hcryp, hcryp->Init.KeySize); @@ -2413,13 +2645,13 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Ti /* Enable CRYP */ __HAL_CRYP_ENABLE(hcryp); - /* Wait for CCF flag to be raised */ - if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + /* Wait for BUSY flag to be raised */ + if (CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK) { /* Disable the CRYP peripheral clock */ __HAL_CRYP_DISABLE(hcryp); - /* Change state & error code*/ + /* Change state */ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; hcryp->State = HAL_CRYP_STATE_READY; @@ -2427,71 +2659,34 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Ti __HAL_UNLOCK(hcryp); return HAL_ERROR; } - /* Clear CCF Flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); + /* Turn back to ALGOMODE of the configuration */ + MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm); - /* Return to decryption operating mode(Mode 3)*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); +#endif /* End AES or CRYP */ } - else /*Mode 4 : decryption & Key preparation*/ + else /*Algorithm CTR */ { /* Set the Key*/ CRYP_SetKey(hcryp, hcryp->Init.KeySize); - - /* Set decryption & Key preparation operating mode*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT); } -#else /* CRYP */ - /* change ALGOMODE to key preparation for decryption*/ - MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_CR_ALGOMODE_AES_KEY ); - - /* Set the Key*/ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); - - /* Enable CRYP */ - __HAL_CRYP_ENABLE(hcryp); - /* Wait for BUSY flag to be raised */ - if(CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK) + /* Set IV */ + if (hcryp->Init.Algorithm != CRYP_AES_ECB) { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); - - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - /* Turn back to ALGOMODE of the configuration */ - MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm ); - -#endif /* End AES or CRYP */ - } - else /*Algorithm CTR */ - { - /* Set the Key*/ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); - } - - /* Set IV */ - if (hcryp->Init.Algorithm != CRYP_AES_ECB) - { - /* Set the Initialization Vector*/ + /* Set the Initialization Vector*/ #if defined (AES) - hcryp->Instance->IVR3 = *(uint32_t*)(hcryp->Init.pInitVect); - hcryp->Instance->IVR2 = *(uint32_t*)(hcryp->Init.pInitVect+1); - hcryp->Instance->IVR1 = *(uint32_t*)(hcryp->Init.pInitVect+2); - hcryp->Instance->IVR0 = *(uint32_t*)(hcryp->Init.pInitVect+3); + hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect); + hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1); + hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2); + hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3); #else /* CRYP */ - hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect); - hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1); - hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2); - hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3); + hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect); + hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1); + hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2); + hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3); #endif /* End AES or CRYP */ - } + } + } /* if (DoKeyIVConfig == 1U) */ /* Set the phase */ hcryp->Phase = CRYP_PHASE_PROCESS; @@ -2501,10 +2696,10 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Ti /*Temporary CrypOutCount Value*/ outcount = hcryp->CrypOutCount; - while((hcryp->CrypInCount < (hcryp->Size/4U)) && (outcount < (hcryp->Size/4U))) + while ((hcryp->CrypInCount < (hcryp->Size / 4U)) && (outcount < (hcryp->Size / 4U))) { /* Write plain data and get cipher data */ - CRYP_AES_ProcessData(hcryp,Timeout); + CRYP_AES_ProcessData(hcryp, Timeout); /*Temporary CrypOutCount Value*/ outcount = hcryp->CrypOutCount; } @@ -2527,15 +2722,80 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Ti static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp) { __IO uint32_t count = 0U; + uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ - /* Key preparation for ECB/CBC */ - if (hcryp->Init.Algorithm != CRYP_AES_CTR) + if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) { -#if defined (AES) - if (hcryp->AutoKeyDerivation == DISABLE)/*Mode 2 Key preparation*/ + if (hcryp->KeyIVConfig == 1U) + { + /* If the Key and IV configuration has to be done only once + and if it has already been done, skip it */ + DoKeyIVConfig = 0U; + } + else + { + /* If the Key and IV configuration has to be done only once + and if it has not been done already, do it and set KeyIVConfig + to keep track it won't have to be done again next time */ + hcryp->KeyIVConfig = 1U; + } + } + + if (DoKeyIVConfig == 1U) + { + /* Key preparation for ECB/CBC */ + if (hcryp->Init.Algorithm != CRYP_AES_CTR) { - /* Set key preparation for decryption operating mode*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION); +#if defined (AES) + if (hcryp->AutoKeyDerivation == DISABLE)/*Mode 2 Key preparation*/ + { + /* Set key preparation for decryption operating mode*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION); + + /* Set the Key*/ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + + /* Enable CRYP */ + __HAL_CRYP_ENABLE(hcryp); + + /* Wait for CCF flag to be raised */ + count = CRYP_TIMEOUT_KEYPREPARATION; + do + { + count-- ; + if (count == 0U) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + + /* Clear CCF Flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); + + /* Return to decryption operating mode(Mode 3)*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); + } + else /*Mode 4 : decryption & key preparation*/ + { + /* Set the Key*/ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + + /* Set decryption & key preparation operating mode*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT); + } +#else /* CRYP */ + + /* change ALGOMODE to key preparation for decryption*/ + MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_CR_ALGOMODE_AES_KEY); /* Set the Key*/ CRYP_SetKey(hcryp, hcryp->Init.KeySize); @@ -2543,16 +2803,13 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp) /* Enable CRYP */ __HAL_CRYP_ENABLE(hcryp); - /* Wait for CCF flag to be raised */ + /* Wait for BUSY flag to be raised */ count = CRYP_TIMEOUT_KEYPREPARATION; do { count-- ; - if(count == 0U) + if (count == 0U) { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); - /* Change state */ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; hcryp->State = HAL_CRYP_STATE_READY; @@ -2561,101 +2818,59 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp) __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } - while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + } while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY)); - /* Clear CCF Flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); + /* Turn back to ALGOMODE of the configuration */ + MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm); - /* Return to decryption operating mode(Mode 3)*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); +#endif /* End AES or CRYP */ } - else /*Mode 4 : decryption & key preparation*/ + + else /*Algorithm CTR */ { /* Set the Key*/ CRYP_SetKey(hcryp, hcryp->Init.KeySize); - - /* Set decryption & key preparation operating mode*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT); } -#else /* CRYP */ - - /* change ALGOMODE to key preparation for decryption*/ - MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_CR_ALGOMODE_AES_KEY ); - - /* Set the Key*/ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); - - /* Enable CRYP */ - __HAL_CRYP_ENABLE(hcryp); - /* Wait for BUSY flag to be raised */ - count = CRYP_TIMEOUT_KEYPREPARATION; - do + /* Set IV */ + if (hcryp->Init.Algorithm != CRYP_AES_ECB) { - count-- ; - if(count == 0U) - { - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - } - while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY)); - - /* Turn back to ALGOMODE of the configuration */ - MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm ); - -#endif /* End AES or CRYP */ - } - - else /*Algorithm CTR */ - { - /* Set the Key*/ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); - } - - /* Set IV */ - if (hcryp->Init.Algorithm != CRYP_AES_ECB) - { - /* Set the Initialization Vector*/ + /* Set the Initialization Vector*/ #if defined (AES) - hcryp->Instance->IVR3 = *(uint32_t*)(hcryp->Init.pInitVect); - hcryp->Instance->IVR2 = *(uint32_t*)(hcryp->Init.pInitVect+1); - hcryp->Instance->IVR1 = *(uint32_t*)(hcryp->Init.pInitVect+2); - hcryp->Instance->IVR0 = *(uint32_t*)(hcryp->Init.pInitVect+3); + hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect); + hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1); + hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2); + hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3); #else /* CRYP */ - hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect); - hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1); - hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2); - hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3); + hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect); + hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1); + hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2); + hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3); #endif /* End AES or CRYP */ - } + } + } /* if (DoKeyIVConfig == 1U) */ + /* Set the phase */ hcryp->Phase = CRYP_PHASE_PROCESS; - if(hcryp->Size != 0U) + if (hcryp->Size != 0U) { #if defined (AES) /* Enable computation complete flag and error interrupts */ - __HAL_CRYP_ENABLE_IT(hcryp,CRYP_IT_CCFIE | CRYP_IT_ERRIE); + __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE); /* Enable CRYP */ __HAL_CRYP_ENABLE(hcryp); /* Write the input block in the IN FIFO */ - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; #else /* CRYP */ @@ -2689,15 +2904,78 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp) static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp) { __IO uint32_t count = 0U; + uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ - /* Key preparation for ECB/CBC */ - if (hcryp->Init.Algorithm != CRYP_AES_CTR) + if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) { -#if defined (AES) - if (hcryp->AutoKeyDerivation == DISABLE)/*Mode 2 key preparation*/ + if (hcryp->KeyIVConfig == 1U) + { + /* If the Key and IV configuration has to be done only once + and if it has already been done, skip it */ + DoKeyIVConfig = 0U; + } + else + { + /* If the Key and IV configuration has to be done only once + and if it has not been done already, do it and set KeyIVConfig + to keep track it won't have to be done again next time */ + hcryp->KeyIVConfig = 1U; + } + } + if (DoKeyIVConfig == 1U) + { + /* Key preparation for ECB/CBC */ + if (hcryp->Init.Algorithm != CRYP_AES_CTR) { - /* Set key preparation for decryption operating mode*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION); +#if defined (AES) + if (hcryp->AutoKeyDerivation == DISABLE)/*Mode 2 key preparation*/ + { + /* Set key preparation for decryption operating mode*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION); + + /* Set the Key*/ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + + /* Enable CRYP */ + __HAL_CRYP_ENABLE(hcryp); + + /* Wait for CCF flag to be raised */ + count = CRYP_TIMEOUT_KEYPREPARATION; + do + { + count-- ; + if (count == 0U) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + + /* Clear CCF Flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); + + /* Return to decryption operating mode(Mode 3)*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); + } + else /*Mode 4 : decryption & key preparation*/ + { + /* Set the Key*/ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + + /* Set decryption & Key preparation operating mode*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT); + } +#else /* CRYP */ + /* change ALGOMODE to key preparation for decryption*/ + MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_CR_ALGOMODE_AES_KEY); /* Set the Key*/ CRYP_SetKey(hcryp, hcryp->Init.KeySize); @@ -2705,12 +2983,12 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp) /* Enable CRYP */ __HAL_CRYP_ENABLE(hcryp); - /* Wait for CCF flag to be raised */ + /* Wait for BUSY flag to be raised */ count = CRYP_TIMEOUT_KEYPREPARATION; do { count-- ; - if(count == 0U) + if (count == 0U) { /* Disable the CRYP peripheral clock */ __HAL_CRYP_DISABLE(hcryp); @@ -2723,87 +3001,43 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp) __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } - while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + } while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY)); - /* Clear CCF Flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); + /* Turn back to ALGOMODE of the configuration */ + MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm); - /* Return to decryption operating mode(Mode 3)*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); +#endif /* End AES or CRYP */ } - else /*Mode 4 : decryption & key preparation*/ + else /*Algorithm CTR */ { /* Set the Key*/ CRYP_SetKey(hcryp, hcryp->Init.KeySize); - - /* Set decryption & Key preparation operating mode*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT); } -#else /* CRYP */ - /* change ALGOMODE to key preparation for decryption*/ - MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_CR_ALGOMODE_AES_KEY ); - - /* Set the Key*/ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); - - /* Enable CRYP */ - __HAL_CRYP_ENABLE(hcryp); - /* Wait for BUSY flag to be raised */ - count = CRYP_TIMEOUT_KEYPREPARATION; - do + if (hcryp->Init.Algorithm != CRYP_AES_ECB) { - count-- ; - if(count == 0U) - { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); - - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - } - while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY)); - - /* Turn back to ALGOMODE of the configuration */ - MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm ); - -#endif /* End AES or CRYP */ - } - else /*Algorithm CTR */ - { - /* Set the Key*/ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); - } - - if (hcryp->Init.Algorithm != CRYP_AES_ECB) - { - /* Set the Initialization Vector*/ + /* Set the Initialization Vector*/ #if defined (AES) - hcryp->Instance->IVR3 = *(uint32_t*)(hcryp->Init.pInitVect); - hcryp->Instance->IVR2 = *(uint32_t*)(hcryp->Init.pInitVect+1); - hcryp->Instance->IVR1 = *(uint32_t*)(hcryp->Init.pInitVect+2); - hcryp->Instance->IVR0 = *(uint32_t*)(hcryp->Init.pInitVect+3); + hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect); + hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1); + hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2); + hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3); #else /* CRYP */ - hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect); - hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1); - hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2); - hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3); + hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect); + hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1); + hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2); + hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3); #endif /* End AES or CRYP */ - } + } + } /* if (DoKeyIVConfig == 1U) */ + /* Set the phase */ hcryp->Phase = CRYP_PHASE_PROCESS; - if(hcryp->Size != 0U) + if (hcryp->Size != 0U) { /* Set the input and output addresses and start DMA transfer */ - CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), (hcryp->Size/4U), (uint32_t)(hcryp->pCrypOutBuffPtr)); + CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), (uint32_t)(hcryp->pCrypOutBuffPtr)); } else { @@ -2826,7 +3060,7 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp) */ static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma) { - CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Disable the DMA transfer for input FIFO request by resetting the DIEN bit in the DMACR register */ @@ -2837,10 +3071,10 @@ static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma) CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAINEN); /* TinyAES2, No output on CCM AES, unlock should be done when input data process complete */ - if((hcryp->Init.Algorithm & CRYP_AES_CCM) == CRYP_AES_CCM) + if ((hcryp->Init.Algorithm & CRYP_AES_CCM) == CRYP_AES_CCM) { /* Clear CCF flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp,CRYP_CCF_CLEAR); + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); /* Change the CRYP state to ready */ hcryp->State = HAL_CRYP_STATE_READY; @@ -2867,7 +3101,7 @@ static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma) */ static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma) { - CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Disable the DMA transfer for output FIFO request by resetting the DOEN bit in the DMACR register */ @@ -2875,25 +3109,25 @@ static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma) #if defined (CRYP) hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DOEN); -#if defined (CRYP_CR_ALGOMODE_AES_GCM) - if((hcryp->Init.Algorithm & CRYP_AES_GCM) != CRYP_AES_GCM) + #if defined (CRYP_CR_ALGOMODE_AES_GCM) + if ((hcryp->Init.Algorithm & CRYP_AES_GCM) != CRYP_AES_GCM) { /* Disable CRYP (not allowed in GCM)*/ __HAL_CRYP_DISABLE(hcryp); } -#else /*NO GCM CCM */ - /* Disable CRYP */ - __HAL_CRYP_DISABLE(hcryp); -#endif /* GCM CCM defined*/ + #else /*NO GCM CCM */ + /* Disable CRYP */ + __HAL_CRYP_DISABLE(hcryp); + #endif /* GCM CCM defined*/ #else /* AES */ CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAOUTEN); /* Clear CCF flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp,CRYP_CCF_CLEAR); + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - if((hcryp->Init.Algorithm & CRYP_AES_GCM_GMAC) != CRYP_AES_GCM_GMAC) + if ((hcryp->Init.Algorithm & CRYP_AES_GCM_GMAC) != CRYP_AES_GCM_GMAC) { /* Disable CRYP (not allowed in GCM)*/ __HAL_CRYP_DISABLE(hcryp); @@ -2922,10 +3156,10 @@ static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma) */ static void CRYP_DMAError(DMA_HandleTypeDef *hdma) { - CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Change the CRYP peripheral state */ - hcryp->State= HAL_CRYP_STATE_READY; + hcryp->State = HAL_CRYP_STATE_READY; /* DMA error code field */ hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA; @@ -2933,7 +3167,7 @@ static void CRYP_DMAError(DMA_HandleTypeDef *hdma) #if defined (AES) /* Clear CCF flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp,CRYP_CCF_CLEAR); + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); #endif /* AES */ @@ -2976,7 +3210,7 @@ static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uin __HAL_CRYP_ENABLE(hcryp); /* Enable the input DMA Stream */ - if ( HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DIN, Size)!=HAL_OK) + if (HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DIN, Size) != HAL_OK) { /* DMA error code field */ hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA; @@ -2991,7 +3225,7 @@ static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uin #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } /* Enable the output DMA Stream */ - if (HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUT, outputaddr, Size)!=HAL_OK) + if (HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUT, outputaddr, Size) != HAL_OK) { /* DMA error code field */ hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA; @@ -3010,14 +3244,15 @@ static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uin #else /* AES */ - if(((hcryp->Init.Algorithm & CRYP_AES_GCM_GMAC) != CRYP_AES_GCM_GMAC) && ((hcryp->Init.Algorithm & CRYP_AES_CCM) != CRYP_AES_CCM)) + if (((hcryp->Init.Algorithm & CRYP_AES_GCM_GMAC) != CRYP_AES_GCM_GMAC) + && ((hcryp->Init.Algorithm & CRYP_AES_CCM) != CRYP_AES_CCM)) { /* Enable CRYP (not allowed in GCM & CCM)*/ __HAL_CRYP_ENABLE(hcryp); } /* Enable the DMA input stream */ - if (HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DINR, Size)!=HAL_OK) + if (HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DINR, Size) != HAL_OK) { /* DMA error code field */ hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA; @@ -3032,7 +3267,7 @@ static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uin #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } /* Enable the DMA output stream */ - if (HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUTR, outputaddr, Size)!=HAL_OK) + if (HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUTR, outputaddr, Size) != HAL_OK) { /* DMA error code field */ hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA; @@ -3046,12 +3281,12 @@ static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uin HAL_CRYP_ErrorCallback(hcryp); #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } - /*AES2v1.1.1 : CCM authentication : no init phase, only header and final phase */ + /*AES2v1.1.1 : CCM authentication : no init phase, only header and final phase */ /* Enable In and Out DMA requests */ - if((hcryp->Init.Algorithm & CRYP_AES_CCM) == CRYP_AES_CCM) + if ((hcryp->Init.Algorithm & CRYP_AES_CCM) == CRYP_AES_CCM) { /* Enable only In DMA requests for CCM*/ - SET_BIT(hcryp->Instance->CR, (AES_CR_DMAINEN )); + SET_BIT(hcryp->Instance->CR, (AES_CR_DMAINEN)); } else { @@ -3071,7 +3306,8 @@ static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uin static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) { - uint32_t temp; /* Temporary CrypOutBuff */ + uint32_t temp[4]; /* Temporary CrypOutBuff */ + uint32_t i; #if defined (CRYP) uint16_t incount; /* Temporary CrypInCount Value */ uint16_t outcount; /* Temporary CrypOutCount Value */ @@ -3082,21 +3318,21 @@ static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) /*Temporary CrypOutCount Value*/ incount = hcryp->CrypInCount; - if(((hcryp->Instance->SR & CRYP_FLAG_IFNF ) != 0x0U) && (incount < (hcryp->Size/4U))) + if (((hcryp->Instance->SR & CRYP_FLAG_IFNF) != 0x0U) && (incount < (hcryp->Size / 4U))) { /* Write the input block in the IN FIFO */ - hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; } /* Wait for OFNE flag to be raised */ - if(CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK) + if (CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK) { /* Disable the CRYP peripheral clock */ __HAL_CRYP_DISABLE(hcryp); @@ -3119,37 +3355,36 @@ static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) /*Temporary CrypOutCount Value*/ outcount = hcryp->CrypOutCount; - if(((hcryp->Instance->SR & CRYP_FLAG_OFNE ) != 0x0U) && (outcount < (hcryp->Size/4U))) + if (((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U) && (outcount < (hcryp->Size / 4U))) { /* Read the output block from the Output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */ - temp = hcryp->Instance->DOUT; - *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp; - hcryp->CrypOutCount++; - temp = hcryp->Instance->DOUT; - *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp; - hcryp->CrypOutCount++; - temp = hcryp->Instance->DOUT; - *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp; - hcryp->CrypOutCount++; - temp = hcryp->Instance->DOUT; - *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp; - hcryp->CrypOutCount++; + for (i = 0U; i < 4U; i++) + { + temp[i] = hcryp->Instance->DOUT; + } + i = 0U; + while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 4U)) + { + *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i]; + hcryp->CrypOutCount++; + i++; + } } #else /* AES */ /* Write the input block in the IN FIFO */ - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; /* Wait for CCF flag to be raised */ - if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) { /* Disable the CRYP peripheral clock */ __HAL_CRYP_DISABLE(hcryp); @@ -3173,19 +3408,17 @@ static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/ - temp = hcryp->Instance->DOUTR; - *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) =temp; - hcryp->CrypOutCount++; - temp = hcryp->Instance->DOUTR; - *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) =temp; - hcryp->CrypOutCount++; - temp = hcryp->Instance->DOUTR; - *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp; - hcryp->CrypOutCount++; - temp = hcryp->Instance->DOUTR; - *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp; - hcryp->CrypOutCount++; - + for (i = 0U; i < 4U; i++) + { + temp[i] = hcryp->Instance->DOUTR; + } + i = 0U; + while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (i < 4U)) + { + *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i]; + hcryp->CrypOutCount++; + i++; + } #endif /* End AES or CRYP */ } @@ -3199,30 +3432,31 @@ static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) */ static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp) { - uint32_t temp; /* Temporary CrypOutBuff */ + uint32_t temp[4]; /* Temporary CrypOutBuff */ + uint32_t i; #if defined (CRYP) uint16_t incount; /* Temporary CrypInCount Value */ uint16_t outcount; /* Temporary CrypOutCount Value */ #endif - if(hcryp->State == HAL_CRYP_STATE_BUSY) + if (hcryp->State == HAL_CRYP_STATE_BUSY) { #if defined (CRYP) /*Temporary CrypOutCount Value*/ incount = hcryp->CrypInCount; - if(((hcryp->Instance->SR & CRYP_FLAG_IFNF ) != 0x0U) && (incount < (hcryp->Size/4U))) + if (((hcryp->Instance->SR & CRYP_FLAG_IFNF) != 0x0U) && (incount < (hcryp->Size / 4U))) { /* Write the input block in the IN FIFO */ - hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - if(hcryp->CrypInCount == ((uint16_t)(hcryp->Size)/4U)) + if (hcryp->CrypInCount == ((uint16_t)(hcryp->Size) / 4U)) { /* Disable interrupts */ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI); @@ -3240,22 +3474,21 @@ static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp) /*Temporary CrypOutCount Value*/ outcount = hcryp->CrypOutCount; - if(((hcryp->Instance->SR & CRYP_FLAG_OFNE ) != 0x0U) && (outcount < (hcryp->Size/4U))) + if (((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U) && (outcount < (hcryp->Size / 4U))) { /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */ - temp = hcryp->Instance->DOUT; - *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp; - hcryp->CrypOutCount++; - temp = hcryp->Instance->DOUT; - *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp; - hcryp->CrypOutCount++; - temp = hcryp->Instance->DOUT; - *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp; - hcryp->CrypOutCount++; - temp = hcryp->Instance->DOUT; - *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp; - hcryp->CrypOutCount++; - if(hcryp->CrypOutCount == ((uint16_t)(hcryp->Size)/4U)) + for (i = 0U; i < 4U; i++) + { + temp[i] = hcryp->Instance->DOUT; + } + i = 0U; + while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 4U)) + { + *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i]; + hcryp->CrypOutCount++; + i++; + } + if (hcryp->CrypOutCount == ((uint16_t)(hcryp->Size) / 4U)) { /* Disable interrupts */ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI); @@ -3269,13 +3502,13 @@ static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp) /* Process unlocked */ __HAL_UNLOCK(hcryp); - /* Call Output transfer complete callback */ + /* Call Output transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) - /*Call registered Output complete callback*/ - hcryp->OutCpltCallback(hcryp); + /*Call registered Output complete callback*/ + hcryp->OutCpltCallback(hcryp); #else - /*Call legacy weak Output complete callback*/ - HAL_CRYP_OutCpltCallback(hcryp); + /*Call legacy weak Output complete callback*/ + HAL_CRYP_OutCpltCallback(hcryp); #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } } @@ -3283,23 +3516,22 @@ static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp) #else /*AES*/ /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/ - temp = hcryp->Instance->DOUTR; - *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) =temp; - hcryp->CrypOutCount++; - temp = hcryp->Instance->DOUTR; - *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) =temp; - hcryp->CrypOutCount++; - temp = hcryp->Instance->DOUTR; - *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp; - hcryp->CrypOutCount++; - temp = hcryp->Instance->DOUTR; - *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp; - hcryp->CrypOutCount++; + for (i = 0U; i < 4U; i++) + { + temp[i] = hcryp->Instance->DOUTR; + } + i = 0U; + while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (i < 4U)) + { + *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i]; + hcryp->CrypOutCount++; + i++; + } - if(hcryp->CrypOutCount == (hcryp->Size/4U)) + if (hcryp->CrypOutCount == (hcryp->Size / 4U)) { /* Disable Computation Complete flag and errors interrupts */ - __HAL_CRYP_DISABLE_IT(hcryp,CRYP_IT_CCFIE|CRYP_IT_ERRIE); + __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE); /* Change the CRYP state */ hcryp->State = HAL_CRYP_STATE_READY; @@ -3322,16 +3554,16 @@ static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp) else { /* Write the input block in the IN FIFO */ - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - if(hcryp->CrypInCount == (hcryp->Size/4U)) + if (hcryp->CrypInCount == (hcryp->Size / 4U)) { /* Call Input transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) @@ -3371,58 +3603,58 @@ static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint32_t KeySize) { #if defined (CRYP) - switch(KeySize) - { - case CRYP_KEYSIZE_256B: - hcryp->Instance->K0LR = *(uint32_t*)(hcryp->Init.pKey); - hcryp->Instance->K0RR = *(uint32_t*)(hcryp->Init.pKey+1); - hcryp->Instance->K1LR = *(uint32_t*)(hcryp->Init.pKey+2); - hcryp->Instance->K1RR = *(uint32_t*)(hcryp->Init.pKey+3); - hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey+4); - hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+5); - hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+6); - hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+7); - break; - case CRYP_KEYSIZE_192B: - hcryp->Instance->K1LR = *(uint32_t*)(hcryp->Init.pKey); - hcryp->Instance->K1RR = *(uint32_t*)(hcryp->Init.pKey+1); - hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey+2); - hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+3); - hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+4); - hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+5); - break; - case CRYP_KEYSIZE_128B: - hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey); - hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+1); - hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+2); - hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+3); - - break; - default: - break; + switch (KeySize) + { + case CRYP_KEYSIZE_256B: + hcryp->Instance->K0LR = *(uint32_t *)(hcryp->Init.pKey); + hcryp->Instance->K0RR = *(uint32_t *)(hcryp->Init.pKey + 1); + hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey + 2); + hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 3); + hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 4); + hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 5); + hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 6); + hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 7); + break; + case CRYP_KEYSIZE_192B: + hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey); + hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1); + hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2); + hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3); + hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4); + hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5); + break; + case CRYP_KEYSIZE_128B: + hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey); + hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 1); + hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 2); + hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 3); + + break; + default: + break; } #else /*AES*/ - switch(KeySize) - { - case CRYP_KEYSIZE_256B: - hcryp->Instance->KEYR7 =*(uint32_t*)(hcryp->Init.pKey); - hcryp->Instance->KEYR6 =*(uint32_t*)(hcryp->Init.pKey+1); - hcryp->Instance->KEYR5 =*(uint32_t*)(hcryp->Init.pKey+2); - hcryp->Instance->KEYR4 =*(uint32_t*)(hcryp->Init.pKey+3); - hcryp->Instance->KEYR3 =*(uint32_t*)(hcryp->Init.pKey+4); - hcryp->Instance->KEYR2 =*(uint32_t*)(hcryp->Init.pKey+5); - hcryp->Instance->KEYR1 =*(uint32_t*)(hcryp->Init.pKey+6); - hcryp->Instance->KEYR0 =*(uint32_t*)(hcryp->Init.pKey+7); - break; - case CRYP_KEYSIZE_128B: - hcryp->Instance->KEYR3 =*(uint32_t*)(hcryp->Init.pKey); - hcryp->Instance->KEYR2 =*(uint32_t*)(hcryp->Init.pKey+1); - hcryp->Instance->KEYR1 =*(uint32_t*)(hcryp->Init.pKey+2); - hcryp->Instance->KEYR0 =*(uint32_t*)(hcryp->Init.pKey+3); - - break; - default: - break; + switch (KeySize) + { + case CRYP_KEYSIZE_256B: + hcryp->Instance->KEYR7 = *(uint32_t *)(hcryp->Init.pKey); + hcryp->Instance->KEYR6 = *(uint32_t *)(hcryp->Init.pKey + 1); + hcryp->Instance->KEYR5 = *(uint32_t *)(hcryp->Init.pKey + 2); + hcryp->Instance->KEYR4 = *(uint32_t *)(hcryp->Init.pKey + 3); + hcryp->Instance->KEYR3 = *(uint32_t *)(hcryp->Init.pKey + 4); + hcryp->Instance->KEYR2 = *(uint32_t *)(hcryp->Init.pKey + 5); + hcryp->Instance->KEYR1 = *(uint32_t *)(hcryp->Init.pKey + 6); + hcryp->Instance->KEYR0 = *(uint32_t *)(hcryp->Init.pKey + 7); + break; + case CRYP_KEYSIZE_128B: + hcryp->Instance->KEYR3 = *(uint32_t *)(hcryp->Init.pKey); + hcryp->Instance->KEYR2 = *(uint32_t *)(hcryp->Init.pKey + 1); + hcryp->Instance->KEYR1 = *(uint32_t *)(hcryp->Init.pKey + 2); + hcryp->Instance->KEYR0 = *(uint32_t *)(hcryp->Init.pKey + 3); + + break; + default: + break; } #endif /* End AES or CRYP */ } @@ -3438,121 +3670,148 @@ static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint32_t KeySize) static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) { uint32_t tickstart; - uint32_t wordsize = (uint32_t)(hcryp->Size)/4U ; + uint32_t wordsize = (uint32_t)(hcryp->Size) / 4U ; uint16_t outcount; /* Temporary CrypOutCount Value */ + uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ + + if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) + { + if (hcryp->KeyIVConfig == 1U) + { + /* If the Key and IV configuration has to be done only once + and if it has already been done, skip it */ + DoKeyIVConfig = 0U; + hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */ + } + else + { + /* If the Key and IV configuration has to be done only once + and if it has not been done already, do it and set KeyIVConfig + to keep track it won't have to be done again next time */ + hcryp->KeyIVConfig = 1U; + hcryp->SizesSum = hcryp->Size; /* Merely store payload length */ + } + } + else + { + hcryp->SizesSum = hcryp->Size; + } - /* Reset CrypHeaderCount */ - hcryp->CrypHeaderCount = 0U; + if (DoKeyIVConfig == 1U) + { + /* Reset CrypHeaderCount */ + hcryp->CrypHeaderCount = 0U; - /****************************** Init phase **********************************/ + /****************************** Init phase **********************************/ - CRYP_SET_PHASE(hcryp,CRYP_PHASE_INIT); + CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT); - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); + /* Set the key */ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); #if defined(CRYP) - /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/ - hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect); - hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1); - hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2); - hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3); + /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/ + hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect); + hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1); + hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2); + hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3); - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); - /* Get tick */ - tickstart = HAL_GetTick(); + /* Get tick */ + tickstart = HAL_GetTick(); - /*Wait for the CRYPEN bit to be cleared*/ - while((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + /*Wait for the CRYPEN bit to be cleared*/ + while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN) { - if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U)) + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } } } - } #else /* AES */ - /* Workaround 1 : only AES. - Datatype configuration must be 32 bits during Init phase. Only, after Init, and before re - enabling the IP, datatype different from 32 bits can be configured.*/ - /* Select DATATYPE 32 */ - MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, CRYP_DATATYPE_32B); - - /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/ - hcryp->Instance->IVR3 = *(uint32_t*)(hcryp->Init.pInitVect); - hcryp->Instance->IVR2 = *(uint32_t*)(hcryp->Init.pInitVect+1); - hcryp->Instance->IVR1 = *(uint32_t*)(hcryp->Init.pInitVect+2); - hcryp->Instance->IVR0 = *(uint32_t*)(hcryp->Init.pInitVect+3); - - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); + /* Workaround 1 : only AES. + Datatype configuration must be 32 bits during Init phase. Only, after Init, and before re + enabling the IP, datatype different from 32 bits can be configured.*/ + /* Select DATATYPE 32 */ + MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, CRYP_DATATYPE_32B); + + /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/ + hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect); + hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1); + hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2); + hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3); - /* just wait for hash computation */ - if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) - { - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); - /* Process unlocked & return error */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - /* Clear CCF flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); + /* just wait for hash computation */ + if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + { + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked & return error */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + /* Clear CCF flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); #endif /* End AES or CRYP */ - /************************ Header phase *************************************/ + /************************ Header phase *************************************/ - if(CRYP_GCMCCM_SetHeaderPhase(hcryp, Timeout) != HAL_OK) - { - return HAL_ERROR; - } + if (CRYP_GCMCCM_SetHeaderPhase(hcryp, Timeout) != HAL_OK) + { + return HAL_ERROR; + } - /*************************Payload phase ************************************/ + /*************************Payload phase ************************************/ - /* Set the phase */ - hcryp->Phase = CRYP_PHASE_PROCESS; + /* Set the phase */ + hcryp->Phase = CRYP_PHASE_PROCESS; #if defined(CRYP) - /* Disable the CRYP peripheral */ - __HAL_CRYP_DISABLE(hcryp); + /* Disable the CRYP peripheral */ + __HAL_CRYP_DISABLE(hcryp); - /* Select payload phase once the header phase is performed */ - CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); + /* Select payload phase once the header phase is performed */ + CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); #else /* AES */ - /* Select payload phase once the header phase is performed */ - CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); + /* Select payload phase once the header phase is performed */ + CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); #endif /* End AES or CRYP */ + } /* if (DoKeyIVConfig == 1U) */ if ((hcryp->Size % 16U) != 0U) { /* recalculate wordsize */ - wordsize = ((wordsize/4U)*4U) ; + wordsize = ((wordsize / 4U) * 4U) ; } /* Get tick */ @@ -3561,18 +3820,18 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t outcount = hcryp->CrypOutCount; /* Write input data and get output Data */ - while((hcryp->CrypInCount < wordsize) && (outcount < wordsize)) + while ((hcryp->CrypInCount < wordsize) && (outcount < wordsize)) { /* Write plain data and get cipher data */ - CRYP_AES_ProcessData(hcryp,Timeout); + CRYP_AES_ProcessData(hcryp, Timeout); /*Temporary CrypOutCount Value*/ outcount = hcryp->CrypOutCount; /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { /* Disable the CRYP peripheral clock */ __HAL_CRYP_DISABLE(hcryp); @@ -3593,7 +3852,7 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t /* Workaround 2 : CRYP1 & AES generates correct TAG for GCM mode only when input block size is multiple of 128 bits. If lthe size of the last block of payload is inferior to 128 bits, when GCM encryption is selected, then the TAG message will be wrong.*/ - CRYP_Workaround(hcryp,Timeout); + CRYP_Workaround(hcryp, Timeout); } /* Return function status */ @@ -3609,245 +3868,271 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp) { __IO uint32_t count = 0U; + uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ #if defined(AES) uint32_t loopcounter; uint32_t lastwordsize; uint32_t npblb; #endif /* AES */ - /* Reset CrypHeaderCount */ - hcryp->CrypHeaderCount =0U; - - /******************************* Init phase *********************************/ - - CRYP_SET_PHASE(hcryp,CRYP_PHASE_INIT); - - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); - -#if defined(CRYP) - /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/ - hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect); - hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1); - hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2); - hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3); - - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); - - /*Wait for the CRYPEN bit to be cleared*/ - count = CRYP_TIMEOUT_GCMCCMINITPHASE; - do + if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) { - count-- ; - if(count == 0U) + if (hcryp->KeyIVConfig == 1U) { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); - - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; + /* If the Key and IV configuration has to be done only once + and if it has already been done, skip it */ + DoKeyIVConfig = 0U; + hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */ + } + else + { + /* If the Key and IV configuration has to be done only once + and if it has not been done already, do it and set KeyIVConfig + to keep track it won't have to be done again next time */ + hcryp->KeyIVConfig = 1U; + hcryp->SizesSum = hcryp->Size; /* Merely store payload length */ } } - while((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN); + else + { + hcryp->SizesSum = hcryp->Size; + } -#else /* AES */ + /* Configure Key, IV and process message (header and payload) */ + if (DoKeyIVConfig == 1U) + { + /* Reset CrypHeaderCount */ + hcryp->CrypHeaderCount = 0U; - /* Workaround 1 : only AES - Datatype configuration must be 32 bits during INIT phase. Only, after INIT, and before re - enabling the IP, datatype different from 32 bits can be configured.*/ - /* Select DATATYPE 32 */ - MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, CRYP_DATATYPE_32B); + /******************************* Init phase *********************************/ - /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/ - hcryp->Instance->IVR3 = *(uint32_t*)(hcryp->Init.pInitVect); - hcryp->Instance->IVR2 = *(uint32_t*)(hcryp->Init.pInitVect+1); - hcryp->Instance->IVR1 = *(uint32_t*)(hcryp->Init.pInitVect+2); - hcryp->Instance->IVR0 = *(uint32_t*)(hcryp->Init.pInitVect+3); + CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT); - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); + /* Set the key */ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); - /* just wait for hash computation */ - count = CRYP_TIMEOUT_GCMCCMINITPHASE; - do - { - count-- ; - if(count == 0U) +#if defined(CRYP) + /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/ + hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect); + hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1); + hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2); + hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3); + + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); + + /*Wait for the CRYPEN bit to be cleared*/ + count = CRYP_TIMEOUT_GCMCCMINITPHASE; + do { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); + count-- ; + if (count == 0U) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - } - while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN); - /* Clear CCF flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); +#else /* AES */ + + /* Workaround 1 : only AES + Datatype configuration must be 32 bits during INIT phase. Only, after INIT, and before re + enabling the IP, datatype different from 32 bits can be configured.*/ + /* Select DATATYPE 32 */ + MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, CRYP_DATATYPE_32B); + + /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/ + hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect); + hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1); + hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2); + hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3); + + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); + + /* just wait for hash computation */ + count = CRYP_TIMEOUT_GCMCCMINITPHASE; + do + { + count-- ; + if (count == 0U) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + + /* Clear CCF flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); #endif /* End AES or CRYP */ - /***************************** Header phase *********************************/ + /***************************** Header phase *********************************/ #if defined(CRYP) - /* Select header phase */ - CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); + /* Select header phase */ + CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); - /* Enable interrupts */ - __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI); + /* Enable interrupts */ + __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI); - /* Enable CRYP */ - __HAL_CRYP_ENABLE(hcryp); + /* Enable CRYP */ + __HAL_CRYP_ENABLE(hcryp); #else /* AES */ - /* Workaround 1: only AES , before re-enabling the IP, datatype can be configured*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType); + /* Workaround 1: only AES , before re-enabling the IP, datatype can be configured*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType); - /* Select header phase */ - CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); + /* Select header phase */ + CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); - /* Enable computation complete flag and error interrupts */ - __HAL_CRYP_ENABLE_IT(hcryp,CRYP_IT_CCFIE | CRYP_IT_ERRIE); + /* Enable computation complete flag and error interrupts */ + __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE); - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); - if(hcryp->Init.HeaderSize == 0U) /*header phase is skipped*/ - { - /* Set the phase */ - hcryp->Phase = CRYP_PHASE_PROCESS; + if (hcryp->Init.HeaderSize == 0U) /*header phase is skipped*/ + { + /* Set the phase */ + hcryp->Phase = CRYP_PHASE_PROCESS; - /* Select payload phase once the header phase is performed */ - MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_PAYLOAD); + /* Select payload phase once the header phase is performed */ + MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_PAYLOAD); - /* Write the payload Input block in the IN FIFO */ - if(hcryp->Size == 0U) - { - /* Disable interrupts */ - __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE| CRYP_IT_ERRIE); + /* Write the payload Input block in the IN FIFO */ + if (hcryp->Size == 0U) + { + /* Disable interrupts */ + __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE); - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_READY; + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_READY; - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - } - else if (hcryp->Size >= 16U) - { - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); - hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); - hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); - hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); - hcryp->CrypInCount++; - if(hcryp->CrypInCount == ( hcryp->Size/4U)) + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + } + else if (hcryp->Size >= 16U) { - /* Call Input transfer complete callback */ + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + if (hcryp->CrypInCount == (hcryp->Size / 4U)) + { + /* Call Input transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) - /*Call registered Input complete callback*/ - hcryp->InCpltCallback(hcryp); + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); #else - /*Call legacy weak Input complete callback*/ - HAL_CRYP_InCpltCallback(hcryp); + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } } - } - else /* Size < 16Bytes : first block is the last block*/ - { - /* Workaround not implemented*/ - /* Size should be %4 otherwise Tag will be incorrectly generated for GCM Encryption: - Workaround is implemented in polling mode, so if last block of - payload <128bit don't use CRYP_Encrypt_IT otherwise TAG is incorrectly generated for GCM Encryption. */ + else /* Size < 16Bytes : first block is the last block*/ + { + /* Workaround not implemented*/ + /* Size should be %4 otherwise Tag will be incorrectly generated for GCM Encryption: + Workaround is implemented in polling mode, so if last block of + payload <128bit don't use CRYP_Encrypt_IT otherwise TAG is incorrectly generated for GCM Encryption. */ - /* Compute the number of padding bytes in last block of payload */ - npblb = 16U- (uint32_t)(hcryp->Size); + /* Compute the number of padding bytes in last block of payload */ + npblb = 16U - (uint32_t)(hcryp->Size); - /* Number of valid words (lastwordsize) in last block */ - if ((npblb % 4U) ==0U) - { - lastwordsize = (16U-npblb)/4U; - } - else - { - lastwordsize = ((16U-npblb)/4U) +1U; - } + /* Number of valid words (lastwordsize) in last block */ + if ((npblb % 4U) == 0U) + { + lastwordsize = (16U - npblb) / 4U; + } + else + { + lastwordsize = ((16U - npblb) / 4U) + 1U; + } - /* last block optionally pad the data with zeros*/ - for(loopcounter = 0U; loopcounter < lastwordsize ; loopcounter++) + /* last block optionally pad the data with zeros*/ + for (loopcounter = 0U; loopcounter < lastwordsize ; loopcounter++) + { + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + } + while (loopcounter < 4U) + { + /* pad the data with zeros to have a complete block */ + hcryp->Instance->DINR = 0x0U; + loopcounter++; + } + } + } + else if ((hcryp->Init.HeaderSize) < 4U) + { + for (loopcounter = 0U; loopcounter < hcryp->Init.HeaderSize ; loopcounter++) { - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); - hcryp->CrypInCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; } - while(loopcounter < 4U ) + while (loopcounter < 4U) { /* pad the data with zeros to have a complete block */ hcryp->Instance->DINR = 0x0U; loopcounter++; } - } - } - else if ((hcryp->Init.HeaderSize) < 4U) - { - for(loopcounter = 0U; loopcounter < hcryp->Init.HeaderSize ; loopcounter++) - { - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - } - while(loopcounter < 4U ) - { - /* pad the data with zeros to have a complete block */ - hcryp->Instance->DINR = 0x0U; - loopcounter++; - } - /* Set the phase */ - hcryp->Phase = CRYP_PHASE_PROCESS; + /* Set the phase */ + hcryp->Phase = CRYP_PHASE_PROCESS; - /* Select payload phase once the header phase is performed */ - CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); + /* Select payload phase once the header phase is performed */ + CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); - /* Call Input transfer complete callback */ + /* Call Input transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) - /*Call registered Input complete callback*/ - hcryp->InCpltCallback(hcryp); + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); #else - /*Call legacy weak Input complete callback*/ - HAL_CRYP_InCpltCallback(hcryp); + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ - } - else if ((hcryp->Init.HeaderSize) >= 4U) - { - /* Write the input block in the IN FIFO */ - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount ); - hcryp->CrypHeaderCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount ); - hcryp->CrypHeaderCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount ); - hcryp->CrypHeaderCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount ); - hcryp->CrypHeaderCount++; - } - else - { - /* Nothing to do */ - } + } + else if ((hcryp->Init.HeaderSize) >= 4U) + { + /* Write the input block in the IN FIFO */ + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++; + } + else + { + /* Nothing to do */ + } #endif /* End AES or CRYP */ + } /* end of if (DoKeyIVConfig == 1U) */ /* Return function status */ return HAL_OK; @@ -3864,114 +4149,140 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp) { __IO uint32_t count = 0U; uint32_t wordsize; + uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ - /* Reset CrypHeaderCount */ - hcryp->CrypHeaderCount = 0U; + if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) + { + if (hcryp->KeyIVConfig == 1U) + { + /* If the Key and IV configuration has to be done only once + and if it has already been done, skip it */ + DoKeyIVConfig = 0U; + hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */ + } + else + { + /* If the Key and IV configuration has to be done only once + and if it has not been done already, do it and set KeyIVConfig + to keep track it won't have to be done again next time */ + hcryp->KeyIVConfig = 1U; + hcryp->SizesSum = hcryp->Size; /* Merely store payload length */ + } + } + else + { + hcryp->SizesSum = hcryp->Size; + } - /*************************** Init phase ************************************/ + if (DoKeyIVConfig == 1U) + { + /* Reset CrypHeaderCount */ + hcryp->CrypHeaderCount = 0U; - CRYP_SET_PHASE(hcryp,CRYP_PHASE_INIT); + /*************************** Init phase ************************************/ - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); + CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT); + + /* Set the key */ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); #if defined(CRYP) - /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/ - hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect); - hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1); - hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2); - hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3); + /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/ + hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect); + hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1); + hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2); + hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3); - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); - /*Wait for the CRYPEN bit to be cleared*/ - count = CRYP_TIMEOUT_GCMCCMINITPHASE; - do - { - count-- ; - if(count == 0U) + /*Wait for the CRYPEN bit to be cleared*/ + count = CRYP_TIMEOUT_GCMCCMINITPHASE; + do { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); + count-- ; + if (count == 0U) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - } - while((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN); + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN); #else /* AES */ - /*Workaround 1 : only AES - Datatype configuration must be 32 bits during Init phase. Only, after Init, and before re - enabling the IP, datatype different from 32 bits can be configured.*/ - /* Select DATATYPE 32 */ - MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, CRYP_DATATYPE_32B); + /*Workaround 1 : only AES + Datatype configuration must be 32 bits during Init phase. Only, after Init, and before re + enabling the IP, datatype different from 32 bits can be configured.*/ + /* Select DATATYPE 32 */ + MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, CRYP_DATATYPE_32B); - /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/ - hcryp->Instance->IVR3 = *(uint32_t*)(hcryp->Init.pInitVect); - hcryp->Instance->IVR2 = *(uint32_t*)(hcryp->Init.pInitVect+1); - hcryp->Instance->IVR1 = *(uint32_t*)(hcryp->Init.pInitVect+2); - hcryp->Instance->IVR0 = *(uint32_t*)(hcryp->Init.pInitVect+3); + /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/ + hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect); + hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1); + hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2); + hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3); - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); - /* just wait for hash computation */ - count = CRYP_TIMEOUT_GCMCCMINITPHASE; - do - { - count-- ; - if(count == 0U) + /* just wait for hash computation */ + count = CRYP_TIMEOUT_GCMCCMINITPHASE; + do { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); + count-- ; + if (count == 0U) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - } - while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); - /* Clear CCF flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); + /* Clear CCF flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); #endif /* End AES or CRYP */ - /************************ Header phase *************************************/ + /************************ Header phase *************************************/ - if(CRYP_GCMCCM_SetHeaderPhase_DMA(hcryp) != HAL_OK) - { - return HAL_ERROR; - } + if (CRYP_GCMCCM_SetHeaderPhase_DMA(hcryp) != HAL_OK) + { + return HAL_ERROR; + } - /************************ Payload phase ************************************/ + /************************ Payload phase ************************************/ - /* Set the phase */ - hcryp->Phase = CRYP_PHASE_PROCESS; + /* Set the phase */ + hcryp->Phase = CRYP_PHASE_PROCESS; #if defined(CRYP) - /* Disable the CRYP peripheral */ - __HAL_CRYP_DISABLE(hcryp); + /* Disable the CRYP peripheral */ + __HAL_CRYP_DISABLE(hcryp); #endif /* CRYP */ - /* Select payload phase once the header phase is performed */ - CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); + /* Select payload phase once the header phase is performed */ + CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); - if(hcryp->Size != 0U) + } /* if (DoKeyIVConfig == 1U) */ + + if (hcryp->Size != 0U) { /* CRYP1 IP V < 2.2.1 Size should be %4 otherwise Tag will be incorrectly generated for GCM Encryption: Workaround is implemented in polling mode, so if last block of @@ -3979,14 +4290,15 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp) /* Set the input and output addresses and start DMA transfer */ if ((hcryp->Size % 16U) == 0U) { - CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), (hcryp->Size/4U), (uint32_t)(hcryp->pCrypOutBuffPtr)); + CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), (uint32_t)(hcryp->pCrypOutBuffPtr)); } else /*to compute last word<128bits, otherwise it will not be encrypted/decrypted */ { - wordsize = (uint32_t)(hcryp->Size)+(16U-((uint32_t)(hcryp->Size)%16U)) ; + wordsize = (uint32_t)(hcryp->Size) + (16U - ((uint32_t)(hcryp->Size) % 16U)) ; /* Set the input and output addresses and start DMA transfer, pCrypOutBuffPtr size should be %4 */ - CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), ((uint16_t)wordsize/4U), (uint32_t)(hcryp->pCrypOutBuffPtr)); + CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), ((uint16_t)wordsize / 4U), + (uint32_t)(hcryp->pCrypOutBuffPtr)); } } else @@ -4014,153 +4326,102 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp) static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) { uint32_t tickstart; - uint32_t wordsize= (uint32_t)(hcryp->Size)/4U; + uint32_t wordsize = (uint32_t)(hcryp->Size) / 4U; uint16_t outcount; /* Temporary CrypOutCount Value */ + uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ #if defined(AES) uint32_t loopcounter; uint32_t npblb; uint32_t lastwordsize; #endif /* AES */ - - /* Reset CrypHeaderCount */ - hcryp->CrypHeaderCount = 0U; - -#if defined(CRYP) - - /********************** Init phase ******************************************/ - - CRYP_SET_PHASE(hcryp,CRYP_PHASE_INIT); - - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); - - /* Set the initialization vector (IV) with CTR1 information */ - hcryp->Instance->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0; - hcryp->Instance->IV0RR = hcryp->Init.B0[1]; - hcryp->Instance->IV1LR = hcryp->Init.B0[2]; - hcryp->Instance->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1)| CRYP_CCM_CTR1_2; - - - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); - - /*Write B0 packet into CRYP_DIN Register*/ - if(hcryp->Init.DataType == CRYP_DATATYPE_8B) - { - hcryp->Instance->DIN = __REV(*(uint32_t*)(hcryp->Init.B0)); - hcryp->Instance->DIN = __REV( *(uint32_t*)(hcryp->Init.B0+1)); - hcryp->Instance->DIN = __REV(*(uint32_t*)(hcryp->Init.B0+2)); - hcryp->Instance->DIN = __REV(*(uint32_t*)(hcryp->Init.B0+3)); - } - else if(hcryp->Init.DataType == CRYP_DATATYPE_16B) - { - hcryp->Instance->DIN = __ROR(*(uint32_t*)(hcryp->Init.B0), 16); - hcryp->Instance->DIN = __ROR( *(uint32_t*)(hcryp->Init.B0+1), 16); - hcryp->Instance->DIN = __ROR(*(uint32_t*)(hcryp->Init.B0+2), 16); - hcryp->Instance->DIN = __ROR(*(uint32_t*)(hcryp->Init.B0+3), 16); - } - else if(hcryp->Init.DataType == CRYP_DATATYPE_1B) - { - hcryp->Instance->DIN = __RBIT(*(uint32_t*)(hcryp->Init.B0)); - hcryp->Instance->DIN = __RBIT( *(uint32_t*)(hcryp->Init.B0+1)); - hcryp->Instance->DIN = __RBIT(*(uint32_t*)(hcryp->Init.B0+2)); - hcryp->Instance->DIN = __RBIT(*(uint32_t*)(hcryp->Init.B0+3)); - } - else - { - hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0); - hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0+1); - hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0+2); - hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0+3); - } - /* Get tick */ - tickstart = HAL_GetTick(); - - /*Wait for the CRYPEN bit to be cleared*/ - while((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U)) - { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); - - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } + + if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) + { + if (hcryp->KeyIVConfig == 1U) + { + /* If the Key and IV configuration has to be done only once + and if it has already been done, skip it */ + DoKeyIVConfig = 0U; + hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */ + } + else + { + /* If the Key and IV configuration has to be done only once + and if it has not been done already, do it and set KeyIVConfig + to keep track it won't have to be done again next time */ + hcryp->KeyIVConfig = 1U; + hcryp->SizesSum = hcryp->Size; /* Merely store payload length */ } } -#else /* AES */ - /*AES2v1.1.1 : CCM authentication : no init phase, only header and final phase */ - /* Select header phase */ - CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); + else + { + hcryp->SizesSum = hcryp->Size; + } - /* configured encryption mode */ - MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT); + if (DoKeyIVConfig == 1U) + { - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); + /* Reset CrypHeaderCount */ + hcryp->CrypHeaderCount = 0U; - /* Set the initialization vector with zero values*/ - hcryp->Instance->IVR3 = 0U; - hcryp->Instance->IVR2 = 0U; - hcryp->Instance->IVR1 = 0U; - hcryp->Instance->IVR0 = 0U; +#if defined(CRYP) - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); + /********************** Init phase ******************************************/ - /*Write the B0 packet into CRYP_DIN*/ - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0); - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0+1); - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0+2); - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0+3); + CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT); - /* wait until the end of computation */ - if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) - { - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; + /* Set the key */ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); - /* Process unlocked & return error */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - /* Clear CCF flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); + /* Set the initialization vector (IV) with CTR1 information */ + hcryp->Instance->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0; + hcryp->Instance->IV0RR = hcryp->Init.B0[1]; + hcryp->Instance->IV1LR = hcryp->Init.B0[2]; + hcryp->Instance->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1) | CRYP_CCM_CTR1_2; - /* Set the phase */ - hcryp->Phase = CRYP_PHASE_PROCESS; - /* From that point the whole message must be processed, first the Header then the payload. - First the Header block(B1) : associated data length expressed in bytes concatenated with Associated Data (A)*/ + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); - if (hcryp->Init.HeaderSize != 0U) - { - if ((hcryp->Init.HeaderSize %4U )== 0U) + /*Write B0 packet into CRYP_DIN Register*/ + if (hcryp->Init.DataType == CRYP_DATATYPE_8B) { - /* HeaderSize %4, no padding */ - for(loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter+=4U) - { - /* Write the Input block in the Data Input register */ - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; + hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0)); + hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 1)); + hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 2)); + hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 3)); + } + else if (hcryp->Init.DataType == CRYP_DATATYPE_16B) + { + hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0), 16); + hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 1), 16); + hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 2), 16); + hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 3), 16); + } + else if (hcryp->Init.DataType == CRYP_DATATYPE_1B) + { + hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0)); + hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 1)); + hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 2)); + hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 3)); + } + else + { + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 1); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 2); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 3); + } + /* Get tick */ + tickstart = HAL_GetTick(); - if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + /*Wait for the CRYPEN bit to be cleared*/ + while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { /* Disable the CRYP peripheral clock */ __HAL_CRYP_DISABLE(hcryp); @@ -4173,26 +4434,133 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t __HAL_UNLOCK(hcryp); return HAL_ERROR; } - /* Clear CCF Flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); } } - else +#else /* AES */ + /*AES2v1.1.1 : CCM authentication : no init phase, only header and final phase */ + /* Select header phase */ + CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); + + /* configured encryption mode */ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT); + + /* Set the key */ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + + /* Set the initialization vector with zero values*/ + hcryp->Instance->IVR3 = 0U; + hcryp->Instance->IVR2 = 0U; + hcryp->Instance->IVR1 = 0U; + hcryp->Instance->IVR0 = 0U; + + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); + + /*Write the B0 packet into CRYP_DIN*/ + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 1); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 2); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 3); + + /* wait until the end of computation */ + if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + { + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked & return error */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + /* Clear CCF flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); + + /* Set the phase */ + hcryp->Phase = CRYP_PHASE_PROCESS; + + /* From that point the whole message must be processed, first the Header then the payload. + First the Header block(B1) : associated data length expressed in bytes concatenated with Associated Data (A)*/ + + if (hcryp->Init.HeaderSize != 0U) { - /*Write Header block in the IN FIFO without last block */ - for(loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize)-(hcryp->Init.HeaderSize %4U ))); loopcounter+=4U) + if ((hcryp->Init.HeaderSize % 4U) == 0U) { - /* Write the input block in the data input register */ - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; + /* HeaderSize %4, no padding */ + for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U) + { + /* Write the Input block in the Data Input register */ + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + + if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + /* Clear CCF Flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); + } + } + else + { + /*Write Header block in the IN FIFO without last block */ + for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U))); loopcounter += 4U) + { + /* Write the input block in the data input register */ + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + + if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + /* Clear CCF Flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); + } + /* Last block optionally pad the data with zeros*/ + for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++) + { + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + } + while (loopcounter < 4U) + { + /* Pad the data with zeros to have a complete block */ + hcryp->Instance->DINR = 0x0U; + loopcounter++; + } - if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) { /* Disable the CRYP peripheral clock */ __HAL_CRYP_DISABLE(hcryp); @@ -4205,39 +4573,11 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t __HAL_UNLOCK(hcryp); return HAL_ERROR; } - /* Clear CCF Flag */ + /* Clear CCF flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); } - /* Last block optionally pad the data with zeros*/ - for(loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize %4U )); loopcounter++) - { - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - } - while(loopcounter <4U ) - { - /* Pad the data with zeros to have a complete block */ - hcryp->Instance->DINR = 0x0U; - loopcounter++; - } - - if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) - { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); - - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - /* Clear CCF flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); } - } + } /* if (DoKeyIVConfig == 1U) */ /* Then the payload: cleartext payload (not the ciphertext payload). Write input Data, no output Data to get */ if (hcryp->Size != 0U) @@ -4245,7 +4585,7 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t if ((hcryp->Size % 16U) != 0U) { /* recalculate wordsize */ - wordsize = ((wordsize/4U)*4U) ; + wordsize = ((wordsize / 4U) * 4U) ; } /* Get tick */ @@ -4253,18 +4593,18 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t /*Temporary CrypOutCount Value*/ outcount = hcryp->CrypOutCount; - while((hcryp->CrypInCount < wordsize) && (outcount < wordsize)) + while ((hcryp->CrypInCount < wordsize) && (outcount < wordsize)) { /* Write plain data and get cipher data */ - CRYP_AES_ProcessData(hcryp,Timeout); + CRYP_AES_ProcessData(hcryp, Timeout); - /*Temporary CrypOutCount Value*/ - outcount = hcryp->CrypOutCount; + /*Temporary CrypOutCount Value*/ + outcount = hcryp->CrypOutCount; /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { /* Disable the CRYP peripheral clock */ __HAL_CRYP_DISABLE(hcryp); @@ -4283,32 +4623,32 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t if ((hcryp->Size % 16U) != 0U) { /* Compute the number of padding bytes in last block of payload */ - npblb = ((((uint32_t)(hcryp->Size)/16U)+1U)*16U)- (uint32_t)(hcryp->Size); + npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size); /* Number of valid words (lastwordsize) in last block */ - if ((npblb%4U) ==0U) + if ((npblb % 4U) == 0U) { - lastwordsize = (16U-npblb)/4U; + lastwordsize = (16U - npblb) / 4U; } else { - lastwordsize = ((16U-npblb)/4U) +1U; + lastwordsize = ((16U - npblb) / 4U) + 1U; } /* Last block optionally pad the data with zeros*/ - for(loopcounter=0U; loopcounter < lastwordsize; loopcounter ++) + for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter ++) { /* Write the last input block in the IN FIFO */ - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; } - while(loopcounter < 4U) + while (loopcounter < 4U) { /* Pad the data with zeros to have a complete block */ hcryp->Instance->DINR = 0U; loopcounter++; } /* Wait for CCF flag to be raised */ - if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) { /* Disable the CRYP peripheral clock */ __HAL_CRYP_DISABLE(hcryp); @@ -4330,33 +4670,35 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t #if defined(CRYP) - /************************* Header phase *************************************/ - /* Header block(B1) : associated data length expressed in bytes concatenated - with Associated Data (A)*/ + /************************* Header phase *************************************/ + /* Header block(B1) : associated data length expressed in bytes concatenated + with Associated Data (A)*/ - if(CRYP_GCMCCM_SetHeaderPhase(hcryp, Timeout) != HAL_OK) - { - return HAL_ERROR; - } + if (CRYP_GCMCCM_SetHeaderPhase(hcryp, Timeout) != HAL_OK) + { + return HAL_ERROR; + } - /********************** Payload phase ***************************************/ + /********************** Payload phase ***************************************/ - /* Set the phase */ - hcryp->Phase = CRYP_PHASE_PROCESS; + /* Set the phase */ + hcryp->Phase = CRYP_PHASE_PROCESS; - /* Disable the CRYP peripheral */ - __HAL_CRYP_DISABLE(hcryp); + /* Disable the CRYP peripheral */ + __HAL_CRYP_DISABLE(hcryp); - /* Select payload phase once the header phase is performed */ - CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); + /* Select payload phase once the header phase is performed */ + CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); + + } /* if (DoKeyIVConfig == 1U) */ if ((hcryp->Size % 16U) != 0U) { /* recalculate wordsize */ - wordsize = ((wordsize/4U)*4U) ; + wordsize = ((wordsize / 4U) * 4U) ; } /* Get tick */ tickstart = HAL_GetTick(); @@ -4364,15 +4706,15 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t outcount = hcryp->CrypOutCount; /* Write input data and get output data */ - while((hcryp->CrypInCount < wordsize) && (outcount < wordsize)) + while ((hcryp->CrypInCount < wordsize) && (outcount < wordsize)) { /* Write plain data and get cipher data */ - CRYP_AES_ProcessData(hcryp,Timeout); + CRYP_AES_ProcessData(hcryp, Timeout); /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { /* Disable the CRYP peripheral clock */ __HAL_CRYP_DISABLE(hcryp); @@ -4393,7 +4735,7 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t /* CRYP Workaround : CRYP1 generates correct TAG during CCM decryption only when ciphertext blocks size is multiple of 128 bits. If lthe size of the last block of payload is inferior to 128 bits, when CCM decryption is selected, then the TAG message will be wrong.*/ - CRYP_Workaround(hcryp,Timeout); + CRYP_Workaround(hcryp, Timeout); } #endif /* CRYP */ @@ -4410,83 +4752,111 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t */ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp) { + uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ #if defined(CRYP) __IO uint32_t count = 0U; #endif /* CRYP */ - /* Reset CrypHeaderCount */ - hcryp->CrypHeaderCount = 0U; + if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) + { + if (hcryp->KeyIVConfig == 1U) + { + /* If the Key and IV configuration has to be done only once + and if it has already been done, skip it */ + DoKeyIVConfig = 0U; + hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */ + } + else + { + /* If the Key and IV configuration has to be done only once + and if it has not been done already, do it and set KeyIVConfig + to keep track it won't have to be done again next time */ + hcryp->KeyIVConfig = 1U; + hcryp->SizesSum = hcryp->Size; /* Merely store payload length */ + } + } + else + { + hcryp->SizesSum = hcryp->Size; + } + + /* Configure Key, IV and process message (header and payload) */ + if (DoKeyIVConfig == 1U) + { + /* Reset CrypHeaderCount */ + hcryp->CrypHeaderCount = 0U; #if defined(CRYP) - /************ Init phase ************/ + /************ Init phase ************/ - CRYP_SET_PHASE(hcryp,CRYP_PHASE_INIT); + CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT); - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); + /* Set the key */ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); - /* Set the initialization vector (IV) with CTR1 information */ - hcryp->Instance->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0; - hcryp->Instance->IV0RR = hcryp->Init.B0[1]; - hcryp->Instance->IV1LR = hcryp->Init.B0[2]; - hcryp->Instance->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1)| CRYP_CCM_CTR1_2; + /* Set the initialization vector (IV) with CTR1 information */ + hcryp->Instance->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0; + hcryp->Instance->IV0RR = hcryp->Init.B0[1]; + hcryp->Instance->IV1LR = hcryp->Init.B0[2]; + hcryp->Instance->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1) | CRYP_CCM_CTR1_2; - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); - /*Write the B0 packet into CRYP_DIN Register*/ - if(hcryp->Init.DataType == CRYP_DATATYPE_8B) - { - hcryp->Instance->DIN = __REV(*(uint32_t*)(hcryp->Init.B0)); - hcryp->Instance->DIN = __REV( *(uint32_t*)(hcryp->Init.B0+1)); - hcryp->Instance->DIN = __REV(*(uint32_t*)(hcryp->Init.B0+2)); - hcryp->Instance->DIN = __REV(*(uint32_t*)(hcryp->Init.B0+3)); - } - else if(hcryp->Init.DataType == CRYP_DATATYPE_16B) - { - hcryp->Instance->DIN = __ROR(*(uint32_t*)(hcryp->Init.B0), 16); - hcryp->Instance->DIN = __ROR( *(uint32_t*)(hcryp->Init.B0+1), 16); - hcryp->Instance->DIN = __ROR(*(uint32_t*)(hcryp->Init.B0+2), 16); - hcryp->Instance->DIN = __ROR(*(uint32_t*)(hcryp->Init.B0+3), 16); - } - else if(hcryp->Init.DataType == CRYP_DATATYPE_1B) - { - hcryp->Instance->DIN = __RBIT(*(uint32_t*)(hcryp->Init.B0)); - hcryp->Instance->DIN = __RBIT( *(uint32_t*)(hcryp->Init.B0+1)); - hcryp->Instance->DIN = __RBIT(*(uint32_t*)(hcryp->Init.B0+2)); - hcryp->Instance->DIN = __RBIT(*(uint32_t*)(hcryp->Init.B0+3)); - } - else - { - hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0); - hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0+1); - hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0+2); - hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0+3); - } - /*Wait for the CRYPEN bit to be cleared*/ - count = CRYP_TIMEOUT_GCMCCMINITPHASE; - do - { - count-- ; - if(count == 0U) + /*Write the B0 packet into CRYP_DIN Register*/ + if (hcryp->Init.DataType == CRYP_DATATYPE_8B) { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); + hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0)); + hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 1)); + hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 2)); + hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 3)); + } + else if (hcryp->Init.DataType == CRYP_DATATYPE_16B) + { + hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0), 16); + hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 1), 16); + hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 2), 16); + hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 3), 16); + } + else if (hcryp->Init.DataType == CRYP_DATATYPE_1B) + { + hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0)); + hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 1)); + hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 2)); + hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 3)); + } + else + { + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 1); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 2); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 3); + } + /*Wait for the CRYPEN bit to be cleared*/ + count = CRYP_TIMEOUT_GCMCCMINITPHASE; + do + { + count-- ; + if (count == 0U) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - } - while((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN); + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN); + + /* Select header phase */ + CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); - /* Select header phase */ - CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); + } /* end of if (DoKeyIVConfig == 1U) */ /* Enable interrupts */ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI); @@ -4496,33 +4866,34 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp) #else /* AES */ - /*AES2v1.1.1 : CCM authentication : no init phase, only header and final phase */ - /* Select header phase */ - CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); + /*AES2v1.1.1 : CCM authentication : no init phase, only header and final phase */ + /* Select header phase */ + CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); - /* configured mode and encryption mode */ - MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT); + /* configured mode and encryption mode */ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT); - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); + /* Set the key */ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); - /* Set the initialization vector with zero values*/ - hcryp->Instance->IVR3 = 0U; - hcryp->Instance->IVR2 = 0U; - hcryp->Instance->IVR1 = 0U; - hcryp->Instance->IVR0 = 0U; + /* Set the initialization vector with zero values*/ + hcryp->Instance->IVR3 = 0U; + hcryp->Instance->IVR2 = 0U; + hcryp->Instance->IVR1 = 0U; + hcryp->Instance->IVR0 = 0U; - /* Enable interrupts */ - __HAL_CRYP_ENABLE_IT(hcryp,CRYP_IT_CCFIE | CRYP_IT_ERRIE); - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); + /* Enable interrupts */ + __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE); + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); - /*Write the B0 packet into CRYP_DIN*/ - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0); - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0+1); - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0+2); - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0+3); + /*Write the B0 packet into CRYP_DIN*/ + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 1); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 2); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 3); + } /* end of if (DoKeyIVConfig == 1U) */ #endif /* End AES or CRYP */ /* Return function status */ @@ -4539,155 +4910,380 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp) { uint32_t wordsize; __IO uint32_t count = 0U; + uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ +#if defined(AES) + uint32_t loopcounter; + uint32_t npblb; + uint32_t lastwordsize; +#endif + + if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) + { + if (hcryp->KeyIVConfig == 1U) + { + /* If the Key and IV configuration has to be done only once + and if it has already been done, skip it */ + DoKeyIVConfig = 0U; + hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */ + } + else + { + /* If the Key and IV configuration has to be done only once + and if it has not been done already, do it and set KeyIVConfig + to keep track it won't have to be done again next time */ + hcryp->KeyIVConfig = 1U; + hcryp->SizesSum = hcryp->Size; /* Merely store payload length */ + } + } + else + { + hcryp->SizesSum = hcryp->Size; + } + + if (DoKeyIVConfig == 1U) + { - /* Reset CrypHeaderCount */ - hcryp->CrypHeaderCount = 0U; + /* Reset CrypHeaderCount */ + hcryp->CrypHeaderCount = 0U; #if defined(CRYP) - /************************** Init phase **************************************/ + /************************** Init phase **************************************/ - CRYP_SET_PHASE(hcryp,CRYP_PHASE_INIT); + CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT); - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); + /* Set the key */ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); - /* Set the initialization vector (IV) with CTR1 information */ - hcryp->Instance->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0; - hcryp->Instance->IV0RR = hcryp->Init.B0[1]; - hcryp->Instance->IV1LR = hcryp->Init.B0[2]; - hcryp->Instance->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1)| CRYP_CCM_CTR1_2; + /* Set the initialization vector (IV) with CTR1 information */ + hcryp->Instance->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0; + hcryp->Instance->IV0RR = hcryp->Init.B0[1]; + hcryp->Instance->IV1LR = hcryp->Init.B0[2]; + hcryp->Instance->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1) | CRYP_CCM_CTR1_2; - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); - /*Write the B0 packet into CRYP_DIN Register*/ - if(hcryp->Init.DataType == CRYP_DATATYPE_8B) - { - hcryp->Instance->DIN = __REV(*(uint32_t*)(hcryp->Init.B0)); - hcryp->Instance->DIN = __REV( *(uint32_t*)(hcryp->Init.B0+1)); - hcryp->Instance->DIN = __REV(*(uint32_t*)(hcryp->Init.B0+2)); - hcryp->Instance->DIN = __REV(*(uint32_t*)(hcryp->Init.B0+3)); - } - else if(hcryp->Init.DataType == CRYP_DATATYPE_16B) - { - hcryp->Instance->DIN = __ROR(*(uint32_t*)(hcryp->Init.B0), 16); - hcryp->Instance->DIN = __ROR( *(uint32_t*)(hcryp->Init.B0+1), 16); - hcryp->Instance->DIN = __ROR(*(uint32_t*)(hcryp->Init.B0+2), 16); - hcryp->Instance->DIN = __ROR(*(uint32_t*)(hcryp->Init.B0+3), 16); - } - else if(hcryp->Init.DataType == CRYP_DATATYPE_1B) - { - hcryp->Instance->DIN = __RBIT(*(uint32_t*)(hcryp->Init.B0)); - hcryp->Instance->DIN = __RBIT( *(uint32_t*)(hcryp->Init.B0+1)); - hcryp->Instance->DIN = __RBIT(*(uint32_t*)(hcryp->Init.B0+2)); - hcryp->Instance->DIN = __RBIT(*(uint32_t*)(hcryp->Init.B0+3)); - } - else - { - hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0); - hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0+1); - hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0+2); - hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0+3); - } + /*Write the B0 packet into CRYP_DIN Register*/ + if (hcryp->Init.DataType == CRYP_DATATYPE_8B) + { + hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0)); + hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 1)); + hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 2)); + hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 3)); + } + else if (hcryp->Init.DataType == CRYP_DATATYPE_16B) + { + hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0), 16); + hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 1), 16); + hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 2), 16); + hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 3), 16); + } + else if (hcryp->Init.DataType == CRYP_DATATYPE_1B) + { + hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0)); + hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 1)); + hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 2)); + hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 3)); + } + else + { + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 1); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 2); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 3); + } - /*Wait for the CRYPEN bit to be cleared*/ - count = CRYP_TIMEOUT_GCMCCMINITPHASE; - do - { - count-- ; - if(count == 0U) + /*Wait for the CRYPEN bit to be cleared*/ + count = CRYP_TIMEOUT_GCMCCMINITPHASE; + do { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); + count-- ; + if (count == 0U) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - } - while((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN); + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN); #else /* AES */ - /*AES2v1.1.1 : CCM authentication : no init phase, only header and final phase */ - /* Select header phase */ - CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); + /*AES2v1.1.1 : CCM authentication : no init phase, only header and final phase */ + /* Select header phase */ + CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); - /* configured CCM chaining mode and encryption mode */ - MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT); + /* configured encryption mode */ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT); - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); + /* Set the key */ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); - /* Set the initialization vector with zero values*/ - hcryp->Instance->IVR3 = 0U; - hcryp->Instance->IVR2 = 0U; - hcryp->Instance->IVR1 = 0U; - hcryp->Instance->IVR0 = 0U; + /* Set the initialization vector with zero values*/ + hcryp->Instance->IVR3 = 0U; + hcryp->Instance->IVR2 = 0U; + hcryp->Instance->IVR1 = 0U; + hcryp->Instance->IVR0 = 0U; - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); - /*Write the B0 packet into CRYP_DIN*/ - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0); - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0+1); - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0+2); - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0+3); + /*Write the B0 packet into CRYP_DIN*/ + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 1); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 2); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 3); - /* wait until the end of computation */ - count = CRYP_TIMEOUT_GCMCCMINITPHASE; - do - { - count-- ; - if(count == 0U) -{ - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); + count = CRYP_TIMEOUT_GCMCCMINITPHASE; + do + { + count-- ; + if (count == 0U) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; -} - } - while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + /* Process Unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + /* Clear CCF flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - /* Clear CCF flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); + /* Set the phase */ + hcryp->Phase = CRYP_PHASE_PROCESS; -#endif /* AES */ + /* From that point the whole message must be processed, first the Header then the payload. + First the Header block(B1) : associated data length expressed in bytes concatenated with Associated Data (A)*/ + + if (hcryp->Init.HeaderSize != 0U) + { + if ((hcryp->Init.HeaderSize % 4U) == 0U) + { + /* HeaderSize %4, no padding */ + for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U) + { + /* Write the Input block in the Data Input register */ + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + + /* wait until the end of computation */ + count = CRYP_TIMEOUT_GCMCCMINITPHASE; + do + { + count-- ; + if (count == 0U) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + /* Clear CCF flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); + } + } + else + { + /*Write Header block in the IN FIFO without last block */ + for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U))); loopcounter += 4U) + { + /* Write the input block in the data input register */ + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + + count = CRYP_TIMEOUT_GCMCCMINITPHASE; + do + { + count-- ; + if (count == 0U) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + /* Clear CCF flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); + } + /* Last block optionally pad the data with zeros*/ + for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++) + { + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + } + while (loopcounter < 4U) + { + /* Pad the data with zeros to have a complete block */ + hcryp->Instance->DINR = 0x0U; + loopcounter++; + } + + count = CRYP_TIMEOUT_GCMCCMINITPHASE; + do + { + count-- ; + if (count == 0U) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); - /********************* Header phase *****************************************/ + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; - if(CRYP_GCMCCM_SetHeaderPhase_DMA(hcryp) != HAL_OK) + /* Process Unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + /* Clear CCF flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); + } + } + } /* if (DoKeyIVConfig == 1U) */ + /* Then the payload: cleartext payload (not the ciphertext payload). + Write input Data, no output Data to get */ + if (hcryp->Size != 0U) { - return HAL_ERROR; - } + if (hcryp->Size >= 16U) + { + if ((hcryp->Size % 16U) == 0U) + { + CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), (uint32_t)(hcryp->pCrypOutBuffPtr)); + } + else /*to compute last word<128bits, otherwise it will not be encrypted/decrypted */ + { + wordsize = (uint32_t)(hcryp->Size) + (16U - ((uint32_t)(hcryp->Size) % 16U)) ; + + /* Set the input and output addresses and start DMA transfer, pCrypOutBuffPtr size should be %4 */ + CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), ((uint16_t)wordsize / 4U), + (uint32_t)(hcryp->pCrypOutBuffPtr)); + } + } + if ((hcryp->Size < 16U) != 0U) + { + /* Compute the number of padding bytes in last block of payload */ + npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size); + + /* Number of valid words (lastwordsize) in last block */ + if ((npblb % 4U) == 0U) + { + lastwordsize = (16U - npblb) / 4U; + } + else + { + lastwordsize = ((16U - npblb) / 4U) + 1U; + } + /* Last block optionally pad the data with zeros*/ + for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter ++) + { + /* Write the last input block in the IN FIFO */ + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + } + while (loopcounter < 4U) + { + /* Pad the data with zeros to have a complete block */ + hcryp->Instance->DINR = 0U; + loopcounter++; + } + count = CRYP_TIMEOUT_GCMCCMINITPHASE; + do + { + count-- ; + if (count == 0U) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); - /******************** Payload phase *****************************************/ + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; - /* Set the phase */ - hcryp->Phase = CRYP_PHASE_PROCESS; + /* Process Unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + /* Clear CCF flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + + /* Change the CRYP state and phase */ + hcryp->State = HAL_CRYP_STATE_READY; + } + } + else + { + /* Process unLocked */ + __HAL_UNLOCK(hcryp); + /* Change the CRYP state and phase */ + hcryp->State = HAL_CRYP_STATE_READY; + } +#endif /* AES */ #if defined(CRYP) + /********************* Header phase *****************************************/ - /* Disable the CRYP peripheral */ - __HAL_CRYP_DISABLE(hcryp); + if (CRYP_GCMCCM_SetHeaderPhase_DMA(hcryp) != HAL_OK) + { + return HAL_ERROR; + } - /* Select payload phase once the header phase is performed */ - CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); + /******************** Payload phase *****************************************/ -#endif /* CRYP */ + /* Set the phase */ + hcryp->Phase = CRYP_PHASE_PROCESS; + + /* Disable the CRYP peripheral */ + __HAL_CRYP_DISABLE(hcryp); - if(hcryp->Size != 0U) + /* Select payload phase once the header phase is performed */ + CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); + + } /* if (DoKeyIVConfig == 1U) */ + if (hcryp->Size != 0U) { /* Size should be %4 otherwise Tag will be incorrectly generated for GCM Encryption & CCM Decryption Workaround is implemented in polling mode, so if last block of @@ -4695,14 +5291,15 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp) /* Set the input and output addresses and start DMA transfer */ if ((hcryp->Size % 16U) == 0U) { - CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), hcryp->Size/4U, (uint32_t)(hcryp->pCrypOutBuffPtr)); + CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), hcryp->Size / 4U, (uint32_t)(hcryp->pCrypOutBuffPtr)); } else { - wordsize = (uint32_t)(hcryp->Size)+16U-((uint32_t)(hcryp->Size) %16U) ; + wordsize = (uint32_t)(hcryp->Size) + 16U - ((uint32_t)(hcryp->Size) % 16U) ; /* Set the input and output addresses and start DMA transfer, pCrypOutBuffPtr size should be %4*/ - CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), (uint16_t)wordsize/4U, (uint32_t)(hcryp->pCrypOutBuffPtr)); + CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (uint16_t)wordsize / 4U, + (uint32_t)(hcryp->pCrypOutBuffPtr)); } } else /*Size = 0*/ @@ -4713,7 +5310,7 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp) /* Change the CRYP state and phase */ hcryp->State = HAL_CRYP_STATE_READY; } - +#endif /* CRYP */ /* Return function status */ return HAL_OK; } @@ -4727,20 +5324,21 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp) static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp) { uint32_t loopcounter; - uint32_t temp; /* Temporary CrypOutBuff */ + uint32_t temp[4]; /* Temporary CrypOutBuff */ uint32_t lastwordsize; uint32_t npblb; - #if defined(AES) + uint32_t i; +#if defined(AES) uint16_t outcount; /* Temporary CrypOutCount Value */ #endif /* AES */ /***************************** Payload phase *******************************/ #if defined(CRYP) - if(hcryp->Size == 0U) + if (hcryp->Size == 0U) { /* Disable interrupts */ - __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI| CRYP_IT_OUTI); + __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI); /* Process unlocked */ __HAL_UNLOCK(hcryp); @@ -4749,18 +5347,18 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp) hcryp->State = HAL_CRYP_STATE_READY; } - else if (((hcryp->Size/4U) - (hcryp->CrypInCount)) >= 4U) + else if (((hcryp->Size / 4U) - (hcryp->CrypInCount)) >= 4U) { /* Write the input block in the IN FIFO */ - hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - if(((hcryp->Size/4U) == hcryp->CrypInCount) &&((hcryp->Size %16U )== 0U)) + if (((hcryp->Size / 4U) == hcryp->CrypInCount) && ((hcryp->Size % 16U) == 0U)) { /* Disable interrupts */ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI); @@ -4774,22 +5372,21 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp) HAL_CRYP_InCpltCallback(hcryp); #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } - if(hcryp->CrypOutCount < (hcryp->Size/4U)) + if (hcryp->CrypOutCount < (hcryp->Size / 4U)) { /* Read the output block from the Output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */ - temp = hcryp->Instance->DOUT; - *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp; - hcryp->CrypOutCount++; - temp = hcryp->Instance->DOUT; - *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp; - hcryp->CrypOutCount++; - temp = hcryp->Instance->DOUT; - *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp; - hcryp->CrypOutCount++; - temp = hcryp->Instance->DOUT; - *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp; - hcryp->CrypOutCount++; - if (((hcryp->Size/4U) == hcryp->CrypOutCount)&&((hcryp->Size %16U )== 0U)) + for (i = 0U; i < 4U; i++) + { + temp[i] = hcryp->Instance->DOUT; + } + i = 0U; + while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 4U)) + { + *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i]; + hcryp->CrypOutCount++; + i++; + } + if (((hcryp->Size / 4U) == hcryp->CrypOutCount) && ((hcryp->Size % 16U) == 0U)) { /* Disable interrupts */ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI); @@ -4814,32 +5411,32 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp) } } } - else if ((hcryp->Size %16U )!= 0U) + else if ((hcryp->Size % 16U) != 0U) { /* Size should be %4 in word and %16 in byte otherwise TAG will be incorrectly generated for GCM Encryption & CCM Decryption Workaround is implemented in polling mode, so if last block of payload <128bit don't use CRYP_AESGCM_Encrypt_IT otherwise TAG is incorrectly generated. */ - /* Compute the number of padding bytes in last block of payload */ - npblb = ((((uint32_t)(hcryp->Size)/16U)+1U)*16U)- (uint32_t)(hcryp->Size); + /* Compute the number of padding bytes in last block of payload */ + npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size); /* Number of valid words (lastwordsize) in last block */ - if ((npblb%4U) ==0U) + if ((npblb % 4U) == 0U) { - lastwordsize = (16U-npblb)/4U; + lastwordsize = (16U - npblb) / 4U; } else { - lastwordsize = ((16U-npblb)/4U) +1U; + lastwordsize = ((16U - npblb) / 4U) + 1U; } /* Last block optionally pad the data with zeros*/ - for(loopcounter = 0U; loopcounter < lastwordsize; loopcounter++) + for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++) { - hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; } - while(loopcounter < 4U ) + while (loopcounter < 4U) { /* Pad the data with zeros to have a complete block */ hcryp->Instance->DIN = 0x0U; @@ -4847,22 +5444,32 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp) } __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI); - if((hcryp->Instance->SR & CRYP_FLAG_OFNE ) != 0x0U) + if ((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U) { - for(loopcounter = 0U; loopcounter < 4U; loopcounter++) + for (i = 0U; i < 4U; i++) { - /* Read the output block from the output FIFO and put them in temporary buffer */ - temp= hcryp->Instance->DOUT; - - /*get CrypOutBuff from temporary buffer */ - *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount))=temp; + temp[i] = hcryp->Instance->DOUT; + } + if (((hcryp->Size) / 4U) == 0U) + { + for (i = 0U; i < ((uint32_t)(hcryp->Size) % 4U); i++) + { + *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i]; + hcryp->CrypOutCount++; + } + } + i = 0x0U; + while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 4U)) + { + *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i]; hcryp->CrypOutCount++; + i++; } } - if(hcryp->CrypOutCount >= (hcryp->Size/4U)) + if (hcryp->CrypOutCount >= (hcryp->Size / 4U)) { /* Disable interrupts */ - __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI|CRYP_IT_INI); + __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI | CRYP_IT_INI); /* Change the CRYP peripheral state */ hcryp->State = HAL_CRYP_STATE_READY; @@ -4887,25 +5494,24 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp) #else /* AES */ /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/ - temp = hcryp->Instance->DOUTR; - *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) =temp; - hcryp->CrypOutCount++; - temp = hcryp->Instance->DOUTR; - *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) =temp; - hcryp->CrypOutCount++; - temp = hcryp->Instance->DOUTR; - *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp; - hcryp->CrypOutCount++; - temp = hcryp->Instance->DOUTR; - *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp; - hcryp->CrypOutCount++; + for (i = 0U; i < 4U; i++) + { + temp[i] = hcryp->Instance->DOUTR; + } + i = 0U; + while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (i < 4U)) + { + *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i]; + hcryp->CrypOutCount++; + i++; + } /*Temporary CrypOutCount Value*/ outcount = hcryp->CrypOutCount; - if((hcryp->CrypOutCount >= (hcryp->Size/4U)) && ((outcount*4U) >= hcryp->Size) ) + if ((hcryp->CrypOutCount >= (hcryp->Size / 4U)) && ((outcount * 4U) >= hcryp->Size)) { /* Disable computation complete flag and errors interrupts */ - __HAL_CRYP_DISABLE_IT(hcryp,CRYP_IT_CCFIE|CRYP_IT_ERRIE); + __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE); /* Change the CRYP state */ hcryp->State = HAL_CRYP_STATE_READY; @@ -4913,28 +5519,28 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp) /* Process unlocked */ __HAL_UNLOCK(hcryp); - /* Call output transfer complete callback */ + /* Call output transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) - /*Call registered Output complete callback*/ - hcryp->OutCpltCallback(hcryp); + /*Call registered Output complete callback*/ + hcryp->OutCpltCallback(hcryp); #else - /*Call legacy weak Output complete callback*/ - HAL_CRYP_OutCpltCallback(hcryp); + /*Call legacy weak Output complete callback*/ + HAL_CRYP_OutCpltCallback(hcryp); #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } - else if (((hcryp->Size/4U) - (hcryp->CrypInCount)) >= 4U) + else if (((hcryp->Size / 4U) - (hcryp->CrypInCount)) >= 4U) { /* Write the input block in the IN FIFO */ - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - if((hcryp->CrypInCount == hcryp->Size) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)) + if ((hcryp->CrypInCount == hcryp->Size) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)) { /* Call Input transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) @@ -4953,25 +5559,25 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp) payload <128bit don't use CRYP_Encrypt_IT otherwise TAG is incorrectly generated for GCM Encryption & CCM Decryption. */ /* Compute the number of padding bytes in last block of payload */ - npblb = ((((uint32_t)(hcryp->Size)/16U)+1U)*16U) - (uint32_t)(hcryp->Size); + npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size); - /* Number of valid words (lastwordsize) in last block */ - if ((npblb%4U) ==0U) + /* Number of valid words (lastwordsize) in last block */ + if ((npblb % 4U) == 0U) { - lastwordsize = (16U-npblb)/4U; + lastwordsize = (16U - npblb) / 4U; } else { - lastwordsize = ((16U-npblb)/4U) +1U; + lastwordsize = ((16U - npblb) / 4U) + 1U; } /* Last block optionally pad the data with zeros*/ - for(loopcounter = 0U; loopcounter < lastwordsize; loopcounter++) + for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++) { - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; } - while(loopcounter < 4U ) + while (loopcounter < 4U) { /* pad the data with zeros to have a complete block */ hcryp->Instance->DINR = 0x0U; @@ -4996,7 +5602,7 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u /***************************** Header phase for GCM/GMAC or CCM *********************************/ - if((hcryp->Init.HeaderSize != 0U)) + if ((hcryp->Init.HeaderSize != 0U)) { #if defined(CRYP) @@ -5007,22 +5613,22 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u /* Enable the CRYP peripheral */ __HAL_CRYP_ENABLE(hcryp); - if ((hcryp->Init.HeaderSize %4U )== 0U) + if ((hcryp->Init.HeaderSize % 4U) == 0U) { /* HeaderSize %4, no padding */ - for(loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter+=4U) + for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U) { - hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; - hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; - hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; - hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; /* Wait for IFEM to be raised */ - if(CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK) + if (CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK) { /* Disable the CRYP peripheral clock */ __HAL_CRYP_DISABLE(hcryp); @@ -5040,19 +5646,19 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u else { /*Write header block in the IN FIFO without last block */ - for(loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize)-(hcryp->Init.HeaderSize %4U ))); loopcounter+= 4U) + for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U))); loopcounter += 4U) { - hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; - hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; - hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; - hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; /* Wait for IFEM to be raised */ - if(CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK) + if (CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK) { /* Disable the CRYP peripheral clock */ __HAL_CRYP_DISABLE(hcryp); @@ -5067,19 +5673,19 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u } } /* Last block optionally pad the data with zeros*/ - for(loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize %4U )); loopcounter++) + for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++) { - hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; } - while(loopcounter <4U ) + while (loopcounter < 4U) { /* pad the data with zeros to have a complete block */ hcryp->Instance->DIN = 0x0U; loopcounter++; } /* Wait for CCF IFEM to be raised */ - if(CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK) + if (CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK) { /* Disable the CRYP peripheral clock */ __HAL_CRYP_DISABLE(hcryp); @@ -5094,7 +5700,7 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u } } /* Wait until the complete message has been processed */ - if(CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK) + if (CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK) { /* Disable the CRYP peripheral clock */ __HAL_CRYP_DISABLE(hcryp); @@ -5110,7 +5716,7 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u #else /* AES */ - if(hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC) + if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC) { /* Workaround 1 :only AES before re-enabling the IP, datatype can be configured.*/ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType); @@ -5122,22 +5728,22 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u __HAL_CRYP_ENABLE(hcryp); } - if ((hcryp->Init.HeaderSize %4U )== 0U) + if ((hcryp->Init.HeaderSize % 4U) == 0U) { /* HeaderSize %4, no padding */ - for(loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter+= 4U) + for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U) { /* Write the input block in the data input register */ - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; - if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) { /* Disable the CRYP peripheral clock */ __HAL_CRYP_DISABLE(hcryp); @@ -5157,19 +5763,19 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u else { /*Write header block in the IN FIFO without last block */ - for(loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize)-(hcryp->Init.HeaderSize %4U ))); loopcounter+=4U) + for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U))); loopcounter += 4U) { /* Write the input block in the data input register */ - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; - if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) { /* Disable the CRYP peripheral clock */ __HAL_CRYP_DISABLE(hcryp); @@ -5186,19 +5792,19 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); } /* Last block optionally pad the data with zeros*/ - for(loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize %4U )); loopcounter++) + for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++) { - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; } - while(loopcounter < 4U ) + while (loopcounter < 4U) { /*Pad the data with zeros to have a complete block */ hcryp->Instance->DINR = 0x0U; loopcounter++; } - if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) { /* Disable the CRYP peripheral clock */ __HAL_CRYP_DISABLE(hcryp); @@ -5219,7 +5825,7 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u else { #if defined(AES) - if(hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC) + if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC) { /*Workaround 1: only AES, before re-enabling the IP, datatype can be configured.*/ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType); @@ -5248,7 +5854,7 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry uint32_t loopcounter; /***************************** Header phase for GCM/GMAC or CCM *********************************/ - if((hcryp->Init.HeaderSize != 0U)) + if ((hcryp->Init.HeaderSize != 0U)) { #if defined(CRYP) @@ -5259,18 +5865,18 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry /* Enable the CRYP peripheral */ __HAL_CRYP_ENABLE(hcryp); - if ((hcryp->Init.HeaderSize %4U )== 0U) + if ((hcryp->Init.HeaderSize % 4U) == 0U) { /* HeaderSize %4, no padding */ - for(loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter+=4U) + for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U) { - hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; - hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; - hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; - hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; /* Wait for IFEM to be raised */ @@ -5278,7 +5884,7 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry do { count-- ; - if(count == 0U) + if (count == 0U) { /* Disable the CRYP peripheral clock */ __HAL_CRYP_DISABLE(hcryp); @@ -5291,22 +5897,21 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } - while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM)); + } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM)); } } else { /*Write header block in the IN FIFO without last block */ - for(loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize)-(hcryp->Init.HeaderSize %4U ))); loopcounter+=4U) + for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U))); loopcounter += 4U) { - hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; - hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; - hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; - hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; /* Wait for IFEM to be raised */ @@ -5314,7 +5919,7 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry do { count-- ; - if(count == 0U) + if (count == 0U) { /* Disable the CRYP peripheral clock */ __HAL_CRYP_DISABLE(hcryp); @@ -5327,16 +5932,15 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } - while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM)); + } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM)); } /* Last block optionally pad the data with zeros*/ - for(loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize %4U )); loopcounter++) + for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++) { - hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; } - while(loopcounter < 4U ) + while (loopcounter < 4U) { /* Pad the data with zeros to have a complete block */ hcryp->Instance->DIN = 0x0U; @@ -5347,7 +5951,7 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry do { count-- ; - if(count == 0U) + if (count == 0U) { /* Disable the CRYP peripheral clock */ __HAL_CRYP_DISABLE(hcryp); @@ -5360,15 +5964,14 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } - while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM)); + } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM)); } /* Wait until the complete message has been processed */ count = CRYP_TIMEOUT_GCMCCMHEADERPHASE; do { count-- ; - if(count == 0U) + if (count == 0U) { /* Disable the CRYP peripheral clock */ __HAL_CRYP_DISABLE(hcryp); @@ -5381,12 +5984,11 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } - while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY)); + } while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY)); #else /* AES */ - if(hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC) + if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC) { /* Workaround 1: only AES, before re-enabling the IP, datatype can be configured.*/ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType); @@ -5397,19 +5999,19 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry /* Enable the CRYP peripheral */ __HAL_CRYP_ENABLE(hcryp); } - if ((hcryp->Init.HeaderSize %4U )== 0U) + if ((hcryp->Init.HeaderSize % 4U) == 0U) { /* HeaderSize %4, no padding */ - for(loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter+=4U) + for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U) { /* Write the input block in the data input register */ - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; /*Wait on CCF flag*/ @@ -5417,7 +6019,7 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry do { count-- ; - if(count == 0U) + if (count == 0U) { /* Disable the CRYP peripheral clock */ __HAL_CRYP_DISABLE(hcryp); @@ -5430,8 +6032,7 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } - while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); /* Clear CCF flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); @@ -5440,16 +6041,16 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry else { /*Write header block in the IN FIFO without last block */ - for(loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize)-(hcryp->Init.HeaderSize %4U ))); loopcounter+=4U) + for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U))); loopcounter += 4U) { /* Write the Input block in the Data Input register */ - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; /*Wait on CCF flag*/ @@ -5457,7 +6058,7 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry do { count-- ; - if(count == 0U) + if (count == 0U) { /* Disable the CRYP peripheral clock */ __HAL_CRYP_DISABLE(hcryp); @@ -5470,19 +6071,18 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } - while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); /* Clear CCF flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); } /* Last block optionally pad the data with zeros*/ - for(loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize %4U )); loopcounter++) + for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++) { - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; } - while(loopcounter <4U ) + while (loopcounter < 4U) { /* Pad the data with zeros to have a complete block */ hcryp->Instance->DINR = 0x0U; @@ -5494,7 +6094,7 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry do { count-- ; - if(count == 0U) + if (count == 0U) { /* Disable the CRYP peripheral clock */ __HAL_CRYP_DISABLE(hcryp); @@ -5507,8 +6107,7 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } - while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); /* Clear CCF flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); @@ -5518,7 +6117,7 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry else { #if defined(AES) - if(hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC) + if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC) { /*Workaround 1: only AES, before re-enabling the IP, datatype can be configured.*/ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType); @@ -5551,10 +6150,10 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp) /***************************** Header phase *********************************/ #if defined(CRYP) - if(hcryp->Init.HeaderSize == hcryp->CrypHeaderCount) + if (hcryp->Init.HeaderSize == hcryp->CrypHeaderCount) { /* Disable interrupts */ - __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI ); + __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI); /* Disable the CRYP peripheral */ __HAL_CRYP_DISABLE(hcryp); @@ -5566,32 +6165,33 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp) CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); /* Enable Interrupts */ - __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI ); + __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI); /* Enable the CRYP peripheral */ __HAL_CRYP_ENABLE(hcryp); } else if (((hcryp->Init.HeaderSize) - (hcryp->CrypHeaderCount)) >= 4U) - { /* HeaderSize %4, no padding */ - hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount ); + { + /* HeaderSize %4, no padding */ + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; - hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; - hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; - hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; } else { /* Last block optionally pad the data with zeros*/ - for(loopcounter = 0U; loopcounter < (hcryp->Init.HeaderSize %4U ); loopcounter++) + for (loopcounter = 0U; loopcounter < (hcryp->Init.HeaderSize % 4U); loopcounter++) { - hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header+ hcryp->CrypHeaderCount); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; } - while(loopcounter <4U ) + while (loopcounter < 4U) { /* Pad the data with zeros to have a complete block */ hcryp->Instance->DIN = 0x0U; @@ -5600,27 +6200,27 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp) } #else /* AES */ - if(hcryp->Init.HeaderSize == hcryp->CrypHeaderCount) + if (hcryp->Init.HeaderSize == hcryp->CrypHeaderCount) { /* Set the phase */ hcryp->Phase = CRYP_PHASE_PROCESS; /* Payload phase not supported in CCM AES2 */ - if(hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC) + if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC) { /* Select payload phase once the header phase is performed */ MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_PAYLOAD); } - if(hcryp->Init.Algorithm == CRYP_AES_CCM) + if (hcryp->Init.Algorithm == CRYP_AES_CCM) { /* Increment CrypHeaderCount to pass in CRYP_GCMCCM_SetPayloadPhase_IT */ hcryp->CrypHeaderCount++; } /* Write the payload Input block in the IN FIFO */ - if(hcryp->Size == 0U) + if (hcryp->Size == 0U) { /* Disable interrupts */ - __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE| CRYP_IT_ERRIE); + __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE); /* Change the CRYP state */ hcryp->State = HAL_CRYP_STATE_READY; @@ -5630,16 +6230,16 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp) } else if (hcryp->Size >= 16U) { - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - if((hcryp->CrypInCount == (hcryp->Size/4U)) &&((hcryp->Size %16U )== 0U)) + if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) { /* Call the input data transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) @@ -5658,25 +6258,25 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp) payload <128bit don't use CRYP_Encrypt_IT otherwise TAG is incorrectly generated for GCM Encryption. */ /* Compute the number of padding bytes in last block of payload */ - npblb = ((((uint32_t)(hcryp->Size)/16U)+1U)*16U) - (uint32_t)(hcryp->Size); + npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size); /* Number of valid words (lastwordsize) in last block */ - if ((npblb % 4U) ==0U) + if ((npblb % 4U) == 0U) { - lastwordsize = (16U-npblb)/4U; + lastwordsize = (16U - npblb) / 4U; } else { - lastwordsize = ((16U-npblb)/4U) +1U; + lastwordsize = ((16U - npblb) / 4U) + 1U; } /* Last block optionally pad the data with zeros*/ - for(loopcounter = 0U; loopcounter < lastwordsize; loopcounter++) + for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++) { - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; } - while(loopcounter <4U ) + while (loopcounter < 4U) { /* Pad the data with zeros to have a complete block */ hcryp->Instance->DINR = 0x0U; @@ -5687,24 +6287,24 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp) else if (((hcryp->Init.HeaderSize) - (hcryp->CrypHeaderCount)) >= 4U) { /* Write the input block in the IN FIFO */ - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++; } else /*HeaderSize < 4 or HeaderSize >4 & HeaderSize %4 != 0*/ { /* Last block optionally pad the data with zeros*/ - for(loopcounter = 0U; loopcounter < (hcryp->Init.HeaderSize %4U ); loopcounter++) + for (loopcounter = 0U; loopcounter < (hcryp->Init.HeaderSize % 4U); loopcounter++) { - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; } - while(loopcounter <4U ) + while (loopcounter < 4U) { /* pad the data with zeros to have a complete block */ hcryp->Instance->DINR = 0x0U; @@ -5722,27 +6322,29 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp) * @param Timeout: specify Timeout value * @retval None */ -static void CRYP_Workaround(CRYP_HandleTypeDef *hcryp, uint32_t Timeout ) +static void CRYP_Workaround(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) { uint32_t lastwordsize; uint32_t npblb; #if defined(CRYP) uint32_t iv1temp; uint32_t temp[4] = {0}; - uint32_t temp2[4]= {0}; + uint32_t temp2[4] = {0}; #endif /* CRYP */ - uint32_t intermediate_data[4]={0}; + uint32_t intermediate_data[4] = {0}; uint32_t index; /* Compute the number of padding bytes in last block of payload */ - npblb = ((((uint32_t)(hcryp->Size)/16U)+1U)*16U)- (uint32_t)(hcryp->Size); + npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size); /* Number of valid words (lastwordsize) in last block */ - if ((npblb%4U) ==0U) - { lastwordsize = (16U-npblb)/4U; + if ((npblb % 4U) == 0U) + { + lastwordsize = (16U - npblb) / 4U; } else - {lastwordsize = ((16U-npblb)/4U) +1U; + { + lastwordsize = ((16U - npblb) / 4U) + 1U; } #if defined(CRYP) @@ -5750,34 +6352,35 @@ static void CRYP_Workaround(CRYP_HandleTypeDef *hcryp, uint32_t Timeout ) /* Workaround 2, case GCM encryption */ if (hcryp->Init.Algorithm == CRYP_AES_GCM) { - if((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_ENCRYPT) - {/*Workaround in order to properly compute authentication tags while doing - a GCM encryption with the last block of payload size inferior to 128 bits*/ + if ((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_ENCRYPT) + { + /*Workaround in order to properly compute authentication tags while doing + a GCM encryption with the last block of payload size inferior to 128 bits*/ /* Disable CRYP to start the final phase */ __HAL_CRYP_DISABLE(hcryp); /*Update CRYP_IV1R register and ALGOMODE*/ - hcryp->Instance->IV1RR = ((hcryp->Instance->CSGCMCCM7R)-1); + hcryp->Instance->IV1RR = ((hcryp->Instance->CSGCMCCM7R) - 1U); MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_CTR); /* Enable CRYP to start the final phase */ __HAL_CRYP_ENABLE(hcryp); } /* Last block optionally pad the data with zeros*/ - for(index=0; index < lastwordsize; index ++) + for (index = 0; index < lastwordsize; index ++) { /* Write the last input block in the IN FIFO */ - hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; } - while(index < 4U) + while (index < 4U) { /* Pad the data with zeros to have a complete block */ hcryp->Instance->DIN = 0U; index++; } /* Wait for OFNE flag to be raised */ - if(CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK) + if (CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK) { /* Disable the CRYP peripheral clock */ __HAL_CRYP_DISABLE(hcryp); @@ -5796,20 +6399,20 @@ static void CRYP_Workaround(CRYP_HandleTypeDef *hcryp, uint32_t Timeout ) HAL_CRYP_ErrorCallback(hcryp); #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } - if((hcryp->Instance->SR & CRYP_FLAG_OFNE ) != 0x0U) + if ((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U) { - for(index=0U; index< 4U;index++) + for (index = 0U; index < 4U; index++) { /* Read the output block from the output FIFO */ intermediate_data[index] = hcryp->Instance->DOUT; /* Intermediate data buffer to be used in for the workaround*/ - *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount))=intermediate_data[index]; + *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = intermediate_data[index]; hcryp->CrypOutCount++; } } - if((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_ENCRYPT) + if ((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_ENCRYPT) { /*workaround in order to properly compute authentication tags while doing a GCM encryption with the last block of payload size inferior to 128 bits*/ @@ -5820,79 +6423,79 @@ static void CRYP_Workaround(CRYP_HandleTypeDef *hcryp, uint32_t Timeout ) /* configured final phase */ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH, CRYP_PHASE_FINAL); - if ( (hcryp->Instance->CR & CRYP_CR_DATATYPE) == CRYP_DATATYPE_32B) + if ((hcryp->Instance->CR & CRYP_CR_DATATYPE) == CRYP_DATATYPE_32B) { - if ((npblb %4U)==1U) + if ((npblb % 4U) == 1U) { - intermediate_data[lastwordsize-1U] &= 0xFFFFFF00U; + intermediate_data[lastwordsize - 1U] &= 0xFFFFFF00U; } - if ((npblb %4U)==2U) + if ((npblb % 4U) == 2U) { - intermediate_data[lastwordsize-1U] &= 0xFFFF0000U; + intermediate_data[lastwordsize - 1U] &= 0xFFFF0000U; } - if ((npblb %4U)==3U) + if ((npblb % 4U) == 3U) { - intermediate_data[lastwordsize-1U] &= 0xFF000000U; + intermediate_data[lastwordsize - 1U] &= 0xFF000000U; } } else if ((hcryp->Instance->CR & CRYP_CR_DATATYPE) == CRYP_DATATYPE_8B) { - if ((npblb %4U)==1U) + if ((npblb % 4U) == 1U) { - intermediate_data[lastwordsize-1U] &= __REV(0xFFFFFF00U); + intermediate_data[lastwordsize - 1U] &= __REV(0xFFFFFF00U); } - if ((npblb %4U)==2U) + if ((npblb % 4U) == 2U) { - intermediate_data[lastwordsize-1U] &= __REV(0xFFFF0000U); + intermediate_data[lastwordsize - 1U] &= __REV(0xFFFF0000U); } - if ((npblb %4U)==3U) + if ((npblb % 4U) == 3U) { - intermediate_data[lastwordsize-1U] &= __REV(0xFF000000U); + intermediate_data[lastwordsize - 1U] &= __REV(0xFF000000U); } } else if ((hcryp->Instance->CR & CRYP_CR_DATATYPE) == CRYP_DATATYPE_16B) { - if ((npblb %4U)==1U) + if ((npblb % 4U) == 1U) { - intermediate_data[lastwordsize-1U] &= __ROR((0xFFFFFF00U), 16); + intermediate_data[lastwordsize - 1U] &= __ROR((0xFFFFFF00U), 16); } - if ((npblb %4U)==2U) + if ((npblb % 4U) == 2U) { - intermediate_data[lastwordsize-1U] &= __ROR((0xFFFF0000U), 16); + intermediate_data[lastwordsize - 1U] &= __ROR((0xFFFF0000U), 16); } - if ((npblb %4U)==3U) + if ((npblb % 4U) == 3U) { - intermediate_data[lastwordsize-1U] &= __ROR((0xFF000000U), 16); + intermediate_data[lastwordsize - 1U] &= __ROR((0xFF000000U), 16); } } else /*CRYP_DATATYPE_1B*/ { - if ((npblb %4U)==1U) + if ((npblb % 4U) == 1U) { - intermediate_data[lastwordsize-1U] &= __RBIT(0xFFFFFF00U); + intermediate_data[lastwordsize - 1U] &= __RBIT(0xFFFFFF00U); } - if ((npblb %4U)==2U) + if ((npblb % 4U) == 2U) { - intermediate_data[lastwordsize-1U] &= __RBIT(0xFFFF0000U); + intermediate_data[lastwordsize - 1U] &= __RBIT(0xFFFF0000U); } - if ((npblb %4U)==3U) + if ((npblb % 4U) == 3U) { - intermediate_data[lastwordsize-1U] &= __RBIT(0xFF000000U); + intermediate_data[lastwordsize - 1U] &= __RBIT(0xFF000000U); } } - for (index=0U; index < lastwordsize; index ++) + for (index = 0U; index < lastwordsize; index ++) { /*Write the intermediate_data in the IN FIFO */ - hcryp->Instance->DIN=intermediate_data[index]; + hcryp->Instance->DIN = intermediate_data[index]; } - while(index < 4U) + while (index < 4U) { /* Pad the data with zeros to have a complete block */ hcryp->Instance->DIN = 0x0U; index++; } /* Wait for OFNE flag to be raised */ - if(CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK) + if (CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK) { /* Disable the CRYP peripheral clock */ __HAL_CRYP_DISABLE(hcryp); @@ -5904,40 +6507,42 @@ static void CRYP_Workaround(CRYP_HandleTypeDef *hcryp, uint32_t Timeout ) /* Process unlocked */ __HAL_UNLOCK(hcryp); #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) - /*Call registered error callback*/ - hcryp->ErrorCallback(hcryp); + /*Call registered error callback*/ + hcryp->ErrorCallback(hcryp); #else - /*Call legacy weak error callback*/ - HAL_CRYP_ErrorCallback(hcryp); + /*Call legacy weak error callback*/ + HAL_CRYP_ErrorCallback(hcryp); #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } - if((hcryp->Instance->SR & CRYP_FLAG_OFNE ) != 0x0U) + if ((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U) { - for( index=0U; index< 4U;index++) + for (index = 0U; index < 4U; index++) { - intermediate_data[index]=hcryp->Instance->DOUT; + intermediate_data[index] = hcryp->Instance->DOUT; } } } } /* End of GCM encryption */ - else{ /* Workaround 2, case CCM decryption, in order to properly compute - authentication tags while doing a CCM decryption with the last block - of payload size inferior to 128 bits*/ + else + { + /* Workaround 2, case CCM decryption, in order to properly compute + authentication tags while doing a CCM decryption with the last block + of payload size inferior to 128 bits*/ - if((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_DECRYPT) + if ((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_DECRYPT) { iv1temp = hcryp->Instance->CSGCMCCM7R; /* Disable CRYP to start the final phase */ __HAL_CRYP_DISABLE(hcryp); - temp[0]= hcryp->Instance->CSGCMCCM0R; - temp[1]= hcryp->Instance->CSGCMCCM1R; - temp[2]= hcryp->Instance->CSGCMCCM2R; - temp[3]= hcryp->Instance->CSGCMCCM3R; + temp[0] = hcryp->Instance->CSGCMCCM0R; + temp[1] = hcryp->Instance->CSGCMCCM1R; + temp[2] = hcryp->Instance->CSGCMCCM2R; + temp[3] = hcryp->Instance->CSGCMCCM3R; - hcryp->Instance->IV1RR= iv1temp; + hcryp->Instance->IV1RR = iv1temp; /* Configured CHMOD CTR */ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_CTR); @@ -5946,20 +6551,20 @@ static void CRYP_Workaround(CRYP_HandleTypeDef *hcryp, uint32_t Timeout ) __HAL_CRYP_ENABLE(hcryp); } /* Last block optionally pad the data with zeros*/ - for(index=0; index < lastwordsize; index ++) + for (index = 0; index < lastwordsize; index ++) { /* Write the last Input block in the IN FIFO */ - hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; } - while(index < 4U) + while (index < 4U) { /* Pad the data with zeros to have a complete block */ hcryp->Instance->DIN = 0U; index++; } /* Wait for OFNE flag to be raised */ - if(CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK) + if (CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK) { /* Disable the CRYP peripheral clock */ __HAL_CRYP_DISABLE(hcryp); @@ -5979,25 +6584,25 @@ static void CRYP_Workaround(CRYP_HandleTypeDef *hcryp, uint32_t Timeout ) #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } - if((hcryp->Instance->SR & CRYP_FLAG_OFNE ) != 0x0U) + if ((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U) { - for(index=0U; index< 4U;index++) + for (index = 0U; index < 4U; index++) { /* Read the Output block from the Output FIFO */ intermediate_data[index] = hcryp->Instance->DOUT; /*intermediate data buffer to be used in for the workaround*/ - *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount))=intermediate_data[index]; + *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = intermediate_data[index]; hcryp->CrypOutCount++; } } - if((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_DECRYPT) + if ((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_DECRYPT) { - temp2[0]= hcryp->Instance->CSGCMCCM0R; - temp2[1]= hcryp->Instance->CSGCMCCM1R; - temp2[2]= hcryp->Instance->CSGCMCCM2R; - temp2[3]= hcryp->Instance->CSGCMCCM3R; + temp2[0] = hcryp->Instance->CSGCMCCM0R; + temp2[1] = hcryp->Instance->CSGCMCCM1R; + temp2[2] = hcryp->Instance->CSGCMCCM2R; + temp2[3] = hcryp->Instance->CSGCMCCM3R; /* configured CHMOD CCM */ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_CCM); @@ -6006,35 +6611,35 @@ static void CRYP_Workaround(CRYP_HandleTypeDef *hcryp, uint32_t Timeout ) MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH, CRYP_PHASE_HEADER); /*set to zero the bits corresponding to the padded bits*/ - for(index = lastwordsize; index<4U; index ++) + for (index = lastwordsize; index < 4U; index ++) { - intermediate_data[index] =0U; + intermediate_data[index] = 0U; } - if ((npblb %4U)==1U) + if ((npblb % 4U) == 1U) { - intermediate_data[lastwordsize-1U] &= 0xFFFFFF00U; + intermediate_data[lastwordsize - 1U] &= 0xFFFFFF00U; } - if ((npblb %4U)==2U) + if ((npblb % 4U) == 2U) { - intermediate_data[lastwordsize-1U] &= 0xFFFF0000U; + intermediate_data[lastwordsize - 1U] &= 0xFFFF0000U; } - if ((npblb %4U)==3U) + if ((npblb % 4U) == 3U) { - intermediate_data[lastwordsize-1U] &= 0xFF000000U; + intermediate_data[lastwordsize - 1U] &= 0xFF000000U; } - for(index=0U; index < 4U ; index ++) + for (index = 0U; index < 4U ; index ++) { intermediate_data[index] ^= temp[index]; intermediate_data[index] ^= temp2[index]; } - for(index = 0U; index < 4U; index ++) + for (index = 0U; index < 4U; index ++) { /* Write the last Input block in the IN FIFO */ hcryp->Instance->DIN = intermediate_data[index] ; } /* Wait for BUSY flag to be raised */ - if(CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK) + if (CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK) { /* Disable the CRYP peripheral clock */ __HAL_CRYP_DISABLE(hcryp); @@ -6046,11 +6651,11 @@ static void CRYP_Workaround(CRYP_HandleTypeDef *hcryp, uint32_t Timeout ) /* Process Unlocked */ __HAL_UNLOCK(hcryp); #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) - /*Call registered error callback*/ - hcryp->ErrorCallback(hcryp); + /*Call registered error callback*/ + hcryp->ErrorCallback(hcryp); #else - /*Call legacy weak error callback*/ - HAL_CRYP_ErrorCallback(hcryp); + /*Call legacy weak error callback*/ + HAL_CRYP_ErrorCallback(hcryp); #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } } @@ -6064,52 +6669,52 @@ static void CRYP_Workaround(CRYP_HandleTypeDef *hcryp, uint32_t Timeout ) /*Workaround 2: case GCM encryption, during payload phase and before inserting the last block of paylaod, which size is inferior to 128 bits */ - if((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT) + if ((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT) { /* configured CHMOD CTR */ MODIFY_REG(hcryp->Instance->CR, AES_CR_CHMOD, CRYP_AES_CTR); } /* last block optionally pad the data with zeros*/ - for(index = 0U; index < lastwordsize; index ++) + for (index = 0U; index < lastwordsize; index ++) { /* Write the last Input block in the IN FIFO */ - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; } - while(index < 4U) + while (index < 4U) { /* pad the data with zeros to have a complete block */ hcryp->Instance->DINR = 0U; index++; } /* Wait for CCF flag to be raised */ - if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) { hcryp->State = HAL_CRYP_STATE_READY; __HAL_UNLOCK(hcryp); #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) - /*Call registered error callback*/ - hcryp->ErrorCallback(hcryp); + /*Call registered error callback*/ + hcryp->ErrorCallback(hcryp); #else - /*Call legacy weak error callback*/ - HAL_CRYP_ErrorCallback(hcryp); + /*Call legacy weak error callback*/ + HAL_CRYP_ErrorCallback(hcryp); #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } /* Clear CCF Flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - for(index = 0U; index< 4U;index++) + for (index = 0U; index < 4U; index++) { /* Read the Output block from the Output FIFO */ intermediate_data[index] = hcryp->Instance->DOUTR; /*intermediate data buffer to be used in the workaround*/ - *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount))= intermediate_data[index]; + *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = intermediate_data[index]; hcryp->CrypOutCount++; } - if((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT) + if ((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT) { /* configured CHMOD GCM */ MODIFY_REG(hcryp->Instance->CR, AES_CR_CHMOD, CRYP_AES_GCM_GMAC); @@ -6117,80 +6722,80 @@ static void CRYP_Workaround(CRYP_HandleTypeDef *hcryp, uint32_t Timeout ) /* Select final phase */ MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_FINAL); - if ( (hcryp->Instance->CR & AES_CR_DATATYPE) == CRYP_DATATYPE_32B) + if ((hcryp->Instance->CR & AES_CR_DATATYPE) == CRYP_DATATYPE_32B) { - if ((npblb %4U)==1U) + if ((npblb % 4U) == 1U) { - intermediate_data[lastwordsize-1U] &= 0xFFFFFF00U; + intermediate_data[lastwordsize - 1U] &= 0xFFFFFF00U; } - if ((npblb %4U)==2U) + if ((npblb % 4U) == 2U) { - intermediate_data[lastwordsize-1U] &= 0xFFFF0000U; + intermediate_data[lastwordsize - 1U] &= 0xFFFF0000U; } - if ((npblb %4U)==3U) + if ((npblb % 4U) == 3U) { - intermediate_data[lastwordsize-1U] &= 0xFF000000U; + intermediate_data[lastwordsize - 1U] &= 0xFF000000U; } } else if ((hcryp->Instance->CR & AES_CR_DATATYPE) == CRYP_DATATYPE_8B) { - if ((npblb %4U)==1U) + if ((npblb % 4U) == 1U) { - intermediate_data[lastwordsize-1U] &= __REV(0xFFFFFF00U); + intermediate_data[lastwordsize - 1U] &= __REV(0xFFFFFF00U); } - if ((npblb %4U)==2U) + if ((npblb % 4U) == 2U) { - intermediate_data[lastwordsize-1U] &= __REV(0xFFFF0000U); + intermediate_data[lastwordsize - 1U] &= __REV(0xFFFF0000U); } - if ((npblb %4U)==3U) + if ((npblb % 4U) == 3U) { - intermediate_data[lastwordsize-1U] &= __REV(0xFF000000U); + intermediate_data[lastwordsize - 1U] &= __REV(0xFF000000U); } } else if ((hcryp->Instance->CR & AES_CR_DATATYPE) == CRYP_DATATYPE_16B) { - if ((npblb %4U)==1U) + if ((npblb % 4U) == 1U) { - intermediate_data[lastwordsize-1U] &= __ROR((0xFFFFFF00U), 16); + intermediate_data[lastwordsize - 1U] &= __ROR((0xFFFFFF00U), 16); } - if ((npblb %4U)==2U) + if ((npblb % 4U) == 2U) { - intermediate_data[lastwordsize-1U] &= __ROR((0xFFFF0000U), 16); + intermediate_data[lastwordsize - 1U] &= __ROR((0xFFFF0000U), 16); } - if ((npblb %4U)==3U) + if ((npblb % 4U) == 3U) { - intermediate_data[lastwordsize-1U] &= __ROR((0xFF000000U), 16); + intermediate_data[lastwordsize - 1U] &= __ROR((0xFF000000U), 16); } } else /*CRYP_DATATYPE_1B*/ { - if ((npblb %4U)==1U) + if ((npblb % 4U) == 1U) { - intermediate_data[lastwordsize-1U] &= __RBIT(0xFFFFFF00U); + intermediate_data[lastwordsize - 1U] &= __RBIT(0xFFFFFF00U); } - if ((npblb %4U)==2U) + if ((npblb % 4U) == 2U) { - intermediate_data[lastwordsize-1U] &= __RBIT(0xFFFF0000U); + intermediate_data[lastwordsize - 1U] &= __RBIT(0xFFFF0000U); } - if ((npblb %4U)==3U) + if ((npblb % 4U) == 3U) { - intermediate_data[lastwordsize-1U] &= __RBIT(0xFF000000U); + intermediate_data[lastwordsize - 1U] &= __RBIT(0xFF000000U); } } /*Write the intermediate_data in the IN FIFO */ - for(index = 0U; index < lastwordsize; index ++) + for (index = 0U; index < lastwordsize; index ++) { hcryp->Instance->DINR = intermediate_data[index]; } - while(index < 4U) + while (index < 4U) { /* pad the data with zeros to have a complete block */ hcryp->Instance->DINR = 0U; index++; } /* Wait for CCF flag to be raised */ - if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) { /* Disable the CRYP peripheral clock */ __HAL_CRYP_DISABLE(hcryp); @@ -6212,9 +6817,9 @@ static void CRYP_Workaround(CRYP_HandleTypeDef *hcryp, uint32_t Timeout ) /* Clear CCF Flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - for( index = 0U; index< 4U;index++) + for (index = 0U; index < 4U; index++) { - intermediate_data[index]=hcryp->Instance->DOUTR; + intermediate_data[index] = hcryp->Instance->DOUTR; } }/*End of Workaround 2*/ #endif /* End AES or CRYP */ @@ -6236,12 +6841,12 @@ static HAL_StatusTypeDef CRYP_WaitOnIFEMFlag(CRYP_HandleTypeDef *hcryp, uint32_t /* Get timeout */ tickstart = HAL_GetTick(); - while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM)) + while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM)) { /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { return HAL_ERROR; } @@ -6264,12 +6869,12 @@ static HAL_StatusTypeDef CRYP_WaitOnBUSYFlag(CRYP_HandleTypeDef *hcryp, uint32_t /* Get timeout */ tickstart = HAL_GetTick(); - while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY)) + while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY)) { /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { return HAL_ERROR; } @@ -6293,12 +6898,12 @@ static HAL_StatusTypeDef CRYP_WaitOnOFNEFlag(CRYP_HandleTypeDef *hcryp, uint32_t /* Get timeout */ tickstart = HAL_GetTick(); - while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE)) + while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE)) { /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { return HAL_ERROR; } @@ -6323,12 +6928,12 @@ static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t T /* Get timeout */ tickstart = HAL_GetTick(); - while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)) + while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)) { /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U) ) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { return HAL_ERROR; } diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cryp_ex.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cryp_ex.c index 6a9f243c63..369a03c689 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cryp_ex.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cryp_ex.c @@ -79,7 +79,7 @@ #define CRYPEx_PHASE_PROCESS 0x02U /*!< CRYP peripheral is in processing phase */ #define CRYPEx_PHASE_FINAL 0x03U /*!< CRYP peripheral is in final phase this is relevant only with CCM and GCM modes */ - /* CTR0 information to use in CCM algorithm */ +/* CTR0 information to use in CCM algorithm */ #define CRYP_CCM_CTR0_0 0x07FFFFFFU #define CRYP_CCM_CTR0_3 0xFFFFFF00U @@ -100,8 +100,8 @@ */ /** @defgroup CRYPEx_Exported_Functions_Group1 Extended AES processing functions - * @brief Extended processing functions. - * + * @brief Extended processing functions. + * @verbatim ============================================================================== ##### Extended AES processing functions ##### @@ -129,10 +129,10 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u { uint32_t tickstart; uint64_t headerlength = (uint64_t)(hcryp->Init.HeaderSize) * 32U; /* Header length in bits */ - uint64_t inputlength = (uint64_t)(hcryp->Size) * 8U; /* input length in bits */ + uint64_t inputlength = (uint64_t)hcryp->SizesSum * 8U; /* input length in bits */ uint32_t tagaddr = (uint32_t)AuthTag; - if(hcryp->State == HAL_CRYP_STATE_READY) + if (hcryp->State == HAL_CRYP_STATE_READY) { /* Process locked */ __HAL_LOCK(hcryp); @@ -141,7 +141,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u hcryp->State = HAL_CRYP_STATE_BUSY; /* Check if initialization phase has already been performed */ - if(hcryp->Phase == CRYPEx_PHASE_PROCESS) + if (hcryp->Phase == CRYPEx_PHASE_PROCESS) { /* Change the CRYP phase */ hcryp->Phase = CRYPEx_PHASE_FINAL; @@ -178,28 +178,28 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u /* Write the number of bits in header (64 bits) followed by the number of bits in the payload */ - if(hcryp->Init.DataType == CRYP_DATATYPE_1B) + if (hcryp->Init.DataType == CRYP_DATATYPE_1B) { hcryp->Instance->DIN = 0U; hcryp->Instance->DIN = __RBIT((uint32_t)(headerlength)); hcryp->Instance->DIN = 0U; hcryp->Instance->DIN = __RBIT((uint32_t)(inputlength)); } - else if(hcryp->Init.DataType == CRYP_DATATYPE_8B) + else if (hcryp->Init.DataType == CRYP_DATATYPE_8B) { hcryp->Instance->DIN = 0U; hcryp->Instance->DIN = __REV((uint32_t)(headerlength)); hcryp->Instance->DIN = 0U; hcryp->Instance->DIN = __REV((uint32_t)(inputlength)); } - else if(hcryp->Init.DataType == CRYP_DATATYPE_16B) + else if (hcryp->Init.DataType == CRYP_DATATYPE_16B) { hcryp->Instance->DIN = 0U; hcryp->Instance->DIN = __ROR((uint32_t)headerlength, 16U); hcryp->Instance->DIN = 0U; hcryp->Instance->DIN = __ROR((uint32_t)inputlength, 16U); } - else if(hcryp->Init.DataType == CRYP_DATATYPE_32B) + else if (hcryp->Init.DataType == CRYP_DATATYPE_32B) { hcryp->Instance->DIN = 0U; hcryp->Instance->DIN = (uint32_t)(headerlength); @@ -213,12 +213,12 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u /* Wait for OFNE flag to be raised */ tickstart = HAL_GetTick(); - while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE)) + while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE)) { /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { /* Disable the CRYP Peripheral Clock */ __HAL_CRYP_DISABLE(hcryp); @@ -235,13 +235,13 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u } /* Read the authentication TAG in the output FIFO */ - *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT; - tagaddr+=4U; - *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT; - tagaddr+=4U; - *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT; - tagaddr+=4U; - *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT; + *(uint32_t *)(tagaddr) = hcryp->Instance->DOUT; + tagaddr += 4U; + *(uint32_t *)(tagaddr) = hcryp->Instance->DOUT; + tagaddr += 4U; + *(uint32_t *)(tagaddr) = hcryp->Instance->DOUT; + tagaddr += 4U; + *(uint32_t *)(tagaddr) = hcryp->Instance->DOUT; #else /* AES*/ @@ -250,28 +250,28 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u /* Write the number of bits in header (64 bits) followed by the number of bits in the payload */ - if(hcryp->Init.DataType == CRYP_DATATYPE_1B) + if (hcryp->Init.DataType == CRYP_DATATYPE_1B) { hcryp->Instance->DINR = 0U; hcryp->Instance->DINR = __RBIT((uint32_t)(headerlength)); hcryp->Instance->DINR = 0U; hcryp->Instance->DINR = __RBIT((uint32_t)(inputlength)); } - else if(hcryp->Init.DataType == CRYP_DATATYPE_8B) + else if (hcryp->Init.DataType == CRYP_DATATYPE_8B) { hcryp->Instance->DINR = 0U; hcryp->Instance->DINR = __REV((uint32_t)(headerlength)); hcryp->Instance->DINR = 0U; hcryp->Instance->DINR = __REV((uint32_t)(inputlength)); } - else if(hcryp->Init.DataType == CRYP_DATATYPE_16B) + else if (hcryp->Init.DataType == CRYP_DATATYPE_16B) { hcryp->Instance->DINR = 0U; hcryp->Instance->DINR = __ROR((uint32_t)headerlength, 16U); hcryp->Instance->DINR = 0U; hcryp->Instance->DINR = __ROR((uint32_t)inputlength, 16U); } - else if(hcryp->Init.DataType == CRYP_DATATYPE_32B) + else if (hcryp->Init.DataType == CRYP_DATATYPE_32B) { hcryp->Instance->DINR = 0U; hcryp->Instance->DINR = (uint32_t)(headerlength); @@ -284,12 +284,12 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u } /* Wait for CCF flag to be raised */ tickstart = HAL_GetTick(); - while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)) + while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)) { /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { /* Disable the CRYP peripheral clock */ __HAL_CRYP_DISABLE(hcryp); @@ -306,13 +306,13 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u } /* Read the authentication TAG in the output FIFO */ - *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR; - tagaddr+=4U; - *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR; - tagaddr+=4U; - *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR; - tagaddr+=4U; - *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR; + *(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR; + tagaddr += 4U; + *(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR; + tagaddr += 4U; + *(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR; + tagaddr += 4U; + *(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR; /* Clear CCF flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); @@ -349,11 +349,11 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout) { uint32_t tagaddr = (uint32_t)AuthTag; - uint32_t ctr0 [4]={0}; + uint32_t ctr0 [4] = {0}; uint32_t ctr0addr = (uint32_t)ctr0; uint32_t tickstart; - if(hcryp->State == HAL_CRYP_STATE_READY) + if (hcryp->State == HAL_CRYP_STATE_READY) { /* Process locked */ __HAL_LOCK(hcryp); @@ -362,7 +362,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u hcryp->State = HAL_CRYP_STATE_BUSY; /* Check if initialization phase has already been performed */ - if(hcryp->Phase == CRYPEx_PHASE_PROCESS) + if (hcryp->Phase == CRYPEx_PHASE_PROCESS) { /* Change the CRYP phase */ hcryp->Phase = CRYPEx_PHASE_FINAL; @@ -389,66 +389,66 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u __HAL_CRYP_DISABLE(hcryp); /* Select final phase & ALGODIR bit must be set to �0�. */ - MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH|CRYP_CR_ALGODIR, CRYP_PHASE_FINAL|CRYP_OPERATINGMODE_ENCRYPT); + MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH | CRYP_CR_ALGODIR, CRYP_PHASE_FINAL | CRYP_OPERATINGMODE_ENCRYPT); /* Enable the CRYP peripheral */ __HAL_CRYP_ENABLE(hcryp); /* Write the counter block in the IN FIFO, CTR0 information from B0 data has to be swapped according to the DATATYPE*/ - ctr0[0]=(hcryp->Init.B0[0]) & CRYP_CCM_CTR0_0; - ctr0[1]=hcryp->Init.B0[1]; - ctr0[2]=hcryp->Init.B0[2]; - ctr0[3]=hcryp->Init.B0[3] & CRYP_CCM_CTR0_3; + ctr0[0] = (hcryp->Init.B0[0]) & CRYP_CCM_CTR0_0; + ctr0[1] = hcryp->Init.B0[1]; + ctr0[2] = hcryp->Init.B0[2]; + ctr0[3] = hcryp->Init.B0[3] & CRYP_CCM_CTR0_3; - if(hcryp->Init.DataType == CRYP_DATATYPE_8B) + if (hcryp->Init.DataType == CRYP_DATATYPE_8B) { - hcryp->Instance->DIN = __REV(*(uint32_t*)(ctr0addr)); - ctr0addr+=4U; - hcryp->Instance->DIN = __REV(*(uint32_t*)(ctr0addr)); - ctr0addr+=4U; - hcryp->Instance->DIN = __REV(*(uint32_t*)(ctr0addr)); - ctr0addr+=4U; - hcryp->Instance->DIN = __REV(*(uint32_t*)(ctr0addr)); + hcryp->Instance->DIN = __REV(*(uint32_t *)(ctr0addr)); + ctr0addr += 4U; + hcryp->Instance->DIN = __REV(*(uint32_t *)(ctr0addr)); + ctr0addr += 4U; + hcryp->Instance->DIN = __REV(*(uint32_t *)(ctr0addr)); + ctr0addr += 4U; + hcryp->Instance->DIN = __REV(*(uint32_t *)(ctr0addr)); } - else if(hcryp->Init.DataType == CRYP_DATATYPE_16B) + else if (hcryp->Init.DataType == CRYP_DATATYPE_16B) { - hcryp->Instance->DIN = __ROR(*(uint32_t*)(ctr0addr), 16U); - ctr0addr+=4U; - hcryp->Instance->DIN = __ROR(*(uint32_t*)(ctr0addr), 16U); - ctr0addr+=4U; - hcryp->Instance->DIN = __ROR(*(uint32_t*)(ctr0addr), 16U); - ctr0addr+=4U; - hcryp->Instance->DIN = __ROR(*(uint32_t*)(ctr0addr), 16U); + hcryp->Instance->DIN = __ROR(*(uint32_t *)(ctr0addr), 16U); + ctr0addr += 4U; + hcryp->Instance->DIN = __ROR(*(uint32_t *)(ctr0addr), 16U); + ctr0addr += 4U; + hcryp->Instance->DIN = __ROR(*(uint32_t *)(ctr0addr), 16U); + ctr0addr += 4U; + hcryp->Instance->DIN = __ROR(*(uint32_t *)(ctr0addr), 16U); } - else if(hcryp->Init.DataType == CRYP_DATATYPE_1B) + else if (hcryp->Init.DataType == CRYP_DATATYPE_1B) { - hcryp->Instance->DIN = __RBIT(*(uint32_t*)(ctr0addr)); - ctr0addr+=4U; - hcryp->Instance->DIN = __RBIT(*(uint32_t*)(ctr0addr)); - ctr0addr+=4U; - hcryp->Instance->DIN = __RBIT(*(uint32_t*)(ctr0addr)); - ctr0addr+=4U; - hcryp->Instance->DIN = __RBIT(*(uint32_t*)(ctr0addr)); + hcryp->Instance->DIN = __RBIT(*(uint32_t *)(ctr0addr)); + ctr0addr += 4U; + hcryp->Instance->DIN = __RBIT(*(uint32_t *)(ctr0addr)); + ctr0addr += 4U; + hcryp->Instance->DIN = __RBIT(*(uint32_t *)(ctr0addr)); + ctr0addr += 4U; + hcryp->Instance->DIN = __RBIT(*(uint32_t *)(ctr0addr)); } else { - hcryp->Instance->DIN = *(uint32_t*)(ctr0addr); - ctr0addr+=4U; - hcryp->Instance->DIN = *(uint32_t*)(ctr0addr); - ctr0addr+=4U; - hcryp->Instance->DIN = *(uint32_t*)(ctr0addr); - ctr0addr+=4U; - hcryp->Instance->DIN = *(uint32_t*)(ctr0addr); + hcryp->Instance->DIN = *(uint32_t *)(ctr0addr); + ctr0addr += 4U; + hcryp->Instance->DIN = *(uint32_t *)(ctr0addr); + ctr0addr += 4U; + hcryp->Instance->DIN = *(uint32_t *)(ctr0addr); + ctr0addr += 4U; + hcryp->Instance->DIN = *(uint32_t *)(ctr0addr); } /* Wait for OFNE flag to be raised */ tickstart = HAL_GetTick(); - while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE)) + while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE)) { /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { /* Disable the CRYP peripheral Clock */ __HAL_CRYP_DISABLE(hcryp); @@ -465,13 +465,13 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u } /* Read the Auth TAG in the IN FIFO */ - *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT; - tagaddr+=4U; - *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT; - tagaddr+=4U; - *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT; - tagaddr+=4U; - *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT; + *(uint32_t *)(tagaddr) = hcryp->Instance->DOUT; + tagaddr += 4U; + *(uint32_t *)(tagaddr) = hcryp->Instance->DOUT; + tagaddr += 4U; + *(uint32_t *)(tagaddr) = hcryp->Instance->DOUT; + tagaddr += 4U; + *(uint32_t *)(tagaddr) = hcryp->Instance->DOUT; #else /* AES */ @@ -480,75 +480,75 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u /* Write the counter block in the IN FIFO, CTR0 information from B0 data has to be swapped according to the DATATYPE*/ - if(hcryp->Init.DataType == CRYP_DATATYPE_8B) + if (hcryp->Init.DataType == CRYP_DATATYPE_8B) { - ctr0[0]=(__REV(hcryp->Init.B0[0]) & CRYP_CCM_CTR0_0); - ctr0[1]=__REV(hcryp->Init.B0[1]); - ctr0[2]=__REV(hcryp->Init.B0[2]); - ctr0[3]=(__REV(hcryp->Init.B0[3])& CRYP_CCM_CTR0_3); - - hcryp->Instance->DINR = __REV(*(uint32_t*)(ctr0addr)); - ctr0addr+=4U; - hcryp->Instance->DINR = __REV(*(uint32_t*)(ctr0addr)); - ctr0addr+=4U; - hcryp->Instance->DINR = __REV(*(uint32_t*)(ctr0addr)); - ctr0addr+=4U; - hcryp->Instance->DINR = __REV(*(uint32_t*)(ctr0addr)); + ctr0[0] = (__REV(hcryp->Init.B0[0]) & CRYP_CCM_CTR0_0); + ctr0[1] = __REV(hcryp->Init.B0[1]); + ctr0[2] = __REV(hcryp->Init.B0[2]); + ctr0[3] = (__REV(hcryp->Init.B0[3])& CRYP_CCM_CTR0_3); + + hcryp->Instance->DINR = __REV(*(uint32_t *)(ctr0addr)); + ctr0addr += 4U; + hcryp->Instance->DINR = __REV(*(uint32_t *)(ctr0addr)); + ctr0addr += 4U; + hcryp->Instance->DINR = __REV(*(uint32_t *)(ctr0addr)); + ctr0addr += 4U; + hcryp->Instance->DINR = __REV(*(uint32_t *)(ctr0addr)); } - else if(hcryp->Init.DataType == CRYP_DATATYPE_16B) + else if (hcryp->Init.DataType == CRYP_DATATYPE_16B) { - ctr0[0]= ( __ROR((hcryp->Init.B0[0]), 16U)& CRYP_CCM_CTR0_0); - ctr0[1]= __ROR((hcryp->Init.B0[1]), 16U); - ctr0[2]= __ROR((hcryp->Init.B0[2]), 16U); - ctr0[3]= ( __ROR((hcryp->Init.B0[3]), 16U)& CRYP_CCM_CTR0_3); - - hcryp->Instance->DINR = __ROR(*(uint32_t*)(ctr0addr), 16U); - ctr0addr+=4U; - hcryp->Instance->DINR = __ROR(*(uint32_t*)(ctr0addr), 16U); - ctr0addr+=4U; - hcryp->Instance->DINR = __ROR(*(uint32_t*)(ctr0addr), 16U); - ctr0addr+=4U; - hcryp->Instance->DINR = __ROR(*(uint32_t*)(ctr0addr), 16U); + ctr0[0] = (__ROR((hcryp->Init.B0[0]), 16U)& CRYP_CCM_CTR0_0); + ctr0[1] = __ROR((hcryp->Init.B0[1]), 16U); + ctr0[2] = __ROR((hcryp->Init.B0[2]), 16U); + ctr0[3] = (__ROR((hcryp->Init.B0[3]), 16U)& CRYP_CCM_CTR0_3); + + hcryp->Instance->DINR = __ROR(*(uint32_t *)(ctr0addr), 16U); + ctr0addr += 4U; + hcryp->Instance->DINR = __ROR(*(uint32_t *)(ctr0addr), 16U); + ctr0addr += 4U; + hcryp->Instance->DINR = __ROR(*(uint32_t *)(ctr0addr), 16U); + ctr0addr += 4U; + hcryp->Instance->DINR = __ROR(*(uint32_t *)(ctr0addr), 16U); } - else if(hcryp->Init.DataType == CRYP_DATATYPE_1B) + else if (hcryp->Init.DataType == CRYP_DATATYPE_1B) { - ctr0[0]=(__RBIT(hcryp->Init.B0[0])& CRYP_CCM_CTR0_0); - ctr0[1]=__RBIT(hcryp->Init.B0[1]); - ctr0[2]=__RBIT(hcryp->Init.B0[2]); - ctr0[3]=(__RBIT(hcryp->Init.B0[3])& CRYP_CCM_CTR0_3); - - hcryp->Instance->DINR = __RBIT(*(uint32_t*)(ctr0addr)); - ctr0addr+=4U; - hcryp->Instance->DINR = __RBIT(*(uint32_t*)(ctr0addr)); - ctr0addr+=4U; - hcryp->Instance->DINR = __RBIT(*(uint32_t*)(ctr0addr)); - ctr0addr+=4U; - hcryp->Instance->DINR = __RBIT(*(uint32_t*)(ctr0addr)); + ctr0[0] = (__RBIT(hcryp->Init.B0[0])& CRYP_CCM_CTR0_0); + ctr0[1] = __RBIT(hcryp->Init.B0[1]); + ctr0[2] = __RBIT(hcryp->Init.B0[2]); + ctr0[3] = (__RBIT(hcryp->Init.B0[3])& CRYP_CCM_CTR0_3); + + hcryp->Instance->DINR = __RBIT(*(uint32_t *)(ctr0addr)); + ctr0addr += 4U; + hcryp->Instance->DINR = __RBIT(*(uint32_t *)(ctr0addr)); + ctr0addr += 4U; + hcryp->Instance->DINR = __RBIT(*(uint32_t *)(ctr0addr)); + ctr0addr += 4U; + hcryp->Instance->DINR = __RBIT(*(uint32_t *)(ctr0addr)); } else { - ctr0[0]=(hcryp->Init.B0[0]) & CRYP_CCM_CTR0_0; - ctr0[1]=hcryp->Init.B0[1]; - ctr0[2]=hcryp->Init.B0[2]; - ctr0[3]=hcryp->Init.B0[3] & CRYP_CCM_CTR0_3; - - hcryp->Instance->DINR = *(uint32_t*)(ctr0addr); - ctr0addr+=4U; - hcryp->Instance->DINR = *(uint32_t*)(ctr0addr); - ctr0addr+=4U; - hcryp->Instance->DINR = *(uint32_t*)(ctr0addr); - ctr0addr+=4U; - hcryp->Instance->DINR = *(uint32_t*)(ctr0addr); + ctr0[0] = (hcryp->Init.B0[0]) & CRYP_CCM_CTR0_0; + ctr0[1] = hcryp->Init.B0[1]; + ctr0[2] = hcryp->Init.B0[2]; + ctr0[3] = hcryp->Init.B0[3] & CRYP_CCM_CTR0_3; + + hcryp->Instance->DINR = *(uint32_t *)(ctr0addr); + ctr0addr += 4U; + hcryp->Instance->DINR = *(uint32_t *)(ctr0addr); + ctr0addr += 4U; + hcryp->Instance->DINR = *(uint32_t *)(ctr0addr); + ctr0addr += 4U; + hcryp->Instance->DINR = *(uint32_t *)(ctr0addr); } /* Wait for CCF flag to be raised */ tickstart = HAL_GetTick(); - while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)) + while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)) { /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { /* Disable the CRYP peripheral Clock */ __HAL_CRYP_DISABLE(hcryp); @@ -565,13 +565,13 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u } /* Read the authentication TAG in the output FIFO */ - *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR; - tagaddr+=4U; - *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR; - tagaddr+=4U; - *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR; - tagaddr+=4U; - *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR; + *(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR; + tagaddr += 4U; + *(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR; + tagaddr += 4U; + *(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR; + tagaddr += 4U; + *(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR; /* Clear CCF Flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); @@ -603,8 +603,8 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u #if defined (AES) /** @defgroup CRYPEx_Exported_Functions_Group2 Key Derivation functions - * @brief AutoKeyDerivation functions - * + * @brief AutoKeyDerivation functions + * @verbatim ============================================================================== ##### Key Derivation functions ##### @@ -624,7 +624,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u */ void HAL_CRYPEx_EnableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp) { - if(hcryp->State == HAL_CRYP_STATE_READY) + if (hcryp->State == HAL_CRYP_STATE_READY) { hcryp->AutoKeyDerivation = ENABLE; } @@ -641,7 +641,7 @@ void HAL_CRYPEx_EnableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp) */ void HAL_CRYPEx_DisableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp) { - if(hcryp->State == HAL_CRYP_STATE_READY) + if (hcryp->State == HAL_CRYP_STATE_READY) { hcryp->AutoKeyDerivation = DISABLE; } diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpi2c.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpi2c.c index 44f64f352c..d4f42d5f05 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpi2c.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpi2c.c @@ -352,13 +352,13 @@ /* Private define to centralize the enable/disable of Interrupts */ -#define FMPI2C_XFER_TX_IT (0x00000001U) -#define FMPI2C_XFER_RX_IT (0x00000002U) -#define FMPI2C_XFER_LISTEN_IT (0x00000004U) +#define FMPI2C_XFER_TX_IT (uint16_t)(0x0001U) /* Bit field can be combinated with @ref FMPI2C_XFER_LISTEN_IT */ +#define FMPI2C_XFER_RX_IT (uint16_t)(0x0002U) /* Bit field can be combinated with @ref FMPI2C_XFER_LISTEN_IT */ +#define FMPI2C_XFER_LISTEN_IT (uint16_t)(0x8000U) /* Bit field can be combinated with @ref FMPI2C_XFER_TX_IT and @ref FMPI2C_XFER_RX_IT */ -#define FMPI2C_XFER_ERROR_IT (0x00000011U) -#define FMPI2C_XFER_CPLT_IT (0x00000012U) -#define FMPI2C_XFER_RELOAD_IT (0x00000012U) +#define FMPI2C_XFER_ERROR_IT (uint16_t)(0x0010U) /* Bit definition to manage addition of global Error and NACK treatment */ +#define FMPI2C_XFER_CPLT_IT (uint16_t)(0x0020U) /* Bit definition to manage only STOP evenement */ +#define FMPI2C_XFER_RELOAD_IT (uint16_t)(0x0040U) /* Bit definition to manage only Reload of NBYTE */ /* Private define Sequential Transfer Options default/reset value */ #define FMPI2C_NO_OPTION_FRAME (0xFFFF0000U) @@ -411,6 +411,9 @@ static HAL_StatusTypeDef FMPI2C_IsAcknowledgeFailed(FMPI2C_HandleTypeDef *hfmpi2 static void FMPI2C_Enable_IRQ(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t InterruptRequest); static void FMPI2C_Disable_IRQ(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t InterruptRequest); +/* Private function to treat different error callback */ +static void FMPI2C_TreatErrorCallback(FMPI2C_HandleTypeDef *hfmpi2c); + /* Private function to flush TXDR register */ static void FMPI2C_Flush_TXDR(FMPI2C_HandleTypeDef *hfmpi2c); @@ -3201,7 +3204,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2 FMPI2C_ConvertOtherXferOptions(hfmpi2c); /* Update xfermode accordingly if no reload is necessary */ - if (hfmpi2c->XferCount < MAX_NBYTE_SIZE) + if (hfmpi2c->XferCount <= MAX_NBYTE_SIZE) { xfermode = hfmpi2c->XferOptions; } @@ -3286,7 +3289,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi FMPI2C_ConvertOtherXferOptions(hfmpi2c); /* Update xfermode accordingly if no reload is necessary */ - if (hfmpi2c->XferCount < MAX_NBYTE_SIZE) + if (hfmpi2c->XferCount <= MAX_NBYTE_SIZE) { xfermode = hfmpi2c->XferOptions; } @@ -3447,7 +3450,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c FMPI2C_ConvertOtherXferOptions(hfmpi2c); /* Update xfermode accordingly if no reload is necessary */ - if (hfmpi2c->XferCount < MAX_NBYTE_SIZE) + if (hfmpi2c->XferCount <= MAX_NBYTE_SIZE) { xfermode = hfmpi2c->XferOptions; } @@ -3532,7 +3535,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2 FMPI2C_ConvertOtherXferOptions(hfmpi2c); /* Update xfermode accordingly if no reload is necessary */ - if (hfmpi2c->XferCount < MAX_NBYTE_SIZE) + if (hfmpi2c->XferCount <= MAX_NBYTE_SIZE) { xfermode = hfmpi2c->XferOptions; } @@ -4252,9 +4255,21 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Abort_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint /* Process Locked */ __HAL_LOCK(hfmpi2c); - /* Disable Interrupts */ - FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_RX_IT); - FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT); + /* Disable Interrupts and Store Previous state */ + if (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_TX) + { + FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT); + hfmpi2c->PreviousState = FMPI2C_STATE_MASTER_BUSY_TX; + } + else if (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX) + { + FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_RX_IT); + hfmpi2c->PreviousState = FMPI2C_STATE_MASTER_BUSY_RX; + } + else + { + /* Do nothing */ + } /* Set State at HAL_FMPI2C_STATE_ABORT */ hfmpi2c->State = HAL_FMPI2C_STATE_ABORT; @@ -5002,6 +5017,7 @@ static HAL_StatusTypeDef FMPI2C_Slave_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfm { uint32_t tmpoptions = hfmpi2c->XferOptions; uint32_t treatdmanack = 0U; + HAL_FMPI2C_StateTypeDef tmpstate; /* Process locked */ __HAL_LOCK(hfmpi2c); @@ -5080,8 +5096,24 @@ static HAL_StatusTypeDef FMPI2C_Slave_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfm /* Set ErrorCode corresponding to a Non-Acknowledge */ hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF; + /* Store current hfmpi2c->State, solve MISRA2012-Rule-13.5 */ + tmpstate = hfmpi2c->State; + if ((tmpoptions == FMPI2C_FIRST_FRAME) || (tmpoptions == FMPI2C_NEXT_FRAME)) { + if ((tmpstate == HAL_FMPI2C_STATE_BUSY_TX) || (tmpstate == HAL_FMPI2C_STATE_BUSY_TX_LISTEN)) + { + hfmpi2c->PreviousState = FMPI2C_STATE_SLAVE_BUSY_TX; + } + else if ((tmpstate == HAL_FMPI2C_STATE_BUSY_RX) || (tmpstate == HAL_FMPI2C_STATE_BUSY_RX_LISTEN)) + { + hfmpi2c->PreviousState = FMPI2C_STATE_SLAVE_BUSY_RX; + } + else + { + /* Do nothing */ + } + /* Call the corresponding callback to inform upper layer of End of Transfer */ FMPI2C_ITError(hfmpi2c, hfmpi2c->ErrorCode); } @@ -5370,9 +5402,27 @@ static void FMPI2C_ITMasterSeqCplt(FMPI2C_HandleTypeDef *hfmpi2c) */ static void FMPI2C_ITSlaveSeqCplt(FMPI2C_HandleTypeDef *hfmpi2c) { + uint32_t tmpcr1value = READ_REG(hfmpi2c->Instance->CR1); + /* Reset FMPI2C handle mode */ hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE; + /* If a DMA is ongoing, Update handle size context */ + if (FMPI2C_CHECK_IT_SOURCE(tmpcr1value, FMPI2C_CR1_TXDMAEN) != RESET) + { + /* Disable DMA Request */ + hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_TXDMAEN; + } + else if (FMPI2C_CHECK_IT_SOURCE(tmpcr1value, FMPI2C_CR1_RXDMAEN) != RESET) + { + /* Disable DMA Request */ + hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_RXDMAEN; + } + else + { + /* Do nothing */ + } + if (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_TX_LISTEN) { /* Remove HAL_FMPI2C_STATE_SLAVE_BUSY_TX, keep only HAL_FMPI2C_STATE_LISTEN */ @@ -5427,19 +5477,36 @@ static void FMPI2C_ITSlaveSeqCplt(FMPI2C_HandleTypeDef *hfmpi2c) static void FMPI2C_ITMasterCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags) { uint32_t tmperror; + uint32_t tmpITFlags = ITFlags; + uint32_t tmp; /* Clear STOP Flag */ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF); + /* Disable Interrupts and Store Previous state */ + if (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_TX) + { + FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT); + hfmpi2c->PreviousState = FMPI2C_STATE_MASTER_BUSY_TX; + } + else if (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX) + { + FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_RX_IT); + hfmpi2c->PreviousState = FMPI2C_STATE_MASTER_BUSY_RX; + } + else + { + /* Do nothing */ + } + /* Clear Configuration Register 2 */ FMPI2C_RESET_CR2(hfmpi2c); /* Reset handle parameters */ - hfmpi2c->PreviousState = FMPI2C_STATE_NONE; hfmpi2c->XferISR = NULL; hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME; - if (FMPI2C_CHECK_FLAG(ITFlags, FMPI2C_FLAG_AF) != RESET) + if (FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_AF) != RESET) { /* Clear NACK Flag */ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF); @@ -5448,12 +5515,18 @@ static void FMPI2C_ITMasterCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags) hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF; } + /* Fetch Last receive data if any */ + if ((hfmpi2c->State == HAL_FMPI2C_STATE_ABORT) && (FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_RXNE) != RESET)) + { + /* Read data from RXDR */ + tmp = (uint8_t)hfmpi2c->Instance->RXDR; + + UNUSED(tmp); + } + /* Flush TX register */ FMPI2C_Flush_TXDR(hfmpi2c); - /* Disable Interrupts */ - FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT | FMPI2C_XFER_RX_IT); - /* Store current volatile hfmpi2c->ErrorCode, misra rule */ tmperror = hfmpi2c->ErrorCode; @@ -5467,6 +5540,7 @@ static void FMPI2C_ITMasterCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags) else if (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_TX) { hfmpi2c->State = HAL_FMPI2C_STATE_READY; + hfmpi2c->PreviousState = FMPI2C_STATE_NONE; if (hfmpi2c->Mode == HAL_FMPI2C_MODE_MEM) { @@ -5501,6 +5575,7 @@ static void FMPI2C_ITMasterCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags) else if (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX) { hfmpi2c->State = HAL_FMPI2C_STATE_READY; + hfmpi2c->PreviousState = FMPI2C_STATE_NONE; if (hfmpi2c->Mode == HAL_FMPI2C_MODE_MEM) { @@ -5547,12 +5622,26 @@ static void FMPI2C_ITSlaveCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags) { uint32_t tmpcr1value = READ_REG(hfmpi2c->Instance->CR1); uint32_t tmpITFlags = ITFlags; + HAL_FMPI2C_StateTypeDef tmpstate = hfmpi2c->State; /* Clear STOP Flag */ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF); - /* Disable all interrupts */ - FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_LISTEN_IT | FMPI2C_XFER_TX_IT | FMPI2C_XFER_RX_IT); + /* Disable Interrupts and Store Previous state */ + if ((tmpstate == HAL_FMPI2C_STATE_BUSY_TX) || (tmpstate == HAL_FMPI2C_STATE_BUSY_TX_LISTEN)) + { + FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_LISTEN_IT | FMPI2C_XFER_TX_IT); + hfmpi2c->PreviousState = FMPI2C_STATE_SLAVE_BUSY_TX; + } + else if ((tmpstate == HAL_FMPI2C_STATE_BUSY_RX) || (tmpstate == HAL_FMPI2C_STATE_BUSY_RX_LISTEN)) + { + FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_LISTEN_IT | FMPI2C_XFER_RX_IT); + hfmpi2c->PreviousState = FMPI2C_STATE_SLAVE_BUSY_RX; + } + else + { + /* Do nothing */ + } /* Disable Address Acknowledge */ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK; @@ -5566,6 +5655,9 @@ static void FMPI2C_ITSlaveCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags) /* If a DMA is ongoing, Update handle size context */ if (FMPI2C_CHECK_IT_SOURCE(tmpcr1value, FMPI2C_CR1_TXDMAEN) != RESET) { + /* Disable DMA Request */ + hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_TXDMAEN; + if (hfmpi2c->hdmatx != NULL) { hfmpi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hfmpi2c->hdmatx); @@ -5573,6 +5665,9 @@ static void FMPI2C_ITSlaveCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags) } else if (FMPI2C_CHECK_IT_SOURCE(tmpcr1value, FMPI2C_CR1_RXDMAEN) != RESET) { + /* Disable DMA Request */ + hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_RXDMAEN; + if (hfmpi2c->hdmarx != NULL) { hfmpi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hfmpi2c->hdmarx); @@ -5609,7 +5704,6 @@ static void FMPI2C_ITSlaveCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags) hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF; } - hfmpi2c->PreviousState = FMPI2C_STATE_NONE; hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE; hfmpi2c->XferISR = NULL; @@ -5632,6 +5726,7 @@ static void FMPI2C_ITSlaveCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags) hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME; hfmpi2c->State = HAL_FMPI2C_STATE_READY; + hfmpi2c->PreviousState = FMPI2C_STATE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hfmpi2c); @@ -5647,6 +5742,7 @@ static void FMPI2C_ITSlaveCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags) else if (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX) { hfmpi2c->State = HAL_FMPI2C_STATE_READY; + hfmpi2c->PreviousState = FMPI2C_STATE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hfmpi2c); @@ -5661,6 +5757,7 @@ static void FMPI2C_ITSlaveCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags) else { hfmpi2c->State = HAL_FMPI2C_STATE_READY; + hfmpi2c->PreviousState = FMPI2C_STATE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hfmpi2c); @@ -5734,6 +5831,7 @@ static void FMPI2C_ITListenCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags) static void FMPI2C_ITError(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ErrorCode) { HAL_FMPI2C_StateTypeDef tmpstate = hfmpi2c->State; + uint32_t tmppreviousstate; /* Reset handle parameters */ hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE; @@ -5753,7 +5851,6 @@ static void FMPI2C_ITError(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ErrorCode) /* keep HAL_FMPI2C_STATE_LISTEN if set */ hfmpi2c->State = HAL_FMPI2C_STATE_LISTEN; - hfmpi2c->PreviousState = FMPI2C_STATE_NONE; hfmpi2c->XferISR = FMPI2C_Slave_ISR_IT; } else @@ -5768,16 +5865,19 @@ static void FMPI2C_ITError(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ErrorCode) /* Set HAL_FMPI2C_STATE_READY */ hfmpi2c->State = HAL_FMPI2C_STATE_READY; } - hfmpi2c->PreviousState = FMPI2C_STATE_NONE; hfmpi2c->XferISR = NULL; } /* Abort DMA TX transfer if any */ - if ((hfmpi2c->Instance->CR1 & FMPI2C_CR1_TXDMAEN) == FMPI2C_CR1_TXDMAEN) + tmppreviousstate = hfmpi2c->PreviousState; + if ((hfmpi2c->hdmatx != NULL) && ((tmppreviousstate == FMPI2C_STATE_MASTER_BUSY_TX) || (tmppreviousstate == FMPI2C_STATE_SLAVE_BUSY_TX))) { - hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_TXDMAEN; + if ((hfmpi2c->Instance->CR1 & FMPI2C_CR1_TXDMAEN) == FMPI2C_CR1_TXDMAEN) + { + hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_TXDMAEN; + } - if (hfmpi2c->hdmatx != NULL) + if (HAL_DMA_GetState(hfmpi2c->hdmatx) != HAL_DMA_STATE_READY) { /* Set the FMPI2C DMA Abort callback : will lead to call HAL_FMPI2C_ErrorCallback() at end of DMA abort procedure */ @@ -5793,13 +5893,20 @@ static void FMPI2C_ITError(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ErrorCode) hfmpi2c->hdmatx->XferAbortCallback(hfmpi2c->hdmatx); } } + else + { + FMPI2C_TreatErrorCallback(hfmpi2c); + } } /* Abort DMA RX transfer if any */ - else if ((hfmpi2c->Instance->CR1 & FMPI2C_CR1_RXDMAEN) == FMPI2C_CR1_RXDMAEN) + else if ((hfmpi2c->hdmarx != NULL) && ((tmppreviousstate == FMPI2C_STATE_MASTER_BUSY_RX) || (tmppreviousstate == FMPI2C_STATE_SLAVE_BUSY_RX))) { - hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_RXDMAEN; + if ((hfmpi2c->Instance->CR1 & FMPI2C_CR1_RXDMAEN) == FMPI2C_CR1_RXDMAEN) + { + hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_RXDMAEN; + } - if (hfmpi2c->hdmarx != NULL) + if (HAL_DMA_GetState(hfmpi2c->hdmarx) != HAL_DMA_STATE_READY) { /* Set the FMPI2C DMA Abort callback : will lead to call HAL_FMPI2C_ErrorCallback() at end of DMA abort procedure */ @@ -5815,10 +5922,28 @@ static void FMPI2C_ITError(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ErrorCode) hfmpi2c->hdmarx->XferAbortCallback(hfmpi2c->hdmarx); } } + else + { + FMPI2C_TreatErrorCallback(hfmpi2c); + } } - else if (hfmpi2c->State == HAL_FMPI2C_STATE_ABORT) + else + { + FMPI2C_TreatErrorCallback(hfmpi2c); + } +} + +/** + * @brief FMPI2C Error callback treatment. + * @param hfmpi2c FMPI2C handle. + * @retval None + */ +static void FMPI2C_TreatErrorCallback(FMPI2C_HandleTypeDef *hfmpi2c) +{ + if (hfmpi2c->State == HAL_FMPI2C_STATE_ABORT) { hfmpi2c->State = HAL_FMPI2C_STATE_READY; + hfmpi2c->PreviousState = FMPI2C_STATE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hfmpi2c); @@ -5832,6 +5957,8 @@ static void FMPI2C_ITError(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ErrorCode) } else { + hfmpi2c->PreviousState = FMPI2C_STATE_NONE; + /* Process Unlocked */ __HAL_UNLOCK(hfmpi2c); @@ -6066,27 +6193,7 @@ static void FMPI2C_DMAAbort(DMA_HandleTypeDef *hdma) hfmpi2c->hdmatx->XferAbortCallback = NULL; hfmpi2c->hdmarx->XferAbortCallback = NULL; - /* Check if come from abort from user */ - if (hfmpi2c->State == HAL_FMPI2C_STATE_ABORT) - { - hfmpi2c->State = HAL_FMPI2C_STATE_READY; - - /* Call the corresponding callback to inform upper layer of End of Transfer */ -#if (USE_HAL_FMPI2C_REGISTER_CALLBACKS == 1) - hfmpi2c->AbortCpltCallback(hfmpi2c); -#else - HAL_FMPI2C_AbortCpltCallback(hfmpi2c); -#endif /* USE_HAL_FMPI2C_REGISTER_CALLBACKS */ - } - else - { - /* Call the corresponding callback to inform upper layer of End of Transfer */ -#if (USE_HAL_FMPI2C_REGISTER_CALLBACKS == 1) - hfmpi2c->ErrorCallback(hfmpi2c); -#else - HAL_FMPI2C_ErrorCallback(hfmpi2c); -#endif /* USE_HAL_FMPI2C_REGISTER_CALLBACKS */ - } + FMPI2C_TreatErrorCallback(hfmpi2c); } /** @@ -6363,19 +6470,19 @@ static void FMPI2C_Enable_IRQ(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t InterruptR tmpisr |= FMPI2C_IT_ADDRI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_ERRI; } - if ((InterruptRequest & FMPI2C_XFER_ERROR_IT) == FMPI2C_XFER_ERROR_IT) + if (InterruptRequest == FMPI2C_XFER_ERROR_IT) { /* Enable ERR and NACK interrupts */ tmpisr |= FMPI2C_IT_ERRI | FMPI2C_IT_NACKI; } - if ((InterruptRequest & FMPI2C_XFER_CPLT_IT) == FMPI2C_XFER_CPLT_IT) + if (InterruptRequest == FMPI2C_XFER_CPLT_IT) { /* Enable STOP interrupts */ - tmpisr |= FMPI2C_IT_STOPI; + tmpisr |= (FMPI2C_IT_STOPI | FMPI2C_IT_TCI); } - if ((InterruptRequest & FMPI2C_XFER_RELOAD_IT) == FMPI2C_XFER_RELOAD_IT) + if (InterruptRequest == FMPI2C_XFER_RELOAD_IT) { /* Enable TC interrupts */ tmpisr |= FMPI2C_IT_TCI; @@ -6401,7 +6508,7 @@ static void FMPI2C_Enable_IRQ(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t InterruptR tmpisr |= FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_RXI; } - if ((InterruptRequest & FMPI2C_XFER_CPLT_IT) == FMPI2C_XFER_CPLT_IT) + if (InterruptRequest == FMPI2C_XFER_CPLT_IT) { /* Enable STOP interrupts */ tmpisr |= FMPI2C_IT_STOPI; @@ -6455,19 +6562,19 @@ static void FMPI2C_Disable_IRQ(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t Interrupt tmpisr |= FMPI2C_IT_ADDRI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_ERRI; } - if ((InterruptRequest & FMPI2C_XFER_ERROR_IT) == FMPI2C_XFER_ERROR_IT) + if (InterruptRequest == FMPI2C_XFER_ERROR_IT) { /* Enable ERR and NACK interrupts */ tmpisr |= FMPI2C_IT_ERRI | FMPI2C_IT_NACKI; } - if ((InterruptRequest & FMPI2C_XFER_CPLT_IT) == FMPI2C_XFER_CPLT_IT) + if (InterruptRequest == FMPI2C_XFER_CPLT_IT) { /* Enable STOP interrupts */ tmpisr |= FMPI2C_IT_STOPI; } - if ((InterruptRequest & FMPI2C_XFER_RELOAD_IT) == FMPI2C_XFER_RELOAD_IT) + if (InterruptRequest == FMPI2C_XFER_RELOAD_IT) { /* Enable TC interrupts */ tmpisr |= FMPI2C_IT_TCI; diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpsmbus.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpsmbus.c new file mode 100644 index 0000000000..3d0cd20ada --- /dev/null +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpsmbus.c @@ -0,0 +1,2675 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_fmpsmbus.c + * @author MCD Application Team + * @brief FMPSMBUS HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the System Management Bus (SMBus) peripheral, + * based on I2C principles of operation : + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral State and Errors functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The FMPSMBUS HAL driver can be used as follows: + + (#) Declare a FMPSMBUS_HandleTypeDef handle structure, for example: + FMPSMBUS_HandleTypeDef hfmpsmbus; + + (#)Initialize the FMPSMBUS low level resources by implementing the @ref HAL_FMPSMBUS_MspInit() API: + (##) Enable the FMPSMBUSx interface clock + (##) FMPSMBUS pins configuration + (+++) Enable the clock for the FMPSMBUS GPIOs + (+++) Configure FMPSMBUS pins as alternate function open-drain + (##) NVIC configuration if you need to use interrupt process + (+++) Configure the FMPSMBUSx interrupt priority + (+++) Enable the NVIC FMPSMBUS IRQ Channel + + (#) Configure the Communication Clock Timing, Bus Timeout, Own Address1, Master Addressing mode, + Dual Addressing mode, Own Address2, Own Address2 Mask, General call, Nostretch mode, + Peripheral mode and Packet Error Check mode in the hfmpsmbus Init structure. + + (#) Initialize the FMPSMBUS registers by calling the @ref HAL_FMPSMBUS_Init() API: + (++) These API's configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) + by calling the customized @ref HAL_FMPSMBUS_MspInit(&hfmpsmbus) API. + + (#) To check if target device is ready for communication, use the function @ref HAL_FMPSMBUS_IsDeviceReady() + + (#) For FMPSMBUS IO operations, only one mode of operations is available within this driver + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Transmit in master/host FMPSMBUS mode an amount of data in non-blocking mode using @ref HAL_FMPSMBUS_Master_Transmit_IT() + (++) At transmission end of transfer @ref HAL_FMPSMBUS_MasterTxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_FMPSMBUS_MasterTxCpltCallback() + (+) Receive in master/host FMPSMBUS mode an amount of data in non-blocking mode using @ref HAL_FMPSMBUS_Master_Receive_IT() + (++) At reception end of transfer @ref HAL_FMPSMBUS_MasterRxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_FMPSMBUS_MasterRxCpltCallback() + (+) Abort a master/host FMPSMBUS process communication with Interrupt using @ref HAL_FMPSMBUS_Master_Abort_IT() + (++) The associated previous transfer callback is called at the end of abort process + (++) mean @ref HAL_FMPSMBUS_MasterTxCpltCallback() in case of previous state was master transmit + (++) mean @ref HAL_FMPSMBUS_MasterRxCpltCallback() in case of previous state was master receive + (+) Enable/disable the Address listen mode in slave/device or host/slave FMPSMBUS mode + using @ref HAL_FMPSMBUS_EnableListen_IT() @ref HAL_FMPSMBUS_DisableListen_IT() + (++) When address slave/device FMPSMBUS match, @ref HAL_FMPSMBUS_AddrCallback() is executed and user can + add his own code to check the Address Match Code and the transmission direction request by master/host (Write/Read). + (++) At Listen mode end @ref HAL_FMPSMBUS_ListenCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_FMPSMBUS_ListenCpltCallback() + (+) Transmit in slave/device FMPSMBUS mode an amount of data in non-blocking mode using @ref HAL_FMPSMBUS_Slave_Transmit_IT() + (++) At transmission end of transfer @ref HAL_FMPSMBUS_SlaveTxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_FMPSMBUS_SlaveTxCpltCallback() + (+) Receive in slave/device FMPSMBUS mode an amount of data in non-blocking mode using @ref HAL_FMPSMBUS_Slave_Receive_IT() + (++) At reception end of transfer @ref HAL_FMPSMBUS_SlaveRxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_FMPSMBUS_SlaveRxCpltCallback() + (+) Enable/Disable the FMPSMBUS alert mode using @ref HAL_FMPSMBUS_EnableAlert_IT() @ref HAL_FMPSMBUS_DisableAlert_IT() + (++) When FMPSMBUS Alert is generated @ref HAL_FMPSMBUS_ErrorCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_FMPSMBUS_ErrorCallback() + to check the Alert Error Code using function @ref HAL_FMPSMBUS_GetError() + (+) Get HAL state machine or error values using @ref HAL_FMPSMBUS_GetState() or @ref HAL_FMPSMBUS_GetError() + (+) In case of transfer Error, @ref HAL_FMPSMBUS_ErrorCallback() function is executed and user can + add his own code by customization of function pointer @ref HAL_FMPSMBUS_ErrorCallback() + to check the Error Code using function @ref HAL_FMPSMBUS_GetError() + + *** FMPSMBUS HAL driver macros list *** + ================================== + [..] + Below the list of most used macros in FMPSMBUS HAL driver. + + (+) @ref __HAL_FMPSMBUS_ENABLE: Enable the FMPSMBUS peripheral + (+) @ref __HAL_FMPSMBUS_DISABLE: Disable the FMPSMBUS peripheral + (+) @ref __HAL_FMPSMBUS_GET_FLAG: Check whether the specified FMPSMBUS flag is set or not + (+) @ref __HAL_FMPSMBUS_CLEAR_FLAG: Clear the specified FMPSMBUS pending flag + (+) @ref __HAL_FMPSMBUS_ENABLE_IT: Enable the specified FMPSMBUS interrupt + (+) @ref __HAL_FMPSMBUS_DISABLE_IT: Disable the specified FMPSMBUS interrupt + + *** Callback registration *** + ============================================= + [..] + The compilation flag USE_HAL_FMPSMBUS_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use Functions @ref HAL_FMPSMBUS_RegisterCallback() or @ref HAL_FMPSMBUS_RegisterAddrCallback() + to register an interrupt callback. + [..] + Function @ref HAL_FMPSMBUS_RegisterCallback() allows to register following callbacks: + (+) MasterTxCpltCallback : callback for Master transmission end of transfer. + (+) MasterRxCpltCallback : callback for Master reception end of transfer. + (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. + (+) SlaveRxCpltCallback : callback for Slave reception end of transfer. + (+) ListenCpltCallback : callback for end of listen mode. + (+) ErrorCallback : callback for error detection. + (+) MspInitCallback : callback for Msp Init. + (+) MspDeInitCallback : callback for Msp DeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + [..] + For specific callback AddrCallback use dedicated register callbacks : @ref HAL_FMPSMBUS_RegisterAddrCallback. + [..] + Use function @ref HAL_FMPSMBUS_UnRegisterCallback to reset a callback to the default + weak function. + @ref HAL_FMPSMBUS_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) MasterTxCpltCallback : callback for Master transmission end of transfer. + (+) MasterRxCpltCallback : callback for Master reception end of transfer. + (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. + (+) SlaveRxCpltCallback : callback for Slave reception end of transfer. + (+) ListenCpltCallback : callback for end of listen mode. + (+) ErrorCallback : callback for error detection. + (+) MspInitCallback : callback for Msp Init. + (+) MspDeInitCallback : callback for Msp DeInit. + [..] + For callback AddrCallback use dedicated register callbacks : @ref HAL_FMPSMBUS_UnRegisterAddrCallback. + [..] + By default, after the @ref HAL_FMPSMBUS_Init() and when the state is @ref HAL_FMPI2C_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples @ref HAL_FMPSMBUS_MasterTxCpltCallback(), @ref HAL_FMPSMBUS_MasterRxCpltCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak functions in the @ref HAL_FMPSMBUS_Init()/ @ref HAL_FMPSMBUS_DeInit() only when + these callbacks are null (not registered beforehand). + If MspInit or MspDeInit are not null, the @ref HAL_FMPSMBUS_Init()/ @ref HAL_FMPSMBUS_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. + [..] + Callbacks can be registered/unregistered in @ref HAL_FMPI2C_STATE_READY state only. + Exception done MspInit/MspDeInit functions that can be registered/unregistered + in @ref HAL_FMPI2C_STATE_READY or @ref HAL_FMPI2C_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + Then, the user first registers the MspInit/MspDeInit user callbacks + using @ref HAL_FMPSMBUS_RegisterCallback() before calling @ref HAL_FMPSMBUS_DeInit() + or @ref HAL_FMPSMBUS_Init() function. + [..] + When the compilation flag USE_HAL_FMPSMBUS_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + [..] + (@) You can refer to the FMPSMBUS HAL driver header file for more useful macros + + @endverbatim + ****************************************************************************** + * @attention + * + *

    © Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

    + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup FMPSMBUS FMPSMBUS + * @brief FMPSMBUS HAL module driver + * @{ + */ + +#ifdef HAL_FMPSMBUS_MODULE_ENABLED + +#if defined(FMPI2C_CR1_PE) +/* Private typedef -----------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup FMPSMBUS_Private_Define FMPSMBUS Private Constants + * @{ + */ +#define TIMING_CLEAR_MASK (0xF0FFFFFFUL) /*!< FMPSMBUS TIMING clear register Mask */ +#define HAL_TIMEOUT_ADDR (10000U) /*!< 10 s */ +#define HAL_TIMEOUT_BUSY (25U) /*!< 25 ms */ +#define HAL_TIMEOUT_DIR (25U) /*!< 25 ms */ +#define HAL_TIMEOUT_RXNE (25U) /*!< 25 ms */ +#define HAL_TIMEOUT_STOPF (25U) /*!< 25 ms */ +#define HAL_TIMEOUT_TC (25U) /*!< 25 ms */ +#define HAL_TIMEOUT_TCR (25U) /*!< 25 ms */ +#define HAL_TIMEOUT_TXIS (25U) /*!< 25 ms */ +#define MAX_NBYTE_SIZE 255U +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup FMPSMBUS_Private_Functions FMPSMBUS Private Functions + * @{ + */ +static HAL_StatusTypeDef FMPSMBUS_WaitOnFlagUntilTimeout(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout); + +static void FMPSMBUS_Enable_IRQ(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t InterruptRequest); +static void FMPSMBUS_Disable_IRQ(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t InterruptRequest); +static HAL_StatusTypeDef FMPSMBUS_Master_ISR(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t StatusFlags); +static HAL_StatusTypeDef FMPSMBUS_Slave_ISR(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t StatusFlags); + +static void FMPSMBUS_ConvertOtherXferOptions(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); + +static void FMPSMBUS_ITErrorHandler(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); + +static void FMPSMBUS_TransferConfig(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup FMPSMBUS_Exported_Functions FMPSMBUS Exported Functions + * @{ + */ + +/** @defgroup FMPSMBUS_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to initialize and + deinitialize the FMPSMBUSx peripheral: + + (+) User must Implement HAL_FMPSMBUS_MspInit() function in which he configures + all related peripherals resources (CLOCK, GPIO, IT and NVIC ). + + (+) Call the function HAL_FMPSMBUS_Init() to configure the selected device with + the selected configuration: + (++) Clock Timing + (++) Bus Timeout + (++) Analog Filer mode + (++) Own Address 1 + (++) Addressing mode (Master, Slave) + (++) Dual Addressing mode + (++) Own Address 2 + (++) Own Address 2 Mask + (++) General call mode + (++) Nostretch mode + (++) Packet Error Check mode + (++) Peripheral mode + + + (+) Call the function HAL_FMPSMBUS_DeInit() to restore the default configuration + of the selected FMPSMBUSx peripheral. + + (+) Enable/Disable Analog/Digital filters with HAL_FMPSMBUS_ConfigAnalogFilter() and + HAL_FMPSMBUS_ConfigDigitalFilter(). + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the FMPSMBUS according to the specified parameters + * in the FMPSMBUS_InitTypeDef and initialize the associated handle. + * @param hfmpsmbus Pointer to a FMPSMBUS_HandleTypeDef structure that contains + * the configuration information for the specified FMPSMBUS. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FMPSMBUS_Init(FMPSMBUS_HandleTypeDef *hfmpsmbus) +{ + /* Check the FMPSMBUS handle allocation */ + if (hfmpsmbus == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_FMPSMBUS_ALL_INSTANCE(hfmpsmbus->Instance)); + assert_param(IS_FMPSMBUS_ANALOG_FILTER(hfmpsmbus->Init.AnalogFilter)); + assert_param(IS_FMPSMBUS_OWN_ADDRESS1(hfmpsmbus->Init.OwnAddress1)); + assert_param(IS_FMPSMBUS_ADDRESSING_MODE(hfmpsmbus->Init.AddressingMode)); + assert_param(IS_FMPSMBUS_DUAL_ADDRESS(hfmpsmbus->Init.DualAddressMode)); + assert_param(IS_FMPSMBUS_OWN_ADDRESS2(hfmpsmbus->Init.OwnAddress2)); + assert_param(IS_FMPSMBUS_OWN_ADDRESS2_MASK(hfmpsmbus->Init.OwnAddress2Masks)); + assert_param(IS_FMPSMBUS_GENERAL_CALL(hfmpsmbus->Init.GeneralCallMode)); + assert_param(IS_FMPSMBUS_NO_STRETCH(hfmpsmbus->Init.NoStretchMode)); + assert_param(IS_FMPSMBUS_PEC(hfmpsmbus->Init.PacketErrorCheckMode)); + assert_param(IS_FMPSMBUS_PERIPHERAL_MODE(hfmpsmbus->Init.PeripheralMode)); + + if (hfmpsmbus->State == HAL_FMPSMBUS_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hfmpsmbus->Lock = HAL_UNLOCKED; + +#if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1) + hfmpsmbus->MasterTxCpltCallback = HAL_FMPSMBUS_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */ + hfmpsmbus->MasterRxCpltCallback = HAL_FMPSMBUS_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */ + hfmpsmbus->SlaveTxCpltCallback = HAL_FMPSMBUS_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */ + hfmpsmbus->SlaveRxCpltCallback = HAL_FMPSMBUS_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */ + hfmpsmbus->ListenCpltCallback = HAL_FMPSMBUS_ListenCpltCallback; /* Legacy weak ListenCpltCallback */ + hfmpsmbus->ErrorCallback = HAL_FMPSMBUS_ErrorCallback; /* Legacy weak ErrorCallback */ + hfmpsmbus->AddrCallback = HAL_FMPSMBUS_AddrCallback; /* Legacy weak AddrCallback */ + + if (hfmpsmbus->MspInitCallback == NULL) + { + hfmpsmbus->MspInitCallback = HAL_FMPSMBUS_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + hfmpsmbus->MspInitCallback(hfmpsmbus); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + HAL_FMPSMBUS_MspInit(hfmpsmbus); +#endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */ + } + + hfmpsmbus->State = HAL_FMPSMBUS_STATE_BUSY; + + /* Disable the selected FMPSMBUS peripheral */ + __HAL_FMPSMBUS_DISABLE(hfmpsmbus); + + /*---------------------------- FMPSMBUSx TIMINGR Configuration ------------------------*/ + /* Configure FMPSMBUSx: Frequency range */ + hfmpsmbus->Instance->TIMINGR = hfmpsmbus->Init.Timing & TIMING_CLEAR_MASK; + + /*---------------------------- FMPSMBUSx TIMEOUTR Configuration ------------------------*/ + /* Configure FMPSMBUSx: Bus Timeout */ + hfmpsmbus->Instance->TIMEOUTR &= ~FMPI2C_TIMEOUTR_TIMOUTEN; + hfmpsmbus->Instance->TIMEOUTR &= ~FMPI2C_TIMEOUTR_TEXTEN; + hfmpsmbus->Instance->TIMEOUTR = hfmpsmbus->Init.SMBusTimeout; + + /*---------------------------- FMPSMBUSx OAR1 Configuration -----------------------*/ + /* Configure FMPSMBUSx: Own Address1 and ack own address1 mode */ + hfmpsmbus->Instance->OAR1 &= ~FMPI2C_OAR1_OA1EN; + + if (hfmpsmbus->Init.OwnAddress1 != 0UL) + { + if (hfmpsmbus->Init.AddressingMode == FMPSMBUS_ADDRESSINGMODE_7BIT) + { + hfmpsmbus->Instance->OAR1 = (FMPI2C_OAR1_OA1EN | hfmpsmbus->Init.OwnAddress1); + } + else /* FMPSMBUS_ADDRESSINGMODE_10BIT */ + { + hfmpsmbus->Instance->OAR1 = (FMPI2C_OAR1_OA1EN | FMPI2C_OAR1_OA1MODE | hfmpsmbus->Init.OwnAddress1); + } + } + + /*---------------------------- FMPSMBUSx CR2 Configuration ------------------------*/ + /* Configure FMPSMBUSx: Addressing Master mode */ + if (hfmpsmbus->Init.AddressingMode == FMPSMBUS_ADDRESSINGMODE_10BIT) + { + hfmpsmbus->Instance->CR2 = (FMPI2C_CR2_ADD10); + } + /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process) */ + /* AUTOEND and NACK bit will be manage during Transfer process */ + hfmpsmbus->Instance->CR2 |= (FMPI2C_CR2_AUTOEND | FMPI2C_CR2_NACK); + + /*---------------------------- FMPSMBUSx OAR2 Configuration -----------------------*/ + /* Configure FMPSMBUSx: Dual mode and Own Address2 */ + hfmpsmbus->Instance->OAR2 = (hfmpsmbus->Init.DualAddressMode | hfmpsmbus->Init.OwnAddress2 | (hfmpsmbus->Init.OwnAddress2Masks << 8U)); + + /*---------------------------- FMPSMBUSx CR1 Configuration ------------------------*/ + /* Configure FMPSMBUSx: Generalcall and NoStretch mode */ + hfmpsmbus->Instance->CR1 = (hfmpsmbus->Init.GeneralCallMode | hfmpsmbus->Init.NoStretchMode | hfmpsmbus->Init.PacketErrorCheckMode | hfmpsmbus->Init.PeripheralMode | hfmpsmbus->Init.AnalogFilter); + + /* Enable Slave Byte Control only in case of Packet Error Check is enabled and FMPSMBUS Peripheral is set in Slave mode */ + if ((hfmpsmbus->Init.PacketErrorCheckMode == FMPSMBUS_PEC_ENABLE) + && ((hfmpsmbus->Init.PeripheralMode == FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_SLAVE) || (hfmpsmbus->Init.PeripheralMode == FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_SLAVE_ARP))) + { + hfmpsmbus->Instance->CR1 |= FMPI2C_CR1_SBC; + } + + /* Enable the selected FMPSMBUS peripheral */ + __HAL_FMPSMBUS_ENABLE(hfmpsmbus); + + hfmpsmbus->ErrorCode = HAL_FMPSMBUS_ERROR_NONE; + hfmpsmbus->PreviousState = HAL_FMPSMBUS_STATE_READY; + hfmpsmbus->State = HAL_FMPSMBUS_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitialize the FMPSMBUS peripheral. + * @param hfmpsmbus Pointer to a FMPSMBUS_HandleTypeDef structure that contains + * the configuration information for the specified FMPSMBUS. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FMPSMBUS_DeInit(FMPSMBUS_HandleTypeDef *hfmpsmbus) +{ + /* Check the FMPSMBUS handle allocation */ + if (hfmpsmbus == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_FMPSMBUS_ALL_INSTANCE(hfmpsmbus->Instance)); + + hfmpsmbus->State = HAL_FMPSMBUS_STATE_BUSY; + + /* Disable the FMPSMBUS Peripheral Clock */ + __HAL_FMPSMBUS_DISABLE(hfmpsmbus); + +#if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1) + if (hfmpsmbus->MspDeInitCallback == NULL) + { + hfmpsmbus->MspDeInitCallback = HAL_FMPSMBUS_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + hfmpsmbus->MspDeInitCallback(hfmpsmbus); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_FMPSMBUS_MspDeInit(hfmpsmbus); +#endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */ + + hfmpsmbus->ErrorCode = HAL_FMPSMBUS_ERROR_NONE; + hfmpsmbus->PreviousState = HAL_FMPSMBUS_STATE_RESET; + hfmpsmbus->State = HAL_FMPSMBUS_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hfmpsmbus); + + return HAL_OK; +} + +/** + * @brief Initialize the FMPSMBUS MSP. + * @param hfmpsmbus Pointer to a FMPSMBUS_HandleTypeDef structure that contains + * the configuration information for the specified FMPSMBUS. + * @retval None + */ +__weak void HAL_FMPSMBUS_MspInit(FMPSMBUS_HandleTypeDef *hfmpsmbus) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfmpsmbus); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_FMPSMBUS_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitialize the FMPSMBUS MSP. + * @param hfmpsmbus Pointer to a FMPSMBUS_HandleTypeDef structure that contains + * the configuration information for the specified FMPSMBUS. + * @retval None + */ +__weak void HAL_FMPSMBUS_MspDeInit(FMPSMBUS_HandleTypeDef *hfmpsmbus) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfmpsmbus); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_FMPSMBUS_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Configure Analog noise filter. + * @param hfmpsmbus Pointer to a FMPSMBUS_HandleTypeDef structure that contains + * the configuration information for the specified FMPSMBUS. + * @param AnalogFilter This parameter can be one of the following values: + * @arg @ref FMPSMBUS_ANALOGFILTER_ENABLE + * @arg @ref FMPSMBUS_ANALOGFILTER_DISABLE + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FMPSMBUS_ConfigAnalogFilter(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t AnalogFilter) +{ + /* Check the parameters */ + assert_param(IS_FMPSMBUS_ALL_INSTANCE(hfmpsmbus->Instance)); + assert_param(IS_FMPSMBUS_ANALOG_FILTER(AnalogFilter)); + + if (hfmpsmbus->State == HAL_FMPSMBUS_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hfmpsmbus); + + hfmpsmbus->State = HAL_FMPSMBUS_STATE_BUSY; + + /* Disable the selected FMPSMBUS peripheral */ + __HAL_FMPSMBUS_DISABLE(hfmpsmbus); + + /* Reset ANOFF bit */ + hfmpsmbus->Instance->CR1 &= ~(FMPI2C_CR1_ANFOFF); + + /* Set analog filter bit*/ + hfmpsmbus->Instance->CR1 |= AnalogFilter; + + __HAL_FMPSMBUS_ENABLE(hfmpsmbus); + + hfmpsmbus->State = HAL_FMPSMBUS_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hfmpsmbus); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Configure Digital noise filter. + * @param hfmpsmbus Pointer to a FMPSMBUS_HandleTypeDef structure that contains + * the configuration information for the specified FMPSMBUS. + * @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FMPSMBUS_ConfigDigitalFilter(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t DigitalFilter) +{ + uint32_t tmpreg; + + /* Check the parameters */ + assert_param(IS_FMPSMBUS_ALL_INSTANCE(hfmpsmbus->Instance)); + assert_param(IS_FMPSMBUS_DIGITAL_FILTER(DigitalFilter)); + + if (hfmpsmbus->State == HAL_FMPSMBUS_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hfmpsmbus); + + hfmpsmbus->State = HAL_FMPSMBUS_STATE_BUSY; + + /* Disable the selected FMPSMBUS peripheral */ + __HAL_FMPSMBUS_DISABLE(hfmpsmbus); + + /* Get the old register value */ + tmpreg = hfmpsmbus->Instance->CR1; + + /* Reset FMPI2C DNF bits [11:8] */ + tmpreg &= ~(FMPI2C_CR1_DNF); + + /* Set FMPI2Cx DNF coefficient */ + tmpreg |= DigitalFilter << FMPI2C_CR1_DNF_Pos; + + /* Store the new register value */ + hfmpsmbus->Instance->CR1 = tmpreg; + + __HAL_FMPSMBUS_ENABLE(hfmpsmbus); + + hfmpsmbus->State = HAL_FMPSMBUS_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hfmpsmbus); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +#if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User FMPSMBUS Callback + * To be used instead of the weak predefined callback + * @param hfmpsmbus Pointer to a FMPSMBUS_HandleTypeDef structure that contains + * the configuration information for the specified FMPSMBUS. + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_FMPSMBUS_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID + * @arg @ref HAL_FMPSMBUS_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID + * @arg @ref HAL_FMPSMBUS_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID + * @arg @ref HAL_FMPSMBUS_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID + * @arg @ref HAL_FMPSMBUS_LISTEN_COMPLETE_CB_ID Listen Complete callback ID + * @arg @ref HAL_FMPSMBUS_ERROR_CB_ID Error callback ID + * @arg @ref HAL_FMPSMBUS_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_FMPSMBUS_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FMPSMBUS_RegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, HAL_FMPSMBUS_CallbackIDTypeDef CallbackID, pFMPSMBUS_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hfmpsmbus->ErrorCode |= HAL_FMPSMBUS_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hfmpsmbus); + + if (HAL_FMPSMBUS_STATE_READY == hfmpsmbus->State) + { + switch (CallbackID) + { + case HAL_FMPSMBUS_MASTER_TX_COMPLETE_CB_ID : + hfmpsmbus->MasterTxCpltCallback = pCallback; + break; + + case HAL_FMPSMBUS_MASTER_RX_COMPLETE_CB_ID : + hfmpsmbus->MasterRxCpltCallback = pCallback; + break; + + case HAL_FMPSMBUS_SLAVE_TX_COMPLETE_CB_ID : + hfmpsmbus->SlaveTxCpltCallback = pCallback; + break; + + case HAL_FMPSMBUS_SLAVE_RX_COMPLETE_CB_ID : + hfmpsmbus->SlaveRxCpltCallback = pCallback; + break; + + case HAL_FMPSMBUS_LISTEN_COMPLETE_CB_ID : + hfmpsmbus->ListenCpltCallback = pCallback; + break; + + case HAL_FMPSMBUS_ERROR_CB_ID : + hfmpsmbus->ErrorCallback = pCallback; + break; + + case HAL_FMPSMBUS_MSPINIT_CB_ID : + hfmpsmbus->MspInitCallback = pCallback; + break; + + case HAL_FMPSMBUS_MSPDEINIT_CB_ID : + hfmpsmbus->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hfmpsmbus->ErrorCode |= HAL_FMPSMBUS_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_FMPSMBUS_STATE_RESET == hfmpsmbus->State) + { + switch (CallbackID) + { + case HAL_FMPSMBUS_MSPINIT_CB_ID : + hfmpsmbus->MspInitCallback = pCallback; + break; + + case HAL_FMPSMBUS_MSPDEINIT_CB_ID : + hfmpsmbus->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hfmpsmbus->ErrorCode |= HAL_FMPSMBUS_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hfmpsmbus->ErrorCode |= HAL_FMPSMBUS_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hfmpsmbus); + return status; +} + +/** + * @brief Unregister an FMPSMBUS Callback + * FMPSMBUS callback is redirected to the weak predefined callback + * @param hfmpsmbus Pointer to a FMPSMBUS_HandleTypeDef structure that contains + * the configuration information for the specified FMPSMBUS. + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * This parameter can be one of the following values: + * @arg @ref HAL_FMPSMBUS_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID + * @arg @ref HAL_FMPSMBUS_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID + * @arg @ref HAL_FMPSMBUS_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID + * @arg @ref HAL_FMPSMBUS_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID + * @arg @ref HAL_FMPSMBUS_LISTEN_COMPLETE_CB_ID Listen Complete callback ID + * @arg @ref HAL_FMPSMBUS_ERROR_CB_ID Error callback ID + * @arg @ref HAL_FMPSMBUS_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_FMPSMBUS_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FMPSMBUS_UnRegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, HAL_FMPSMBUS_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hfmpsmbus); + + if (HAL_FMPSMBUS_STATE_READY == hfmpsmbus->State) + { + switch (CallbackID) + { + case HAL_FMPSMBUS_MASTER_TX_COMPLETE_CB_ID : + hfmpsmbus->MasterTxCpltCallback = HAL_FMPSMBUS_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */ + break; + + case HAL_FMPSMBUS_MASTER_RX_COMPLETE_CB_ID : + hfmpsmbus->MasterRxCpltCallback = HAL_FMPSMBUS_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */ + break; + + case HAL_FMPSMBUS_SLAVE_TX_COMPLETE_CB_ID : + hfmpsmbus->SlaveTxCpltCallback = HAL_FMPSMBUS_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */ + break; + + case HAL_FMPSMBUS_SLAVE_RX_COMPLETE_CB_ID : + hfmpsmbus->SlaveRxCpltCallback = HAL_FMPSMBUS_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */ + break; + + case HAL_FMPSMBUS_LISTEN_COMPLETE_CB_ID : + hfmpsmbus->ListenCpltCallback = HAL_FMPSMBUS_ListenCpltCallback; /* Legacy weak ListenCpltCallback */ + break; + + case HAL_FMPSMBUS_ERROR_CB_ID : + hfmpsmbus->ErrorCallback = HAL_FMPSMBUS_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_FMPSMBUS_MSPINIT_CB_ID : + hfmpsmbus->MspInitCallback = HAL_FMPSMBUS_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_FMPSMBUS_MSPDEINIT_CB_ID : + hfmpsmbus->MspDeInitCallback = HAL_FMPSMBUS_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hfmpsmbus->ErrorCode |= HAL_FMPSMBUS_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_FMPSMBUS_STATE_RESET == hfmpsmbus->State) + { + switch (CallbackID) + { + case HAL_FMPSMBUS_MSPINIT_CB_ID : + hfmpsmbus->MspInitCallback = HAL_FMPSMBUS_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_FMPSMBUS_MSPDEINIT_CB_ID : + hfmpsmbus->MspDeInitCallback = HAL_FMPSMBUS_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hfmpsmbus->ErrorCode |= HAL_FMPSMBUS_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hfmpsmbus->ErrorCode |= HAL_FMPSMBUS_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hfmpsmbus); + return status; +} + +/** + * @brief Register the Slave Address Match FMPSMBUS Callback + * To be used instead of the weak HAL_FMPSMBUS_AddrCallback() predefined callback + * @param hfmpsmbus Pointer to a FMPSMBUS_HandleTypeDef structure that contains + * the configuration information for the specified FMPSMBUS. + * @param pCallback pointer to the Address Match Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FMPSMBUS_RegisterAddrCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, pFMPSMBUS_AddrCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hfmpsmbus->ErrorCode |= HAL_FMPSMBUS_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hfmpsmbus); + + if (HAL_FMPSMBUS_STATE_READY == hfmpsmbus->State) + { + hfmpsmbus->AddrCallback = pCallback; + } + else + { + /* Update the error code */ + hfmpsmbus->ErrorCode |= HAL_FMPSMBUS_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hfmpsmbus); + return status; +} + +/** + * @brief UnRegister the Slave Address Match FMPSMBUS Callback + * Info Ready FMPSMBUS Callback is redirected to the weak HAL_FMPSMBUS_AddrCallback() predefined callback + * @param hfmpsmbus Pointer to a FMPSMBUS_HandleTypeDef structure that contains + * the configuration information for the specified FMPSMBUS. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FMPSMBUS_UnRegisterAddrCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hfmpsmbus); + + if (HAL_FMPSMBUS_STATE_READY == hfmpsmbus->State) + { + hfmpsmbus->AddrCallback = HAL_FMPSMBUS_AddrCallback; /* Legacy weak AddrCallback */ + } + else + { + /* Update the error code */ + hfmpsmbus->ErrorCode |= HAL_FMPSMBUS_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hfmpsmbus); + return status; +} + +#endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup FMPSMBUS_Exported_Functions_Group2 Input and Output operation functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the FMPSMBUS data + transfers. + + (#) Blocking mode function to check if device is ready for usage is : + (++) HAL_FMPSMBUS_IsDeviceReady() + + (#) There is only one mode of transfer: + (++) Non-Blocking mode : The communication is performed using Interrupts. + These functions return the status of the transfer startup. + The end of the data processing will be indicated through the + dedicated FMPSMBUS IRQ when using Interrupt mode. + + (#) Non-Blocking mode functions with Interrupt are : + (++) HAL_FMPSMBUS_Master_Transmit_IT() + (++) HAL_FMPSMBUS_Master_Receive_IT() + (++) HAL_FMPSMBUS_Slave_Transmit_IT() + (++) HAL_FMPSMBUS_Slave_Receive_IT() + (++) HAL_FMPSMBUS_EnableListen_IT() or alias HAL_FMPSMBUS_EnableListen_IT() + (++) HAL_FMPSMBUS_DisableListen_IT() + (++) HAL_FMPSMBUS_EnableAlert_IT() + (++) HAL_FMPSMBUS_DisableAlert_IT() + + (#) A set of Transfer Complete Callbacks are provided in non-Blocking mode: + (++) HAL_FMPSMBUS_MasterTxCpltCallback() + (++) HAL_FMPSMBUS_MasterRxCpltCallback() + (++) HAL_FMPSMBUS_SlaveTxCpltCallback() + (++) HAL_FMPSMBUS_SlaveRxCpltCallback() + (++) HAL_FMPSMBUS_AddrCallback() + (++) HAL_FMPSMBUS_ListenCpltCallback() + (++) HAL_FMPSMBUS_ErrorCallback() + +@endverbatim + * @{ + */ + +/** + * @brief Transmit in master/host FMPSMBUS mode an amount of data in non-blocking mode with Interrupt. + * @param hfmpsmbus Pointer to a FMPSMBUS_HandleTypeDef structure that contains + * the configuration information for the specified FMPSMBUS. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref FMPSMBUS_XferOptions_definition + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FMPSMBUS_Master_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + uint32_t tmp; + + /* Check the parameters */ + assert_param(IS_FMPSMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (hfmpsmbus->State == HAL_FMPSMBUS_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hfmpsmbus); + + hfmpsmbus->State = HAL_FMPSMBUS_STATE_MASTER_BUSY_TX; + hfmpsmbus->ErrorCode = HAL_FMPSMBUS_ERROR_NONE; + /* Prepare transfer parameters */ + hfmpsmbus->pBuffPtr = pData; + hfmpsmbus->XferCount = Size; + hfmpsmbus->XferOptions = XferOptions; + + /* In case of Quick command, remove autoend mode */ + /* Manage the stop generation by software */ + if (hfmpsmbus->pBuffPtr == NULL) + { + hfmpsmbus->XferOptions &= ~FMPSMBUS_AUTOEND_MODE; + } + + if (Size > MAX_NBYTE_SIZE) + { + hfmpsmbus->XferSize = MAX_NBYTE_SIZE; + } + else + { + hfmpsmbus->XferSize = Size; + } + + /* Send Slave Address */ + /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */ + if ((hfmpsmbus->XferSize < hfmpsmbus->XferCount) && (hfmpsmbus->XferSize == MAX_NBYTE_SIZE)) + { + FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, (uint8_t)hfmpsmbus->XferSize, FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE), FMPSMBUS_GENERATE_START_WRITE); + } + else + { + /* If transfer direction not change, do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + + /* Store current volatile XferOptions, misra rule */ + tmp = hfmpsmbus->XferOptions; + + if ((hfmpsmbus->PreviousState == HAL_FMPSMBUS_STATE_MASTER_BUSY_TX) && (IS_FMPSMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0)) + { + FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, (uint8_t)hfmpsmbus->XferSize, hfmpsmbus->XferOptions, FMPSMBUS_NO_STARTSTOP); + } + /* Else transfer direction change, so generate Restart with new transfer direction */ + else + { + /* Convert OTHER_xxx XferOptions if any */ + FMPSMBUS_ConvertOtherXferOptions(hfmpsmbus); + + /* Handle Transfer */ + FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, (uint8_t)hfmpsmbus->XferSize, hfmpsmbus->XferOptions, FMPSMBUS_GENERATE_START_WRITE); + } + + /* If PEC mode is enable, size to transmit manage by SW part should be Size-1 byte, corresponding to PEC byte */ + /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ + if (FMPSMBUS_GET_PEC_MODE(hfmpsmbus) != 0UL) + { + hfmpsmbus->XferSize--; + hfmpsmbus->XferCount--; + } + } + + /* Process Unlocked */ + __HAL_UNLOCK(hfmpsmbus); + + /* Note : The FMPSMBUS interrupts must be enabled after unlocking current process + to avoid the risk of FMPSMBUS interrupt handle execution before current + process unlock */ + FMPSMBUS_Enable_IRQ(hfmpsmbus, FMPSMBUS_IT_TX); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in master/host FMPSMBUS mode an amount of data in non-blocking mode with Interrupt. + * @param hfmpsmbus Pointer to a FMPSMBUS_HandleTypeDef structure that contains + * the configuration information for the specified FMPSMBUS. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref FMPSMBUS_XferOptions_definition + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FMPSMBUS_Master_Receive_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + uint32_t tmp; + + /* Check the parameters */ + assert_param(IS_FMPSMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (hfmpsmbus->State == HAL_FMPSMBUS_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hfmpsmbus); + + hfmpsmbus->State = HAL_FMPSMBUS_STATE_MASTER_BUSY_RX; + hfmpsmbus->ErrorCode = HAL_FMPSMBUS_ERROR_NONE; + + /* Prepare transfer parameters */ + hfmpsmbus->pBuffPtr = pData; + hfmpsmbus->XferCount = Size; + hfmpsmbus->XferOptions = XferOptions; + + /* In case of Quick command, remove autoend mode */ + /* Manage the stop generation by software */ + if (hfmpsmbus->pBuffPtr == NULL) + { + hfmpsmbus->XferOptions &= ~FMPSMBUS_AUTOEND_MODE; + } + + if (Size > MAX_NBYTE_SIZE) + { + hfmpsmbus->XferSize = MAX_NBYTE_SIZE; + } + else + { + hfmpsmbus->XferSize = Size; + } + + /* Send Slave Address */ + /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */ + if ((hfmpsmbus->XferSize < hfmpsmbus->XferCount) && (hfmpsmbus->XferSize == MAX_NBYTE_SIZE)) + { + FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, (uint8_t)hfmpsmbus->XferSize, FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE), FMPSMBUS_GENERATE_START_READ); + } + else + { + /* If transfer direction not change, do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + + /* Store current volatile XferOptions, Misra rule */ + tmp = hfmpsmbus->XferOptions; + + if ((hfmpsmbus->PreviousState == HAL_FMPSMBUS_STATE_MASTER_BUSY_RX) && (IS_FMPSMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0)) + { + FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, (uint8_t)hfmpsmbus->XferSize, hfmpsmbus->XferOptions, FMPSMBUS_NO_STARTSTOP); + } + /* Else transfer direction change, so generate Restart with new transfer direction */ + else + { + /* Convert OTHER_xxx XferOptions if any */ + FMPSMBUS_ConvertOtherXferOptions(hfmpsmbus); + + /* Handle Transfer */ + FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, (uint8_t)hfmpsmbus->XferSize, hfmpsmbus->XferOptions, FMPSMBUS_GENERATE_START_READ); + } + } + + /* Process Unlocked */ + __HAL_UNLOCK(hfmpsmbus); + + /* Note : The FMPSMBUS interrupts must be enabled after unlocking current process + to avoid the risk of FMPSMBUS interrupt handle execution before current + process unlock */ + FMPSMBUS_Enable_IRQ(hfmpsmbus, FMPSMBUS_IT_RX); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Abort a master/host FMPSMBUS process communication with Interrupt. + * @note This abort can be called only if state is ready + * @param hfmpsmbus Pointer to a FMPSMBUS_HandleTypeDef structure that contains + * the configuration information for the specified FMPSMBUS. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FMPSMBUS_Master_Abort_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress) +{ + if (hfmpsmbus->State == HAL_FMPSMBUS_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hfmpsmbus); + + /* Keep the same state as previous */ + /* to perform as well the call of the corresponding end of transfer callback */ + if (hfmpsmbus->PreviousState == HAL_FMPSMBUS_STATE_MASTER_BUSY_TX) + { + hfmpsmbus->State = HAL_FMPSMBUS_STATE_MASTER_BUSY_TX; + } + else if (hfmpsmbus->PreviousState == HAL_FMPSMBUS_STATE_MASTER_BUSY_RX) + { + hfmpsmbus->State = HAL_FMPSMBUS_STATE_MASTER_BUSY_RX; + } + else + { + /* Wrong usage of abort function */ + /* This function should be used only in case of abort monitored by master device */ + return HAL_ERROR; + } + hfmpsmbus->ErrorCode = HAL_FMPSMBUS_ERROR_NONE; + + /* Set NBYTES to 1 to generate a dummy read on FMPSMBUS peripheral */ + /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */ + FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, 1, FMPSMBUS_AUTOEND_MODE, FMPSMBUS_NO_STARTSTOP); + + /* Process Unlocked */ + __HAL_UNLOCK(hfmpsmbus); + + /* Note : The FMPSMBUS interrupts must be enabled after unlocking current process + to avoid the risk of FMPSMBUS interrupt handle execution before current + process unlock */ + if (hfmpsmbus->State == HAL_FMPSMBUS_STATE_MASTER_BUSY_TX) + { + FMPSMBUS_Enable_IRQ(hfmpsmbus, FMPSMBUS_IT_TX); + } + else if (hfmpsmbus->State == HAL_FMPSMBUS_STATE_MASTER_BUSY_RX) + { + FMPSMBUS_Enable_IRQ(hfmpsmbus, FMPSMBUS_IT_RX); + } + else + { + /* Nothing to do */ + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in slave/device FMPSMBUS mode an amount of data in non-blocking mode with Interrupt. + * @param hfmpsmbus Pointer to a FMPSMBUS_HandleTypeDef structure that contains + * the configuration information for the specified FMPSMBUS. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref FMPSMBUS_XferOptions_definition + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FMPSMBUS_Slave_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + /* Check the parameters */ + assert_param(IS_FMPSMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if ((hfmpsmbus->State & HAL_FMPSMBUS_STATE_LISTEN) == HAL_FMPSMBUS_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0UL)) + { + hfmpsmbus->ErrorCode = HAL_FMPSMBUS_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + FMPSMBUS_Disable_IRQ(hfmpsmbus, FMPSMBUS_IT_ADDR | FMPSMBUS_IT_TX); + + /* Process Locked */ + __HAL_LOCK(hfmpsmbus); + + hfmpsmbus->State = (HAL_FMPSMBUS_STATE_SLAVE_BUSY_TX | HAL_FMPSMBUS_STATE_LISTEN); + hfmpsmbus->ErrorCode = HAL_FMPSMBUS_ERROR_NONE; + + /* Set SBC bit to manage Acknowledge at each bit */ + hfmpsmbus->Instance->CR1 |= FMPI2C_CR1_SBC; + + /* Enable Address Acknowledge */ + hfmpsmbus->Instance->CR2 &= ~FMPI2C_CR2_NACK; + + /* Prepare transfer parameters */ + hfmpsmbus->pBuffPtr = pData; + hfmpsmbus->XferCount = Size; + hfmpsmbus->XferOptions = XferOptions; + + /* Convert OTHER_xxx XferOptions if any */ + FMPSMBUS_ConvertOtherXferOptions(hfmpsmbus); + + if (Size > MAX_NBYTE_SIZE) + { + hfmpsmbus->XferSize = MAX_NBYTE_SIZE; + } + else + { + hfmpsmbus->XferSize = Size; + } + + /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */ + if ((hfmpsmbus->XferSize < hfmpsmbus->XferCount) && (hfmpsmbus->XferSize == MAX_NBYTE_SIZE)) + { + FMPSMBUS_TransferConfig(hfmpsmbus, 0, (uint8_t)hfmpsmbus->XferSize, FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE), FMPSMBUS_NO_STARTSTOP); + } + else + { + /* Set NBYTE to transmit */ + FMPSMBUS_TransferConfig(hfmpsmbus, 0, (uint8_t)hfmpsmbus->XferSize, hfmpsmbus->XferOptions, FMPSMBUS_NO_STARTSTOP); + + /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */ + /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ + if (FMPSMBUS_GET_PEC_MODE(hfmpsmbus) != 0UL) + { + hfmpsmbus->XferSize--; + hfmpsmbus->XferCount--; + } + } + + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action will generate an acknowledge to the HOST */ + __HAL_FMPSMBUS_CLEAR_FLAG(hfmpsmbus, FMPSMBUS_FLAG_ADDR); + + /* Process Unlocked */ + __HAL_UNLOCK(hfmpsmbus); + + /* Note : The FMPSMBUS interrupts must be enabled after unlocking current process + to avoid the risk of FMPSMBUS interrupt handle execution before current + process unlock */ + /* REnable ADDR interrupt */ + FMPSMBUS_Enable_IRQ(hfmpsmbus, FMPSMBUS_IT_TX | FMPSMBUS_IT_ADDR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in slave/device FMPSMBUS mode an amount of data in non-blocking mode with Interrupt. + * @param hfmpsmbus Pointer to a FMPSMBUS_HandleTypeDef structure that contains + * the configuration information for the specified FMPSMBUS. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref FMPSMBUS_XferOptions_definition + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FMPSMBUS_Slave_Receive_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + /* Check the parameters */ + assert_param(IS_FMPSMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if ((hfmpsmbus->State & HAL_FMPSMBUS_STATE_LISTEN) == HAL_FMPSMBUS_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0UL)) + { + hfmpsmbus->ErrorCode = HAL_FMPSMBUS_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + FMPSMBUS_Disable_IRQ(hfmpsmbus, FMPSMBUS_IT_ADDR | FMPSMBUS_IT_RX); + + /* Process Locked */ + __HAL_LOCK(hfmpsmbus); + + hfmpsmbus->State = (HAL_FMPSMBUS_STATE_SLAVE_BUSY_RX | HAL_FMPSMBUS_STATE_LISTEN); + hfmpsmbus->ErrorCode = HAL_FMPSMBUS_ERROR_NONE; + + /* Set SBC bit to manage Acknowledge at each bit */ + hfmpsmbus->Instance->CR1 |= FMPI2C_CR1_SBC; + + /* Enable Address Acknowledge */ + hfmpsmbus->Instance->CR2 &= ~FMPI2C_CR2_NACK; + + /* Prepare transfer parameters */ + hfmpsmbus->pBuffPtr = pData; + hfmpsmbus->XferSize = Size; + hfmpsmbus->XferCount = Size; + hfmpsmbus->XferOptions = XferOptions; + + /* Convert OTHER_xxx XferOptions if any */ + FMPSMBUS_ConvertOtherXferOptions(hfmpsmbus); + + /* Set NBYTE to receive */ + /* If XferSize equal "1", or XferSize equal "2" with PEC requested (mean 1 data byte + 1 PEC byte */ + /* no need to set RELOAD bit mode, a ACK will be automatically generated in that case */ + /* else need to set RELOAD bit mode to generate an automatic ACK at each byte Received */ + /* This RELOAD bit will be reset for last BYTE to be receive in FMPSMBUS_Slave_ISR */ + if (((FMPSMBUS_GET_PEC_MODE(hfmpsmbus) != 0UL) && (hfmpsmbus->XferSize == 2U)) || (hfmpsmbus->XferSize == 1U)) + { + FMPSMBUS_TransferConfig(hfmpsmbus, 0, (uint8_t)hfmpsmbus->XferSize, hfmpsmbus->XferOptions, FMPSMBUS_NO_STARTSTOP); + } + else + { + FMPSMBUS_TransferConfig(hfmpsmbus, 0, 1, hfmpsmbus->XferOptions | FMPSMBUS_RELOAD_MODE, FMPSMBUS_NO_STARTSTOP); + } + + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action will generate an acknowledge to the HOST */ + __HAL_FMPSMBUS_CLEAR_FLAG(hfmpsmbus, FMPSMBUS_FLAG_ADDR); + + /* Process Unlocked */ + __HAL_UNLOCK(hfmpsmbus); + + /* Note : The FMPSMBUS interrupts must be enabled after unlocking current process + to avoid the risk of FMPSMBUS interrupt handle execution before current + process unlock */ + /* REnable ADDR interrupt */ + FMPSMBUS_Enable_IRQ(hfmpsmbus, FMPSMBUS_IT_RX | FMPSMBUS_IT_ADDR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Enable the Address listen mode with Interrupt. + * @param hfmpsmbus Pointer to a FMPSMBUS_HandleTypeDef structure that contains + * the configuration information for the specified FMPSMBUS. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FMPSMBUS_EnableListen_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus) +{ + hfmpsmbus->State = HAL_FMPSMBUS_STATE_LISTEN; + + /* Enable the Address Match interrupt */ + FMPSMBUS_Enable_IRQ(hfmpsmbus, FMPSMBUS_IT_ADDR); + + return HAL_OK; +} + +/** + * @brief Disable the Address listen mode with Interrupt. + * @param hfmpsmbus Pointer to a FMPSMBUS_HandleTypeDef structure that contains + * the configuration information for the specified FMPSMBUS. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FMPSMBUS_DisableListen_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus) +{ + /* Disable Address listen mode only if a transfer is not ongoing */ + if (hfmpsmbus->State == HAL_FMPSMBUS_STATE_LISTEN) + { + hfmpsmbus->State = HAL_FMPSMBUS_STATE_READY; + + /* Disable the Address Match interrupt */ + FMPSMBUS_Disable_IRQ(hfmpsmbus, FMPSMBUS_IT_ADDR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Enable the FMPSMBUS alert mode with Interrupt. + * @param hfmpsmbus Pointer to a FMPSMBUS_HandleTypeDef structure that contains + * the configuration information for the specified FMPSMBUSx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FMPSMBUS_EnableAlert_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus) +{ + /* Enable SMBus alert */ + hfmpsmbus->Instance->CR1 |= FMPI2C_CR1_ALERTEN; + + /* Clear ALERT flag */ + __HAL_FMPSMBUS_CLEAR_FLAG(hfmpsmbus, FMPSMBUS_FLAG_ALERT); + + /* Enable Alert Interrupt */ + FMPSMBUS_Enable_IRQ(hfmpsmbus, FMPSMBUS_IT_ALERT); + + return HAL_OK; +} +/** + * @brief Disable the FMPSMBUS alert mode with Interrupt. + * @param hfmpsmbus Pointer to a FMPSMBUS_HandleTypeDef structure that contains + * the configuration information for the specified FMPSMBUSx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FMPSMBUS_DisableAlert_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus) +{ + /* Enable SMBus alert */ + hfmpsmbus->Instance->CR1 &= ~FMPI2C_CR1_ALERTEN; + + /* Disable Alert Interrupt */ + FMPSMBUS_Disable_IRQ(hfmpsmbus, FMPSMBUS_IT_ALERT); + + return HAL_OK; +} + +/** + * @brief Check if target device is ready for communication. + * @param hfmpsmbus Pointer to a FMPSMBUS_HandleTypeDef structure that contains + * the configuration information for the specified FMPSMBUS. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param Trials Number of trials + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FMPSMBUS_IsDeviceReady(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout) +{ + uint32_t tickstart; + + __IO uint32_t FMPSMBUS_Trials = 0UL; + + FlagStatus tmp1; + FlagStatus tmp2; + + if (hfmpsmbus->State == HAL_FMPSMBUS_STATE_READY) + { + if (__HAL_FMPSMBUS_GET_FLAG(hfmpsmbus, FMPSMBUS_FLAG_BUSY) != RESET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hfmpsmbus); + + hfmpsmbus->State = HAL_FMPSMBUS_STATE_BUSY; + hfmpsmbus->ErrorCode = HAL_FMPSMBUS_ERROR_NONE; + + do + { + /* Generate Start */ + hfmpsmbus->Instance->CR2 = FMPSMBUS_GENERATE_START(hfmpsmbus->Init.AddressingMode, DevAddress); + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is set or a NACK flag is set*/ + tickstart = HAL_GetTick(); + + tmp1 = __HAL_FMPSMBUS_GET_FLAG(hfmpsmbus, FMPSMBUS_FLAG_STOPF); + tmp2 = __HAL_FMPSMBUS_GET_FLAG(hfmpsmbus, FMPSMBUS_FLAG_AF); + + while ((tmp1 == RESET) && (tmp2 == RESET)) + { + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) + { + /* Device is ready */ + hfmpsmbus->State = HAL_FMPSMBUS_STATE_READY; + + /* Update FMPSMBUS error code */ + hfmpsmbus->ErrorCode |= HAL_FMPSMBUS_ERROR_HALTIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hfmpsmbus); + return HAL_ERROR; + } + } + + tmp1 = __HAL_FMPSMBUS_GET_FLAG(hfmpsmbus, FMPSMBUS_FLAG_STOPF); + tmp2 = __HAL_FMPSMBUS_GET_FLAG(hfmpsmbus, FMPSMBUS_FLAG_AF); + } + + /* Check if the NACKF flag has not been set */ + if (__HAL_FMPSMBUS_GET_FLAG(hfmpsmbus, FMPSMBUS_FLAG_AF) == RESET) + { + /* Wait until STOPF flag is reset */ + if (FMPSMBUS_WaitOnFlagUntilTimeout(hfmpsmbus, FMPSMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear STOP Flag */ + __HAL_FMPSMBUS_CLEAR_FLAG(hfmpsmbus, FMPSMBUS_FLAG_STOPF); + + /* Device is ready */ + hfmpsmbus->State = HAL_FMPSMBUS_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hfmpsmbus); + + return HAL_OK; + } + else + { + /* Wait until STOPF flag is reset */ + if (FMPSMBUS_WaitOnFlagUntilTimeout(hfmpsmbus, FMPSMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear NACK Flag */ + __HAL_FMPSMBUS_CLEAR_FLAG(hfmpsmbus, FMPSMBUS_FLAG_AF); + + /* Clear STOP Flag, auto generated with autoend*/ + __HAL_FMPSMBUS_CLEAR_FLAG(hfmpsmbus, FMPSMBUS_FLAG_STOPF); + } + + /* Check if the maximum allowed number of trials has been reached */ + if (FMPSMBUS_Trials == Trials) + { + /* Generate Stop */ + hfmpsmbus->Instance->CR2 |= FMPI2C_CR2_STOP; + + /* Wait until STOPF flag is reset */ + if (FMPSMBUS_WaitOnFlagUntilTimeout(hfmpsmbus, FMPSMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear STOP Flag */ + __HAL_FMPSMBUS_CLEAR_FLAG(hfmpsmbus, FMPSMBUS_FLAG_STOPF); + } + + /* Increment Trials */ + FMPSMBUS_Trials++; + } + while (FMPSMBUS_Trials < Trials); + + hfmpsmbus->State = HAL_FMPSMBUS_STATE_READY; + + /* Update FMPSMBUS error code */ + hfmpsmbus->ErrorCode |= HAL_FMPSMBUS_ERROR_HALTIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hfmpsmbus); + + return HAL_ERROR; + } + else + { + return HAL_BUSY; + } +} +/** + * @} + */ + +/** @defgroup FMPSMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks + * @{ + */ + +/** + * @brief Handle FMPSMBUS event interrupt request. + * @param hfmpsmbus Pointer to a FMPSMBUS_HandleTypeDef structure that contains + * the configuration information for the specified FMPSMBUS. + * @retval None + */ +void HAL_FMPSMBUS_EV_IRQHandler(FMPSMBUS_HandleTypeDef *hfmpsmbus) +{ + /* Use a local variable to store the current ISR flags */ + /* This action will avoid a wrong treatment due to ISR flags change during interrupt handler */ + uint32_t tmpisrvalue = READ_REG(hfmpsmbus->Instance->ISR); + uint32_t tmpcr1value = READ_REG(hfmpsmbus->Instance->CR1); + + /* FMPSMBUS in mode Transmitter ---------------------------------------------------*/ + if ((FMPSMBUS_CHECK_IT_SOURCE(tmpcr1value, (FMPSMBUS_IT_TCI | FMPSMBUS_IT_STOPI | FMPSMBUS_IT_NACKI | FMPSMBUS_IT_TXI)) != RESET) && ((FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_TXIS) != RESET) || (FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_TCR) != RESET) || (FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_TC) != RESET) || (FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_STOPF) != RESET) || (FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_AF) != RESET))) + { + /* Slave mode selected */ + if ((hfmpsmbus->State & HAL_FMPSMBUS_STATE_SLAVE_BUSY_TX) == HAL_FMPSMBUS_STATE_SLAVE_BUSY_TX) + { + (void)FMPSMBUS_Slave_ISR(hfmpsmbus, tmpisrvalue); + } + /* Master mode selected */ + else if ((hfmpsmbus->State & HAL_FMPSMBUS_STATE_MASTER_BUSY_TX) == HAL_FMPSMBUS_STATE_MASTER_BUSY_TX) + { + (void)FMPSMBUS_Master_ISR(hfmpsmbus, tmpisrvalue); + } + else + { + /* Nothing to do */ + } + } + + /* FMPSMBUS in mode Receiver ----------------------------------------------------*/ + if ((FMPSMBUS_CHECK_IT_SOURCE(tmpcr1value, (FMPSMBUS_IT_TCI | FMPSMBUS_IT_STOPI | FMPSMBUS_IT_NACKI | FMPSMBUS_IT_RXI)) != RESET) && ((FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_RXNE) != RESET) || (FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_TCR) != RESET) || (FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_TC) != RESET) || (FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_STOPF) != RESET) || (FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_AF) != RESET))) + { + /* Slave mode selected */ + if ((hfmpsmbus->State & HAL_FMPSMBUS_STATE_SLAVE_BUSY_RX) == HAL_FMPSMBUS_STATE_SLAVE_BUSY_RX) + { + (void)FMPSMBUS_Slave_ISR(hfmpsmbus, tmpisrvalue); + } + /* Master mode selected */ + else if ((hfmpsmbus->State & HAL_FMPSMBUS_STATE_MASTER_BUSY_RX) == HAL_FMPSMBUS_STATE_MASTER_BUSY_RX) + { + (void)FMPSMBUS_Master_ISR(hfmpsmbus, tmpisrvalue); + } + else + { + /* Nothing to do */ + } + } + + /* FMPSMBUS in mode Listener Only --------------------------------------------------*/ + if (((FMPSMBUS_CHECK_IT_SOURCE(tmpcr1value, FMPSMBUS_IT_ADDRI) != RESET) || (FMPSMBUS_CHECK_IT_SOURCE(tmpcr1value, FMPSMBUS_IT_STOPI) != RESET) || (FMPSMBUS_CHECK_IT_SOURCE(tmpcr1value, FMPSMBUS_IT_NACKI) != RESET)) && ((FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_ADDR) != RESET) || (FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_STOPF) != RESET) || (FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_AF) != RESET))) + { + if ((hfmpsmbus->State & HAL_FMPSMBUS_STATE_LISTEN) == HAL_FMPSMBUS_STATE_LISTEN) + { + (void)FMPSMBUS_Slave_ISR(hfmpsmbus, tmpisrvalue); + } + } +} + +/** + * @brief Handle FMPSMBUS error interrupt request. + * @param hfmpsmbus Pointer to a FMPSMBUS_HandleTypeDef structure that contains + * the configuration information for the specified FMPSMBUS. + * @retval None + */ +void HAL_FMPSMBUS_ER_IRQHandler(FMPSMBUS_HandleTypeDef *hfmpsmbus) +{ + FMPSMBUS_ITErrorHandler(hfmpsmbus); +} + +/** + * @brief Master Tx Transfer completed callback. + * @param hfmpsmbus Pointer to a FMPSMBUS_HandleTypeDef structure that contains + * the configuration information for the specified FMPSMBUS. + * @retval None + */ +__weak void HAL_FMPSMBUS_MasterTxCpltCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfmpsmbus); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_FMPSMBUS_MasterTxCpltCallback() could be implemented in the user file + */ +} + +/** + * @brief Master Rx Transfer completed callback. + * @param hfmpsmbus Pointer to a FMPSMBUS_HandleTypeDef structure that contains + * the configuration information for the specified FMPSMBUS. + * @retval None + */ +__weak void HAL_FMPSMBUS_MasterRxCpltCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfmpsmbus); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_FMPSMBUS_MasterRxCpltCallback() could be implemented in the user file + */ +} + +/** @brief Slave Tx Transfer completed callback. + * @param hfmpsmbus Pointer to a FMPSMBUS_HandleTypeDef structure that contains + * the configuration information for the specified FMPSMBUS. + * @retval None + */ +__weak void HAL_FMPSMBUS_SlaveTxCpltCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfmpsmbus); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_FMPSMBUS_SlaveTxCpltCallback() could be implemented in the user file + */ +} + +/** + * @brief Slave Rx Transfer completed callback. + * @param hfmpsmbus Pointer to a FMPSMBUS_HandleTypeDef structure that contains + * the configuration information for the specified FMPSMBUS. + * @retval None + */ +__weak void HAL_FMPSMBUS_SlaveRxCpltCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfmpsmbus); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_FMPSMBUS_SlaveRxCpltCallback() could be implemented in the user file + */ +} + +/** + * @brief Slave Address Match callback. + * @param hfmpsmbus Pointer to a FMPSMBUS_HandleTypeDef structure that contains + * the configuration information for the specified FMPSMBUS. + * @param TransferDirection Master request Transfer Direction (Write/Read) + * @param AddrMatchCode Address Match Code + * @retval None + */ +__weak void HAL_FMPSMBUS_AddrCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfmpsmbus); + UNUSED(TransferDirection); + UNUSED(AddrMatchCode); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_FMPSMBUS_AddrCallback() could be implemented in the user file + */ +} + +/** + * @brief Listen Complete callback. + * @param hfmpsmbus Pointer to a FMPSMBUS_HandleTypeDef structure that contains + * the configuration information for the specified FMPSMBUS. + * @retval None + */ +__weak void HAL_FMPSMBUS_ListenCpltCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfmpsmbus); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_FMPSMBUS_ListenCpltCallback() could be implemented in the user file + */ +} + +/** + * @brief FMPSMBUS error callback. + * @param hfmpsmbus Pointer to a FMPSMBUS_HandleTypeDef structure that contains + * the configuration information for the specified FMPSMBUS. + * @retval None + */ +__weak void HAL_FMPSMBUS_ErrorCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfmpsmbus); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_FMPSMBUS_ErrorCallback() could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup FMPSMBUS_Exported_Functions_Group3 Peripheral State and Errors functions + * @brief Peripheral State and Errors functions + * +@verbatim + =============================================================================== + ##### Peripheral State and Errors functions ##### + =============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the FMPSMBUS handle state. + * @param hfmpsmbus Pointer to a FMPSMBUS_HandleTypeDef structure that contains + * the configuration information for the specified FMPSMBUS. + * @retval HAL state + */ +uint32_t HAL_FMPSMBUS_GetState(FMPSMBUS_HandleTypeDef *hfmpsmbus) +{ + /* Return FMPSMBUS handle state */ + return hfmpsmbus->State; +} + +/** +* @brief Return the FMPSMBUS error code. + * @param hfmpsmbus Pointer to a FMPSMBUS_HandleTypeDef structure that contains + * the configuration information for the specified FMPSMBUS. +* @retval FMPSMBUS Error Code +*/ +uint32_t HAL_FMPSMBUS_GetError(FMPSMBUS_HandleTypeDef *hfmpsmbus) +{ + return hfmpsmbus->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup FMPSMBUS_Private_Functions FMPSMBUS Private Functions + * @brief Data transfers Private functions + * @{ + */ + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode. + * @param hfmpsmbus Pointer to a FMPSMBUS_HandleTypeDef structure that contains + * the configuration information for the specified FMPSMBUS. + * @param StatusFlags Value of Interrupt Flags. + * @retval HAL status + */ +static HAL_StatusTypeDef FMPSMBUS_Master_ISR(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t StatusFlags) +{ + uint16_t DevAddress; + + /* Process Locked */ + __HAL_LOCK(hfmpsmbus); + + if (FMPSMBUS_CHECK_FLAG(StatusFlags, FMPSMBUS_FLAG_AF) != RESET) + { + /* Clear NACK Flag */ + __HAL_FMPSMBUS_CLEAR_FLAG(hfmpsmbus, FMPSMBUS_FLAG_AF); + + /* Set corresponding Error Code */ + /* No need to generate STOP, it is automatically done */ + hfmpsmbus->ErrorCode |= HAL_FMPSMBUS_ERROR_ACKF; + + /* Process Unlocked */ + __HAL_UNLOCK(hfmpsmbus); + + /* Call the Error callback to inform upper layer */ +#if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1) + hfmpsmbus->ErrorCallback(hfmpsmbus); +#else + HAL_FMPSMBUS_ErrorCallback(hfmpsmbus); +#endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */ + } + else if (FMPSMBUS_CHECK_FLAG(StatusFlags, FMPSMBUS_FLAG_STOPF) != RESET) + { + /* Check and treat errors if errors occurs during STOP process */ + FMPSMBUS_ITErrorHandler(hfmpsmbus); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + if (hfmpsmbus->State == HAL_FMPSMBUS_STATE_MASTER_BUSY_TX) + { + /* Disable Interrupt */ + FMPSMBUS_Disable_IRQ(hfmpsmbus, FMPSMBUS_IT_TX); + + /* Clear STOP Flag */ + __HAL_FMPSMBUS_CLEAR_FLAG(hfmpsmbus, FMPSMBUS_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + FMPSMBUS_RESET_CR2(hfmpsmbus); + + /* Flush remaining data in Fifo register in case of error occurs before TXEmpty */ + /* Disable the selected FMPSMBUS peripheral */ + __HAL_FMPSMBUS_DISABLE(hfmpsmbus); + + hfmpsmbus->PreviousState = HAL_FMPSMBUS_STATE_READY; + hfmpsmbus->State = HAL_FMPSMBUS_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hfmpsmbus); + + /* REenable the selected FMPSMBUS peripheral */ + __HAL_FMPSMBUS_ENABLE(hfmpsmbus); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1) + hfmpsmbus->MasterTxCpltCallback(hfmpsmbus); +#else + HAL_FMPSMBUS_MasterTxCpltCallback(hfmpsmbus); +#endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */ + } + else if (hfmpsmbus->State == HAL_FMPSMBUS_STATE_MASTER_BUSY_RX) + { + /* Store Last receive data if any */ + if (FMPSMBUS_CHECK_FLAG(StatusFlags, FMPSMBUS_FLAG_RXNE) != RESET) + { + /* Read data from RXDR */ + *hfmpsmbus->pBuffPtr = (uint8_t)(hfmpsmbus->Instance->RXDR); + + /* Increment Buffer pointer */ + hfmpsmbus->pBuffPtr++; + + if ((hfmpsmbus->XferSize > 0U)) + { + hfmpsmbus->XferSize--; + hfmpsmbus->XferCount--; + } + } + + /* Disable Interrupt */ + FMPSMBUS_Disable_IRQ(hfmpsmbus, FMPSMBUS_IT_RX); + + /* Clear STOP Flag */ + __HAL_FMPSMBUS_CLEAR_FLAG(hfmpsmbus, FMPSMBUS_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + FMPSMBUS_RESET_CR2(hfmpsmbus); + + hfmpsmbus->PreviousState = HAL_FMPSMBUS_STATE_READY; + hfmpsmbus->State = HAL_FMPSMBUS_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hfmpsmbus); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1) + hfmpsmbus->MasterRxCpltCallback(hfmpsmbus); +#else + HAL_FMPSMBUS_MasterRxCpltCallback(hfmpsmbus); +#endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */ + } + else + { + /* Nothing to do */ + } + } + else if (FMPSMBUS_CHECK_FLAG(StatusFlags, FMPSMBUS_FLAG_RXNE) != RESET) + { + /* Read data from RXDR */ + *hfmpsmbus->pBuffPtr = (uint8_t)(hfmpsmbus->Instance->RXDR); + + /* Increment Buffer pointer */ + hfmpsmbus->pBuffPtr++; + + /* Increment Size counter */ + hfmpsmbus->XferSize--; + hfmpsmbus->XferCount--; + } + else if (FMPSMBUS_CHECK_FLAG(StatusFlags, FMPSMBUS_FLAG_TXIS) != RESET) + { + /* Write data to TXDR */ + hfmpsmbus->Instance->TXDR = *hfmpsmbus->pBuffPtr; + + /* Increment Buffer pointer */ + hfmpsmbus->pBuffPtr++; + + /* Increment Size counter */ + hfmpsmbus->XferSize--; + hfmpsmbus->XferCount--; + } + else if (FMPSMBUS_CHECK_FLAG(StatusFlags, FMPSMBUS_FLAG_TCR) != RESET) + { + if ((hfmpsmbus->XferCount != 0U) && (hfmpsmbus->XferSize == 0U)) + { + DevAddress = (uint16_t)(hfmpsmbus->Instance->CR2 & FMPI2C_CR2_SADD); + + if (hfmpsmbus->XferCount > MAX_NBYTE_SIZE) + { + FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, MAX_NBYTE_SIZE, (FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE)), FMPSMBUS_NO_STARTSTOP); + hfmpsmbus->XferSize = MAX_NBYTE_SIZE; + } + else + { + hfmpsmbus->XferSize = hfmpsmbus->XferCount; + FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, (uint8_t)hfmpsmbus->XferSize, hfmpsmbus->XferOptions, FMPSMBUS_NO_STARTSTOP); + /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */ + /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ + if (FMPSMBUS_GET_PEC_MODE(hfmpsmbus) != 0UL) + { + hfmpsmbus->XferSize--; + hfmpsmbus->XferCount--; + } + } + } + else if ((hfmpsmbus->XferCount == 0U) && (hfmpsmbus->XferSize == 0U)) + { + /* Call TxCpltCallback() if no stop mode is set */ + if (FMPSMBUS_GET_STOP_MODE(hfmpsmbus) != FMPSMBUS_AUTOEND_MODE) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + if (hfmpsmbus->State == HAL_FMPSMBUS_STATE_MASTER_BUSY_TX) + { + /* Disable Interrupt */ + FMPSMBUS_Disable_IRQ(hfmpsmbus, FMPSMBUS_IT_TX); + hfmpsmbus->PreviousState = hfmpsmbus->State; + hfmpsmbus->State = HAL_FMPSMBUS_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hfmpsmbus); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1) + hfmpsmbus->MasterTxCpltCallback(hfmpsmbus); +#else + HAL_FMPSMBUS_MasterTxCpltCallback(hfmpsmbus); +#endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */ + } + else if (hfmpsmbus->State == HAL_FMPSMBUS_STATE_MASTER_BUSY_RX) + { + FMPSMBUS_Disable_IRQ(hfmpsmbus, FMPSMBUS_IT_RX); + hfmpsmbus->PreviousState = hfmpsmbus->State; + hfmpsmbus->State = HAL_FMPSMBUS_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hfmpsmbus); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1) + hfmpsmbus->MasterRxCpltCallback(hfmpsmbus); +#else + HAL_FMPSMBUS_MasterRxCpltCallback(hfmpsmbus); +#endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */ + } + else + { + /* Nothing to do */ + } + } + } + else + { + /* Nothing to do */ + } + } + else if (FMPSMBUS_CHECK_FLAG(StatusFlags, FMPSMBUS_FLAG_TC) != RESET) + { + if (hfmpsmbus->XferCount == 0U) + { + /* Specific use case for Quick command */ + if (hfmpsmbus->pBuffPtr == NULL) + { + /* Generate a Stop command */ + hfmpsmbus->Instance->CR2 |= FMPI2C_CR2_STOP; + } + /* Call TxCpltCallback() if no stop mode is set */ + else if (FMPSMBUS_GET_STOP_MODE(hfmpsmbus) != FMPSMBUS_AUTOEND_MODE) + { + /* No Generate Stop, to permit restart mode */ + /* The stop will be done at the end of transfer, when FMPSMBUS_AUTOEND_MODE enable */ + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + if (hfmpsmbus->State == HAL_FMPSMBUS_STATE_MASTER_BUSY_TX) + { + /* Disable Interrupt */ + FMPSMBUS_Disable_IRQ(hfmpsmbus, FMPSMBUS_IT_TX); + hfmpsmbus->PreviousState = hfmpsmbus->State; + hfmpsmbus->State = HAL_FMPSMBUS_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hfmpsmbus); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1) + hfmpsmbus->MasterTxCpltCallback(hfmpsmbus); +#else + HAL_FMPSMBUS_MasterTxCpltCallback(hfmpsmbus); +#endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */ + } + else if (hfmpsmbus->State == HAL_FMPSMBUS_STATE_MASTER_BUSY_RX) + { + FMPSMBUS_Disable_IRQ(hfmpsmbus, FMPSMBUS_IT_RX); + hfmpsmbus->PreviousState = hfmpsmbus->State; + hfmpsmbus->State = HAL_FMPSMBUS_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hfmpsmbus); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1) + hfmpsmbus->MasterRxCpltCallback(hfmpsmbus); +#else + HAL_FMPSMBUS_MasterRxCpltCallback(hfmpsmbus); +#endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */ + } + else + { + /* Nothing to do */ + } + } + else + { + /* Nothing to do */ + } + } + } + else + { + /* Nothing to do */ + } + + /* Process Unlocked */ + __HAL_UNLOCK(hfmpsmbus); + + return HAL_OK; +} +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode. + * @param hfmpsmbus Pointer to a FMPSMBUS_HandleTypeDef structure that contains + * the configuration information for the specified FMPSMBUS. + * @param StatusFlags Value of Interrupt Flags. + * @retval HAL status + */ +static HAL_StatusTypeDef FMPSMBUS_Slave_ISR(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t StatusFlags) +{ + uint8_t TransferDirection; + uint16_t SlaveAddrCode; + + /* Process Locked */ + __HAL_LOCK(hfmpsmbus); + + if (FMPSMBUS_CHECK_FLAG(StatusFlags, FMPSMBUS_FLAG_AF) != RESET) + { + /* Check that FMPSMBUS transfer finished */ + /* if yes, normal usecase, a NACK is sent by the HOST when Transfer is finished */ + /* Mean XferCount == 0*/ + /* So clear Flag NACKF only */ + if (hfmpsmbus->XferCount == 0U) + { + /* Clear NACK Flag */ + __HAL_FMPSMBUS_CLEAR_FLAG(hfmpsmbus, FMPSMBUS_FLAG_AF); + + /* Process Unlocked */ + __HAL_UNLOCK(hfmpsmbus); + } + else + { + /* if no, error usecase, a Non-Acknowledge of last Data is generated by the HOST*/ + /* Clear NACK Flag */ + __HAL_FMPSMBUS_CLEAR_FLAG(hfmpsmbus, FMPSMBUS_FLAG_AF); + + /* Set HAL State to "Idle" State, mean to LISTEN state */ + /* So reset Slave Busy state */ + hfmpsmbus->PreviousState = hfmpsmbus->State; + hfmpsmbus->State &= ~((uint32_t)HAL_FMPSMBUS_STATE_SLAVE_BUSY_TX); + hfmpsmbus->State &= ~((uint32_t)HAL_FMPSMBUS_STATE_SLAVE_BUSY_RX); + + /* Disable RX/TX Interrupts, keep only ADDR Interrupt */ + FMPSMBUS_Disable_IRQ(hfmpsmbus, FMPSMBUS_IT_RX | FMPSMBUS_IT_TX); + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hfmpsmbus->ErrorCode |= HAL_FMPSMBUS_ERROR_ACKF; + + /* Process Unlocked */ + __HAL_UNLOCK(hfmpsmbus); + + /* Call the Error callback to inform upper layer */ +#if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1) + hfmpsmbus->ErrorCallback(hfmpsmbus); +#else + HAL_FMPSMBUS_ErrorCallback(hfmpsmbus); +#endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */ + } + } + else if (FMPSMBUS_CHECK_FLAG(StatusFlags, FMPSMBUS_FLAG_ADDR) != RESET) + { + TransferDirection = (uint8_t)(FMPSMBUS_GET_DIR(hfmpsmbus)); + SlaveAddrCode = (uint16_t)(FMPSMBUS_GET_ADDR_MATCH(hfmpsmbus)); + + /* Disable ADDR interrupt to prevent multiple ADDRInterrupt*/ + /* Other ADDRInterrupt will be treat in next Listen usecase */ + __HAL_FMPSMBUS_DISABLE_IT(hfmpsmbus, FMPSMBUS_IT_ADDRI); + + /* Process Unlocked */ + __HAL_UNLOCK(hfmpsmbus); + + /* Call Slave Addr callback */ +#if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1) + hfmpsmbus->AddrCallback(hfmpsmbus, TransferDirection, SlaveAddrCode); +#else + HAL_FMPSMBUS_AddrCallback(hfmpsmbus, TransferDirection, SlaveAddrCode); +#endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */ + } + else if ((FMPSMBUS_CHECK_FLAG(StatusFlags, FMPSMBUS_FLAG_RXNE) != RESET) || (FMPSMBUS_CHECK_FLAG(StatusFlags, FMPSMBUS_FLAG_TCR) != RESET)) + { + if ((hfmpsmbus->State & HAL_FMPSMBUS_STATE_SLAVE_BUSY_RX) == HAL_FMPSMBUS_STATE_SLAVE_BUSY_RX) + { + /* Read data from RXDR */ + *hfmpsmbus->pBuffPtr = (uint8_t)(hfmpsmbus->Instance->RXDR); + + /* Increment Buffer pointer */ + hfmpsmbus->pBuffPtr++; + + hfmpsmbus->XferSize--; + hfmpsmbus->XferCount--; + + if (hfmpsmbus->XferCount == 1U) + { + /* Receive last Byte, can be PEC byte in case of PEC BYTE enabled */ + /* or only the last Byte of Transfer */ + /* So reset the RELOAD bit mode */ + hfmpsmbus->XferOptions &= ~FMPSMBUS_RELOAD_MODE; + FMPSMBUS_TransferConfig(hfmpsmbus, 0, 1, hfmpsmbus->XferOptions, FMPSMBUS_NO_STARTSTOP); + } + else if (hfmpsmbus->XferCount == 0U) + { + /* Last Byte is received, disable Interrupt */ + FMPSMBUS_Disable_IRQ(hfmpsmbus, FMPSMBUS_IT_RX); + + /* Remove HAL_FMPSMBUS_STATE_SLAVE_BUSY_RX, keep only HAL_FMPSMBUS_STATE_LISTEN */ + hfmpsmbus->PreviousState = hfmpsmbus->State; + hfmpsmbus->State &= ~((uint32_t)HAL_FMPSMBUS_STATE_SLAVE_BUSY_RX); + + /* Process Unlocked */ + __HAL_UNLOCK(hfmpsmbus); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1) + hfmpsmbus->SlaveRxCpltCallback(hfmpsmbus); +#else + HAL_FMPSMBUS_SlaveRxCpltCallback(hfmpsmbus); +#endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */ + } + else + { + /* Set Reload for next Bytes */ + FMPSMBUS_TransferConfig(hfmpsmbus, 0, 1, FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE), FMPSMBUS_NO_STARTSTOP); + + /* Ack last Byte Read */ + hfmpsmbus->Instance->CR2 &= ~FMPI2C_CR2_NACK; + } + } + else if ((hfmpsmbus->State & HAL_FMPSMBUS_STATE_SLAVE_BUSY_TX) == HAL_FMPSMBUS_STATE_SLAVE_BUSY_TX) + { + if ((hfmpsmbus->XferCount != 0U) && (hfmpsmbus->XferSize == 0U)) + { + if (hfmpsmbus->XferCount > MAX_NBYTE_SIZE) + { + FMPSMBUS_TransferConfig(hfmpsmbus, 0, MAX_NBYTE_SIZE, (FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE)), FMPSMBUS_NO_STARTSTOP); + hfmpsmbus->XferSize = MAX_NBYTE_SIZE; + } + else + { + hfmpsmbus->XferSize = hfmpsmbus->XferCount; + FMPSMBUS_TransferConfig(hfmpsmbus, 0, (uint8_t)hfmpsmbus->XferSize, hfmpsmbus->XferOptions, FMPSMBUS_NO_STARTSTOP); + /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */ + /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ + if (FMPSMBUS_GET_PEC_MODE(hfmpsmbus) != 0UL) + { + hfmpsmbus->XferSize--; + hfmpsmbus->XferCount--; + } + } + } + } + else + { + /* Nothing to do */ + } + } + else if (FMPSMBUS_CHECK_FLAG(StatusFlags, FMPSMBUS_FLAG_TXIS) != RESET) + { + /* Write data to TXDR only if XferCount not reach "0" */ + /* A TXIS flag can be set, during STOP treatment */ + /* Check if all Data have already been sent */ + /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */ + if (hfmpsmbus->XferCount > 0U) + { + /* Write data to TXDR */ + hfmpsmbus->Instance->TXDR = *hfmpsmbus->pBuffPtr; + + /* Increment Buffer pointer */ + hfmpsmbus->pBuffPtr++; + + hfmpsmbus->XferCount--; + hfmpsmbus->XferSize--; + } + + if (hfmpsmbus->XferCount == 0U) + { + /* Last Byte is Transmitted */ + /* Remove HAL_FMPSMBUS_STATE_SLAVE_BUSY_TX, keep only HAL_FMPSMBUS_STATE_LISTEN */ + FMPSMBUS_Disable_IRQ(hfmpsmbus, FMPSMBUS_IT_TX); + hfmpsmbus->PreviousState = hfmpsmbus->State; + hfmpsmbus->State &= ~((uint32_t)HAL_FMPSMBUS_STATE_SLAVE_BUSY_TX); + + /* Process Unlocked */ + __HAL_UNLOCK(hfmpsmbus); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1) + hfmpsmbus->SlaveTxCpltCallback(hfmpsmbus); +#else + HAL_FMPSMBUS_SlaveTxCpltCallback(hfmpsmbus); +#endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */ + } + } + else + { + /* Nothing to do */ + } + + /* Check if STOPF is set */ + if (FMPSMBUS_CHECK_FLAG(StatusFlags, FMPSMBUS_FLAG_STOPF) != RESET) + { + if ((hfmpsmbus->State & HAL_FMPSMBUS_STATE_LISTEN) == HAL_FMPSMBUS_STATE_LISTEN) + { + /* Store Last receive data if any */ + if (__HAL_FMPSMBUS_GET_FLAG(hfmpsmbus, FMPSMBUS_FLAG_RXNE) != RESET) + { + /* Read data from RXDR */ + *hfmpsmbus->pBuffPtr = (uint8_t)(hfmpsmbus->Instance->RXDR); + + /* Increment Buffer pointer */ + hfmpsmbus->pBuffPtr++; + + if ((hfmpsmbus->XferSize > 0U)) + { + hfmpsmbus->XferSize--; + hfmpsmbus->XferCount--; + } + } + + /* Disable RX and TX Interrupts */ + FMPSMBUS_Disable_IRQ(hfmpsmbus, FMPSMBUS_IT_RX | FMPSMBUS_IT_TX); + + /* Disable ADDR Interrupt */ + FMPSMBUS_Disable_IRQ(hfmpsmbus, FMPSMBUS_IT_ADDR); + + /* Disable Address Acknowledge */ + hfmpsmbus->Instance->CR2 |= FMPI2C_CR2_NACK; + + /* Clear Configuration Register 2 */ + FMPSMBUS_RESET_CR2(hfmpsmbus); + + /* Clear STOP Flag */ + __HAL_FMPSMBUS_CLEAR_FLAG(hfmpsmbus, FMPSMBUS_FLAG_STOPF); + + /* Clear ADDR flag */ + __HAL_FMPSMBUS_CLEAR_FLAG(hfmpsmbus, FMPSMBUS_FLAG_ADDR); + + hfmpsmbus->XferOptions = 0; + hfmpsmbus->PreviousState = hfmpsmbus->State; + hfmpsmbus->State = HAL_FMPSMBUS_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hfmpsmbus); + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ +#if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1) + hfmpsmbus->ListenCpltCallback(hfmpsmbus); +#else + HAL_FMPSMBUS_ListenCpltCallback(hfmpsmbus); +#endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */ + } + } + + /* Process Unlocked */ + __HAL_UNLOCK(hfmpsmbus); + + return HAL_OK; +} +/** + * @brief Manage the enabling of Interrupts. + * @param hfmpsmbus Pointer to a FMPSMBUS_HandleTypeDef structure that contains + * the configuration information for the specified FMPSMBUS. + * @param InterruptRequest Value of @ref FMPSMBUS_Interrupt_configuration_definition. + * @retval HAL status + */ +static void FMPSMBUS_Enable_IRQ(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t InterruptRequest) +{ + uint32_t tmpisr = 0UL; + + if ((InterruptRequest & FMPSMBUS_IT_ALERT) == FMPSMBUS_IT_ALERT) + { + /* Enable ERR interrupt */ + tmpisr |= FMPSMBUS_IT_ERRI; + } + + if ((InterruptRequest & FMPSMBUS_IT_ADDR) == FMPSMBUS_IT_ADDR) + { + /* Enable ADDR, STOP interrupt */ + tmpisr |= FMPSMBUS_IT_ADDRI | FMPSMBUS_IT_STOPI | FMPSMBUS_IT_NACKI | FMPSMBUS_IT_ERRI; + } + + if ((InterruptRequest & FMPSMBUS_IT_TX) == FMPSMBUS_IT_TX) + { + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ + tmpisr |= FMPSMBUS_IT_ERRI | FMPSMBUS_IT_TCI | FMPSMBUS_IT_STOPI | FMPSMBUS_IT_NACKI | FMPSMBUS_IT_TXI; + } + + if ((InterruptRequest & FMPSMBUS_IT_RX) == FMPSMBUS_IT_RX) + { + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + tmpisr |= FMPSMBUS_IT_ERRI | FMPSMBUS_IT_TCI | FMPSMBUS_IT_STOPI | FMPSMBUS_IT_NACKI | FMPSMBUS_IT_RXI; + } + + /* Enable interrupts only at the end */ + /* to avoid the risk of FMPSMBUS interrupt handle execution before */ + /* all interrupts requested done */ + __HAL_FMPSMBUS_ENABLE_IT(hfmpsmbus, tmpisr); +} +/** + * @brief Manage the disabling of Interrupts. + * @param hfmpsmbus Pointer to a FMPSMBUS_HandleTypeDef structure that contains + * the configuration information for the specified FMPSMBUS. + * @param InterruptRequest Value of @ref FMPSMBUS_Interrupt_configuration_definition. + * @retval HAL status + */ +static void FMPSMBUS_Disable_IRQ(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t InterruptRequest) +{ + uint32_t tmpisr = 0UL; + uint32_t tmpstate = hfmpsmbus->State; + + if ((tmpstate == HAL_FMPSMBUS_STATE_READY) && ((InterruptRequest & FMPSMBUS_IT_ALERT) == FMPSMBUS_IT_ALERT)) + { + /* Disable ERR interrupt */ + tmpisr |= FMPSMBUS_IT_ERRI; + } + + if ((InterruptRequest & FMPSMBUS_IT_TX) == FMPSMBUS_IT_TX) + { + /* Disable TC, STOP, NACK and TXI interrupt */ + tmpisr |= FMPSMBUS_IT_TCI | FMPSMBUS_IT_TXI; + + if ((FMPSMBUS_GET_ALERT_ENABLED(hfmpsmbus) == 0UL) + && ((tmpstate & HAL_FMPSMBUS_STATE_LISTEN) != HAL_FMPSMBUS_STATE_LISTEN)) + { + /* Disable ERR interrupt */ + tmpisr |= FMPSMBUS_IT_ERRI; + } + + if ((tmpstate & HAL_FMPSMBUS_STATE_LISTEN) != HAL_FMPSMBUS_STATE_LISTEN) + { + /* Disable STOP and NACK interrupt */ + tmpisr |= FMPSMBUS_IT_STOPI | FMPSMBUS_IT_NACKI; + } + } + + if ((InterruptRequest & FMPSMBUS_IT_RX) == FMPSMBUS_IT_RX) + { + /* Disable TC, STOP, NACK and RXI interrupt */ + tmpisr |= FMPSMBUS_IT_TCI | FMPSMBUS_IT_RXI; + + if ((FMPSMBUS_GET_ALERT_ENABLED(hfmpsmbus) == 0UL) + && ((tmpstate & HAL_FMPSMBUS_STATE_LISTEN) != HAL_FMPSMBUS_STATE_LISTEN)) + { + /* Disable ERR interrupt */ + tmpisr |= FMPSMBUS_IT_ERRI; + } + + if ((tmpstate & HAL_FMPSMBUS_STATE_LISTEN) != HAL_FMPSMBUS_STATE_LISTEN) + { + /* Disable STOP and NACK interrupt */ + tmpisr |= FMPSMBUS_IT_STOPI | FMPSMBUS_IT_NACKI; + } + } + + if ((InterruptRequest & FMPSMBUS_IT_ADDR) == FMPSMBUS_IT_ADDR) + { + /* Disable ADDR, STOP and NACK interrupt */ + tmpisr |= FMPSMBUS_IT_ADDRI | FMPSMBUS_IT_STOPI | FMPSMBUS_IT_NACKI; + + if (FMPSMBUS_GET_ALERT_ENABLED(hfmpsmbus) == 0UL) + { + /* Disable ERR interrupt */ + tmpisr |= FMPSMBUS_IT_ERRI; + } + } + + /* Disable interrupts only at the end */ + /* to avoid a breaking situation like at "t" time */ + /* all disable interrupts request are not done */ + __HAL_FMPSMBUS_DISABLE_IT(hfmpsmbus, tmpisr); +} + +/** + * @brief FMPSMBUS interrupts error handler. + * @param hfmpsmbus FMPSMBUS handle. + * @retval None + */ +static void FMPSMBUS_ITErrorHandler(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus) +{ + uint32_t itflags = READ_REG(hfmpsmbus->Instance->ISR); + uint32_t itsources = READ_REG(hfmpsmbus->Instance->CR1); + uint32_t tmpstate; + uint32_t tmperror; + + /* FMPSMBUS Bus error interrupt occurred ------------------------------------*/ + if (((itflags & FMPSMBUS_FLAG_BERR) == FMPSMBUS_FLAG_BERR) && ((itsources & FMPSMBUS_IT_ERRI) == FMPSMBUS_IT_ERRI)) + { + hfmpsmbus->ErrorCode |= HAL_FMPSMBUS_ERROR_BERR; + + /* Clear BERR flag */ + __HAL_FMPSMBUS_CLEAR_FLAG(hfmpsmbus, FMPSMBUS_FLAG_BERR); + } + + /* FMPSMBUS Over-Run/Under-Run interrupt occurred ----------------------------------------*/ + if (((itflags & FMPSMBUS_FLAG_OVR) == FMPSMBUS_FLAG_OVR) && ((itsources & FMPSMBUS_IT_ERRI) == FMPSMBUS_IT_ERRI)) + { + hfmpsmbus->ErrorCode |= HAL_FMPSMBUS_ERROR_OVR; + + /* Clear OVR flag */ + __HAL_FMPSMBUS_CLEAR_FLAG(hfmpsmbus, FMPSMBUS_FLAG_OVR); + } + + /* FMPSMBUS Arbitration Loss error interrupt occurred ------------------------------------*/ + if (((itflags & FMPSMBUS_FLAG_ARLO) == FMPSMBUS_FLAG_ARLO) && ((itsources & FMPSMBUS_IT_ERRI) == FMPSMBUS_IT_ERRI)) + { + hfmpsmbus->ErrorCode |= HAL_FMPSMBUS_ERROR_ARLO; + + /* Clear ARLO flag */ + __HAL_FMPSMBUS_CLEAR_FLAG(hfmpsmbus, FMPSMBUS_FLAG_ARLO); + } + + /* FMPSMBUS Timeout error interrupt occurred ---------------------------------------------*/ + if (((itflags & FMPSMBUS_FLAG_TIMEOUT) == FMPSMBUS_FLAG_TIMEOUT) && ((itsources & FMPSMBUS_IT_ERRI) == FMPSMBUS_IT_ERRI)) + { + hfmpsmbus->ErrorCode |= HAL_FMPSMBUS_ERROR_BUSTIMEOUT; + + /* Clear TIMEOUT flag */ + __HAL_FMPSMBUS_CLEAR_FLAG(hfmpsmbus, FMPSMBUS_FLAG_TIMEOUT); + } + + /* FMPSMBUS Alert error interrupt occurred -----------------------------------------------*/ + if (((itflags & FMPSMBUS_FLAG_ALERT) == FMPSMBUS_FLAG_ALERT) && ((itsources & FMPSMBUS_IT_ERRI) == FMPSMBUS_IT_ERRI)) + { + hfmpsmbus->ErrorCode |= HAL_FMPSMBUS_ERROR_ALERT; + + /* Clear ALERT flag */ + __HAL_FMPSMBUS_CLEAR_FLAG(hfmpsmbus, FMPSMBUS_FLAG_ALERT); + } + + /* FMPSMBUS Packet Error Check error interrupt occurred ----------------------------------*/ + if (((itflags & FMPSMBUS_FLAG_PECERR) == FMPSMBUS_FLAG_PECERR) && ((itsources & FMPSMBUS_IT_ERRI) == FMPSMBUS_IT_ERRI)) + { + hfmpsmbus->ErrorCode |= HAL_FMPSMBUS_ERROR_PECERR; + + /* Clear PEC error flag */ + __HAL_FMPSMBUS_CLEAR_FLAG(hfmpsmbus, FMPSMBUS_FLAG_PECERR); + } + + /* Store current volatile hfmpsmbus->State, misra rule */ + tmperror = hfmpsmbus->ErrorCode; + + /* Call the Error Callback in case of Error detected */ + if ((tmperror != HAL_FMPSMBUS_ERROR_NONE) && (tmperror != HAL_FMPSMBUS_ERROR_ACKF)) + { + /* Do not Reset the HAL state in case of ALERT error */ + if ((tmperror & HAL_FMPSMBUS_ERROR_ALERT) != HAL_FMPSMBUS_ERROR_ALERT) + { + /* Store current volatile hfmpsmbus->State, misra rule */ + tmpstate = hfmpsmbus->State; + + if (((tmpstate & HAL_FMPSMBUS_STATE_SLAVE_BUSY_TX) == HAL_FMPSMBUS_STATE_SLAVE_BUSY_TX) + || ((tmpstate & HAL_FMPSMBUS_STATE_SLAVE_BUSY_RX) == HAL_FMPSMBUS_STATE_SLAVE_BUSY_RX)) + { + /* Reset only HAL_FMPSMBUS_STATE_SLAVE_BUSY_XX */ + /* keep HAL_FMPSMBUS_STATE_LISTEN if set */ + hfmpsmbus->PreviousState = HAL_FMPSMBUS_STATE_READY; + hfmpsmbus->State = HAL_FMPSMBUS_STATE_LISTEN; + } + } + + /* Call the Error callback to inform upper layer */ +#if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1) + hfmpsmbus->ErrorCallback(hfmpsmbus); +#else + HAL_FMPSMBUS_ErrorCallback(hfmpsmbus); +#endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */ + } +} + +/** + * @brief Handle FMPSMBUS Communication Timeout. + * @param hfmpsmbus Pointer to a FMPSMBUS_HandleTypeDef structure that contains + * the configuration information for the specified FMPSMBUS. + * @param Flag Specifies the FMPSMBUS flag to check. + * @param Status The new Flag status (SET or RESET). + * @param Timeout Timeout duration + * @retval HAL status + */ +static HAL_StatusTypeDef FMPSMBUS_WaitOnFlagUntilTimeout(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout) +{ + uint32_t tickstart = HAL_GetTick(); + + /* Wait until flag is set */ + while ((FlagStatus)(__HAL_FMPSMBUS_GET_FLAG(hfmpsmbus, Flag)) == Status) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) + { + hfmpsmbus->PreviousState = hfmpsmbus->State; + hfmpsmbus->State = HAL_FMPSMBUS_STATE_READY; + + /* Update FMPSMBUS error code */ + hfmpsmbus->ErrorCode |= HAL_FMPSMBUS_ERROR_HALTIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hfmpsmbus); + + return HAL_ERROR; + } + } + } + + return HAL_OK; +} + +/** + * @brief Handle FMPSMBUSx communication when starting transfer or during transfer (TC or TCR flag are set). + * @param hfmpsmbus FMPSMBUS handle. + * @param DevAddress specifies the slave address to be programmed. + * @param Size specifies the number of bytes to be programmed. + * This parameter must be a value between 0 and 255. + * @param Mode New state of the FMPSMBUS START condition generation. + * This parameter can be one or a combination of the following values: + * @arg @ref FMPSMBUS_RELOAD_MODE Enable Reload mode. + * @arg @ref FMPSMBUS_AUTOEND_MODE Enable Automatic end mode. + * @arg @ref FMPSMBUS_SOFTEND_MODE Enable Software end mode and Reload mode. + * @arg @ref FMPSMBUS_SENDPEC_MODE Enable Packet Error Calculation mode. + * @param Request New state of the FMPSMBUS START condition generation. + * This parameter can be one of the following values: + * @arg @ref FMPSMBUS_NO_STARTSTOP Don't Generate stop and start condition. + * @arg @ref FMPSMBUS_GENERATE_STOP Generate stop condition (Size should be set to 0). + * @arg @ref FMPSMBUS_GENERATE_START_READ Generate Restart for read request. + * @arg @ref FMPSMBUS_GENERATE_START_WRITE Generate Restart for write request. + * @retval None + */ +static void FMPSMBUS_TransferConfig(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) +{ + /* Check the parameters */ + assert_param(IS_FMPSMBUS_ALL_INSTANCE(hfmpsmbus->Instance)); + assert_param(IS_FMPSMBUS_TRANSFER_MODE(Mode)); + assert_param(IS_FMPSMBUS_TRANSFER_REQUEST(Request)); + + /* update CR2 register */ + MODIFY_REG(hfmpsmbus->Instance->CR2, ((FMPI2C_CR2_SADD | FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | FMPI2C_CR2_AUTOEND | (FMPI2C_CR2_RD_WRN & (uint32_t)(Request >> (31UL - FMPI2C_CR2_RD_WRN_Pos))) | FMPI2C_CR2_START | FMPI2C_CR2_STOP | FMPI2C_CR2_PECBYTE)), \ + (uint32_t)(((uint32_t)DevAddress & FMPI2C_CR2_SADD) | (((uint32_t)Size << FMPI2C_CR2_NBYTES_Pos) & FMPI2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request)); +} + +/** + * @brief Convert FMPSMBUSx OTHER_xxx XferOptions to functionnal XferOptions. + * @param hfmpsmbus FMPSMBUS handle. + * @retval None + */ +static void FMPSMBUS_ConvertOtherXferOptions(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus) +{ + /* if user set XferOptions to FMPSMBUS_OTHER_FRAME_NO_PEC */ + /* it request implicitly to generate a restart condition */ + /* set XferOptions to FMPSMBUS_FIRST_FRAME */ + if (hfmpsmbus->XferOptions == FMPSMBUS_OTHER_FRAME_NO_PEC) + { + hfmpsmbus->XferOptions = FMPSMBUS_FIRST_FRAME; + } + /* else if user set XferOptions to FMPSMBUS_OTHER_FRAME_WITH_PEC */ + /* it request implicitly to generate a restart condition */ + /* set XferOptions to FMPSMBUS_FIRST_FRAME | FMPSMBUS_SENDPEC_MODE */ + else if (hfmpsmbus->XferOptions == FMPSMBUS_OTHER_FRAME_WITH_PEC) + { + hfmpsmbus->XferOptions = FMPSMBUS_FIRST_FRAME | FMPSMBUS_SENDPEC_MODE; + } + /* else if user set XferOptions to FMPSMBUS_OTHER_AND_LAST_FRAME_NO_PEC */ + /* it request implicitly to generate a restart condition */ + /* then generate a stop condition at the end of transfer */ + /* set XferOptions to FMPSMBUS_FIRST_AND_LAST_FRAME_NO_PEC */ + else if (hfmpsmbus->XferOptions == FMPSMBUS_OTHER_AND_LAST_FRAME_NO_PEC) + { + hfmpsmbus->XferOptions = FMPSMBUS_FIRST_AND_LAST_FRAME_NO_PEC; + } + /* else if user set XferOptions to FMPSMBUS_OTHER_AND_LAST_FRAME_WITH_PEC */ + /* it request implicitly to generate a restart condition */ + /* then generate a stop condition at the end of transfer */ + /* set XferOptions to FMPSMBUS_FIRST_AND_LAST_FRAME_WITH_PEC */ + else if (hfmpsmbus->XferOptions == FMPSMBUS_OTHER_AND_LAST_FRAME_WITH_PEC) + { + hfmpsmbus->XferOptions = FMPSMBUS_FIRST_AND_LAST_FRAME_WITH_PEC; + } + else + { + /* Nothing to do */ + } +} +/** + * @} + */ + +#endif /* FMPI2C_CR1_PE */ +#endif /* HAL_FMPSMBUS_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hcd.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hcd.c index 6d90fdcdd3..1e384d6f02 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hcd.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hcd.c @@ -373,14 +373,13 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, uint16_t length, uint8_t do_ping) { - UNUSED(do_ping); - hhcd->hc[ch_num].ep_is_in = direction; hhcd->hc[ch_num].ep_type = ep_type; if (token == 0U) { hhcd->hc[ch_num].data_pid = HC_PID_SETUP; + hhcd->hc[ch_num].do_ping = do_ping; } else { @@ -534,20 +533,19 @@ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd) /* Handle Host Disconnect Interrupts */ if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT)) { + __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT); - /* Cleanup HPRT */ - USBx_HPRT0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | \ - USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG); - - /* Handle Host Port Disconnect Interrupt */ + if ((USBx_HPRT0 & USB_OTG_HPRT_PCSTS) == 0U) + { + /* Handle Host Port Disconnect Interrupt */ #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) - hhcd->DisconnectCallback(hhcd); + hhcd->DisconnectCallback(hhcd); #else - HAL_HCD_Disconnect_Callback(hhcd); + HAL_HCD_Disconnect_Callback(hhcd); #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ - (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ); - __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT); + (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ); + } } /* Handle Host Port Interrupts */ @@ -1009,6 +1007,7 @@ HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd) __HAL_HCD_ENABLE(hhcd); (void)USB_DriveVbus(hhcd->Instance, 1U); __HAL_UNLOCK(hhcd); + return HAL_OK; } @@ -1023,6 +1022,7 @@ HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd) __HAL_LOCK(hhcd); (void)USB_StopHost(hhcd->Instance); __HAL_UNLOCK(hhcd); + return HAL_OK; } @@ -1170,6 +1170,13 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_AHBERR); __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); } + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_BBERR) == USB_OTG_HCINT_BBERR) + { + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_BBERR); + hhcd->hc[ch_num].state = HC_BBLERR; + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + } else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_ACK) == USB_OTG_HCINT_ACK) { __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_ACK); @@ -1225,6 +1232,17 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) USBx_HC(ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM; hhcd->hc[ch_num].urb_state = URB_DONE; +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); +#else + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + } + else if (hhcd->hc[ch_num].ep_type == EP_TYPE_ISOC) + { + hhcd->hc[ch_num].urb_state = URB_DONE; + hhcd->hc[ch_num].toggle_in ^= 1U; + #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); #else @@ -1279,6 +1297,11 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) tmpreg |= USB_OTG_HCCHAR_CHENA; USBx_HC(ch_num)->HCCHAR = tmpreg; } + else if (hhcd->hc[ch_num].state == HC_BBLERR) + { + hhcd->hc[ch_num].ErrCnt++; + hhcd->hc[ch_num].urb_state = URB_ERROR; + } else { /* ... */ @@ -1555,8 +1578,6 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd) { if ((hprt0 & USB_OTG_HPRT_PCSTS) == USB_OTG_HPRT_PCSTS) { - USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_DISCINT); - #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) hhcd->ConnectCallback(hhcd); #else @@ -1593,10 +1614,8 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd) } #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) hhcd->PortEnabledCallback(hhcd); - hhcd->ConnectCallback(hhcd); #else HAL_HCD_PortEnabled_Callback(hhcd); - HAL_HCD_Connect_Callback(hhcd); #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ } @@ -1607,12 +1626,6 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd) #else HAL_HCD_PortDisabled_Callback(hhcd); #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ - - /* Cleanup HPRT */ - USBx_HPRT0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | \ - USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG); - - USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_DISCINT); } } diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s.c index 20a0e9567c..51e75bdbe6 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s.c @@ -88,6 +88,10 @@ (+) Pause the DMA Transfer using HAL_I2S_DMAPause() (+) Resume the DMA Transfer using HAL_I2S_DMAResume() (+) Stop the DMA Transfer using HAL_I2S_DMAStop() + In Slave mode, if HAL_I2S_DMAStop is used to stop the communication, an error + HAL_I2S_ERROR_BUSY_LINE_RX is raised as the master continue to transmit data. + In this case __HAL_I2S_FLUSH_RX_DR macro must be used to flush the remaining data + inside DR register and avoid using DeInit/Init process for the next transfer. *** I2S HAL driver macros list *** =================================== @@ -100,6 +104,7 @@ (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not + (+) __HAL_I2S_FLUSH_RX_DR: Read DR Register to Flush RX Data [..] (@) You can refer to the I2S HAL driver header file for more useful macros @@ -194,6 +199,7 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ +#define I2S_TIMEOUT_FLAG 100U /*!< Timeout 100 ms */ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ @@ -1454,6 +1460,9 @@ HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s) */ HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s) { +#if defined (SPI_I2S_FULLDUPLEX_SUPPORT) + uint32_t tickstart; +#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */ HAL_StatusTypeDef errorcode = HAL_OK; /* The Lock is not implemented on this API to allow the user application to call the HAL SPI API under callbacks HAL_I2S_TxCpltCallback() or HAL_I2S_RxCpltCallback() @@ -1461,46 +1470,180 @@ HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s) and the correspond call back is executed HAL_I2S_TxCpltCallback() or HAL_I2S_RxCpltCallback() */ - /* Disable the I2S Tx/Rx DMA requests */ - CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN); - CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN); - - /* Abort the I2S DMA tx Stream/Channel */ - if (hi2s->hdmatx != NULL) + if ((hi2s->Init.Mode == I2S_MODE_MASTER_TX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_TX)) { - /* Disable the I2S DMA tx Stream/Channel */ - if (HAL_OK != HAL_DMA_Abort(hi2s->hdmatx)) + /* Abort the I2S DMA tx Stream/Channel */ + if (hi2s->hdmatx != NULL) { - SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA); - errorcode = HAL_ERROR; + /* Disable the I2S DMA tx Stream/Channel */ + if (HAL_OK != HAL_DMA_Abort(hi2s->hdmatx)) + { + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA); + errorcode = HAL_ERROR; + } } + + /* Wait until TXE flag is set */ + if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, I2S_TIMEOUT_FLAG) != HAL_OK) + { + /* Set the error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT); + hi2s->State = HAL_I2S_STATE_READY; + errorcode = HAL_ERROR; + } + + /* Wait until BSY flag is Reset */ + if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, RESET, I2S_TIMEOUT_FLAG) != HAL_OK) + { + /* Set the error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT); + hi2s->State = HAL_I2S_STATE_READY; + errorcode = HAL_ERROR; + } + + /* Disable I2S peripheral */ + __HAL_I2S_DISABLE(hi2s); + + /* Clear UDR flag */ + __HAL_I2S_CLEAR_UDRFLAG(hi2s); + + /* Disable the I2S Tx DMA requests */ + CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN); + +#if defined (SPI_I2S_FULLDUPLEX_SUPPORT) + + if (hi2s->State == HAL_I2S_STATE_BUSY_TX_RX) + { + /* Abort the I2S DMA rx Stream/Channel */ + if (hi2s->hdmarx != NULL) + { + /* Disable the I2S DMA rx Stream/Channel */ + if (HAL_OK != HAL_DMA_Abort(hi2s->hdmarx)) + { + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA); + errorcode = HAL_ERROR; + } + } + + /* Disable I2Sext peripheral */ + __HAL_I2SEXT_DISABLE(hi2s); + + /* Clear OVR flag */ + __HAL_I2SEXT_CLEAR_OVRFLAG(hi2s); + + /* Disable the I2SxEXT DMA request */ + CLEAR_BIT(I2SxEXT(hi2s->Instance)->CR2, SPI_CR2_RXDMAEN); + + if (hi2s->Init.Mode == I2S_MODE_SLAVE_TX) + { + /* Set the error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_BUSY_LINE_RX); + + /* Set the I2S State ready */ + hi2s->State = HAL_I2S_STATE_READY; + errorcode = HAL_ERROR; + } + else + { + /* Read DR to Flush RX Data */ + READ_REG(I2SxEXT(hi2s->Instance)->DR); + } + } +#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */ } - /* Abort the I2S DMA rx Stream/Channel */ - if (hi2s->hdmarx != NULL) + else if ((hi2s->Init.Mode == I2S_MODE_MASTER_RX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_RX)) { - /* Disable the I2S DMA rx Stream/Channel */ - if (HAL_OK != HAL_DMA_Abort(hi2s->hdmarx)) + /* Abort the I2S DMA rx Stream/Channel */ + if (hi2s->hdmarx != NULL) { - SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA); - errorcode = HAL_ERROR; + /* Disable the I2S DMA rx Stream/Channel */ + if (HAL_OK != HAL_DMA_Abort(hi2s->hdmarx)) + { + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA); + errorcode = HAL_ERROR; + } } - } #if defined (SPI_I2S_FULLDUPLEX_SUPPORT) - /* In case of Full-Duplex, disable the I2SxEXT Tx/Rx DMA requests*/ - if (hi2s->State == HAL_I2S_STATE_BUSY_TX_RX) - { - /* Disable the I2SxEXT DMA requests */ - CLEAR_BIT(I2SxEXT(hi2s->Instance)->CR2, SPI_CR2_TXDMAEN); - CLEAR_BIT(I2SxEXT(hi2s->Instance)->CR2, SPI_CR2_RXDMAEN); - /* Disable I2Sext peripheral */ - __HAL_I2SEXT_DISABLE(hi2s); - } + if (hi2s->State == HAL_I2S_STATE_BUSY_TX_RX) + { + /* Abort the I2S DMA tx Stream/Channel */ + if (hi2s->hdmatx != NULL) + { + /* Disable the I2S DMA tx Stream/Channel */ + if (HAL_OK != HAL_DMA_Abort(hi2s->hdmatx)) + { + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA); + errorcode = HAL_ERROR; + } + } + + tickstart = HAL_GetTick(); + + /* Wait until TXE flag is set */ + while (__HAL_I2SEXT_GET_FLAG(hi2s, I2S_FLAG_TXE) != SET) + { + if (((HAL_GetTick() - tickstart) > I2S_TIMEOUT_FLAG)) + { + /* Set the error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT); + + /* Set the I2S State ready */ + hi2s->State = HAL_I2S_STATE_READY; + errorcode = HAL_ERROR; + } + } + + /* Wait until BSY flag is Reset */ + while (__HAL_I2SEXT_GET_FLAG(hi2s, I2S_FLAG_BSY) != RESET) + { + if (((HAL_GetTick() - tickstart) > I2S_TIMEOUT_FLAG)) + { + /* Set the error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT); + + /* Set the I2S State ready */ + hi2s->State = HAL_I2S_STATE_READY; + errorcode = HAL_ERROR; + } + } + + /* Disable I2Sext peripheral */ + __HAL_I2SEXT_DISABLE(hi2s); + + /* Clear UDR flag */ + __HAL_I2SEXT_CLEAR_UDRFLAG(hi2s); + + /* Disable the I2SxEXT DMA request */ + CLEAR_BIT(I2SxEXT(hi2s->Instance)->CR2, SPI_CR2_TXDMAEN); + } #endif /* SPI_I2S_FULLDUPLEX_SUPPORT */ - /* Disable I2S peripheral */ - __HAL_I2S_DISABLE(hi2s); + /* Disable I2S peripheral */ + __HAL_I2S_DISABLE(hi2s); + + /* Clear OVR flag */ + __HAL_I2S_CLEAR_OVRFLAG(hi2s); + + /* Disable the I2S Rx DMA request */ + CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN); + + if (hi2s->Init.Mode == I2S_MODE_SLAVE_RX) + { + /* Set the error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_BUSY_LINE_RX); + + /* Set the I2S State ready */ + hi2s->State = HAL_I2S_STATE_READY; + errorcode = HAL_ERROR; + } + else + { + /* Read DR to Flush RX Data */ + READ_REG((hi2s->Instance)->DR); + } + } hi2s->State = HAL_I2S_STATE_READY; diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s_ex.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s_ex.c index 11cfb82367..791c2192e0 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s_ex.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s_ex.c @@ -52,6 +52,10 @@ add his own code by customization of function pointer HAL_I2S_TxRxCpltCallback (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can add his own code by customization of function pointer HAL_I2S_ErrorCallback + (+) __HAL_I2SEXT_FLUSH_RX_DR: In Full-Duplex Slave mode, if HAL_I2S_DMAStop is used to stop the + communication, an error HAL_I2S_ERROR_BUSY_LINE_RX is raised as the master continue to transmit data. + In this case __HAL_I2SEXT_FLUSH_RX_DR macro must be used to flush the remaining data + inside I2Sx and I2Sx_ext DR registers and avoid using DeInit/Init process for the next transfer. @endverbatim Additional Figure: The Extended block uses the same clock sources as its master. diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c index cc5081ffeb..cda95bee8a 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c @@ -1058,6 +1058,38 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS); } + /* Handle RxQLevel Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL)) + { + USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); + + temp = USBx->GRXSTSP; + + ep = &hpcd->OUT_ep[temp & USB_OTG_GRXSTSP_EPNUM]; + + if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT) + { + if ((temp & USB_OTG_GRXSTSP_BCNT) != 0U) + { + (void)USB_ReadPacket(USBx, ep->xfer_buff, + (uint16_t)((temp & USB_OTG_GRXSTSP_BCNT) >> 4)); + + ep->xfer_buff += (temp & USB_OTG_GRXSTSP_BCNT) >> 4; + ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4; + } + } + else if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_SETUP_UPDT) + { + (void)USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U); + ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4; + } + else + { + /* ... */ + } + USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); + } + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT)) { epnum = 0U; @@ -1079,9 +1111,9 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) if ((epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP); /* Class B setup phase done for previous decoded setup */ (void)PCD_EP_OutSetupPacket_int(hpcd, epnum); - CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP); } if ((epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS) @@ -1092,10 +1124,6 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /* Clear Status Phase Received interrupt */ if ((epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) { - if (hpcd->Init.dma_enable == 1U) - { - (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); - } CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR); } @@ -1133,16 +1161,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) if (hpcd->Init.dma_enable == 1U) { hpcd->IN_ep[epnum].xfer_buff += hpcd->IN_ep[epnum].maxpacket; - } -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->DataInStageCallback(hpcd, (uint8_t)epnum); -#else - HAL_PCD_DataInStageCallback(hpcd, (uint8_t)epnum); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - - if (hpcd->Init.dma_enable == 1U) - { /* this is ZLP, so prepare EP0 for next setup */ if ((epnum == 0U) && (hpcd->IN_ep[epnum].xfer_len == 0U)) { @@ -1150,6 +1169,12 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); } } + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DataInStageCallback(hpcd, (uint8_t)epnum); +#else + HAL_PCD_DataInStageCallback(hpcd, (uint8_t)epnum); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } if ((epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC) { @@ -1255,8 +1280,10 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) { USBx_INEP(i)->DIEPINT = 0xFB7FU; USBx_INEP(i)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; + USBx_INEP(i)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK; USBx_OUTEP(i)->DOEPINT = 0xFB7FU; USBx_OUTEP(i)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; + USBx_OUTEP(i)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK; } USBx_DEVICE->DAINTMSK |= 0x10001U; @@ -1313,38 +1340,6 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE); } - /* Handle RxQLevel Interrupt */ - if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL)) - { - USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); - - temp = USBx->GRXSTSP; - - ep = &hpcd->OUT_ep[temp & USB_OTG_GRXSTSP_EPNUM]; - - if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT) - { - if ((temp & USB_OTG_GRXSTSP_BCNT) != 0U) - { - (void)USB_ReadPacket(USBx, ep->xfer_buff, - (uint16_t)((temp & USB_OTG_GRXSTSP_BCNT) >> 4)); - - ep->xfer_buff += (temp & USB_OTG_GRXSTSP_BCNT) >> 4; - ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4; - } - } - else if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_SETUP_UPDT) - { - (void)USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U); - ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4; - } - else - { - /* ... */ - } - USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); - } - /* Handle SOF Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF)) { @@ -2071,16 +2066,6 @@ static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); } - - /* Inform the upper layer that a setup packet is available */ -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->SetupStageCallback(hpcd); -#else - HAL_PCD_SetupStageCallback(hpcd); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - - (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); - CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP); } else if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) /* Class E */ { @@ -2103,17 +2088,16 @@ static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint hpcd->OUT_ep[epnum].xfer_buff += hpcd->OUT_ep[epnum].maxpacket; -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); -#else - HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - if ((epnum == 0U) && (hpcd->OUT_ep[epnum].xfer_len == 0U)) { /* this is ZLP, so prepare EP0 for next setup */ (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); } +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); +#else + HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } } else @@ -2146,6 +2130,12 @@ static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint } else { + if ((epnum == 0U) && (hpcd->OUT_ep[epnum].xfer_len == 0U)) + { + /* this is ZLP, so prepare EP0 for next setup */ + (void)USB_EP0_OutStart(hpcd->Instance, 0U, (uint8_t *)hpcd->Setup); + } + #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); #else @@ -2171,22 +2161,10 @@ static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U); uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT; - if (hpcd->Init.dma_enable == 1U) + if ((gSNPSiD > USB_OTG_CORE_ID_300A) && + ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)) { - /* StupPktRcvd = 1 pending setup packet int */ - if ((gSNPSiD > USB_OTG_CORE_ID_300A) && - ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)) - { - CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); - } - } - else - { - if ((gSNPSiD == USB_OTG_CORE_ID_310A) && - ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)) - { - CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); - } + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); } /* Inform the upper layer that a setup packet is available */ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_qspi.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_qspi.c index 2c65a4f938..0ca4380e65 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_qspi.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_qspi.c @@ -24,7 +24,7 @@ [..] (#) As prerequisite, fill in the HAL_QSPI_MspInit() : (++) Enable QuadSPI clock interface with __HAL_RCC_QSPI_CLK_ENABLE(). - (++) Reset QuadSPI IP with __HAL_RCC_QSPI_FORCE_RESET() and __HAL_RCC_QSPI_RELEASE_RESET(). + (++) Reset QuadSPI Peripheral with __HAL_RCC_QSPI_FORCE_RESET() and __HAL_RCC_QSPI_RELEASE_RESET(). (++) Enable the clocks for the QuadSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE(). (++) Configure these QuadSPI pins in alternate mode using HAL_GPIO_Init(). (++) If interrupt mode is used, enable and configure QuadSPI global @@ -108,7 +108,7 @@ the address range. HAL_QSPI_TimeOutCallback() will be called when the timeout expires. *** Errors management and abort functionality *** - ================================================== + ================================================= [..] (#) HAL_QSPI_GetError() function gives the error raised during the last operation. (#) HAL_QSPI_Abort() and HAL_QSPI_AbortIT() functions aborts any on-going operation and @@ -116,7 +116,7 @@ (++) In polling mode, the output of the function is done when the transfer complete bit is set and the busy bit cleared. (++) In interrupt mode, HAL_QSPI_AbortCpltCallback() will be called when - the transfer complete bi is set. + the transfer complete bit is set. *** Control functions *** ========================= @@ -125,6 +125,7 @@ (#) HAL_QSPI_SetTimeout() function configures the timeout value used in the driver. (#) HAL_QSPI_SetFifoThreshold() function configures the threshold on the Fifo of the QSPI IP. (#) HAL_QSPI_GetFifoThreshold() function gives the current of the Fifo's threshold + (#) HAL_QSPI_SetFlashID() function configures the index of the flash memory to be accessed. *** Callback registration *** ============================================= @@ -195,13 +196,13 @@ ****************************************************************************** * @attention * - *

    © Copyright (c) 2017 STMicroelectronics. + *

    © Copyright (c) 2016 STMicroelectronics. * All rights reserved.

    * * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -209,6 +210,8 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hal.h" +#if defined(QUADSPI) + /** @addtogroup STM32F4xx_HAL_Driver * @{ */ @@ -219,12 +222,10 @@ */ #ifdef HAL_QSPI_MODULE_ENABLED -#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ - defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) - /* Private typedef -----------------------------------------------------------*/ + /* Private define ------------------------------------------------------------*/ -/** @addtogroup QSPI_Private_Constants +/** @defgroup QSPI_Private_Constants QSPI Private Constants * @{ */ #define QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE 0x00000000U /*!Instance->CR, QUADSPI_CR_FTHRES, ((hqspi->Init.FifoThreshold - 1U) << 8U)); + MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES, + ((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos)); /* Wait till BUSY flag reset */ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout); if(status == HAL_OK) { - /* Configure QSPI Clock Prescaler and Sample Shift */ - MODIFY_REG(hqspi->Instance->CR,(QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT | QUADSPI_CR_FSEL | QUADSPI_CR_DFM), ((hqspi->Init.ClockPrescaler << 24U)| hqspi->Init.SampleShifting | hqspi->Init.FlashID| hqspi->Init.DualFlash )); + MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT | QUADSPI_CR_FSEL | QUADSPI_CR_DFM), + ((hqspi->Init.ClockPrescaler << QUADSPI_CR_PRESCALER_Pos) | + hqspi->Init.SampleShifting | hqspi->Init.FlashID | hqspi->Init.DualFlash)); /* Configure QSPI Flash Size, CS High Time and Clock Mode */ MODIFY_REG(hqspi->Instance->DCR, (QUADSPI_DCR_FSIZE | QUADSPI_DCR_CSHT | QUADSPI_DCR_CKMODE), - ((hqspi->Init.FlashSize << 16U) | hqspi->Init.ChipSelectHighTime | hqspi->Init.ClockMode)); + ((hqspi->Init.FlashSize << QUADSPI_DCR_FSIZE_Pos) | + hqspi->Init.ChipSelectHighTime | hqspi->Init.ClockMode)); /* Enable the QSPI peripheral */ __HAL_QSPI_ENABLE(hqspi); @@ -386,8 +385,8 @@ HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi) } /** - * @brief DeInitializes the QSPI peripheral - * @param hqspi qspi handle + * @brief De-Initialize the QSPI peripheral. + * @param hqspi : QSPI handle * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi) @@ -427,11 +426,11 @@ HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi) } /** - * @brief QSPI MSP Init - * @param hqspi QSPI handle + * @brief Initialize the QSPI MSP. + * @param hqspi : QSPI handle * @retval None */ - __weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi) +__weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi) { /* Prevent unused argument(s) compilation warning */ UNUSED(hqspi); @@ -442,11 +441,11 @@ HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi) } /** - * @brief QSPI MSP DeInit - * @param hqspi QSPI handle + * @brief DeInitialize the QSPI MSP. + * @param hqspi : QSPI handle * @retval None */ - __weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi) +__weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi) { /* Prevent unused argument(s) compilation warning */ UNUSED(hqspi); @@ -460,14 +459,14 @@ HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi) * @} */ -/** @defgroup QSPI_Exported_Functions_Group2 IO operation functions +/** @defgroup QSPI_Exported_Functions_Group2 Input and Output operation functions * @brief QSPI Transmit/Receive functions * @verbatim =============================================================================== ##### IO operation functions ##### =============================================================================== - [..] + [..] This subsection provides a set of functions allowing to : (+) Handle the interrupts. (+) Handle the command sequence. @@ -481,9 +480,9 @@ HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi) */ /** - * @brief This function handles QSPI interrupt request. - * @param hqspi QSPI handle - * @retval None. + * @brief Handle QSPI interrupt request. + * @param hqspi : QSPI handle + * @retval None */ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) { @@ -492,19 +491,20 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) uint32_t itsource = READ_REG(hqspi->Instance->CR); /* QSPI Fifo Threshold interrupt occurred ----------------------------------*/ - if(((flag & QSPI_FLAG_FT)!= RESET) && ((itsource & QSPI_IT_FT)!= RESET)) + if(((flag & QSPI_FLAG_FT) != 0U) && ((itsource & QSPI_IT_FT) != 0U)) { data_reg = &hqspi->Instance->DR; if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX) { /* Transmission process */ - while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != 0U) + while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != RESET) { if (hqspi->TxXferCount > 0U) { - /* Fill the FIFO until it is full */ - *(__IO uint8_t *)data_reg = *hqspi->pTxBuffPtr++; + /* Fill the FIFO until the threshold is reached */ + *((__IO uint8_t *)data_reg) = *hqspi->pTxBuffPtr; + hqspi->pTxBuffPtr++; hqspi->TxXferCount--; } else @@ -519,12 +519,13 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX) { /* Receiving Process */ - while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != 0U) + while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != RESET) { if (hqspi->RxXferCount > 0U) { - /* Read the FIFO until it is empty */ - *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg; + /* Read the FIFO until the threshold is reached */ + *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg); + hqspi->pRxBuffPtr++; hqspi->RxXferCount--; } else @@ -536,6 +537,10 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) } } } + else + { + /* Nothing to do */ + } /* FIFO Threshold callback */ #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) @@ -546,7 +551,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) } /* QSPI Transfer Complete interrupt occurred -------------------------------*/ - else if(((flag & QSPI_FLAG_TC)!= RESET) && ((itsource & QSPI_IT_TC)!= RESET)) + else if(((flag & QSPI_FLAG_TC) != 0U) && ((itsource & QSPI_IT_TC) != 0U)) { /* Clear interrupt */ WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TC); @@ -557,7 +562,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) /* Transfer complete callback */ if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX) { - if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET) + if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U) { /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */ CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); @@ -581,7 +586,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) } else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX) { - if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET) + if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U) { /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */ CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); @@ -597,7 +602,8 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) if (hqspi->RxXferCount > 0U) { /* Read the last data received in the FIFO until it is empty */ - *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg; + *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg); + hqspi->pRxBuffPtr++; hqspi->RxXferCount--; } else @@ -607,6 +613,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) } } } + /* Workaround - Extra data written in the FIFO at the end of a read transfer */ HAL_QSPI_Abort_IT(hqspi); @@ -634,6 +641,9 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) } else if(hqspi->State == HAL_QSPI_STATE_ABORT) { + /* Reset functional mode configuration to indirect write mode by default */ + CLEAR_BIT(hqspi->Instance->CCR, QUADSPI_CCR_FMODE); + /* Change state of QSPI */ hqspi->State = HAL_QSPI_STATE_READY; @@ -660,10 +670,14 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) #endif } } + else + { + /* Nothing to do */ + } } /* QSPI Status Match interrupt occurred ------------------------------------*/ - else if(((flag & QSPI_FLAG_SM)!= RESET) && ((itsource & QSPI_IT_SM)!= RESET)) + else if(((flag & QSPI_FLAG_SM) != 0U) && ((itsource & QSPI_IT_SM) != 0U)) { /* Clear interrupt */ WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_SM); @@ -687,7 +701,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) } /* QSPI Transfer Error interrupt occurred ----------------------------------*/ - else if(((flag & QSPI_FLAG_TE)!= RESET) && ((itsource & QSPI_IT_TE)!= RESET)) + else if(((flag & QSPI_FLAG_TE) != 0U) && ((itsource & QSPI_IT_TE) != 0U)) { /* Clear interrupt */ WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TE); @@ -698,7 +712,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) /* Set error code */ hqspi->ErrorCode |= HAL_QSPI_ERROR_TRANSFER; - if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET) + if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U) { /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */ CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); @@ -736,7 +750,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) } /* QSPI Timeout interrupt occurred -----------------------------------------*/ - else if(((flag & QSPI_FLAG_TO)!= RESET) && ((itsource & QSPI_IT_TO)!= RESET)) + else if(((flag & QSPI_FLAG_TO) != 0U) && ((itsource & QSPI_IT_TO) != 0U)) { /* Clear interrupt */ WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TO); @@ -748,19 +762,24 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) HAL_QSPI_TimeOutCallback(hqspi); #endif } + + else + { + /* Nothing to do */ + } } /** - * @brief Sets the command configuration. - * @param hqspi QSPI handle - * @param cmd structure that contains the command configuration information - * @param Timeout Time out duration + * @brief Set the command configuration. + * @param hqspi : QSPI handle + * @param cmd : structure that contains the command configuration information + * @param Timeout : Timeout duration * @note This function is used only in Indirect Read or Write Modes * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout) { - HAL_StatusTypeDef status = HAL_ERROR; + HAL_StatusTypeDef status; uint32_t tickstart = HAL_GetTick(); /* Check the parameters */ @@ -820,7 +839,6 @@ HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDe /* Update QSPI state */ hqspi->State = HAL_QSPI_STATE_READY; } - } else { @@ -842,16 +860,16 @@ HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDe } /** - * @brief Sets the command configuration in interrupt mode. - * @param hqspi QSPI handle - * @param cmd structure that contains the command configuration information + * @brief Set the command configuration in interrupt mode. + * @param hqspi : QSPI handle + * @param cmd : structure that contains the command configuration information * @note This function is used only in Indirect Read or Write Modes * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd) { - __IO uint32_t count = 0U; - HAL_StatusTypeDef status = HAL_OK; + HAL_StatusTypeDef status; + uint32_t tickstart = HAL_GetTick(); /* Check the parameters */ assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode)); @@ -890,17 +908,7 @@ HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTyp hqspi->State = HAL_QSPI_STATE_BUSY; /* Wait till BUSY flag reset */ - count = (hqspi->Timeout) * (SystemCoreClock / 16U / 1000U); - do - { - if (count-- == 0U) - { - hqspi->State = HAL_QSPI_STATE_ERROR; - hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT; - status = HAL_TIMEOUT; - } - } - while ((__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_BUSY)) != RESET); + status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout); if (status == HAL_OK) { @@ -952,15 +960,15 @@ HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTyp /** * @brief Transmit an amount of data in blocking mode. - * @param hqspi QSPI handle - * @param pData pointer to data buffer - * @param Timeout Time out duration + * @param hqspi : QSPI handle + * @param pData : pointer to data buffer + * @param Timeout : Timeout duration * @note This function is used only in Indirect Write Mode * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout) { - HAL_StatusTypeDef status = HAL_OK; + HAL_StatusTypeDef status = HAL_OK; uint32_t tickstart = HAL_GetTick(); __IO uint32_t *data_reg = &hqspi->Instance->DR; @@ -994,7 +1002,8 @@ HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, u break; } - *(__IO uint8_t *)data_reg = *hqspi->pTxBuffPtr++; + *((__IO uint8_t *)data_reg) = *hqspi->pTxBuffPtr; + hqspi->pTxBuffPtr++; hqspi->TxXferCount--; } @@ -1035,10 +1044,10 @@ HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, u /** - * @brief Receive an amount of data in blocking mode - * @param hqspi QSPI handle - * @param pData pointer to data buffer - * @param Timeout Time out duration + * @brief Receive an amount of data in blocking mode. + * @param hqspi : QSPI handle + * @param pData : pointer to data buffer + * @param Timeout : Timeout duration * @note This function is used only in Indirect Read Mode * @retval HAL status */ @@ -1055,6 +1064,7 @@ HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, ui if(hqspi->State == HAL_QSPI_STATE_READY) { hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; + if(pData != NULL ) { /* Update state */ @@ -1081,7 +1091,8 @@ HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, ui break; } - *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg; + *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg); + hqspi->pRxBuffPtr++; hqspi->RxXferCount--; } @@ -1095,8 +1106,8 @@ HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, ui /* Clear Transfer Complete bit */ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); - /* Workaround - Extra data written in the FIFO at the end of a read transfer */ - status = HAL_QSPI_Abort(hqspi); + /* Workaround - Extra data written in the FIFO at the end of a read transfer */ + status = HAL_QSPI_Abort(hqspi); } } @@ -1121,9 +1132,9 @@ HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, ui } /** - * @brief Send an amount of data in interrupt mode - * @param hqspi QSPI handle - * @param pData pointer to data buffer + * @brief Send an amount of data in non-blocking mode with interrupt. + * @param hqspi : QSPI handle + * @param pData : pointer to data buffer * @note This function is used only in Indirect Write Mode * @retval HAL status */ @@ -1137,6 +1148,7 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData if(hqspi->State == HAL_QSPI_STATE_READY) { hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; + if(pData != NULL ) { /* Update state */ @@ -1147,18 +1159,17 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U; hqspi->pTxBuffPtr = pData; - /* Configure QSPI: CCR register with functional as indirect write */ - MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); - /* Clear interrupt */ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC); + /* Configure QSPI: CCR register with functional as indirect write */ + MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); + /* Process unlocked */ __HAL_UNLOCK(hqspi); /* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */ __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC); - } else { @@ -1181,9 +1192,9 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData } /** - * @brief Receive an amount of data in no-blocking mode with Interrupt - * @param hqspi QSPI handle - * @param pData pointer to data buffer + * @brief Receive an amount of data in non-blocking mode with interrupt. + * @param hqspi : QSPI handle + * @param pData : pointer to data buffer * @note This function is used only in Indirect Read Mode * @retval HAL status */ @@ -1209,15 +1220,15 @@ HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData) hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U; hqspi->pRxBuffPtr = pData; + /* Clear interrupt */ + __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC); + /* Configure QSPI: CCR register with functional as indirect read */ MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ); /* Start the transfer by re-writing the address in AR register */ WRITE_REG(hqspi->Instance->AR, addr_reg); - /* Clear interrupt */ - __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC); - /* Process unlocked */ __HAL_UNLOCK(hqspi); @@ -1245,9 +1256,9 @@ HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData) } /** - * @brief Sends an amount of data in non blocking mode with DMA. - * @param hqspi QSPI handle - * @param pData pointer to data buffer + * @brief Send an amount of data in non-blocking mode with DMA. + * @param hqspi : QSPI handle + * @param pData : pointer to data buffer * @note This function is used only in Indirect Write Mode * @note If DMA peripheral access is configured as halfword, the number * of data and the fifo threshold should be aligned on halfword @@ -1258,7 +1269,6 @@ HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData) HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData) { HAL_StatusTypeDef status = HAL_OK; - uint32_t *tmp; uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1U); /* Process locked */ @@ -1290,7 +1300,7 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pDat } else { - hqspi->TxXferCount = (data_size >> 1); + hqspi->TxXferCount = (data_size >> 1U); } } else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD) @@ -1310,41 +1320,45 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pDat hqspi->TxXferCount = (data_size >> 2U); } } + else + { + /* Nothing to do */ + } if (status == HAL_OK) { - /* Update state */ - hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX; + /* Update state */ + hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX; - /* Clear interrupt */ - __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC)); + /* Clear interrupt */ + __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC)); - /* Configure size and pointer of the handle */ - hqspi->TxXferSize = hqspi->TxXferCount; - hqspi->pTxBuffPtr = pData; + /* Configure size and pointer of the handle */ + hqspi->TxXferSize = hqspi->TxXferCount; + hqspi->pTxBuffPtr = pData; - /* Configure QSPI: CCR register with functional mode as indirect write */ - MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); + /* Configure QSPI: CCR register with functional mode as indirect write */ + MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); - /* Set the QSPI DMA transfer complete callback */ - hqspi->hdma->XferCpltCallback = QSPI_DMATxCplt; + /* Set the QSPI DMA transfer complete callback */ + hqspi->hdma->XferCpltCallback = QSPI_DMATxCplt; - /* Set the QSPI DMA Half transfer complete callback */ - hqspi->hdma->XferHalfCpltCallback = QSPI_DMATxHalfCplt; + /* Set the QSPI DMA Half transfer complete callback */ + hqspi->hdma->XferHalfCpltCallback = QSPI_DMATxHalfCplt; - /* Set the DMA error callback */ - hqspi->hdma->XferErrorCallback = QSPI_DMAError; + /* Set the DMA error callback */ + hqspi->hdma->XferErrorCallback = QSPI_DMAError; - /* Clear the DMA abort callback */ - hqspi->hdma->XferAbortCallback = NULL; + /* Clear the DMA abort callback */ + hqspi->hdma->XferAbortCallback = NULL; #if defined (QSPI1_V2_1L) - /* Bug "ES0305 section 2.1.8 In some specific cases, DMA2 data corruption occurs when managing - AHB and APB2 peripherals in a concurrent way" Workaround Implementation: - Change the following configuration of DMA peripheral - - Enable peripheral increment - - Disable memory increment - - Set DMA direction as peripheral to memory mode */ + /* Bug "ES0305 section 2.1.8 In some specific cases, DMA2 data corruption occurs when managing + AHB and APB2 peripherals in a concurrent way" Workaround Implementation: + Change the following configuration of DMA peripheral + - Enable peripheral increment + - Disable memory increment + - Set DMA direction as peripheral to memory mode */ /* Enable peripheral increment mode of the DMA */ hqspi->hdma->Init.PeriphInc = DMA_PINC_ENABLE; @@ -1358,31 +1372,39 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pDat /* Configure the direction of the DMA */ hqspi->hdma->Init.Direction = DMA_PERIPH_TO_MEMORY; #else - /* Configure the direction of the DMA */ - hqspi->hdma->Init.Direction = DMA_MEMORY_TO_PERIPH; + /* Configure the direction of the DMA */ + hqspi->hdma->Init.Direction = DMA_MEMORY_TO_PERIPH; #endif /* QSPI1_V2_1L */ - /* Update direction mode bit */ - MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction); + /* Update direction mode bit */ + MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction); - /* Enable the QSPI transmit DMA Channel */ - tmp = (uint32_t*)&pData; - HAL_DMA_Start_IT(hqspi->hdma, *(uint32_t*)tmp, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSize); + /* Enable the QSPI transmit DMA Channel */ + if (HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)pData, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSize) == HAL_OK) + { + /* Process unlocked */ + __HAL_UNLOCK(hqspi); - /* Process unlocked */ - __HAL_UNLOCK(hqspi); + /* Enable the QSPI transfer error Interrupt */ + __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE); - /* Enable the QSPI transfer error Interrupt */ - __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE); + /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */ + SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); + } + else + { + status = HAL_ERROR; + hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; + hqspi->State = HAL_QSPI_STATE_READY; - /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */ - SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); - } + /* Process unlocked */ + __HAL_UNLOCK(hqspi); + } + } } else { hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; - status = HAL_ERROR; /* Process unlocked */ @@ -1401,9 +1423,9 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pDat } /** - * @brief Receives an amount of data in non blocking mode with DMA. - * @param hqspi QSPI handle - * @param pData pointer to data buffer. + * @brief Receive an amount of data in non-blocking mode with DMA. + * @param hqspi : QSPI handle + * @param pData : pointer to data buffer. * @note This function is used only in Indirect Read Mode * @note If DMA peripheral access is configured as halfword, the number * of data and the fifo threshold should be aligned on halfword @@ -1414,7 +1436,6 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pDat HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData) { HAL_StatusTypeDef status = HAL_OK; - uint32_t *tmp; uint32_t addr_reg = READ_REG(hqspi->Instance->AR); uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1U); @@ -1423,6 +1444,7 @@ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData if(hqspi->State == HAL_QSPI_STATE_READY) { + /* Clear the error code */ hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; if(pData != NULL ) @@ -1437,7 +1459,7 @@ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData if (((data_size % 2U) != 0U) || ((hqspi->Init.FifoThreshold % 2U) != 0U)) { /* The number of data or the fifo threshold is not aligned on halfword - => no transfer possible with DMA peripheral access configured as halfword */ + => no transfer possible with DMA peripheral access configured as halfword */ hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; status = HAL_ERROR; @@ -1454,7 +1476,7 @@ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData if (((data_size % 4U) != 0U) || ((hqspi->Init.FifoThreshold % 4U) != 0U)) { /* The number of data or the fifo threshold is not aligned on word - => no transfer possible with DMA peripheral access configured as word */ + => no transfer possible with DMA peripheral access configured as word */ hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; status = HAL_ERROR; @@ -1466,6 +1488,10 @@ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData hqspi->RxXferCount = (data_size >> 2U); } } + else + { + /* Nothing to do */ + } if (status == HAL_OK) { @@ -1516,53 +1542,40 @@ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData /* 4 Extra words (32-bits) are needed for read operation to guarantee the last data is transferred from DMA FIFO to RAM memory */ WRITE_REG(hqspi->Instance->DLR, (data_size - 1U + 16U)); - - /* Update direction mode bit */ - MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction); - - /* Configure QSPI: CCR register with functional as indirect read */ - MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ); - - /* Start the transfer by re-writing the address in AR register */ - WRITE_REG(hqspi->Instance->AR, addr_reg); - - /* Enable the DMA Channel */ - tmp = (uint32_t*)&pData; - HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, *(uint32_t*)tmp, hqspi->RxXferSize); - - /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */ - SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); - - /* Process unlocked */ - __HAL_UNLOCK(hqspi); - - /* Enable the QSPI transfer error Interrupt */ - __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE); #else /* Configure the direction of the DMA */ hqspi->hdma->Init.Direction = DMA_PERIPH_TO_MEMORY; - +#endif + /* Update direction mode bit */ MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction); /* Enable the DMA Channel */ - tmp = (uint32_t*)&pData; - HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, *(uint32_t*)tmp, hqspi->RxXferSize); + if (HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, (uint32_t)pData, hqspi->RxXferSize) == HAL_OK) + { + /* Configure QSPI: CCR register with functional as indirect read */ + MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ); - /* Configure QSPI: CCR register with functional as indirect read */ - MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ); + /* Start the transfer by re-writing the address in AR register */ + WRITE_REG(hqspi->Instance->AR, addr_reg); - /* Start the transfer by re-writing the address in AR register */ - WRITE_REG(hqspi->Instance->AR, addr_reg); + /* Process unlocked */ + __HAL_UNLOCK(hqspi); - /* Process unlocked */ - __HAL_UNLOCK(hqspi); + /* Enable the QSPI transfer error Interrupt */ + __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE); - /* Enable the QSPI transfer error Interrupt */ - __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE); + /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */ + SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); + } + else + { + status = HAL_ERROR; + hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; + hqspi->State = HAL_QSPI_STATE_READY; - /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */ - SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); -#endif /* QSPI1_V2_1L */ + /* Process unlocked */ + __HAL_UNLOCK(hqspi); + } } } else @@ -1587,16 +1600,16 @@ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData /** * @brief Configure the QSPI Automatic Polling Mode in blocking mode. - * @param hqspi QSPI handle - * @param cmd structure that contains the command configuration information. - * @param cfg structure that contains the polling configuration information. - * @param Timeout Time out duration + * @param hqspi : QSPI handle + * @param cmd : structure that contains the command configuration information. + * @param cfg : structure that contains the polling configuration information. + * @param Timeout : Timeout duration * @note This function is used only in Automatic Polling Mode * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout) { - HAL_StatusTypeDef status = HAL_ERROR; + HAL_StatusTypeDef status; uint32_t tickstart = HAL_GetTick(); /* Check the parameters */ @@ -1634,7 +1647,6 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTy if(hqspi->State == HAL_QSPI_STATE_READY) { - hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; /* Update state */ @@ -1679,6 +1691,7 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTy { status = HAL_BUSY; } + /* Process unlocked */ __HAL_UNLOCK(hqspi); @@ -1688,16 +1701,16 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTy /** * @brief Configure the QSPI Automatic Polling Mode in non-blocking mode. - * @param hqspi QSPI handle - * @param cmd structure that contains the command configuration information. - * @param cfg structure that contains the polling configuration information. + * @param hqspi : QSPI handle + * @param cmd : structure that contains the command configuration information. + * @param cfg : structure that contains the polling configuration information. * @note This function is used only in Automatic Polling Mode * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg) { - __IO uint32_t count = 0U; - HAL_StatusTypeDef status = HAL_OK; + HAL_StatusTypeDef status; + uint32_t tickstart = HAL_GetTick(); /* Check the parameters */ assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode)); @@ -1741,17 +1754,7 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_Comman hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING; /* Wait till BUSY flag reset */ - count = (hqspi->Timeout) * (SystemCoreClock / 16U / 1000U); - do - { - if (count-- == 0U) - { - hqspi->State = HAL_QSPI_STATE_ERROR; - hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT; - status = HAL_TIMEOUT; - } - } - while ((__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_BUSY)) != RESET); + status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout); if (status == HAL_OK) { @@ -1802,15 +1805,15 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_Comman /** * @brief Configure the Memory Mapped mode. - * @param hqspi QSPI handle - * @param cmd structure that contains the command configuration information. - * @param cfg structure that contains the memory mapped configuration information. + * @param hqspi : QSPI handle + * @param cmd : structure that contains the command configuration information. + * @param cfg : structure that contains the memory mapped configuration information. * @note This function is used only in Memory mapped Mode * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg) { - HAL_StatusTypeDef status = HAL_ERROR; + HAL_StatusTypeDef status; uint32_t tickstart = HAL_GetTick(); /* Check the parameters */ @@ -1890,8 +1893,8 @@ HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandT } /** - * @brief Transfer Error callbacks - * @param hqspi QSPI handle + * @brief Transfer Error callback. + * @param hqspi : QSPI handle * @retval None */ __weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi) @@ -1899,14 +1902,14 @@ __weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi) /* Prevent unused argument(s) compilation warning */ UNUSED(hqspi); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_QSPI_ErrorCallback could be implemented in the user file */ } /** * @brief Abort completed callback. - * @param hqspi QSPI handle + * @param hqspi : QSPI handle * @retval None */ __weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi) @@ -1921,7 +1924,7 @@ __weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Command completed callback. - * @param hqspi QSPI handle + * @param hqspi : QSPI handle * @retval None */ __weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi) @@ -1929,14 +1932,14 @@ __weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi) /* Prevent unused argument(s) compilation warning */ UNUSED(hqspi); - /* NOTE: This function Should not be modified, when the callback is needed, + /* NOTE: This function should not be modified, when the callback is needed, the HAL_QSPI_CmdCpltCallback could be implemented in the user file */ } /** - * @brief Rx Transfer completed callbacks. - * @param hqspi QSPI handle + * @brief Rx Transfer completed callback. + * @param hqspi : QSPI handle * @retval None */ __weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi) @@ -1944,29 +1947,29 @@ __weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi) /* Prevent unused argument(s) compilation warning */ UNUSED(hqspi); - /* NOTE: This function Should not be modified, when the callback is needed, + /* NOTE: This function should not be modified, when the callback is needed, the HAL_QSPI_RxCpltCallback could be implemented in the user file */ } /** - * @brief Tx Transfer completed callbacks. - * @param hqspi QSPI handle + * @brief Tx Transfer completed callback. + * @param hqspi : QSPI handle * @retval None */ - __weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi) +__weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi) { /* Prevent unused argument(s) compilation warning */ UNUSED(hqspi); - /* NOTE: This function Should not be modified, when the callback is needed, + /* NOTE: This function should not be modified, when the callback is needed, the HAL_QSPI_TxCpltCallback could be implemented in the user file */ } /** - * @brief Rx Half Transfer completed callbacks. - * @param hqspi QSPI handle + * @brief Rx Half Transfer completed callback. + * @param hqspi : QSPI handle * @retval None */ __weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi) @@ -1974,29 +1977,29 @@ __weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi) /* Prevent unused argument(s) compilation warning */ UNUSED(hqspi); - /* NOTE: This function Should not be modified, when the callback is needed, + /* NOTE: This function should not be modified, when the callback is needed, the HAL_QSPI_RxHalfCpltCallback could be implemented in the user file */ } /** - * @brief Tx Half Transfer completed callbacks. - * @param hqspi QSPI handle + * @brief Tx Half Transfer completed callback. + * @param hqspi : QSPI handle * @retval None */ - __weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi) +__weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi) { /* Prevent unused argument(s) compilation warning */ UNUSED(hqspi); - /* NOTE: This function Should not be modified, when the callback is needed, + /* NOTE: This function should not be modified, when the callback is needed, the HAL_QSPI_TxHalfCpltCallback could be implemented in the user file */ } /** - * @brief FIFO Threshold callbacks - * @param hqspi QSPI handle + * @brief FIFO Threshold callback. + * @param hqspi : QSPI handle * @retval None */ __weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi) @@ -2004,14 +2007,14 @@ __weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi) /* Prevent unused argument(s) compilation warning */ UNUSED(hqspi); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_QSPI_FIFOThresholdCallback could be implemented in the user file */ } /** - * @brief Status Match callbacks - * @param hqspi QSPI handle + * @brief Status Match callback. + * @param hqspi : QSPI handle * @retval None */ __weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi) @@ -2019,14 +2022,14 @@ __weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi) /* Prevent unused argument(s) compilation warning */ UNUSED(hqspi); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_QSPI_StatusMatchCallback could be implemented in the user file */ } /** - * @brief Timeout callbacks - * @param hqspi QSPI handle + * @brief Timeout callback. + * @param hqspi : QSPI handle * @retval None */ __weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi) @@ -2034,7 +2037,7 @@ __weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi) /* Prevent unused argument(s) compilation warning */ UNUSED(hqspi); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_QSPI_TimeOutCallback could be implemented in the user file */ } @@ -2277,13 +2280,14 @@ HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QS (+) Check the error code set during last operation. (+) Abort any operation. + @endverbatim * @{ */ /** * @brief Return the QSPI handle state. - * @param hqspi QSPI handle + * @param hqspi : QSPI handle * @retval HAL state */ HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi) @@ -2293,8 +2297,8 @@ HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi) } /** -* @brief Return the QSPI error code -* @param hqspi QSPI handle +* @brief Return the QSPI error code. +* @param hqspi : QSPI handle * @retval QSPI Error Code */ uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi) @@ -2303,8 +2307,8 @@ uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi) } /** -* @brief Abort the current transmission -* @param hqspi QSPI handle +* @brief Abort the current transmission. +* @param hqspi : QSPI handle * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi) @@ -2313,12 +2317,12 @@ HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi) uint32_t tickstart = HAL_GetTick(); /* Check if the state is in one of the busy states */ - if ((hqspi->State & 0x2U) != 0U) + if (((uint32_t)hqspi->State & 0x2U) != 0U) { /* Process unlocked */ __HAL_UNLOCK(hqspi); - if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET) + if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U) { /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */ CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); @@ -2337,7 +2341,7 @@ HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi) /* Wait until TC flag is set to go back in idle state */ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, hqspi->Timeout); - if(status == HAL_OK) + if (status == HAL_OK) { __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); @@ -2347,6 +2351,9 @@ HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi) if (status == HAL_OK) { + /* Reset functional mode configuration to indirect write mode by default */ + CLEAR_BIT(hqspi->Instance->CCR, QUADSPI_CCR_FMODE); + /* Update state */ hqspi->State = HAL_QSPI_STATE_READY; } @@ -2357,7 +2364,7 @@ HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi) /** * @brief Abort the current transmission (non-blocking function) -* @param hqspi QSPI handle +* @param hqspi : QSPI handle * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi) @@ -2365,7 +2372,7 @@ HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi) HAL_StatusTypeDef status = HAL_OK; /* Check if the state is in one of the busy states */ - if ((hqspi->State & 0x2U) != 0U) + if (((uint32_t)hqspi->State & 0x2U) != 0U) { /* Process unlocked */ __HAL_UNLOCK(hqspi); @@ -2376,7 +2383,7 @@ HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi) /* Disable all interrupts */ __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_TO | QSPI_IT_SM | QSPI_IT_FT | QSPI_IT_TC | QSPI_IT_TE)); - if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET) + if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U) { /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */ CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); @@ -2408,13 +2415,12 @@ HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi) SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT); } } - return status; } -/** @brief Set QSPI timeout - * @param hqspi QSPI handle. - * @param Timeout Timeout for the QSPI memory access. +/** @brief Set QSPI timeout. + * @param hqspi : QSPI handle. + * @param Timeout : Timeout for the QSPI memory access. * @retval None */ void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout) @@ -2423,8 +2429,8 @@ void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout) } /** @brief Set QSPI Fifo threshold. - * @param hqspi QSPI handle. - * @param Threshold Threshold of the Fifo (value between 1 and 16). + * @param hqspi : QSPI handle. + * @param Threshold : Threshold of the Fifo (value between 1 and 16). * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold) @@ -2456,7 +2462,7 @@ HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t } /** @brief Get QSPI Fifo threshold. - * @param hqspi QSPI handle. + * @param hqspi : QSPI handle. * @retval Fifo threshold (value between 1 and 16) */ uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi) @@ -2464,20 +2470,63 @@ uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi) return ((READ_BIT(hqspi->Instance->CR, QUADSPI_CR_FTHRES) >> QUADSPI_CR_FTHRES_Pos) + 1U); } +/** @brief Set FlashID. + * @param hqspi : QSPI handle. + * @param FlashID : Index of the flash memory to be accessed. + * This parameter can be a value of @ref QSPI_Flash_Select. + * @note The FlashID is ignored when dual flash mode is enabled. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_QSPI_SetFlashID(QSPI_HandleTypeDef *hqspi, uint32_t FlashID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameter */ + assert_param(IS_QSPI_FLASH_ID(FlashID)); + + /* Process locked */ + __HAL_LOCK(hqspi); + + if(hqspi->State == HAL_QSPI_STATE_READY) + { + /* Synchronize init structure with new FlashID value */ + hqspi->Init.FlashID = FlashID; + + /* Configure QSPI FlashID */ + MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FSEL, FlashID); + } + else + { + status = HAL_BUSY; + } + + /* Process unlocked */ + __HAL_UNLOCK(hqspi); + + /* Return function status */ + return status; +} + +/** + * @} + */ + /** * @} */ -/* Private functions ---------------------------------------------------------*/ +/** @defgroup QSPI_Private_Functions QSPI Private Functions + * @{ + */ /** * @brief DMA QSPI receive process complete callback. - * @param hdma DMA handle + * @param hdma : DMA handle * @retval None */ static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma) { - QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent); hqspi->RxXferCount = 0U; /* Enable the QSPI transfer complete Interrupt */ @@ -2486,12 +2535,12 @@ static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA QSPI transmit process complete callback. - * @param hdma DMA handle + * @param hdma : DMA handle * @retval None */ static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma) { - QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent); hqspi->TxXferCount = 0U; /* Enable the QSPI transfer complete Interrupt */ @@ -2499,13 +2548,13 @@ static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma) } /** - * @brief DMA QSPI receive process half complete callback - * @param hdma DMA handle + * @brief DMA QSPI receive process half complete callback. + * @param hdma : DMA handle * @retval None */ static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma) { - QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent); #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) hqspi->RxHalfCpltCallback(hqspi); @@ -2515,13 +2564,13 @@ static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma) } /** - * @brief DMA QSPI transmit process half complete callback - * @param hdma DMA handle + * @brief DMA QSPI transmit process half complete callback. + * @param hdma : DMA handle * @retval None */ static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma) { - QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent); #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) hqspi->TxHalfCpltCallback(hqspi); @@ -2532,36 +2581,37 @@ static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA QSPI communication error callback. - * @param hdma DMA handle + * @param hdma : DMA handle * @retval None */ static void QSPI_DMAError(DMA_HandleTypeDef *hdma) { - QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )(hdma->Parent); /* if DMA error is FIFO error ignore it */ if(HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE) { - hqspi->RxXferCount = 0U; - hqspi->TxXferCount = 0U; - hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; + hqspi->RxXferCount = 0U; + hqspi->TxXferCount = 0U; + hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; - /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */ - CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); + /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */ + CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); + + /* Abort the QSPI */ + (void)HAL_QSPI_Abort_IT(hqspi); - /* Abort the QSPI */ - HAL_QSPI_Abort_IT(hqspi); } } /** * @brief DMA QSPI abort complete callback. - * @param hdma DMA handle + * @param hdma : DMA handle * @retval None */ static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma) { - QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )(hdma->Parent); hqspi->RxXferCount = 0U; hqspi->TxXferCount = 0U; @@ -2585,28 +2635,33 @@ static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma) hqspi->State = HAL_QSPI_STATE_READY; /* Error callback */ +#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) + hqspi->ErrorCallback(hqspi); +#else HAL_QSPI_ErrorCallback(hqspi); +#endif } } + /** * @brief Wait for a flag state until timeout. - * @param hqspi QSPI handle - * @param Flag Flag checked - * @param State Value of the flag expected - * @param Timeout Duration of the time out - * @param tickstart tick start value + * @param hqspi : QSPI handle + * @param Flag : Flag checked + * @param State : Value of the flag expected + * @param Tickstart : Tick start value + * @param Timeout : Duration of the timeout * @retval HAL status */ static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, - FlagStatus State, uint32_t tickstart, uint32_t Timeout) + FlagStatus State, uint32_t Tickstart, uint32_t Timeout) { /* Wait until flag is in expected state */ - while((FlagStatus)(__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State) + while((__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State) { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) + if(((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { hqspi->State = HAL_QSPI_STATE_ERROR; hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT; @@ -2620,9 +2675,9 @@ static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqsp /** * @brief Configure the communication registers. - * @param hqspi QSPI handle - * @param cmd structure that contains the command configuration information - * @param FunctionalMode functional mode to configured + * @param hqspi : QSPI handle + * @param cmd : structure that contains the command configuration information + * @param FunctionalMode : functional mode to configured * This parameter can be one of the following values: * @arg QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE: Indirect write mode * @arg QSPI_FUNCTIONAL_MODE_INDIRECT_READ: Indirect read mode @@ -2652,9 +2707,10 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin /*---- Command with instruction, address and alternate bytes ----*/ /* Configure QSPI: CCR register with all communications parameters */ WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | - cmd->DataMode | (cmd->DummyCycles << 18U) | cmd->AlternateBytesSize | - cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMode | - cmd->InstructionMode | cmd->Instruction | FunctionalMode)); + cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | + cmd->AlternateBytesSize | cmd->AlternateByteMode | + cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode | + cmd->Instruction | FunctionalMode)); if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED) { @@ -2667,8 +2723,9 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin /*---- Command with instruction and alternate bytes ----*/ /* Configure QSPI: CCR register with all communications parameters */ WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | - cmd->DataMode | (cmd->DummyCycles << 18U) | cmd->AlternateBytesSize | - cmd->AlternateByteMode | cmd->AddressMode | cmd->InstructionMode | + cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | + cmd->AlternateBytesSize | cmd->AlternateByteMode | + cmd->AddressMode | cmd->InstructionMode | cmd->Instruction | FunctionalMode)); } } @@ -2679,9 +2736,9 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin /*---- Command with instruction and address ----*/ /* Configure QSPI: CCR register with all communications parameters */ WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | - cmd->DataMode | (cmd->DummyCycles << 18U) | cmd->AlternateByteMode | - cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode | - cmd->Instruction | FunctionalMode)); + cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | + cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMode | + cmd->InstructionMode | cmd->Instruction | FunctionalMode)); if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED) { @@ -2694,9 +2751,9 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin /*---- Command with only instruction ----*/ /* Configure QSPI: CCR register with all communications parameters */ WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | - cmd->DataMode | (cmd->DummyCycles << 18U) | cmd->AlternateByteMode | - cmd->AddressMode | cmd->InstructionMode | cmd->Instruction | - FunctionalMode)); + cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | + cmd->AlternateByteMode | cmd->AddressMode | + cmd->InstructionMode | cmd->Instruction | FunctionalMode)); } } } @@ -2712,8 +2769,9 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin /*---- Command with address and alternate bytes ----*/ /* Configure QSPI: CCR register with all communications parameters */ WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | - cmd->DataMode | (cmd->DummyCycles << 18U) | cmd->AlternateBytesSize | - cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMode | + cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | + cmd->AlternateBytesSize | cmd->AlternateByteMode | + cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode | FunctionalMode)); if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED) @@ -2727,9 +2785,9 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin /*---- Command with only alternate bytes ----*/ /* Configure QSPI: CCR register with all communications parameters */ WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | - cmd->DataMode | (cmd->DummyCycles << 18U) | cmd->AlternateBytesSize | - cmd->AlternateByteMode | cmd->AddressMode | cmd->InstructionMode | - FunctionalMode)); + cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | + cmd->AlternateBytesSize | cmd->AlternateByteMode | + cmd->AddressMode | cmd->InstructionMode | FunctionalMode)); } } else @@ -2739,9 +2797,9 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin /*---- Command with only address ----*/ /* Configure QSPI: CCR register with all communications parameters */ WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | - cmd->DataMode | (cmd->DummyCycles << 18U) | cmd->AlternateByteMode | - cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode | - FunctionalMode)); + cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | + cmd->AlternateByteMode | cmd->AddressSize | + cmd->AddressMode | cmd->InstructionMode | FunctionalMode)); if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED) { @@ -2756,18 +2814,22 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin { /* Configure QSPI: CCR register with all communications parameters */ WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | - cmd->DataMode | (cmd->DummyCycles << 18U) | cmd->AlternateByteMode | - cmd->AddressMode | cmd->InstructionMode | FunctionalMode)); + cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | + cmd->AlternateByteMode | cmd->AddressMode | + cmd->InstructionMode | FunctionalMode)); } } } } } + +/** + * @} + */ + /** * @} */ -#endif /* STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx - STM32F413xx || STM32F423xx */ #endif /* HAL_QSPI_MODULE_ENABLED */ /** @@ -2778,4 +2840,6 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin * @} */ +#endif /* defined(QUADSPI) || defined(QUADSPI1) || defined(QUADSPI2) */ + /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c index 1857df2288..7640b65f4f 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c @@ -539,7 +539,7 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc else { /* Do not return HAL_ERROR if request repeats the current configuration */ - pll_config = RCC->CFGR; + pll_config = RCC->PLLCFGR; if((READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) || (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != RCC_OscInitStruct->PLL.PLLN) || diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c index d16667467d..99531f7178 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c @@ -2710,8 +2710,17 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) } #endif /* USE_SPI_CRC */ - /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */ - CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); + /* Check if we are in Master RX 2 line mode */ + if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) + { + /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); + } + else + { + /* Normal case */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + } /* Check the end of the transaction */ if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fmpi2c.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fmpi2c.c new file mode 100644 index 0000000000..7d7aeaaf82 --- /dev/null +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fmpi2c.c @@ -0,0 +1,220 @@ +/** + ****************************************************************************** + * @file stm32f4xx_ll_fmpi2c.c + * @author MCD Application Team + * @brief FMPI2C LL module driver. + ****************************************************************************** + * @attention + * + *

    © Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

    + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +#if defined(FMPI2C_CR1_PE) +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_ll_fmpi2c.h" +#include "stm32f4xx_ll_bus.h" +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif + +/** @addtogroup STM32F4xx_LL_Driver + * @{ + */ + +#if defined (FMPI2C1) + +/** @defgroup FMPI2C_LL FMPI2C + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup FMPI2C_LL_Private_Macros + * @{ + */ + +#define IS_LL_FMPI2C_PERIPHERAL_MODE(__VALUE__) (((__VALUE__) == LL_FMPI2C_MODE_I2C) || \ + ((__VALUE__) == LL_FMPI2C_MODE_SMBUS_HOST) || \ + ((__VALUE__) == LL_FMPI2C_MODE_SMBUS_DEVICE) || \ + ((__VALUE__) == LL_FMPI2C_MODE_SMBUS_DEVICE_ARP)) + +#define IS_LL_FMPI2C_ANALOG_FILTER(__VALUE__) (((__VALUE__) == LL_FMPI2C_ANALOGFILTER_ENABLE) || \ + ((__VALUE__) == LL_FMPI2C_ANALOGFILTER_DISABLE)) + +#define IS_LL_FMPI2C_DIGITAL_FILTER(__VALUE__) ((__VALUE__) <= 0x0000000FU) + +#define IS_LL_FMPI2C_OWN_ADDRESS1(__VALUE__) ((__VALUE__) <= 0x000003FFU) + +#define IS_LL_FMPI2C_TYPE_ACKNOWLEDGE(__VALUE__) (((__VALUE__) == LL_FMPI2C_ACK) || \ + ((__VALUE__) == LL_FMPI2C_NACK)) + +#define IS_LL_FMPI2C_OWN_ADDRSIZE(__VALUE__) (((__VALUE__) == LL_FMPI2C_OWNADDRESS1_7BIT) || \ + ((__VALUE__) == LL_FMPI2C_OWNADDRESS1_10BIT)) +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup FMPI2C_LL_Exported_Functions + * @{ + */ + +/** @addtogroup FMPI2C_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize the FMPI2C registers to their default reset values. + * @param FMPI2Cx FMPI2C Instance. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: FMPI2C registers are de-initialized + * - ERROR: FMPI2C registers are not de-initialized + */ +ErrorStatus LL_FMPI2C_DeInit(FMPI2C_TypeDef *FMPI2Cx) +{ + ErrorStatus status = SUCCESS; + + /* Check the FMPI2C Instance FMPI2Cx */ + assert_param(IS_FMPI2C_ALL_INSTANCE(FMPI2Cx)); + + if (FMPI2Cx == FMPI2C1) + { + /* Force reset of FMPI2C clock */ + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_FMPI2C1); + + /* Release reset of FMPI2C clock */ + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_FMPI2C1); + } + else + { + status = ERROR; + } + + return status; +} + +/** + * @brief Initialize the FMPI2C registers according to the specified parameters in FMPI2C_InitStruct. + * @param FMPI2Cx FMPI2C Instance. + * @param FMPI2C_InitStruct pointer to a @ref LL_FMPI2C_InitTypeDef structure. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: FMPI2C registers are initialized + * - ERROR: Not applicable + */ +ErrorStatus LL_FMPI2C_Init(FMPI2C_TypeDef *FMPI2Cx, LL_FMPI2C_InitTypeDef *FMPI2C_InitStruct) +{ + /* Check the FMPI2C Instance FMPI2Cx */ + assert_param(IS_FMPI2C_ALL_INSTANCE(FMPI2Cx)); + + /* Check the FMPI2C parameters from FMPI2C_InitStruct */ + assert_param(IS_LL_FMPI2C_PERIPHERAL_MODE(FMPI2C_InitStruct->PeripheralMode)); + assert_param(IS_LL_FMPI2C_ANALOG_FILTER(FMPI2C_InitStruct->AnalogFilter)); + assert_param(IS_LL_FMPI2C_DIGITAL_FILTER(FMPI2C_InitStruct->DigitalFilter)); + assert_param(IS_LL_FMPI2C_OWN_ADDRESS1(FMPI2C_InitStruct->OwnAddress1)); + assert_param(IS_LL_FMPI2C_TYPE_ACKNOWLEDGE(FMPI2C_InitStruct->TypeAcknowledge)); + assert_param(IS_LL_FMPI2C_OWN_ADDRSIZE(FMPI2C_InitStruct->OwnAddrSize)); + + /* Disable the selected FMPI2Cx Peripheral */ + LL_FMPI2C_Disable(FMPI2Cx); + + /*---------------------------- FMPI2Cx CR1 Configuration ------------------------ + * Configure the analog and digital noise filters with parameters : + * - AnalogFilter: FMPI2C_CR1_ANFOFF bit + * - DigitalFilter: FMPI2C_CR1_DNF[3:0] bits + */ + LL_FMPI2C_ConfigFilters(FMPI2Cx, FMPI2C_InitStruct->AnalogFilter, FMPI2C_InitStruct->DigitalFilter); + + /*---------------------------- FMPI2Cx TIMINGR Configuration -------------------- + * Configure the SDA setup, hold time and the SCL high, low period with parameter : + * - Timing: FMPI2C_TIMINGR_PRESC[3:0], FMPI2C_TIMINGR_SCLDEL[3:0], FMPI2C_TIMINGR_SDADEL[3:0], + * FMPI2C_TIMINGR_SCLH[7:0] and FMPI2C_TIMINGR_SCLL[7:0] bits + */ + LL_FMPI2C_SetTiming(FMPI2Cx, FMPI2C_InitStruct->Timing); + + /* Enable the selected FMPI2Cx Peripheral */ + LL_FMPI2C_Enable(FMPI2Cx); + + /*---------------------------- FMPI2Cx OAR1 Configuration ----------------------- + * Disable, Configure and Enable FMPI2Cx device own address 1 with parameters : + * - OwnAddress1: FMPI2C_OAR1_OA1[9:0] bits + * - OwnAddrSize: FMPI2C_OAR1_OA1MODE bit + */ + LL_FMPI2C_DisableOwnAddress1(FMPI2Cx); + LL_FMPI2C_SetOwnAddress1(FMPI2Cx, FMPI2C_InitStruct->OwnAddress1, FMPI2C_InitStruct->OwnAddrSize); + + /* OwnAdress1 == 0 is reserved for General Call address */ + if (FMPI2C_InitStruct->OwnAddress1 != 0U) + { + LL_FMPI2C_EnableOwnAddress1(FMPI2Cx); + } + + /*---------------------------- FMPI2Cx MODE Configuration ----------------------- + * Configure FMPI2Cx peripheral mode with parameter : + * - PeripheralMode: FMPI2C_CR1_SMBDEN and FMPI2C_CR1_SMBHEN bits + */ + LL_FMPI2C_SetMode(FMPI2Cx, FMPI2C_InitStruct->PeripheralMode); + + /*---------------------------- FMPI2Cx CR2 Configuration ------------------------ + * Configure the ACKnowledge or Non ACKnowledge condition + * after the address receive match code or next received byte with parameter : + * - TypeAcknowledge: FMPI2C_CR2_NACK bit + */ + LL_FMPI2C_AcknowledgeNextData(FMPI2Cx, FMPI2C_InitStruct->TypeAcknowledge); + + return SUCCESS; +} + +/** + * @brief Set each @ref LL_FMPI2C_InitTypeDef field to default value. + * @param FMPI2C_InitStruct Pointer to a @ref LL_FMPI2C_InitTypeDef structure. + * @retval None + */ +void LL_FMPI2C_StructInit(LL_FMPI2C_InitTypeDef *FMPI2C_InitStruct) +{ + /* Set FMPI2C_InitStruct fields to default values */ + FMPI2C_InitStruct->PeripheralMode = LL_FMPI2C_MODE_I2C; + FMPI2C_InitStruct->Timing = 0U; + FMPI2C_InitStruct->AnalogFilter = LL_FMPI2C_ANALOGFILTER_ENABLE; + FMPI2C_InitStruct->DigitalFilter = 0U; + FMPI2C_InitStruct->OwnAddress1 = 0U; + FMPI2C_InitStruct->TypeAcknowledge = LL_FMPI2C_NACK; + FMPI2C_InitStruct->OwnAddrSize = LL_FMPI2C_OWNADDRESS1_7BIT; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* FMPI2C1 */ + +/** + * @} + */ + +#endif /* FMPI2C_CR1_PE */ +#endif /* USE_FULL_LL_DRIVER */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c index 9263fc3183..8e7c747294 100644 --- a/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c +++ b/system/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c @@ -290,6 +290,8 @@ HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cf /* VBUS Sensing setup */ if (cfg.vbus_sensing_enable == 0U) { + USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS; + /* Deactivate VBUS Sensing B */ USBx->GCCFG &= ~USB_OTG_GCCFG_VBDEN; @@ -310,6 +312,7 @@ HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cf * Disable HW VBUS sensing. VBUS is internally considered to be always * at VBUS-Valid level (5V). */ + USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS; USBx->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS; USBx->GCCFG &= ~USB_OTG_GCCFG_VBUSBSEN; USBx->GCCFG &= ~USB_OTG_GCCFG_VBUSASEN; @@ -317,7 +320,7 @@ HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cf else { /* Enable HW VBUS sensing */ - USBx->GOTGCTL &= ~USB_OTG_GCCFG_NOVBUSSENS; + USBx->GCCFG &= ~USB_OTG_GCCFG_NOVBUSSENS; USBx->GCCFG |= USB_OTG_GCCFG_VBUSBSEN; } #endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */ @@ -409,17 +412,6 @@ HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cf USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM); - if (cfg.dma_enable == 1U) - { - /*Set threshold parameters */ - USBx_DEVICE->DTHRCTL = USB_OTG_DTHRCTL_TXTHRLEN_6 | - USB_OTG_DTHRCTL_RXTHRLEN_6; - - USBx_DEVICE->DTHRCTL |= USB_OTG_DTHRCTL_RXTHREN | - USB_OTG_DTHRCTL_ISOTHREN | - USB_OTG_DTHRCTL_NONISOTHREN; - } - /* Disable all interrupts. */ USBx->GINTMSK = 0U; @@ -641,6 +633,12 @@ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EP /* Read DEPCTLn register */ if (ep->is_in == 1U) { + if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) + { + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK; + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_EPDIS; + } + USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_USBAEP | @@ -651,6 +649,12 @@ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EP } else { + if ((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) + { + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK; + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_EPDIS; + } + USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16)); USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16)); USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_USBAEP | @@ -676,11 +680,23 @@ HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, U /* Read DEPCTLn register */ if (ep->is_in == 1U) { + if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) + { + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK; + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_EPDIS; + } + USBx_INEP(epnum)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP; USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); } else { + if ((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) + { + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK; + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_EPDIS; + } + USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP; USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16)); } @@ -1247,13 +1263,9 @@ HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx) { uint32_t USBx_BASE = (uint32_t)USBx; - /* Set the MPS of the IN EP based on the enumeration speed */ + /* Set the MPS of the IN EP0 to 64 bytes */ USBx_INEP(0U)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ; - if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_LS_PHY_6MHZ) - { - USBx_INEP(0U)->DIEPCTL |= 3U; - } USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK; return HAL_OK; @@ -1367,7 +1379,7 @@ HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c if ((USBx->CID & (0x1U << 8)) != 0U) { - if (cfg.speed == USB_OTG_SPEED_FULL) + if (cfg.speed == USBH_FSLS_SPEED) { /* Force Device Enumeration to FS/LS mode only */ USBx_HOST->HCFG |= USB_OTG_HCFG_FSLSS; @@ -1936,7 +1948,6 @@ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx) uint32_t value; uint32_t i; - (void)USB_DisableGlobalInt(USBx); /* Flush FIFO */ @@ -1975,6 +1986,7 @@ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx) /* Clear any pending Host interrupts */ USBx_HOST->HAINT = 0xFFFFFFFFU; USBx->GINTSTS = 0xFFFFFFFFU; + (void)USB_EnableGlobalInt(USBx); return HAL_OK; diff --git a/system/Drivers/STM32F4xx_HAL_Driver/_htmresc/st_logo.png b/system/Drivers/STM32F4xx_HAL_Driver/_htmresc/st_logo.png index 1c29daab8c..8b80057fd3 100644 Binary files a/system/Drivers/STM32F4xx_HAL_Driver/_htmresc/st_logo.png and b/system/Drivers/STM32F4xx_HAL_Driver/_htmresc/st_logo.png differ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h index 889db8f18f..90767ed33b 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -7,7 +7,7 @@ ****************************************************************************** * @attention * - *

    © Copyright (c) 2018 STMicroelectronics. + *

    © Copyright (c) 2019 STMicroelectronics. * All rights reserved.

    * * This software component is licensed by ST under BSD 3-Clause license, @@ -236,6 +236,16 @@ #define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE #define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE +#if defined(STM32G4) || defined(STM32H7) +#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL +#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL +#endif + +#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) +#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID +#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID +#endif + /** * @} */ @@ -296,8 +306,17 @@ #define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING +#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI +#endif + #endif /* STM32L4 */ +#if defined(STM32G0) +#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1 +#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2 +#endif + #if defined(STM32H7) #define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1 @@ -355,6 +374,9 @@ #define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT #define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT +#define DAC_TRIGGER_LP1_OUT DAC_TRIGGER_LPTIM1_OUT +#define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT + #endif /* STM32H7 */ /** @@ -450,7 +472,9 @@ #define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2 #define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2 #define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2 -#endif +#define FLASH_FLAG_WDW FLASH_FLAG_WBNE +#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL +#endif /* STM32H7 */ /** * @} @@ -486,6 +510,13 @@ #define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1 #define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2 #define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3 +#if defined(STM32G4) + +#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOSwitchBooster +#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOSwitchBooster +#define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD +#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD +#endif /* STM32G4 */ /** * @} */ @@ -494,7 +525,7 @@ /** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose * @{ */ -#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) +#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4) #define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE #define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE #define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8 @@ -547,18 +578,25 @@ #define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2 #define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2 #define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2 -#endif + +#if defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) || defined (STM32H742xx) || \ + defined (STM32H745xx) || defined (STM32H755xx) || defined (STM32H747xx) || defined (STM32H757xx) +#define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS +#define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS +#define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS +#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */ +#endif /* STM32H7 */ #define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1 #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 -#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32H7) +#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM #define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH -#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32H7*/ +#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7*/ #if defined(STM32L1) #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW @@ -599,6 +637,185 @@ #define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER #define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE #define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE + +#if defined(STM32G4) +#define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig +#define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable +#define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable +#define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset +#endif /* STM32G4 */ + +#if defined(STM32H7) +#define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 + +#define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 +#endif /* STM32H7 */ + +#if defined(STM32F3) +/** @brief Constants defining available sources associated to external events. + */ +#define HRTIM_EVENTSRC_1 (0x00000000U) +#define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0) +#define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1) +#define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) + +/** @brief Constants defining the events that can be selected to configure the + * set/reset crossbar of a timer output + */ +#define HRTIM_OUTPUTSET_TIMEV_1 (HRTIM_SET1R_TIMEVNT1) +#define HRTIM_OUTPUTSET_TIMEV_2 (HRTIM_SET1R_TIMEVNT2) +#define HRTIM_OUTPUTSET_TIMEV_3 (HRTIM_SET1R_TIMEVNT3) +#define HRTIM_OUTPUTSET_TIMEV_4 (HRTIM_SET1R_TIMEVNT4) +#define HRTIM_OUTPUTSET_TIMEV_5 (HRTIM_SET1R_TIMEVNT5) +#define HRTIM_OUTPUTSET_TIMEV_6 (HRTIM_SET1R_TIMEVNT6) +#define HRTIM_OUTPUTSET_TIMEV_7 (HRTIM_SET1R_TIMEVNT7) +#define HRTIM_OUTPUTSET_TIMEV_8 (HRTIM_SET1R_TIMEVNT8) +#define HRTIM_OUTPUTSET_TIMEV_9 (HRTIM_SET1R_TIMEVNT9) + +#define HRTIM_OUTPUTRESET_TIMEV_1 (HRTIM_RST1R_TIMEVNT1) +#define HRTIM_OUTPUTRESET_TIMEV_2 (HRTIM_RST1R_TIMEVNT2) +#define HRTIM_OUTPUTRESET_TIMEV_3 (HRTIM_RST1R_TIMEVNT3) +#define HRTIM_OUTPUTRESET_TIMEV_4 (HRTIM_RST1R_TIMEVNT4) +#define HRTIM_OUTPUTRESET_TIMEV_5 (HRTIM_RST1R_TIMEVNT5) +#define HRTIM_OUTPUTRESET_TIMEV_6 (HRTIM_RST1R_TIMEVNT6) +#define HRTIM_OUTPUTRESET_TIMEV_7 (HRTIM_RST1R_TIMEVNT7) +#define HRTIM_OUTPUTRESET_TIMEV_8 (HRTIM_RST1R_TIMEVNT8) +#define HRTIM_OUTPUTRESET_TIMEV_9 (HRTIM_RST1R_TIMEVNT9) + +/** @brief Constants defining the event filtering applied to external events + * by a timer + */ +#define HRTIM_TIMEVENTFILTER_NONE (0x00000000U) +#define HRTIM_TIMEVENTFILTER_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0) +#define HRTIM_TIMEVENTFILTER_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1) +#define HRTIM_TIMEVENTFILTER_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) +#define HRTIM_TIMEVENTFILTER_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2) +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3) +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) +#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) +#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) +#define HRTIM_TIMEVENTFILTER_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) + +/** @brief Constants defining the DLL calibration periods (in micro seconds) + */ +#define HRTIM_CALIBRATIONRATE_7300 0x00000000U +#define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) +#define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) +#define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) + +#endif /* STM32F3 */ /** * @} */ @@ -738,6 +955,12 @@ #define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 #define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 +#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) +#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID +#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID +#endif + + /** * @} */ @@ -753,7 +976,6 @@ #define I2S_FLAG_TXE I2S_FLAG_TXP #define I2S_FLAG_RXNE I2S_FLAG_RXP - #define I2S_FLAG_FRE I2S_FLAG_TIFRE #endif #if defined(STM32F7) @@ -824,6 +1046,16 @@ #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 +#if defined(STM32H7) +#define RTC_TAMPCR_TAMPXE RTC_TAMPER_X +#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT + +#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1 +#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2 +#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3 +#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMPALL +#endif /* STM32H7 */ + /** * @} */ @@ -971,6 +1203,24 @@ #define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE #endif +#if defined(STM32H7) +#define TIM_TIM1_ETR_COMP1_OUT TIM_TIM1_ETR_COMP1 +#define TIM_TIM1_ETR_COMP2_OUT TIM_TIM1_ETR_COMP2 +#define TIM_TIM8_ETR_COMP1_OUT TIM_TIM8_ETR_COMP1 +#define TIM_TIM8_ETR_COMP2_OUT TIM_TIM8_ETR_COMP2 +#define TIM_TIM2_ETR_COMP1_OUT TIM_TIM2_ETR_COMP1 +#define TIM_TIM2_ETR_COMP2_OUT TIM_TIM2_ETR_COMP2 +#define TIM_TIM3_ETR_COMP1_OUT TIM_TIM3_ETR_COMP1 +#define TIM_TIM1_TI1_COMP1_OUT TIM_TIM1_TI1_COMP1 +#define TIM_TIM8_TI1_COMP2_OUT TIM_TIM8_TI1_COMP2 +#define TIM_TIM2_TI4_COMP1_OUT TIM_TIM2_TI4_COMP1 +#define TIM_TIM2_TI4_COMP2_OUT TIM_TIM2_TI4_COMP2 +#define TIM_TIM2_TI4_COMP1COMP2_OUT TIM_TIM2_TI4_COMP1_COMP2 +#define TIM_TIM3_TI1_COMP1_OUT TIM_TIM3_TI1_COMP1 +#define TIM_TIM3_TI1_COMP2_OUT TIM_TIM3_TI1_COMP2 +#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2 +#endif + /** * @} */ @@ -1199,6 +1449,30 @@ #define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY #define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY + +#if defined(STM32L4) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7) + +#define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt +#define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End +#define HAL_HASH_MD5_Accumulate_IT HAL_HASH_MD5_Accmlt_IT +#define HAL_HASH_MD5_Accumulate_End_IT HAL_HASH_MD5_Accmlt_End_IT + +#define HAL_HASH_SHA1_Accumulate HAL_HASH_SHA1_Accmlt +#define HAL_HASH_SHA1_Accumulate_End HAL_HASH_SHA1_Accmlt_End +#define HAL_HASH_SHA1_Accumulate_IT HAL_HASH_SHA1_Accmlt_IT +#define HAL_HASH_SHA1_Accumulate_End_IT HAL_HASH_SHA1_Accmlt_End_IT + +#define HAL_HASHEx_SHA224_Accumulate HAL_HASHEx_SHA224_Accmlt +#define HAL_HASHEx_SHA224_Accumulate_End HAL_HASHEx_SHA224_Accmlt_End +#define HAL_HASHEx_SHA224_Accumulate_IT HAL_HASHEx_SHA224_Accmlt_IT +#define HAL_HASHEx_SHA224_Accumulate_End_IT HAL_HASHEx_SHA224_Accmlt_End_IT + +#define HAL_HASHEx_SHA256_Accumulate HAL_HASHEx_SHA256_Accmlt +#define HAL_HASHEx_SHA256_Accumulate_End HAL_HASHEx_SHA256_Accmlt_End +#define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT +#define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT + +#endif /* STM32L4 || STM32F4 || STM32F7 || STM32H7 */ /** * @} */ @@ -1221,6 +1495,13 @@ #endif #define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) #define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor()) +#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ) +#define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode +#define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode +#define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode +#define HAL_DisableSRDomainDBGStandbyMode HAL_DisableDomain3DBGStandbyMode +#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ || STM32H7B0xxQ */ + /** * @} */ @@ -1250,16 +1531,18 @@ #define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) -#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) #define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT #define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT #define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT #define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT +#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 */ +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) #define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA #define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA #define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA #define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA -#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 */ +#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 */ #if defined(STM32F4) #define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT @@ -1278,6 +1561,13 @@ /** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose * @{ */ + +#if defined(STM32G0) +#define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD +#define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD +#define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD +#define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler +#endif #define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD #define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg #define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown @@ -1350,14 +1640,14 @@ #define HAL_TIM_DMAError TIM_DMAError #define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt #define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt -#if defined(STM32H7) || defined(STM32G0) || defined(STM32F7) || defined(STM32F4) || defined(STM32L0) +#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) #define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro #define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT #define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback #define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent #define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT #define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA -#endif /* STM32H7 || STM32G0 || STM32F7 || STM32F4 || STM32L0 */ +#endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */ /** * @} */ @@ -2476,12 +2766,28 @@ #define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE #define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE #define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET + +#if defined(STM32H7) +#define __HAL_RCC_WWDG_CLK_DISABLE __HAL_RCC_WWDG1_CLK_DISABLE +#define __HAL_RCC_WWDG_CLK_ENABLE __HAL_RCC_WWDG1_CLK_ENABLE +#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE +#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE + +#define __HAL_RCC_WWDG_FORCE_RESET ((void)0U) /* Not available on the STM32H7*/ +#define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/ + + +#define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED +#define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED +#endif + #define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE #define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE #define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE #define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE #define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET #define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET + #define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE #define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE #define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET @@ -2814,6 +3120,15 @@ #define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED #define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED +#if defined(STM32L1) +#define __HAL_RCC_CRYP_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE +#define __HAL_RCC_CRYP_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE +#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE +#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE +#define __HAL_RCC_CRYP_FORCE_RESET __HAL_RCC_AES_FORCE_RESET +#define __HAL_RCC_CRYP_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET +#endif /* STM32L1 */ + #if defined(STM32F4) #define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET #define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET @@ -2930,7 +3245,7 @@ #if defined(STM32L4) #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE -#elif defined(STM32WB) || defined(STM32G0) +#elif defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) #else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK #endif @@ -3058,7 +3373,7 @@ /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose * @{ */ -#if defined (STM32G0) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) +#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) #else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #endif @@ -3174,14 +3489,14 @@ #define SDIO_IRQHandler SDMMC1_IRQHandler #endif -#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) +#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7) #define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef #define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef #define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef #define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef #endif -#if defined(STM32H7) +#if defined(STM32H7) || defined(STM32L5) #define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback #define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback #define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback @@ -3421,18 +3736,28 @@ /** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose * @{ */ -#if defined (STM32H7) || defined (STM32F3) -#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT -#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA -#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart -#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT -#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA -#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop +#if defined (STM32H7) || defined (STM32G4) || defined (STM32F3) +#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT +#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA +#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart +#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT +#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA +#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop #endif /** * @} */ +/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) +#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE +#endif /* STM32L4 || STM32F4 || STM32F7 */ +/** + * @} + */ + /** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose * @{ */ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32f7xx_hal_can_legacy.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32f7xx_hal_can_legacy.h index 76b6385d48..1a1697a14d 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32f7xx_hal_can_legacy.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32f7xx_hal_can_legacy.h @@ -6,13 +6,29 @@ ****************************************************************************** * @attention * - *

    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

    + *

    © COPYRIGHT(c) 2017 STMicroelectronics

    * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** */ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h index c57cdb2a69..86bbbd01f3 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h @@ -18,8 +18,8 @@ */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F7xx_ADC_H -#define __STM32F7xx_ADC_H +#ifndef STM32F7xx_ADC_H +#define STM32F7xx_ADC_H #ifdef __cplusplus extern "C" { @@ -416,8 +416,10 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to #define ADC_CHANNEL_17 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0)) #define ADC_CHANNEL_18 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1)) +#define ADC_INTERNAL_NONE 0x80000000U #define ADC_CHANNEL_VREFINT ((uint32_t)ADC_CHANNEL_17) #define ADC_CHANNEL_VBAT ((uint32_t)ADC_CHANNEL_18) +#define ADC_CHANNEL_TEMPSENSOR ((uint32_t)(ADC_CHANNEL_18 | 0x10000000U)) /** * @} */ @@ -732,6 +734,10 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); */ #define ADC_CLEAR_ERRORCODE(__HANDLE__) \ ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) + +#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) <= ADC_CHANNEL_18) || \ + ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR) || \ + ((CHANNEL) == ADC_INTERNAL_NONE)) #define IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__) (((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV2) || \ ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV4) || \ ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV6) || \ @@ -947,7 +953,7 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); } #endif -#endif /*__STM32F7xx_ADC_H */ +#endif /* STM32F7xx_ADC_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h index c53e7639f4..85577478f0 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h @@ -18,8 +18,8 @@ */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F7xx_ADC_EX_H -#define __STM32F7xx_ADC_EX_H +#ifndef STM32F7xx_ADC_EX_H +#define STM32F7xx_ADC_EX_H #ifdef __cplusplus extern "C" { @@ -210,7 +210,7 @@ typedef struct /** @defgroup ADCEx_channels ADC Specific Channels * @{ */ -#define ADC_CHANNEL_TEMPSENSOR ((uint32_t)ADC_CHANNEL_18 | 0x10000000U) + /** * @} */ @@ -274,8 +274,6 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_ /** @defgroup ADCEx_Private_Macros ADC Private Macros * @{ */ -#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) <= ADC_CHANNEL_18) || \ - ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR)) #define IS_ADC_MODE(__MODE__) (((__MODE__) == ADC_MODE_INDEPENDENT) || \ ((__MODE__) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \ @@ -352,7 +350,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_ } #endif -#endif /*__STM32F7xx_ADC_EX_H */ +#endif /* STM32F7xx_ADC_EX_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cryp.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cryp.h index 4d00f584a7..6ea9cd92c0 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cryp.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cryp.h @@ -22,7 +22,7 @@ #define __STM32F7xx_HAL_CRYP_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif @@ -53,20 +53,23 @@ typedef struct This parameter can be a value of @ref CRYP_Data_Type */ uint32_t KeySize; /*!< Used only in AES mode : 128, 192 or 256 bit key length in CRYP1. 128 or 256 bit key length in TinyAES This parameter can be a value of @ref CRYP_Key_Size */ - uint32_t* pKey; /*!< The key used for encryption/decryption */ - uint32_t* pInitVect; /*!< The initialization vector used also as initialization + uint32_t *pKey; /*!< The key used for encryption/decryption */ + uint32_t *pInitVect; /*!< The initialization vector used also as initialization counter in CTR mode */ uint32_t Algorithm; /*!< DES/ TDES Algorithm ECB/CBC AES Algorithm ECB/CBC/CTR/GCM or CCM This parameter can be a value of @ref CRYP_Algorithm_Mode */ - uint32_t* Header; /*!< used only in AES GCM and CCM Algorithm for authentication, + uint32_t *Header; /*!< used only in AES GCM and CCM Algorithm for authentication, GCM : also known as Additional Authentication Data CCM : named B1 composed of the associated data length and Associated Data. */ uint32_t HeaderSize; /*!< The size of header buffer in word */ - uint32_t* B0; /*!< B0 is first authentication block used only in AES CCM mode */ + uint32_t *B0; /*!< B0 is first authentication block used only in AES CCM mode */ uint32_t DataWidthUnit; /*!< Data With Unit, this parameter can be value of @ref CRYP_Data_Width_Unit*/ + uint32_t KeyIVConfigSkip; /*!< CRYP peripheral Key and IV configuration skip, to config Key and Initialization + Vector only once and to skip configuration for consecutive processings. + This parameter can be a value of @ref CRYP_Configuration_Skip */ -}CRYP_ConfigTypeDef; +} CRYP_ConfigTypeDef; /** @@ -78,7 +81,7 @@ typedef enum HAL_CRYP_STATE_RESET = 0x00U, /*!< CRYP not yet initialized or disabled */ HAL_CRYP_STATE_READY = 0x01U, /*!< CRYP initialized and ready for use */ HAL_CRYP_STATE_BUSY = 0x02U /*!< CRYP BUSY, internal processing is ongoing */ -}HAL_CRYP_STATETypeDef; +} HAL_CRYP_STATETypeDef; /** @@ -88,50 +91,57 @@ typedef enum typedef struct __CRYP_HandleTypeDef { #if defined (CRYP) - CRYP_TypeDef *Instance; /*!< CRYP registers base address */ + CRYP_TypeDef *Instance; /*!< CRYP registers base address */ #else /* AES*/ - AES_TypeDef *Instance; /*!< AES Register base address */ + AES_TypeDef *Instance; /*!< AES Register base address */ #endif /* End AES or CRYP */ - CRYP_ConfigTypeDef Init; /*!< CRYP required parameters */ + CRYP_ConfigTypeDef Init; /*!< CRYP required parameters */ - FunctionalState AutoKeyDerivation; /*!< Used only in TinyAES to allows to bypass or not key write-up before decryption. + FunctionalState AutoKeyDerivation; /*!< Used only in TinyAES to allows to bypass or not key write-up before decryption. This parameter can be a value of ENABLE/DISABLE */ - uint32_t *pCrypInBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */ + uint32_t *pCrypInBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */ - uint32_t *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */ + uint32_t *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */ - __IO uint16_t CrypHeaderCount; /*!< Counter of header data */ + __IO uint16_t CrypHeaderCount; /*!< Counter of header data */ - __IO uint16_t CrypInCount; /*!< Counter of input data */ + __IO uint16_t CrypInCount; /*!< Counter of input data */ - __IO uint16_t CrypOutCount; /*!< Counter of output data */ + __IO uint16_t CrypOutCount; /*!< Counter of output data */ - uint16_t Size; /*!< length of input data in word */ + uint16_t Size; /*!< length of input data in word */ - uint32_t Phase; /*!< CRYP peripheral phase */ + uint32_t Phase; /*!< CRYP peripheral phase */ - DMA_HandleTypeDef *hdmain; /*!< CRYP In DMA handle parameters */ + DMA_HandleTypeDef *hdmain; /*!< CRYP In DMA handle parameters */ - DMA_HandleTypeDef *hdmaout; /*!< CRYP Out DMA handle parameters */ + DMA_HandleTypeDef *hdmaout; /*!< CRYP Out DMA handle parameters */ - HAL_LockTypeDef Lock; /*!< CRYP locking object */ + HAL_LockTypeDef Lock; /*!< CRYP locking object */ - __IO HAL_CRYP_STATETypeDef State; /*!< CRYP peripheral state */ + __IO HAL_CRYP_STATETypeDef State; /*!< CRYP peripheral state */ - __IO uint32_t ErrorCode; /*!< CRYP peripheral error code */ + __IO uint32_t ErrorCode; /*!< CRYP peripheral error code */ + + uint32_t KeyIVConfig; /*!< CRYP peripheral Key and IV configuration flag, used when + configuration can be skipped */ + + uint32_t SizesSum; /*!< Sum of successive payloads lengths (in bytes), stored + for a single signature computation after several + messages processing */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) - void (*InCpltCallback) (struct __CRYP_HandleTypeDef * hcryp); /*!< CRYP Input FIFO transfer completed callback */ - void (*OutCpltCallback) (struct __CRYP_HandleTypeDef * hcryp); /*!< CRYP Output FIFO transfer completed callback */ - void (*ErrorCallback) (struct __CRYP_HandleTypeDef * hcryp); /*!< CRYP Error callback */ + void (*InCpltCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Input FIFO transfer completed callback */ + void (*OutCpltCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Output FIFO transfer completed callback */ + void (*ErrorCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Error callback */ - void (* MspInitCallback) (struct __CRYP_HandleTypeDef * hcryp); /*!< CRYP Msp Init callback */ - void (* MspDeInitCallback)(struct __CRYP_HandleTypeDef * hcryp); /*!< CRYP Msp DeInit callback */ + void (* MspInitCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Msp Init callback */ + void (* MspDeInitCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Msp DeInit callback */ #endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */ -}CRYP_HandleTypeDef; +} CRYP_HandleTypeDef; /** @@ -152,7 +162,7 @@ typedef enum HAL_CRYP_MSPINIT_CB_ID = 0x04U, /*!< CRYP MspInit callback ID */ HAL_CRYP_MSPDEINIT_CB_ID = 0x05U /*!< CRYP MspDeInit callback ID */ -}HAL_CRYP_CallbackIDTypeDef; +} HAL_CRYP_CallbackIDTypeDef; /** * @} */ @@ -162,7 +172,7 @@ typedef enum * @{ */ -typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef * hcryp); /*!< pointer to a common CRYP callback function */ +typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp); /*!< pointer to a common CRYP callback function */ /** * @} @@ -309,6 +319,17 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef * hcryp); /*!< point #define CRYP_ERR_CLEAR AES_CR_ERRC /*!< Error Flag Clear */ #endif /* End AES or CRYP */ +/** + * @} + */ + +/** @defgroup CRYP_Configuration_Skip CRYP Key and IV Configuration Skip Mode + * @{ + */ + +#define CRYP_KEYIVCONFIG_ALWAYS 0x00000000U /*!< Peripheral Key and IV configuration to do systematically */ +#define CRYP_KEYIVCONFIG_ONCE 0x00000001U /*!< Peripheral Key and IV configuration to do only once */ + /** * @} */ @@ -366,12 +387,12 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef * hcryp); /*!< point * @arg CRYP_FLAG_OFNE: Output FIFO is not empty * @arg CRYP_FLAG_OFFU: Output FIFO is full * @arg CRYP_FLAG_OUTRIS: Input FIFO service raw interrupt is pending - * @retval The state of __FLAG__ (TRUE or FALSE). + * @retval The state of __FLAG__ (TRUE or FALSE). */ #define CRYP_FLAG_MASK 0x0000001FU #if defined(CRYP) #define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 24)) == 0x01U)?((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)): \ - ((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK))) + ((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK))) #else /* AES*/ #define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) #endif /* End AES or CRYP */ @@ -398,7 +419,8 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef * hcryp); /*!< point * @retval State of interruption (TRUE or FALSE). */ -#define __HAL_CRYP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__)) +#define __HAL_CRYP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR\ + & (__INTERRUPT__)) == (__INTERRUPT__)) #endif /* AES */ @@ -415,7 +437,8 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef * hcryp); /*!< point * @retval The state of __INTERRUPT__ (TRUE or FALSE). */ #if defined(CRYP) -#define __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->MISR & (__INTERRUPT__)) == (__INTERRUPT__)) +#define __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->MISR\ + & (__INTERRUPT__)) == (__INTERRUPT__)) #else /* AES*/ #define __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__)) #endif /* End AES or CRYP */ @@ -473,10 +496,11 @@ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp); HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp); void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp); void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp); -HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf ); -HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf ); +HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf); +HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf); #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID, pCRYP_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID, + pCRYP_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ /** @@ -488,8 +512,10 @@ HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRY */ /* encryption/decryption ***********************************/ -HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout); -HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout); +HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, + uint32_t Timeout); +HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, + uint32_t Timeout); HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output); HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output); HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output); @@ -529,23 +555,23 @@ uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp); */ #if defined(CRYP) #define IS_CRYP_ALGORITHM(ALGORITHM) (((ALGORITHM) == CRYP_DES_ECB) || \ - ((ALGORITHM) == CRYP_DES_CBC) || \ - ((ALGORITHM) == CRYP_TDES_ECB) || \ - ((ALGORITHM) == CRYP_TDES_CBC) || \ - ((ALGORITHM) == CRYP_AES_ECB) || \ - ((ALGORITHM) == CRYP_AES_CBC) || \ - ((ALGORITHM) == CRYP_AES_CTR) || \ - ((ALGORITHM) == CRYP_AES_GCM) || \ - ((ALGORITHM) == CRYP_AES_CCM)) + ((ALGORITHM) == CRYP_DES_CBC) || \ + ((ALGORITHM) == CRYP_TDES_ECB) || \ + ((ALGORITHM) == CRYP_TDES_CBC) || \ + ((ALGORITHM) == CRYP_AES_ECB) || \ + ((ALGORITHM) == CRYP_AES_CBC) || \ + ((ALGORITHM) == CRYP_AES_CTR) || \ + ((ALGORITHM) == CRYP_AES_GCM) || \ + ((ALGORITHM) == CRYP_AES_CCM)) #define IS_CRYP_KEYSIZE(KEYSIZE)(((KEYSIZE) == CRYP_KEYSIZE_128B) || \ ((KEYSIZE) == CRYP_KEYSIZE_192B) || \ ((KEYSIZE) == CRYP_KEYSIZE_256B)) #else /* AES*/ #define IS_CRYP_ALGORITHM(ALGORITHM) (((ALGORITHM) == CRYP_AES_ECB) || \ - ((ALGORITHM) == CRYP_AES_CBC) || \ - ((ALGORITHM) == CRYP_AES_CTR) || \ - ((ALGORITHM) == CRYP_AES_GCM_GMAC)|| \ - ((ALGORITHM) == CRYP_AES_CCM)) + ((ALGORITHM) == CRYP_AES_CBC) || \ + ((ALGORITHM) == CRYP_AES_CTR) || \ + ((ALGORITHM) == CRYP_AES_GCM_GMAC)|| \ + ((ALGORITHM) == CRYP_AES_CCM)) #define IS_CRYP_KEYSIZE(KEYSIZE)(((KEYSIZE) == CRYP_KEYSIZE_128B) || \ @@ -557,6 +583,8 @@ uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp); ((DATATYPE) == CRYP_DATATYPE_8B) || \ ((DATATYPE) == CRYP_DATATYPE_1B)) +#define IS_CRYP_INIT(CONFIG)(((CONFIG) == CRYP_KEYIVCONFIG_ALWAYS) || \ + ((CONFIG) == CRYP_KEYIVCONFIG_ONCE)) /** * @} */ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cryp_ex.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cryp_ex.h index 3913bf20ae..d9fa776f07 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cryp_ex.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cryp_ex.h @@ -22,7 +22,7 @@ #define __STM32F7xx_HAL_CRYP_EX_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -84,9 +84,9 @@ * @{ */ - /** +/** * @} - */ + */ /* Private functions ---------------------------------------------------------*/ /** @defgroup CRYPEx_Private_Functions CRYPEx Private Functions diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dcmi.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dcmi.h index 5cee0a3f55..5fed28be90 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dcmi.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dcmi.h @@ -18,11 +18,11 @@ */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F7xx_HAL_DCMI_H -#define __STM32F7xx_HAL_DCMI_H +#ifndef STM32F7xx_HAL_DCMI_H +#define STM32F7xx_HAL_DCMI_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -54,7 +54,7 @@ typedef enum HAL_DCMI_STATE_TIMEOUT = 0x03U, /*!< DCMI timeout state */ HAL_DCMI_STATE_ERROR = 0x04U, /*!< DCMI error state */ HAL_DCMI_STATE_SUSPENDED = 0x05U /*!< DCMI suspend state */ -}HAL_DCMI_StateTypeDef; +} HAL_DCMI_StateTypeDef; /** * @brief DCMIEx Embedded Synchronisation CODE Init structure definition @@ -65,8 +65,18 @@ typedef struct uint8_t LineStartCode; /*!< Specifies the code of the line start delimiter. */ uint8_t LineEndCode; /*!< Specifies the code of the line end delimiter. */ uint8_t FrameEndCode; /*!< Specifies the code of the frame end delimiter. */ -}DCMI_CodesInitTypeDef; +} DCMI_CodesInitTypeDef; +/** + * @brief DCMI Embedded Synchronisation CODE Init structure definition + */ +typedef struct +{ + uint8_t FrameStartUnmask; /*!< Specifies the frame start delimiter unmask. */ + uint8_t LineStartUnmask; /*!< Specifies the line start delimiter unmask. */ + uint8_t LineEndUnmask; /*!< Specifies the line end delimiter unmask. */ + uint8_t FrameEndUnmask; /*!< Specifies the frame end delimiter unmask. */ +} DCMI_SyncUnmaskTypeDef; /** * @brief DCMI Init structure definition */ @@ -96,6 +106,7 @@ typedef struct uint32_t JPEGMode; /*!< Enable or Disable the JPEG mode. This parameter can be a value of @ref DCMI_MODE_JPEG */ +#ifdef DCMI_CR_BSM uint32_t ByteSelectMode; /*!< Specifies the data to be captured by the interface This parameter can be a value of @ref DCMI_Byte_Select_Mode */ @@ -107,7 +118,8 @@ typedef struct uint32_t LineSelectStart; /*!< Specifies if the line of data to be captured by the interface is even or odd This parameter can be a value of @ref DCMI_Line_Select_Start */ -}DCMI_InitTypeDef; +#endif +} DCMI_InitTypeDef; /** * @brief DCMI handle Structure definition @@ -134,14 +146,14 @@ typedef struct __DCMI_HandleTypeDef __IO uint32_t ErrorCode; /*!< DCMI Error code */ #if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1) - void (* FrameEventCallback) ( struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Frame Event Callback */ - void (* VsyncEventCallback) ( struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Vsync Event Callback */ - void (* LineEventCallback ) ( struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Line Event Callback */ - void (* ErrorCallback) ( struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Error Callback */ - void (* MspInitCallback) ( struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Msp Init callback */ - void (* MspDeInitCallback) ( struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Msp DeInit callback */ + void (* FrameEventCallback)(struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Frame Event Callback */ + void (* VsyncEventCallback)(struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Vsync Event Callback */ + void (* LineEventCallback)(struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Line Event Callback */ + void (* ErrorCallback)(struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Error Callback */ + void (* MspInitCallback)(struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Msp Init callback */ + void (* MspDeInitCallback)(struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Msp DeInit callback */ #endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */ -}DCMI_HandleTypeDef; +} DCMI_HandleTypeDef; #if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1) typedef enum @@ -153,7 +165,7 @@ typedef enum HAL_DCMI_MSPINIT_CB_ID = 0x04U, /*!< DCMI MspInit callback ID */ HAL_DCMI_MSPDEINIT_CB_ID = 0x05U /*!< DCMI MspDeInit callback ID */ -}HAL_DCMI_CallbackIDTypeDef; +} HAL_DCMI_CallbackIDTypeDef; typedef void (*pDCMI_CallbackTypeDef)(DCMI_HandleTypeDef *hdcmi); #endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */ @@ -500,8 +512,8 @@ typedef void (*pDCMI_CallbackTypeDef)(DCMI_HandleTypeDef *hdcmi); /* Initialization and de-initialization functions *****************************/ HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi); HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi); -void HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi); -void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi); +void HAL_DCMI_MspInit(DCMI_HandleTypeDef *hdcmi); +void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef *hdcmi); /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1) @@ -516,10 +528,10 @@ HAL_StatusTypeDef HAL_DCMI_UnRegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCM * @{ */ /* IO operation functions *****************************************************/ -HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length); -HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi); -HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef* hdcmi); -HAL_StatusTypeDef HAL_DCMI_Resume(DCMI_HandleTypeDef* hdcmi); +HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef *hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length); +HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef *hdcmi); +HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef *hdcmi); +HAL_StatusTypeDef HAL_DCMI_Resume(DCMI_HandleTypeDef *hdcmi); void HAL_DCMI_ErrorCallback(DCMI_HandleTypeDef *hdcmi); void HAL_DCMI_LineEventCallback(DCMI_HandleTypeDef *hdcmi); void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi); @@ -536,6 +548,7 @@ void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi); HAL_StatusTypeDef HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize); HAL_StatusTypeDef HAL_DCMI_EnableCrop(DCMI_HandleTypeDef *hdcmi); HAL_StatusTypeDef HAL_DCMI_DisableCrop(DCMI_HandleTypeDef *hdcmi); +HAL_StatusTypeDef HAL_DCMI_ConfigSyncUnmask(DCMI_HandleTypeDef *hdcmi, DCMI_SyncUnmaskTypeDef *SyncUnmask); /** * @} @@ -640,6 +653,6 @@ uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi); } #endif -#endif /* __STM32F7xx_HAL_DCMI_H */ +#endif /* STM32F7xx_HAL_DCMI_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h index b62eade50e..e64414ffcf 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h @@ -18,8 +18,8 @@ */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F7xx_HAL_EXTI_H -#define __STM32F7xx_HAL_EXTI_H +#ifndef STM32F7xx_HAL_EXTI_H +#define STM32F7xx_HAL_EXTI_H #ifdef __cplusplus extern "C" { @@ -38,14 +38,13 @@ extern "C" { */ /* Exported types ------------------------------------------------------------*/ + /** @defgroup EXTI_Exported_Types EXTI Exported Types * @{ */ typedef enum { - HAL_EXTI_COMMON_CB_ID = 0x00U, - HAL_EXTI_RISING_CB_ID = 0x01U, - HAL_EXTI_FALLING_CB_ID = 0x02U, + HAL_EXTI_COMMON_CB_ID = 0x00U } EXTI_CallbackIDTypeDef; /** @@ -68,6 +67,9 @@ typedef struct This parameter can be a combination of @ref EXTI_Mode */ uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter can be a value of @ref EXTI_Trigger */ + uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured. + This parameter is only possible for line 0 to 15. It + can be a value of @ref EXTI_GPIOSel */ } EXTI_ConfigTypeDef; /** @@ -82,48 +84,36 @@ typedef struct /** @defgroup EXTI_Line EXTI Line * @{ */ -#define EXTI_LINE_0 EXTI_IMR_IM0 /*!< External interrupt line 0 */ -#define EXTI_LINE_1 EXTI_IMR_IM1 /*!< External interrupt line 1 */ -#define EXTI_LINE_2 EXTI_IMR_IM2 /*!< External interrupt line 2 */ -#define EXTI_LINE_3 EXTI_IMR_IM3 /*!< External interrupt line 3 */ -#define EXTI_LINE_4 EXTI_IMR_IM4 /*!< External interrupt line 4 */ -#define EXTI_LINE_5 EXTI_IMR_IM5 /*!< External interrupt line 5 */ -#define EXTI_LINE_6 EXTI_IMR_IM6 /*!< External interrupt line 6 */ -#define EXTI_LINE_7 EXTI_IMR_IM7 /*!< External interrupt line 7 */ -#define EXTI_LINE_8 EXTI_IMR_IM8 /*!< External interrupt line 8 */ -#define EXTI_LINE_9 EXTI_IMR_IM9 /*!< External interrupt line 9 */ -#define EXTI_LINE_10 EXTI_IMR_IM10 /*!< External interrupt line 10 */ -#define EXTI_LINE_11 EXTI_IMR_IM11 /*!< External interrupt line 11 */ -#define EXTI_LINE_12 EXTI_IMR_IM12 /*!< External interrupt line 12 */ -#define EXTI_LINE_13 EXTI_IMR_IM13 /*!< External interrupt line 13 */ -#define EXTI_LINE_14 EXTI_IMR_IM14 /*!< External interrupt line 14 */ -#define EXTI_LINE_15 EXTI_IMR_IM15 /*!< External interrupt line 15 */ -#if defined(EXTI_IMR_IM16) -#define EXTI_LINE_16 EXTI_IMR_IM16 /*!< External interrupt line 16 Connected to the PVD Output */ -#endif /* EXTI_IMR_IM16 */ -#if defined(EXTI_IMR_IM17) -#define EXTI_LINE_17 EXTI_IMR_IM17 /*!< External interrupt line 17 Connected to the RTC Alarm event */ -#endif /* EXTI_IMR_IM17 */ -#if defined(EXTI_IMR_IM18) -#define EXTI_LINE_18 EXTI_IMR_IM18 /*!< External interrupt line 18 Connected to the USB OTG FS Wakeup from suspend event */ -#endif /* EXTI_IMR_IM18 */ -#if defined(EXTI_IMR_IM19) -#define EXTI_LINE_19 EXTI_IMR_IM19 /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */ -#endif /* EXTI_IMR_IM19 */ -#if defined(EXTI_IMR_IM20) -#define EXTI_LINE_20 EXTI_IMR_IM20 /*!< External interrupt line 20 Connected to the USB OTG HS (configured in FS) Wakeup event */ -#endif /* EXTI_IMR_IM20 */ -#if defined(EXTI_IMR_IM21) -#define EXTI_LINE_21 EXTI_IMR_IM21 /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */ -#endif /* EXTI_IMR_IM21 */ -#if defined(EXTI_IMR_IM22) -#define EXTI_LINE_22 EXTI_IMR_IM22 /*!< External interrupt line 22 Connected to the RTC Wakeup event */ -#endif /* EXTI_IMR_IM22 */ -#if defined(EXTI_IMR_IM23) -#define EXTI_LINE_23 EXTI_IMR_IM23 /*!< External interrupt line 23 Connected to the LPTIM Wakeup event */ -#endif /* EXTI_IMR_IM23 */ +#define EXTI_LINE_0 (EXTI_GPIO | 0x00u) /*!< External interrupt line 0 */ +#define EXTI_LINE_1 (EXTI_GPIO | 0x01u) /*!< External interrupt line 1 */ +#define EXTI_LINE_2 (EXTI_GPIO | 0x02u) /*!< External interrupt line 2 */ +#define EXTI_LINE_3 (EXTI_GPIO | 0x03u) /*!< External interrupt line 3 */ +#define EXTI_LINE_4 (EXTI_GPIO | 0x04u) /*!< External interrupt line 4 */ +#define EXTI_LINE_5 (EXTI_GPIO | 0x05u) /*!< External interrupt line 5 */ +#define EXTI_LINE_6 (EXTI_GPIO | 0x06u) /*!< External interrupt line 6 */ +#define EXTI_LINE_7 (EXTI_GPIO | 0x07u) /*!< External interrupt line 7 */ +#define EXTI_LINE_8 (EXTI_GPIO | 0x08u) /*!< External interrupt line 8 */ +#define EXTI_LINE_9 (EXTI_GPIO | 0x09u) /*!< External interrupt line 9 */ +#define EXTI_LINE_10 (EXTI_GPIO | 0x0Au) /*!< External interrupt line 10 */ +#define EXTI_LINE_11 (EXTI_GPIO | 0x0Bu) /*!< External interrupt line 11 */ +#define EXTI_LINE_12 (EXTI_GPIO | 0x0Cu) /*!< External interrupt line 12 */ +#define EXTI_LINE_13 (EXTI_GPIO | 0x0Du) /*!< External interrupt line 13 */ +#define EXTI_LINE_14 (EXTI_GPIO | 0x0Eu) /*!< External interrupt line 14 */ +#define EXTI_LINE_15 (EXTI_GPIO | 0x0Fu) /*!< External interrupt line 15 */ +#define EXTI_LINE_16 (EXTI_CONFIG | 0x10u) /*!< External interrupt line 16 Connected to the PVD Output */ +#define EXTI_LINE_17 (EXTI_CONFIG | 0x11u) /*!< External interrupt line 17 Connected to the RTC Alarm event */ +#define EXTI_LINE_18 (EXTI_CONFIG | 0x12u) /*!< External interrupt line 18 Connected to the USB OTG FS Wakeup from suspend event */ +#if defined(ETH) +#define EXTI_LINE_19 (EXTI_CONFIG | 0x13u) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */ +#else +#define EXTI_LINE_19 (EXTI_RESERVED | 0x13u) /*!< No interrupt supported in this line */ +#endif /* ETH */ +#define EXTI_LINE_20 (EXTI_CONFIG | 0x14u) /*!< External interrupt line 20 Connected to the USB OTG HS (configured in FS) Wakeup event */ +#define EXTI_LINE_21 (EXTI_CONFIG | 0x15u) /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */ +#define EXTI_LINE_22 (EXTI_CONFIG | 0x16u) /*!< External interrupt line 22 Connected to the RTC Wakeup event */ +#define EXTI_LINE_23 (EXTI_CONFIG | 0x17u) /*!< External interrupt line 23 Connected to the LPTIM Wakeup event */ #if defined(EXTI_IMR_IM24) -#define EXTI_LINE_24 EXTI_IMR_IM24 /*!< External interrupt line 24 Connected to the MDIO Slave global Interrupt Wakeup event */ +#define EXTI_LINE_24 (EXTI_CONFIG | 0x18u) /*!< External interrupt line 24 Connected to the MDIO Slave global Interrupt Wakeup event */ #endif /* EXTI_IMR_IM24 */ /** * @} @@ -142,6 +132,7 @@ typedef struct /** @defgroup EXTI_Trigger EXTI Trigger * @{ */ + #define EXTI_TRIGGER_NONE 0x00000000u #define EXTI_TRIGGER_RISING 0x00000001u #define EXTI_TRIGGER_FALLING 0x00000002u @@ -150,6 +141,24 @@ typedef struct * @} */ +/** @defgroup EXTI_GPIOSel EXTI GPIOSel + * @brief + * @{ + */ +#define EXTI_GPIOA 0x00000000u +#define EXTI_GPIOB 0x00000001u +#define EXTI_GPIOC 0x00000002u +#define EXTI_GPIOD 0x00000003u +#define EXTI_GPIOE 0x00000004u +#define EXTI_GPIOF 0x00000005u +#define EXTI_GPIOG 0x00000006u +#define EXTI_GPIOH 0x00000007u +#define EXTI_GPIOI 0x00000008u +#define EXTI_GPIOJ 0x00000009u +#if defined (GPIOK) +#define EXTI_GPIOK 0x0000000Au +#endif /* GPIOK */ + /** * @} */ @@ -167,6 +176,20 @@ typedef struct /** @defgroup EXTI_Private_Constants EXTI Private Constants * @{ */ +/** + * @brief EXTI Line property definition + */ +#define EXTI_PROPERTY_SHIFT 24u +#define EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT) +#define EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG) +#define EXTI_RESERVED (0x08uL << EXTI_PROPERTY_SHIFT) +#define EXTI_PROPERTY_MASK (EXTI_CONFIG | EXTI_GPIO) + +/** + * @brief EXTI bit usage + */ +#define EXTI_PIN_MASK 0x0000001Fu + /** * @brief EXTI Mask for interrupt & event mode */ @@ -175,12 +198,17 @@ typedef struct /** * @brief EXTI Mask for trigger possibilities */ -#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING | EXTI_TRIGGER_RISING_FALLING) +#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) /** * @brief EXTI Line number */ +#if defined(EXTI_IMR_IM24) #define EXTI_LINE_NB 25u +#else +#define EXTI_LINE_NB 24u +#endif /* EXTI_IMR_IM24 */ + /** * @} @@ -190,16 +218,47 @@ typedef struct /** @defgroup EXTI_Private_Macros EXTI Private Macros * @{ */ -#define IS_EXTI_LINE(__LINE__) ((((__LINE__) & ~EXTI_IMR_IM) == 0x00U) && (__LINE__)) +#define IS_EXTI_LINE(__LINE__) ((((__LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_PIN_MASK)) == 0x00u) && \ + ((((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \ + (((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \ + (((__LINE__) & EXTI_PIN_MASK) < EXTI_LINE_NB)) -#define IS_EXTI_MODE(__LINE__) ((((__LINE__) & ~EXTI_MODE_MASK) == 0x00U)) +#define IS_EXTI_MODE(__LINE__) ((((__LINE__) & EXTI_MODE_MASK) != 0x00u) && \ + (((__LINE__) & ~EXTI_MODE_MASK) == 0x00u)) -#define IS_EXTI_TRIGGER(__LINE__) (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00U) +#define IS_EXTI_TRIGGER(__LINE__) (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u) #define IS_EXTI_PENDING_EDGE(__LINE__) (((__LINE__) == EXTI_TRIGGER_FALLING) || \ ((__LINE__) == EXTI_TRIGGER_RISING) || \ ((__LINE__) == EXTI_TRIGGER_RISING_FALLING)) +#define IS_EXTI_CONFIG_LINE(__LINE__) (((__LINE__) & EXTI_CONFIG) != 0x00u) + +#if defined (GPIOK) +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOE) || \ + ((__PORT__) == EXTI_GPIOF) || \ + ((__PORT__) == EXTI_GPIOG) || \ + ((__PORT__) == EXTI_GPIOH) || \ + ((__PORT__) == EXTI_GPIOI) || \ + ((__PORT__) == EXTI_GPIOJ) || \ + ((__PORT__) == EXTI_GPIOK)) +#else +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOE) || \ + ((__PORT__) == EXTI_GPIOF) || \ + ((__PORT__) == EXTI_GPIOG) || \ + ((__PORT__) == EXTI_GPIOH) || \ + ((__PORT__) == EXTI_GPIOI) || \ + ((__PORT__) == EXTI_GPIOJ)) +#endif /* GPIOK */ + #define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16U) /** * @} @@ -255,6 +314,6 @@ void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti); } #endif -#endif /* __STM32F7xx_HAL_EXTI_H */ +#endif /* STM32F7xx_HAL_EXTI_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h index c590c5021b..a155e029b0 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h @@ -262,7 +262,7 @@ void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); * @{ */ #define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET)) -#define IS_GPIO_PIN(__PIN__) ((((__PIN__) & GPIO_PIN_MASK) != (uint32_t)0x00)) +#define IS_GPIO_PIN(__PIN__) ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00U)) #define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\ ((MODE) == GPIO_MODE_OUTPUT_PP) ||\ ((MODE) == GPIO_MODE_OUTPUT_OD) ||\ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_hash.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_hash.h index 3cf5c25900..93177b716e 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_hash.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_hash.h @@ -152,6 +152,8 @@ typedef struct __IO uint32_t ErrorCode; /*!< HASH Error code */ + __IO uint32_t Accumulation; /*!< HASH multi buffers accumulation flag */ + #if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) void (* InCpltCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH input completion callback */ @@ -226,11 +228,11 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer /** @defgroup HASH_flags_definition HASH flags definitions * @{ */ -#define HASH_FLAG_DINIS HASH_SR_DINIS /*!< 16 locations are free in the DIN : a new block can be entered in the IP */ -#define HASH_FLAG_DCIS HASH_SR_DCIS /*!< Digest calculation complete */ -#define HASH_FLAG_DMAS HASH_SR_DMAS /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing */ -#define HASH_FLAG_BUSY HASH_SR_BUSY /*!< The hash core is Busy, processing a block of data */ -#define HASH_FLAG_DINNE HASH_CR_DINNE /*!< DIN not empty : the input buffer contains at least one word of data */ +#define HASH_FLAG_DINIS HASH_SR_DINIS /*!< 16 locations are free in the DIN : a new block can be entered in the Peripheral */ +#define HASH_FLAG_DCIS HASH_SR_DCIS /*!< Digest calculation complete */ +#define HASH_FLAG_DMAS HASH_SR_DMAS /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing */ +#define HASH_FLAG_BUSY HASH_SR_BUSY /*!< The hash core is Busy, processing a block of data */ +#define HASH_FLAG_DINNE HASH_CR_DINNE /*!< DIN not empty : the input buffer contains at least one word of data */ /** * @} @@ -276,7 +278,7 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer */ /** @brief Check whether or not the specified HASH flag is set. - * @param __FLAG__: specifies the flag to check. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg @ref HASH_FLAG_DINIS A new block can be entered into the input buffer. * @arg @ref HASH_FLAG_DCIS Digest calculation complete. @@ -291,7 +293,7 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer /** @brief Clear the specified HASH flag. - * @param __FLAG__: specifies the flag to clear. + * @param __FLAG__ specifies the flag to clear. * This parameter can be one of the following values: * @arg @ref HASH_FLAG_DINIS A new block can be entered into the input buffer. * @arg @ref HASH_FLAG_DCIS Digest calculation complete @@ -301,7 +303,7 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer /** @brief Enable the specified HASH interrupt. - * @param __INTERRUPT__: specifies the HASH interrupt source to enable. + * @param __INTERRUPT__ specifies the HASH interrupt source to enable. * This parameter can be one of the following values: * @arg @ref HASH_IT_DINI A new block can be entered into the input buffer (DIN) * @arg @ref HASH_IT_DCI Digest calculation complete @@ -310,7 +312,7 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer #define __HAL_HASH_ENABLE_IT(__INTERRUPT__) SET_BIT(HASH->IMR, (__INTERRUPT__)) /** @brief Disable the specified HASH interrupt. - * @param __INTERRUPT__: specifies the HASH interrupt source to disable. + * @param __INTERRUPT__ specifies the HASH interrupt source to disable. * This parameter can be one of the following values: * @arg @ref HASH_IT_DINI A new block can be entered into the input buffer (DIN) * @arg @ref HASH_IT_DCI Digest calculation complete @@ -319,7 +321,7 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer #define __HAL_HASH_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(HASH->IMR, (__INTERRUPT__)) /** @brief Reset HASH handle state. - * @param __HANDLE__: HASH handle. + * @param __HANDLE__ HASH handle. * @retval None */ @@ -335,7 +337,7 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer /** @brief Reset HASH handle status. - * @param __HANDLE__: HASH handle. + * @param __HANDLE__ HASH handle. * @retval None */ #define __HAL_HASH_RESET_HANDLE_STATUS(__HANDLE__) ((__HANDLE__)->Status = HAL_OK) @@ -362,7 +364,7 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer /** * @brief Set the number of valid bits in the last word written in data register DIN. - * @param __SIZE__: size in bytes of last data written in Data register. + * @param __SIZE__ size in bytes of last data written in Data register. * @retval None */ #define __HAL_HASH_SET_NBVALIDBITS(__SIZE__) MODIFY_REG(HASH->STR, HASH_STR_NBLW, 8U * ((__SIZE__) % 4U)) @@ -397,7 +399,7 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer /** * @brief Ensure that HASH input data type is valid. - * @param __DATATYPE__: HASH input data type. + * @param __DATATYPE__ HASH input data type. * @retval SET (__DATATYPE__ is valid) or RESET (__DATATYPE__ is invalid) */ #define IS_HASH_DATATYPE(__DATATYPE__) (((__DATATYPE__) == HASH_DATATYPE_32B)|| \ @@ -405,21 +407,11 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer ((__DATATYPE__) == HASH_DATATYPE_8B) || \ ((__DATATYPE__) == HASH_DATATYPE_1B)) - - -/** - * @brief Ensure that input data buffer size is valid for multi-buffer HASH - * processing in polling mode. - * @note This check is valid only for multi-buffer HASH processing in polling mode. - * @param __SIZE__: input data buffer size. - * @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid) - */ -#define IS_HASH_POLLING_MULTIBUFFER_SIZE(__SIZE__) (((__SIZE__) % 4U) == 0U) /** * @brief Ensure that input data buffer size is valid for multi-buffer HASH * processing in DMA mode. * @note This check is valid only for multi-buffer HASH processing in DMA mode. - * @param __SIZE__: input data buffer size. + * @param __SIZE__ input data buffer size. * @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid) */ #define IS_HASH_DMA_MULTIBUFFER_SIZE(__SIZE__) ((READ_BIT(HASH->CR, HASH_CR_MDMAT) == 0U) || (((__SIZE__) % 4U) == 0U)) @@ -428,21 +420,21 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer * @brief Ensure that input data buffer size is valid for multi-buffer HMAC * processing in DMA mode. * @note This check is valid only for multi-buffer HMAC processing in DMA mode. - * @param __HANDLE__: HASH handle. - * @param __SIZE__: input data buffer size. + * @param __HANDLE__ HASH handle. + * @param __SIZE__ input data buffer size. * @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid) */ #define IS_HMAC_DMA_MULTIBUFFER_SIZE(__HANDLE__,__SIZE__) ((((__HANDLE__)->DigestCalculationDisable) == RESET) || (((__SIZE__) % 4U) == 0U)) /** * @brief Ensure that handle phase is set to HASH processing. - * @param __HANDLE__: HASH handle. + * @param __HANDLE__ HASH handle. * @retval SET (handle phase is set to HASH processing) or RESET (handle phase is not set to HASH processing) */ #define IS_HASH_PROCESSING(__HANDLE__) ((__HANDLE__)->Phase == HAL_HASH_PHASE_PROCESS) /** * @brief Ensure that handle phase is set to HMAC processing. - * @param __HANDLE__: HASH handle. + * @param __HANDLE__ HASH handle. * @retval SET (handle phase is set to HMAC processing) or RESET (handle phase is not set to HMAC processing) */ #define IS_HMAC_PROCESSING(__HANDLE__) (((__HANDLE__)->Phase == HAL_HASH_PHASE_HMAC_STEP_1) || \ @@ -492,8 +484,11 @@ HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HAS /* HASH processing using polling *********************************************/ HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout); HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASH_MD5_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout); +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout); + /** * @} @@ -505,7 +500,11 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *p /* HASH processing using IT **************************************************/ HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer); +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer); HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer); +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer); void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash); /** * @} @@ -591,6 +590,7 @@ uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash); /* Private functions */ HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm); HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm); +HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm); HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm); HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm); HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout); diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_hash_ex.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_hash_ex.h index 6c0fc99faf..60717df1bb 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_hash_ex.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_hash_ex.h @@ -52,9 +52,11 @@ */ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout); HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout); /** * @} @@ -65,7 +67,11 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate(HASH_HandleTypeDef *hhash, uint8_ */ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer); +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer); HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer); +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer); /** * @} diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_hcd.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_hcd.h index 7488da76dc..28c578efc8 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_hcd.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_hcd.h @@ -108,9 +108,10 @@ typedef struct /** @defgroup HCD_Speed HCD Speed * @{ */ -#define HCD_SPEED_HIGH 0U -#define HCD_SPEED_LOW 2U -#define HCD_SPEED_FULL 3U +#define HCD_SPEED_HIGH USBH_HS_SPEED +#define HCD_SPEED_FULL USBH_FSLS_SPEED +#define HCD_SPEED_LOW USBH_FSLS_SPEED + /** * @} */ @@ -169,19 +170,15 @@ typedef struct /** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions * @{ */ -HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd); -HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd); -HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, - uint8_t ch_num, - uint8_t epnum, - uint8_t dev_address, - uint8_t speed, - uint8_t ep_type, - uint16_t mps); +HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd); +HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd); +HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num, + uint8_t epnum, uint8_t dev_address, + uint8_t speed, uint8_t ep_type, uint16_t mps); -HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num); -void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd); -void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd); +HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num); +void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd); +void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd); #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) /** @defgroup HAL_HCD_Callback_ID_enumeration_definition HAL USB OTG HCD Callback ID enumeration definition @@ -190,14 +187,14 @@ void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd); */ typedef enum { - HAL_HCD_SOF_CB_ID = 0x01, /*!< USB HCD SOF callback ID */ - HAL_HCD_CONNECT_CB_ID = 0x02, /*!< USB HCD Connect callback ID */ - HAL_HCD_DISCONNECT_CB_ID = 0x03, /*!< USB HCD Disconnect callback ID */ - HAL_HCD_PORT_ENABLED_CB_ID = 0x04, /*!< USB HCD Port Enable callback ID */ - HAL_HCD_PORT_DISABLED_CB_ID = 0x05, /*!< USB HCD Port Disable callback ID */ + HAL_HCD_SOF_CB_ID = 0x01, /*!< USB HCD SOF callback ID */ + HAL_HCD_CONNECT_CB_ID = 0x02, /*!< USB HCD Connect callback ID */ + HAL_HCD_DISCONNECT_CB_ID = 0x03, /*!< USB HCD Disconnect callback ID */ + HAL_HCD_PORT_ENABLED_CB_ID = 0x04, /*!< USB HCD Port Enable callback ID */ + HAL_HCD_PORT_DISABLED_CB_ID = 0x05, /*!< USB HCD Port Disable callback ID */ - HAL_HCD_MSPINIT_CB_ID = 0x06, /*!< USB HCD MspInit callback ID */ - HAL_HCD_MSPDEINIT_CB_ID = 0x07 /*!< USB HCD MspDeInit callback ID */ + HAL_HCD_MSPINIT_CB_ID = 0x06, /*!< USB HCD MspInit callback ID */ + HAL_HCD_MSPDEINIT_CB_ID = 0x07 /*!< USB HCD MspDeInit callback ID */ } HAL_HCD_CallbackIDTypeDef; /** @@ -231,25 +228,20 @@ HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef /** @addtogroup HCD_Exported_Functions_Group2 Input and Output operation functions * @{ */ -HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, - uint8_t ch_num, - uint8_t direction, - uint8_t ep_type, - uint8_t token, - uint8_t *pbuff, - uint16_t length, - uint8_t do_ping); +HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, uint8_t ch_num, + uint8_t direction, uint8_t ep_type, + uint8_t token, uint8_t *pbuff, + uint16_t length, uint8_t do_ping); /* Non-Blocking mode: Interrupt */ -void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd); -void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd); -void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd); -void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd); -void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd); -void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd); -void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, - uint8_t chnum, - HCD_URBStateTypeDef urb_state); +void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd); +void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd); +void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd); +void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd); +void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd); +void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd); +void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum, + HCD_URBStateTypeDef urb_state); /** * @} */ @@ -258,9 +250,9 @@ void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, /** @addtogroup HCD_Exported_Functions_Group3 Peripheral Control functions * @{ */ -HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd); -HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd); -HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd); +HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd); +HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd); +HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd); /** * @} */ @@ -271,8 +263,8 @@ HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd); */ HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd); HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum); -uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum); HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum); +uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum); uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd); uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd); /** diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h index f377d8187d..f45be67b70 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h @@ -167,6 +167,9 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); (((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \ (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1)) #endif /* SYSCFG_PMC_I2C1_FMP && SYSCFG_PMC_I2C2_FMP && SYSCFG_PMC_I2C3_FMP && SYSCFG_PMC_I2C4_FMP */ + + + /** * @} */ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_irda.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_irda.h index f382d73c0b..09baf21516 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_irda.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_irda.h @@ -434,8 +434,8 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer */ /** - * @} - */ + * @} + */ /* Exported macros -----------------------------------------------------------*/ /** @defgroup IRDA_Exported_Macros IRDA Exported Macros @@ -465,10 +465,10 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer * @retval None */ #define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__) \ - do{ \ - SET_BIT((__HANDLE__)->Instance->RQR, IRDA_RXDATA_FLUSH_REQUEST); \ - SET_BIT((__HANDLE__)->Instance->RQR, IRDA_TXDATA_FLUSH_REQUEST); \ - } while(0U) + do{ \ + SET_BIT((__HANDLE__)->Instance->RQR, IRDA_RXDATA_FLUSH_REQUEST); \ + SET_BIT((__HANDLE__)->Instance->RQR, IRDA_TXDATA_FLUSH_REQUEST); \ + } while(0U) /** @brief Clear the specified IRDA pending flag. * @param __HANDLE__ specifies the IRDA Handle. @@ -582,7 +582,8 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer * @arg @ref IRDA_IT_PE Parity Error interrupt * @retval The new state of __IT__ (SET or RESET). */ -#define __HAL_IRDA_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR & (0x01U << (((__INTERRUPT__) & IRDA_ISR_MASK)>> IRDA_ISR_POS))) != 0U) ? SET : RESET) +#define __HAL_IRDA_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\ + & (0x01U << (((__INTERRUPT__) & IRDA_ISR_MASK)>> IRDA_ISR_POS))) != 0U) ? SET : RESET) /** @brief Check whether the specified IRDA interrupt source is enabled or not. * @param __HANDLE__ specifies the IRDA Handle. @@ -597,8 +598,8 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer * @retval The new state of __IT__ (SET or RESET). */ #define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 : \ - (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 0x02U)? (__HANDLE__)->Instance->CR2 : \ - (__HANDLE__)->Instance->CR3)) & ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__)) & IRDA_IT_MASK))) != 0U) ? SET : RESET) + (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 0x02U)? (__HANDLE__)->Instance->CR2 : \ + (__HANDLE__)->Instance->CR3)) & ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__)) & IRDA_IT_MASK))) != 0U) ? SET : RESET) /** @brief Clear the specified IRDA ISR flag, in setting the proper ICR register flag. * @param __HANDLE__ specifies the IRDA Handle. @@ -636,7 +637,8 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer * @param __HANDLE__ specifies the IRDA Handle. * @retval None */ -#define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT)) +#define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3\ + &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT)) /** @brief Enable UART/USART associated to IRDA Handle. * @param __HANDLE__ specifies the IRDA Handle. @@ -683,7 +685,8 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer * @param __MODE__ IRDA communication mode. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) */ -#define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(IRDA_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U)) +#define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__)\ + & (~((uint32_t)(IRDA_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U)) /** @brief Ensure that IRDA power mode is valid. * @param __MODE__ IRDA power mode. @@ -735,8 +738,8 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer ((__PARAM__) == IRDA_RXDATA_FLUSH_REQUEST) || \ ((__PARAM__) == IRDA_TXDATA_FLUSH_REQUEST)) /** - * @} - */ + * @} + */ /* Include IRDA HAL Extended module */ #include "stm32f7xx_hal_irda_ex.h" @@ -758,7 +761,8 @@ void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda); #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) /* Callbacks Register/UnRegister functions ***********************************/ -HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID, pIRDA_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID, + pIRDA_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_irda_ex.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_irda_ex.h index 247cb740ae..7e95fd6ac5 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_irda_ex.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_irda_ex.h @@ -32,7 +32,8 @@ extern "C" { * @{ */ -/** @addtogroup IRDAEx +/** @defgroup IRDAEx IRDAEx + * @brief IRDA Extended HAL module driver * @{ */ @@ -73,8 +74,8 @@ extern "C" { do { \ if((__HANDLE__)->Instance == USART1) \ { \ - switch(__HAL_RCC_GET_USART1_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ case RCC_USART1CLKSOURCE_PCLK2: \ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2; \ break; \ @@ -90,12 +91,12 @@ extern "C" { default: \ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ else if((__HANDLE__)->Instance == USART2) \ { \ - switch(__HAL_RCC_GET_USART2_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_USART2_SOURCE()) \ + { \ case RCC_USART2CLKSOURCE_PCLK1: \ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \ break; \ @@ -111,12 +112,12 @@ extern "C" { default: \ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ else if((__HANDLE__)->Instance == USART3) \ { \ - switch(__HAL_RCC_GET_USART3_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_USART3_SOURCE()) \ + { \ case RCC_USART3CLKSOURCE_PCLK1: \ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \ break; \ @@ -132,12 +133,12 @@ extern "C" { default: \ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ else if((__HANDLE__)->Instance == UART4) \ { \ - switch(__HAL_RCC_GET_UART4_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_UART4_SOURCE()) \ + { \ case RCC_UART4CLKSOURCE_PCLK1: \ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \ break; \ @@ -153,12 +154,12 @@ extern "C" { default: \ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ else if ((__HANDLE__)->Instance == UART5) \ { \ - switch(__HAL_RCC_GET_UART5_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_UART5_SOURCE()) \ + { \ case RCC_UART5CLKSOURCE_PCLK1: \ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \ break; \ @@ -174,12 +175,12 @@ extern "C" { default: \ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ else if((__HANDLE__)->Instance == USART6) \ { \ - switch(__HAL_RCC_GET_USART6_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_USART6_SOURCE()) \ + { \ case RCC_USART6CLKSOURCE_PCLK2: \ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2; \ break; \ @@ -195,12 +196,12 @@ extern "C" { default: \ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ else if ((__HANDLE__)->Instance == UART7) \ { \ - switch(__HAL_RCC_GET_UART7_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_UART7_SOURCE()) \ + { \ case RCC_UART7CLKSOURCE_PCLK1: \ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \ break; \ @@ -216,12 +217,12 @@ extern "C" { default: \ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ else if ((__HANDLE__)->Instance == UART8) \ { \ - switch(__HAL_RCC_GET_UART8_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_UART8_SOURCE()) \ + { \ case RCC_UART8CLKSOURCE_PCLK1: \ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \ break; \ @@ -237,7 +238,7 @@ extern "C" { default: \ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ else \ { \ @@ -252,44 +253,44 @@ extern "C" { */ #define IRDA_MASK_COMPUTATION(__HANDLE__) \ do { \ - if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B) \ - { \ - if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \ - { \ + if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B) \ + { \ + if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \ + { \ (__HANDLE__)->Mask = 0x01FFU ; \ - } \ - else \ - { \ + } \ + else \ + { \ (__HANDLE__)->Mask = 0x00FFU ; \ - } \ - } \ - else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B) \ - { \ - if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \ - { \ + } \ + } \ + else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B) \ + { \ + if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \ + { \ (__HANDLE__)->Mask = 0x00FFU ; \ - } \ - else \ - { \ + } \ + else \ + { \ (__HANDLE__)->Mask = 0x007FU ; \ - } \ - } \ - else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_7B) \ - { \ - if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \ - { \ + } \ + } \ + else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_7B) \ + { \ + if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \ + { \ (__HANDLE__)->Mask = 0x007FU ; \ - } \ - else \ - { \ + } \ + else \ + { \ (__HANDLE__)->Mask = 0x003FU ; \ - } \ - } \ - else \ - { \ - (__HANDLE__)->Mask = 0x0000U; \ - } \ -} while(0U) + } \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x0000U; \ + } \ + } while(0U) /** @brief Ensure that IRDA frame length is valid. * @param __LENGTH__ IRDA frame length. diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_lptim.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_lptim.h index c5fad40138..9241b88fea 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_lptim.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_lptim.h @@ -18,11 +18,11 @@ */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F7xx_HAL_LPTIM_H -#define __STM32F7xx_HAL_LPTIM_H +#ifndef STM32F7xx_HAL_LPTIM_H +#define STM32F7xx_HAL_LPTIM_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -32,8 +32,9 @@ * @{ */ -/** @defgroup LPTIM LPTIM - * @brief LPTIM HAL module driver +#if defined (LPTIM1) + +/** @addtogroup LPTIM * @{ */ @@ -41,14 +42,7 @@ /** @defgroup LPTIM_Exported_Types LPTIM Exported Types * @{ */ - -/** @defgroup LPTIM_WAKEUPTIMER_EXTILINE LPTIM WAKEUP Timer EXTI Line - * @{ - */ -#define LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT ((uint32_t)EXTI_IMR_MR23) /*!< External interrupt line 23 Connected to the LPTIM EXTI Line */ -/** - * @} - */ +#define LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT EXTI_IMR_MR23 /*!< External interrupt line 23 Connected to the LPTIM EXTI Line */ /** * @brief LPTIM Clock configuration definition @@ -61,7 +55,7 @@ typedef struct uint32_t Prescaler; /*!< Specifies the counter clock Prescaler. This parameter can be a value of @ref LPTIM_Clock_Prescaler */ -}LPTIM_ClockConfigTypeDef; +} LPTIM_ClockConfigTypeDef; /** * @brief LPTIM Clock configuration definition @@ -79,7 +73,7 @@ typedef struct Note: This parameter is used only when Ultra low power clock source is used. This parameter can be a value of @ref LPTIM_Clock_Sample_Time */ -}LPTIM_ULPClockConfigTypeDef; +} LPTIM_ULPClockConfigTypeDef; /** * @brief LPTIM Trigger configuration definition @@ -96,7 +90,7 @@ typedef struct uint32_t SampleTime; /*!< Selects the trigger sampling time to configure the clock glitch filter. Note: This parameter is used only when an external trigger is used. This parameter can be a value of @ref LPTIM_Trigger_Sample_Time */ -}LPTIM_TriggerConfigTypeDef; +} LPTIM_TriggerConfigTypeDef; /** * @brief LPTIM Initialization Structure definition @@ -112,53 +106,58 @@ typedef struct uint32_t OutputPolarity; /*!< Specifies the Output polarity. This parameter can be a value of @ref LPTIM_Output_Polarity */ - uint32_t UpdateMode; /*!< Specifies whether the update of the autorelaod and the compare + uint32_t UpdateMode; /*!< Specifies whether the update of the autoreload and the compare values is done immediately or after the end of current period. This parameter can be a value of @ref LPTIM_Updating_Mode */ uint32_t CounterSource; /*!< Specifies whether the counter is incremented each internal event or each external event. This parameter can be a value of @ref LPTIM_Counter_Source */ - -}LPTIM_InitTypeDef; +} LPTIM_InitTypeDef; /** * @brief HAL LPTIM State structure definition */ -typedef enum __HAL_LPTIM_StateTypeDef +typedef enum { HAL_LPTIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */ HAL_LPTIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ HAL_LPTIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ HAL_LPTIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ - HAL_LPTIM_STATE_ERROR = 0x04U /*!< Internal Process is ongoing */ -}HAL_LPTIM_StateTypeDef; + HAL_LPTIM_STATE_ERROR = 0x04U /*!< Internal Process is ongoing */ +} HAL_LPTIM_StateTypeDef; /** * @brief LPTIM handle Structure definition */ +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) typedef struct __LPTIM_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ { - LPTIM_TypeDef *Instance; /*!< Register base address */ - LPTIM_InitTypeDef Init; /*!< LPTIM required parameters */ - HAL_StatusTypeDef Status; /*!< LPTIM peripheral status */ - HAL_LockTypeDef Lock; /*!< LPTIM locking object */ - __IO HAL_LPTIM_StateTypeDef State; /*!< LPTIM peripheral state */ + LPTIM_TypeDef *Instance; /*!< Register base address */ + + LPTIM_InitTypeDef Init; /*!< LPTIM required parameters */ + + HAL_StatusTypeDef Status; /*!< LPTIM peripheral status */ + + HAL_LockTypeDef Lock; /*!< LPTIM locking object */ + + __IO HAL_LPTIM_StateTypeDef State; /*!< LPTIM peripheral state */ #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) - void (* MspInitCallback) (struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Msp Init Callback */ - void (* MspDeInitCallback) (struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Msp DeInit Callback */ - - void (* CompareMatchCallback) (struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Compare Match Callback */ - void (* AutoReloadMatchCallback) (struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Auto Reload Match Callback */ - void (* TriggerCallback) (struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Trigger Callback */ - void (* CompareWriteCallback) (struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Compare Write Callback */ - void (* AutoReloadWriteCallback) (struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Auto Reload Write Callback */ - void (* DirectionUpCallback) (struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Direction Up Callback */ - void (* DirectionDownCallback) (struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Direction Down Callback */ + void (* MspInitCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Base Msp Init Callback */ + void (* MspDeInitCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Base Msp DeInit Callback */ + void (* CompareMatchCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Compare match Callback */ + void (* AutoReloadMatchCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Auto-reload match Callback */ + void (* TriggerCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< External trigger event detection Callback */ + void (* CompareWriteCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Compare register write complete Callback */ + void (* AutoReloadWriteCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Auto-reload register write complete Callback */ + void (* DirectionUpCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Up-counting direction change Callback */ + void (* DirectionDownCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Down-counting direction change Callback */ #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ - -}LPTIM_HandleTypeDef; +} LPTIM_HandleTypeDef; #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) /** @@ -166,25 +165,23 @@ typedef struct __LPTIM_HandleTypeDef */ typedef enum { - HAL_LPTIM_MSPINIT_CB_ID = 0x00U, /*!< LPTIM MspInit Callback ID */ - HAL_LPTIM_MSPDEINIT_CB_ID = 0x01U, /*!< LPTIM MspDeInit Callback ID */ - - HAL_LPTIM_COMPARE_MATCH_CB_ID = 0x02U, /*!< LPTIM Compare Match Callback ID */ - HAL_LPTIM_AUTO_RELOAD_MATCH_CB_ID = 0x03U, /*!< LPTIM Auto Reload Match Callback ID */ - HAL_LPTIM_TRIGGER_CB_ID = 0x04U, /*!< LPTIM Trigger Callback ID */ - HAL_LPTIM_COMPARE_WRITE_CB_ID = 0x05U, /*!< LPTIM Compare Write Callback ID */ - HAL_LPTIM_AUTO_RELOAD_WRITE_CB_ID = 0x06U, /*!< LPTIM Auto Reload Write Callback ID */ - HAL_LPTIM_DIRECTION_UP_CB_ID = 0x07U, /*!< LPTIM Direction Up Callback ID */ - HAL_LPTIM_DIRECTION_DOWN_CB_ID = 0x08U, /*!< LPTIM Direction Down Callback ID */ -}HAL_LPTIM_CallbackIDTypeDef; + HAL_LPTIM_MSPINIT_CB_ID = 0x00U, /*!< LPTIM Base Msp Init Callback ID */ + HAL_LPTIM_MSPDEINIT_CB_ID = 0x01U, /*!< LPTIM Base Msp DeInit Callback ID */ + HAL_LPTIM_COMPARE_MATCH_CB_ID = 0x02U, /*!< Compare match Callback ID */ + HAL_LPTIM_AUTORELOAD_MATCH_CB_ID = 0x03U, /*!< Auto-reload match Callback ID */ + HAL_LPTIM_TRIGGER_CB_ID = 0x04U, /*!< External trigger event detection Callback ID */ + HAL_LPTIM_COMPARE_WRITE_CB_ID = 0x05U, /*!< Compare register write complete Callback ID */ + HAL_LPTIM_AUTORELOAD_WRITE_CB_ID = 0x06U, /*!< Auto-reload register write complete Callback ID */ + HAL_LPTIM_DIRECTION_UP_CB_ID = 0x07U, /*!< Up-counting direction change Callback ID */ + HAL_LPTIM_DIRECTION_DOWN_CB_ID = 0x08U, /*!< Down-counting direction change Callback ID */ +} HAL_LPTIM_CallbackIDTypeDef; /** - * @brief HAL LPTIM Callback pointer definition + * @brief HAL TIM Callback pointer definition */ -typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef * hlptim); /*!< pointer to the LPTIM callback function */ +typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< pointer to the LPTIM callback function */ #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ - /** * @} */ @@ -197,7 +194,7 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef * hlptim); /*!< poin /** @defgroup LPTIM_Clock_Source LPTIM Clock Source * @{ */ -#define LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC ((uint32_t)0x00U) +#define LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC 0x00000000U #define LPTIM_CLOCKSOURCE_ULPTIM LPTIM_CFGR_CKSEL /** * @} @@ -206,14 +203,14 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef * hlptim); /*!< poin /** @defgroup LPTIM_Clock_Prescaler LPTIM Clock Prescaler * @{ */ -#define LPTIM_PRESCALER_DIV1 ((uint32_t)0x000000U) +#define LPTIM_PRESCALER_DIV1 0x00000000U #define LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0 #define LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1 -#define LPTIM_PRESCALER_DIV8 ((uint32_t)(LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_1)) +#define LPTIM_PRESCALER_DIV8 (LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_1) #define LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2 -#define LPTIM_PRESCALER_DIV32 ((uint32_t)(LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_2)) -#define LPTIM_PRESCALER_DIV64 ((uint32_t)(LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_2)) -#define LPTIM_PRESCALER_DIV128 ((uint32_t)LPTIM_CFGR_PRESC) +#define LPTIM_PRESCALER_DIV32 (LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_2) +#define LPTIM_PRESCALER_DIV64 (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_2) +#define LPTIM_PRESCALER_DIV128 LPTIM_CFGR_PRESC /** * @} */ @@ -222,8 +219,8 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef * hlptim); /*!< poin * @{ */ -#define LPTIM_OUTPUTPOLARITY_HIGH ((uint32_t)0x00000000U) -#define LPTIM_OUTPUTPOLARITY_LOW (LPTIM_CFGR_WAVPOL) +#define LPTIM_OUTPUTPOLARITY_HIGH 0x00000000U +#define LPTIM_OUTPUTPOLARITY_LOW LPTIM_CFGR_WAVPOL /** * @} */ @@ -231,10 +228,10 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef * hlptim); /*!< poin /** @defgroup LPTIM_Clock_Sample_Time LPTIM Clock Sample Time * @{ */ -#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION ((uint32_t)0x00000000U) -#define LPTIM_CLOCKSAMPLETIME_2TRANSITIONS LPTIM_CFGR_CKFLT_0 -#define LPTIM_CLOCKSAMPLETIME_4TRANSITIONS LPTIM_CFGR_CKFLT_1 -#define LPTIM_CLOCKSAMPLETIME_8TRANSITIONS LPTIM_CFGR_CKFLT +#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION 0x00000000U +#define LPTIM_CLOCKSAMPLETIME_2TRANSITIONS LPTIM_CFGR_CKFLT_0 +#define LPTIM_CLOCKSAMPLETIME_4TRANSITIONS LPTIM_CFGR_CKFLT_1 +#define LPTIM_CLOCKSAMPLETIME_8TRANSITIONS LPTIM_CFGR_CKFLT /** * @} */ @@ -242,10 +239,9 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef * hlptim); /*!< poin /** @defgroup LPTIM_Clock_Polarity LPTIM Clock Polarity * @{ */ - -#define LPTIM_CLOCKPOLARITY_RISING ((uint32_t)0x00000000U) -#define LPTIM_CLOCKPOLARITY_FALLING LPTIM_CFGR_CKPOL_0 -#define LPTIM_CLOCKPOLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1 +#define LPTIM_CLOCKPOLARITY_RISING 0x00000000U +#define LPTIM_CLOCKPOLARITY_FALLING LPTIM_CFGR_CKPOL_0 +#define LPTIM_CLOCKPOLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1 /** * @} */ @@ -253,13 +249,13 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef * hlptim); /*!< poin /** @defgroup LPTIM_Trigger_Source LPTIM Trigger Source * @{ */ -#define LPTIM_TRIGSOURCE_SOFTWARE ((uint32_t)0x0000FFFFU) -#define LPTIM_TRIGSOURCE_0 ((uint32_t)0x00000000U) -#define LPTIM_TRIGSOURCE_1 ((uint32_t)LPTIM_CFGR_TRIGSEL_0) +#define LPTIM_TRIGSOURCE_SOFTWARE 0x0000FFFFU +#define LPTIM_TRIGSOURCE_0 0x00000000U +#define LPTIM_TRIGSOURCE_1 LPTIM_CFGR_TRIGSEL_0 #define LPTIM_TRIGSOURCE_2 LPTIM_CFGR_TRIGSEL_1 -#define LPTIM_TRIGSOURCE_3 ((uint32_t)LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1) +#define LPTIM_TRIGSOURCE_3 (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1) #define LPTIM_TRIGSOURCE_4 LPTIM_CFGR_TRIGSEL_2 -#define LPTIM_TRIGSOURCE_5 ((uint32_t)LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_2) +#define LPTIM_TRIGSOURCE_5 (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_2) /** * @} */ @@ -277,7 +273,7 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef * hlptim); /*!< poin /** @defgroup LPTIM_Trigger_Sample_Time LPTIM Trigger Sample Time * @{ */ -#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION ((uint32_t)0x00000000U) +#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION 0x00000000U #define LPTIM_TRIGSAMPLETIME_2TRANSITIONS LPTIM_CFGR_TRGFLT_0 #define LPTIM_TRIGSAMPLETIME_4TRANSITIONS LPTIM_CFGR_TRGFLT_1 #define LPTIM_TRIGSAMPLETIME_8TRANSITIONS LPTIM_CFGR_TRGFLT @@ -289,7 +285,7 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef * hlptim); /*!< poin * @{ */ -#define LPTIM_UPDATE_IMMEDIATE ((uint32_t)0x00000000U) +#define LPTIM_UPDATE_IMMEDIATE 0x00000000U #define LPTIM_UPDATE_ENDOFPERIOD LPTIM_CFGR_PRELOAD /** * @} @@ -299,13 +295,13 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef * hlptim); /*!< poin * @{ */ -#define LPTIM_COUNTERSOURCE_INTERNAL ((uint32_t)0x00000000U) +#define LPTIM_COUNTERSOURCE_INTERNAL 0x00000000U #define LPTIM_COUNTERSOURCE_EXTERNAL LPTIM_CFGR_COUNTMODE /** * @} */ -/** @defgroup LPTIM_Flag_Definition LPTIM Flag Definition +/** @defgroup LPTIM_Flag_Definition LPTIM Flags Definition * @{ */ @@ -323,7 +319,6 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef * hlptim); /*!< poin /** @defgroup LPTIM_Interrupts_Definition LPTIM Interrupts Definition * @{ */ - #define LPTIM_IT_DOWN LPTIM_IER_DOWNIE #define LPTIM_IT_UP LPTIM_IER_UPIE #define LPTIM_IT_ARROK LPTIM_IER_ARROKIE @@ -339,54 +334,79 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef * hlptim); /*!< poin * @} */ -/* Exported macro ------------------------------------------------------------*/ +/* Exported macros -----------------------------------------------------------*/ /** @defgroup LPTIM_Exported_Macros LPTIM Exported Macros * @{ */ -/** @brief Reset LPTIM handle state +/** @brief Reset LPTIM handle state. * @param __HANDLE__ LPTIM handle * @retval None */ +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) +#define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_LPTIM_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else #define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LPTIM_STATE_RESET) +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ /** - * @brief Enable/Disable the LPTIM peripheral. + * @brief Enable the LPTIM peripheral. * @param __HANDLE__ LPTIM handle * @retval None */ -#define __HAL_LPTIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (LPTIM_CR_ENABLE)) -#define __HAL_LPTIM_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(LPTIM_CR_ENABLE)) +#define __HAL_LPTIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (LPTIM_CR_ENABLE)) /** - * @brief Starts the LPTIM peripheral in Continuous or in single mode. - * @param __HANDLE__ DMA handle + * @brief Disable the LPTIM peripheral. + * @param __HANDLE__ LPTIM handle + * @note The following sequence is required to solve LPTIM disable HW limitation. + * Please check Errata Sheet ES0335 for more details under "MCU may remain + * stuck in LPTIM interrupt when entering Stop mode" section. + * @note Please call @ref HAL_LPTIM_GetState() after a call to __HAL_LPTIM_DISABLE to + * check for TIMEOUT. + * @retval None + */ +#define __HAL_LPTIM_DISABLE(__HANDLE__) LPTIM_Disable(__HANDLE__) + +/** + * @brief Start the LPTIM peripheral in Continuous mode. + * @param __HANDLE__ LPTIM handle * @retval None */ #define __HAL_LPTIM_START_CONTINUOUS(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_CNTSTRT) +/** + * @brief Start the LPTIM peripheral in single mode. + * @param __HANDLE__ LPTIM handle + * @retval None + */ #define __HAL_LPTIM_START_SINGLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_SNGSTRT) - /** - * @brief Writes the passed parameter in the Autoreload register. + * @brief Write the passed parameter in the Autoreload register. * @param __HANDLE__ LPTIM handle - * @param __VALUE__ Autoreload value + * @param __VALUE__ Autoreload value * @retval None + * @note The ARR register can only be modified when the LPTIM instance is enabled. */ #define __HAL_LPTIM_AUTORELOAD_SET(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->ARR = (__VALUE__)) /** - * @brief Writes the passed parameter in the Compare register. + * @brief Write the passed parameter in the Compare register. * @param __HANDLE__ LPTIM handle - * @param __VALUE__ Compare value + * @param __VALUE__ Compare value * @retval None + * @note The CMP register can only be modified when the LPTIM instance is enabled. */ #define __HAL_LPTIM_COMPARE_SET(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->CMP = (__VALUE__)) /** - * @brief Checks whether the specified LPTIM flag is set or not. + * @brief Check whether the specified LPTIM flag is set or not. * @param __HANDLE__ LPTIM handle - * @param __FLAG__ LPTIM flag to check + * @param __FLAG__ LPTIM flag to check * This parameter can be a value of: * @arg LPTIM_FLAG_DOWN : Counter direction change up Flag. * @arg LPTIM_FLAG_UP : Counter direction change down to up Flag. @@ -400,9 +420,9 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef * hlptim); /*!< poin #define __HAL_LPTIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR &(__FLAG__)) == (__FLAG__)) /** - * @brief Clears the specified LPTIM flag. + * @brief Clear the specified LPTIM flag. * @param __HANDLE__ LPTIM handle. - * @param __FLAG__ LPTIM flag to clear. + * @param __FLAG__ LPTIM flag to clear. * This parameter can be a value of: * @arg LPTIM_FLAG_DOWN : Counter direction change up Flag. * @arg LPTIM_FLAG_UP : Counter direction change down to up Flag. @@ -413,12 +433,12 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef * hlptim); /*!< poin * @arg LPTIM_FLAG_CMPM : Compare match Flag. * @retval None. */ -#define __HAL_LPTIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) +#define __HAL_LPTIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) /** * @brief Enable the specified LPTIM interrupt. - * @param __HANDLE__ LPTIM handle. - * @param __INTERRUPT__ LPTIM interrupt to set. + * @param __HANDLE__ LPTIM handle. + * @param __INTERRUPT__ LPTIM interrupt to set. * This parameter can be a value of: * @arg LPTIM_IT_DOWN : Counter direction change up Interrupt. * @arg LPTIM_IT_UP : Counter direction change down to up Interrupt. @@ -428,13 +448,14 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef * hlptim); /*!< poin * @arg LPTIM_IT_ARRM : Autoreload match Interrupt. * @arg LPTIM_IT_CMPM : Compare match Interrupt. * @retval None. + * @note The LPTIM interrupts can only be enabled when the LPTIM instance is disabled. */ -#define __HAL_LPTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) +#define __HAL_LPTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) - /** +/** * @brief Disable the specified LPTIM interrupt. - * @param __HANDLE__ LPTIM handle. - * @param __INTERRUPT__ LPTIM interrupt to set. + * @param __HANDLE__ LPTIM handle. + * @param __INTERRUPT__ LPTIM interrupt to set. * This parameter can be a value of: * @arg LPTIM_IT_DOWN : Counter direction change up Interrupt. * @arg LPTIM_IT_UP : Counter direction change down to up Interrupt. @@ -444,13 +465,14 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef * hlptim); /*!< poin * @arg LPTIM_IT_ARRM : Autoreload match Interrupt. * @arg LPTIM_IT_CMPM : Compare match Interrupt. * @retval None. + * @note The LPTIM interrupts can only be disabled when the LPTIM instance is disabled. */ -#define __HAL_LPTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__))) +#define __HAL_LPTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__))) - /** - * @brief Checks whether the specified LPTIM interrupt is set or not. - * @param __HANDLE__ LPTIM handle. - * @param __INTERRUPT__ LPTIM interrupt to check. +/** + * @brief Check whether the specified LPTIM interrupt source is enabled or not. + * @param __HANDLE__ LPTIM handle. + * @param __INTERRUPT__ LPTIM interrupt to check. * This parameter can be a value of: * @arg LPTIM_IT_DOWN : Counter direction change up Interrupt. * @arg LPTIM_IT_UP : Counter direction change down to up Interrupt. @@ -522,7 +544,6 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef * hlptim); /*!< poin /** * @brief Disable rising & falling edge trigger on the LPTIM Wake-up Timer associated Exti line. - * This parameter can be: * @retval None. */ #define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() do{__HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();\ @@ -556,6 +577,10 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef * hlptim); /*!< poin * @{ */ +/** @addtogroup LPTIM_Exported_Functions_Group1 + * @brief Initialization and Configuration functions. + * @{ + */ /* Initialization/de-initialization functions ********************************/ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim); HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim); @@ -563,7 +588,14 @@ HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim); /* MSP functions *************************************************************/ void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim); void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim); +/** + * @} + */ +/** @addtogroup LPTIM_Exported_Functions_Group2 + * @brief Start-Stop operation functions. + * @{ + */ /* Start/Stop operation functions *********************************************/ /* ################################# PWM Mode ################################*/ /* Blocking mode: Polling */ @@ -612,12 +644,26 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim); /* Non-Blocking mode: Interrupt */ HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period); HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim); +/** + * @} + */ +/** @addtogroup LPTIM_Exported_Functions_Group3 + * @brief Read operation functions. + * @{ + */ /* Reading operation functions ************************************************/ uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim); uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim); uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim); +/** + * @} + */ +/** @addtogroup LPTIM_Exported_Functions_Group4 + * @brief LPTIM IRQ handler and callback functions. + * @{ + */ /* LPTIM IRQ functions *******************************************************/ void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim); @@ -632,12 +678,22 @@ void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim); /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *hlptim, HAL_LPTIM_CallbackIDTypeDef CallbackID, pLPTIM_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlptim, HAL_LPTIM_CallbackIDTypeDef CallbackID); +HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID, pLPTIM_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ +/** + * @} + */ +/** @addtogroup LPTIM_Group5 + * @brief Peripheral State functions. + * @{ + */ /* Peripheral State functions ************************************************/ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim); +/** + * @} + */ /** * @} @@ -675,61 +731,63 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim); * @{ */ -#define IS_LPTIM_CLOCK_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_CLOCKSOURCE_ULPTIM) || \ - ((__SOURCE__) == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC)) +#define IS_LPTIM_CLOCK_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_CLOCKSOURCE_ULPTIM) || \ + ((__SOURCE__) == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC)) + + +#define IS_LPTIM_CLOCK_PRESCALER(__PRESCALER__) (((__PRESCALER__) == LPTIM_PRESCALER_DIV1 ) || \ + ((__PRESCALER__) == LPTIM_PRESCALER_DIV2 ) || \ + ((__PRESCALER__) == LPTIM_PRESCALER_DIV4 ) || \ + ((__PRESCALER__) == LPTIM_PRESCALER_DIV8 ) || \ + ((__PRESCALER__) == LPTIM_PRESCALER_DIV16 ) || \ + ((__PRESCALER__) == LPTIM_PRESCALER_DIV32 ) || \ + ((__PRESCALER__) == LPTIM_PRESCALER_DIV64 ) || \ + ((__PRESCALER__) == LPTIM_PRESCALER_DIV128)) -#define IS_LPTIM_CLOCK_PRESCALER(__PRESCALER__) (((__PRESCALER__) == LPTIM_PRESCALER_DIV1 ) || \ - ((__PRESCALER__) == LPTIM_PRESCALER_DIV2 ) || \ - ((__PRESCALER__) == LPTIM_PRESCALER_DIV4 ) || \ - ((__PRESCALER__) == LPTIM_PRESCALER_DIV8 ) || \ - ((__PRESCALER__) == LPTIM_PRESCALER_DIV16 ) || \ - ((__PRESCALER__) == LPTIM_PRESCALER_DIV32 ) || \ - ((__PRESCALER__) == LPTIM_PRESCALER_DIV64 ) || \ - ((__PRESCALER__) == LPTIM_PRESCALER_DIV128)) #define IS_LPTIM_CLOCK_PRESCALERDIV1(__PRESCALER__) ((__PRESCALER__) == LPTIM_PRESCALER_DIV1) -#define IS_LPTIM_OUTPUT_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_OUTPUTPOLARITY_LOW ) || \ - ((__POLARITY__) == LPTIM_OUTPUTPOLARITY_HIGH)) +#define IS_LPTIM_OUTPUT_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_OUTPUTPOLARITY_LOW ) || \ + ((__POLARITY__) == LPTIM_OUTPUTPOLARITY_HIGH)) -#define IS_LPTIM_CLOCK_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION) || \ - ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_2TRANSITIONS) || \ - ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_4TRANSITIONS) || \ - ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_8TRANSITIONS)) +#define IS_LPTIM_CLOCK_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION) || \ + ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_2TRANSITIONS) || \ + ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_4TRANSITIONS) || \ + ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_8TRANSITIONS)) -#define IS_LPTIM_CLOCK_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING) || \ - ((__POLARITY__) == LPTIM_CLOCKPOLARITY_FALLING) || \ - ((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING_FALLING)) +#define IS_LPTIM_CLOCK_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING) || \ + ((__POLARITY__) == LPTIM_CLOCKPOLARITY_FALLING) || \ + ((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING_FALLING)) -#define IS_LPTIM_TRG_SOURCE(__TRIG__) (((__TRIG__) == LPTIM_TRIGSOURCE_SOFTWARE) || \ - ((__TRIG__) == LPTIM_TRIGSOURCE_0) || \ - ((__TRIG__) == LPTIM_TRIGSOURCE_1) || \ - ((__TRIG__) == LPTIM_TRIGSOURCE_2) || \ - ((__TRIG__) == LPTIM_TRIGSOURCE_3) || \ - ((__TRIG__) == LPTIM_TRIGSOURCE_4) || \ - ((__TRIG__) == LPTIM_TRIGSOURCE_5)) +#define IS_LPTIM_TRG_SOURCE(__TRIG__) (((__TRIG__) == LPTIM_TRIGSOURCE_SOFTWARE) || \ + ((__TRIG__) == LPTIM_TRIGSOURCE_0) || \ + ((__TRIG__) == LPTIM_TRIGSOURCE_1) || \ + ((__TRIG__) == LPTIM_TRIGSOURCE_2) || \ + ((__TRIG__) == LPTIM_TRIGSOURCE_3) || \ + ((__TRIG__) == LPTIM_TRIGSOURCE_4) || \ + ((__TRIG__) == LPTIM_TRIGSOURCE_5)) -#define IS_LPTIM_EXT_TRG_POLARITY(__POLAR__) (((__POLAR__) == LPTIM_ACTIVEEDGE_RISING ) || \ - ((__POLAR__) == LPTIM_ACTIVEEDGE_FALLING ) || \ - ((__POLAR__) == LPTIM_ACTIVEEDGE_RISING_FALLING )) +#define IS_LPTIM_EXT_TRG_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING ) || \ + ((__POLARITY__) == LPTIM_ACTIVEEDGE_FALLING ) || \ + ((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING_FALLING )) -#define IS_LPTIM_TRIG_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION) || \ - ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_2TRANSITIONS ) || \ - ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_4TRANSITIONS ) || \ - ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_8TRANSITIONS )) +#define IS_LPTIM_TRIG_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION) || \ + ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_2TRANSITIONS ) || \ + ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_4TRANSITIONS ) || \ + ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_8TRANSITIONS )) -#define IS_LPTIM_UPDATE_MODE(__MODE__) (((__MODE__) == LPTIM_UPDATE_IMMEDIATE) || \ - ((__MODE__) == LPTIM_UPDATE_ENDOFPERIOD)) +#define IS_LPTIM_UPDATE_MODE(__MODE__) (((__MODE__) == LPTIM_UPDATE_IMMEDIATE) || \ + ((__MODE__) == LPTIM_UPDATE_ENDOFPERIOD)) -#define IS_LPTIM_COUNTER_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || \ - ((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL)) +#define IS_LPTIM_COUNTER_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || \ + ((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL)) -#define IS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((__AUTORELOAD__) <= 0x0000FFFFU) +#define IS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((__AUTORELOAD__) <= 0x0000FFFFUL) -#define IS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) <= 0x0000FFFFU) +#define IS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) <= 0x0000FFFFUL) -#define IS_LPTIM_PERIOD(PERIOD) ((PERIOD) <= 0x0000FFFFU) +#define IS_LPTIM_PERIOD(__PERIOD__) ((__PERIOD__) <= 0x0000FFFFUL) -#define IS_LPTIM_PULSE(PULSE) ((PULSE) <= 0x0000FFFFU) +#define IS_LPTIM_PULSE(__PULSE__) ((__PULSE__) <= 0x0000FFFFUL) /** * @} @@ -739,7 +797,7 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim); /** @defgroup LPTIM_Private_Functions LPTIM Private Functions * @{ */ - +void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim); /** * @} */ @@ -748,6 +806,7 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim); * @} */ +#endif /* LPTIM1 */ /** * @} */ @@ -756,6 +815,6 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim); } #endif -#endif /* __STM32F7xx_HAL_LPTIM_H */ +#endif /* STM32F7xx_HAL_LPTIM_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_mmc.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_mmc.h index 00f4399230..539678c571 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_mmc.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_mmc.h @@ -12,14 +12,16 @@ * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F7xx_HAL_MMC_H -#define __STM32F7xx_HAL_MMC_H +#ifndef STM32F7xx_HAL_MMC_H +#define STM32F7xx_HAL_MMC_H + +#if defined(SDMMC1) #ifdef __cplusplus extern "C" { @@ -46,14 +48,14 @@ */ typedef enum { - HAL_MMC_STATE_RESET = ((uint32_t)0x00000000U), /*!< MMC not yet initialized or disabled */ - HAL_MMC_STATE_READY = ((uint32_t)0x00000001U), /*!< MMC initialized and ready for use */ - HAL_MMC_STATE_TIMEOUT = ((uint32_t)0x00000002U), /*!< MMC Timeout state */ - HAL_MMC_STATE_BUSY = ((uint32_t)0x00000003U), /*!< MMC process ongoing */ - HAL_MMC_STATE_PROGRAMMING = ((uint32_t)0x00000004U), /*!< MMC Programming State */ - HAL_MMC_STATE_RECEIVING = ((uint32_t)0x00000005U), /*!< MMC Receinving State */ - HAL_MMC_STATE_TRANSFER = ((uint32_t)0x00000006U), /*!< MMC Transfert State */ - HAL_MMC_STATE_ERROR = ((uint32_t)0x0000000FU) /*!< MMC is in error state */ + HAL_MMC_STATE_RESET = 0x00000000U, /*!< MMC not yet initialized or disabled */ + HAL_MMC_STATE_READY = 0x00000001U, /*!< MMC initialized and ready for use */ + HAL_MMC_STATE_TIMEOUT = 0x00000002U, /*!< MMC Timeout state */ + HAL_MMC_STATE_BUSY = 0x00000003U, /*!< MMC process ongoing */ + HAL_MMC_STATE_PROGRAMMING = 0x00000004U, /*!< MMC Programming State */ + HAL_MMC_STATE_RECEIVING = 0x00000005U, /*!< MMC Receinving State */ + HAL_MMC_STATE_TRANSFER = 0x00000006U, /*!< MMC Transfert State */ + HAL_MMC_STATE_ERROR = 0x0000000FU /*!< MMC is in error state */ }HAL_MMC_StateTypeDef; /** * @} @@ -62,18 +64,17 @@ typedef enum /** @defgroup MMC_Exported_Types_Group2 MMC Card State enumeration structure * @{ */ -typedef enum -{ - HAL_MMC_CARD_READY = ((uint32_t)0x00000001U), /*!< Card state is ready */ - HAL_MMC_CARD_IDENTIFICATION = ((uint32_t)0x00000002U), /*!< Card is in identification state */ - HAL_MMC_CARD_STANDBY = ((uint32_t)0x00000003U), /*!< Card is in standby state */ - HAL_MMC_CARD_TRANSFER = ((uint32_t)0x00000004U), /*!< Card is in transfer state */ - HAL_MMC_CARD_SENDING = ((uint32_t)0x00000005U), /*!< Card is sending an operation */ - HAL_MMC_CARD_RECEIVING = ((uint32_t)0x00000006U), /*!< Card is receiving operation information */ - HAL_MMC_CARD_PROGRAMMING = ((uint32_t)0x00000007U), /*!< Card is in programming state */ - HAL_MMC_CARD_DISCONNECTED = ((uint32_t)0x00000008U), /*!< Card is disconnected */ - HAL_MMC_CARD_ERROR = ((uint32_t)0x000000FFU) /*!< Card response Error */ -}HAL_MMC_CardStateTypeDef; +typedef uint32_t HAL_MMC_CardStateTypeDef; + +#define HAL_MMC_CARD_READY 0x00000001U /*!< Card state is ready */ +#define HAL_MMC_CARD_IDENTIFICATION 0x00000002U /*!< Card is in identification state */ +#define HAL_MMC_CARD_STANDBY 0x00000003U /*!< Card is in standby state */ +#define HAL_MMC_CARD_TRANSFER 0x00000004U /*!< Card is in transfer state */ +#define HAL_MMC_CARD_SENDING 0x00000005U /*!< Card is sending an operation */ +#define HAL_MMC_CARD_RECEIVING 0x00000006U /*!< Card is receiving operation information */ +#define HAL_MMC_CARD_PROGRAMMING 0x00000007U /*!< Card is in programming state */ +#define HAL_MMC_CARD_DISCONNECTED 0x00000008U /*!< Card is disconnected */ +#define HAL_MMC_CARD_ERROR 0x000000FFU /*!< Card response Error */ /** * @} */ @@ -114,23 +115,23 @@ typedef struct __MMC_HandleTypeDef typedef struct #endif /* USE_HAL_MMC_REGISTER_CALLBACKS */ { - MMC_TypeDef *Instance; /*!< MMC registers base address */ + MMC_TypeDef *Instance; /*!< MMC registers base address */ - MMC_InitTypeDef Init; /*!< MMC required parameters */ + MMC_InitTypeDef Init; /*!< MMC required parameters */ HAL_LockTypeDef Lock; /*!< MMC locking object */ - uint32_t *pTxBuffPtr; /*!< Pointer to MMC Tx transfer Buffer */ + uint8_t *pTxBuffPtr; /*!< Pointer to MMC Tx transfer Buffer */ uint32_t TxXferSize; /*!< MMC Tx Transfer size */ - uint32_t *pRxBuffPtr; /*!< Pointer to MMC Rx transfer Buffer */ + uint8_t *pRxBuffPtr; /*!< Pointer to MMC Rx transfer Buffer */ uint32_t RxXferSize; /*!< MMC Rx Transfer size */ __IO uint32_t Context; /*!< MMC transfer context */ - __IO HAL_MMC_StateTypeDef State; /*!< MMC card State */ + __IO HAL_MMC_StateTypeDef State; /*!< MMC card State */ __IO uint32_t ErrorCode; /*!< MMC Card Error codes */ @@ -138,13 +139,13 @@ typedef struct DMA_HandleTypeDef *hdmatx; /*!< MMC Tx DMA handle parameters */ - HAL_MMC_CardInfoTypeDef MmcCard; /*!< MMC Card information */ + HAL_MMC_CardInfoTypeDef MmcCard; /*!< MMC Card information */ - uint32_t CSD[4]; /*!< MMC card specific data table */ + uint32_t CSD[4U]; /*!< MMC card specific data table */ - uint32_t CID[4]; /*!< MMC card identification number table */ + uint32_t CID[4U]; /*!< MMC card identification number table */ - #if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) void (* TxCpltCallback) (struct __MMC_HandleTypeDef *hmmc); void (* RxCpltCallback) (struct __MMC_HandleTypeDef *hmmc); void (* ErrorCallback) (struct __MMC_HandleTypeDef *hmmc); @@ -193,7 +194,7 @@ typedef struct __IO uint8_t WriteBlockPaPartial; /*!< Partial blocks for write allowed */ __IO uint8_t Reserved3; /*!< Reserved */ __IO uint8_t ContentProtectAppli; /*!< Content protection application */ - __IO uint8_t FileFormatGrouop; /*!< File format group */ + __IO uint8_t FileFormatGroup; /*!< File format group */ __IO uint8_t CopyFlag; /*!< Copy flag (OTP) */ __IO uint8_t PermWrProtect; /*!< Permanent write protection */ __IO uint8_t TempWrProtect; /*!< Temporary write protection */ @@ -227,6 +228,7 @@ typedef struct /** * @} */ + #if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) /** @defgroup MMC_Exported_Types_Group6 MMC Callback ID enumeration definition * @{ @@ -262,8 +264,7 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc); * @{ */ -#define BLOCKSIZE ((uint32_t)512U) /*!< Block size is 512 bytes */ -#define CAPACITY ((uint32_t)0x80000000U) /*!< 2 G bytes constant */ +#define MMC_BLOCKSIZE 512U /*!< Block size is 512 bytes */ /** @defgroup MMC_Exported_Constansts_Group1 MMC Error status enumeration Structure definition * @{ @@ -304,6 +305,7 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc); #define HAL_MMC_ERROR_BUSY SDMMC_ERROR_BUSY /*!< Error when transfer process is busy */ #define HAL_MMC_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */ #define HAL_MMC_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */ + #if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) #define HAL_MMC_ERROR_INVALID_CALLBACK SDMMC_ERROR_INVALID_PARAMETER /*!< Invalid callback error */ #endif @@ -314,13 +316,13 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc); /** @defgroup MMC_Exported_Constansts_Group2 MMC context enumeration * @{ */ -#define MMC_CONTEXT_NONE ((uint32_t)0x00000000U) /*!< None */ -#define MMC_CONTEXT_READ_SINGLE_BLOCK ((uint32_t)0x00000001U) /*!< Read single block operation */ -#define MMC_CONTEXT_READ_MULTIPLE_BLOCK ((uint32_t)0x00000002U) /*!< Read multiple blocks operation */ -#define MMC_CONTEXT_WRITE_SINGLE_BLOCK ((uint32_t)0x00000010U) /*!< Write single block operation */ -#define MMC_CONTEXT_WRITE_MULTIPLE_BLOCK ((uint32_t)0x00000020U) /*!< Write multiple blocks operation */ -#define MMC_CONTEXT_IT ((uint32_t)0x00000008U) /*!< Process in Interrupt mode */ -#define MMC_CONTEXT_DMA ((uint32_t)0x00000080U) /*!< Process in DMA mode */ +#define MMC_CONTEXT_NONE 0x00000000U /*!< None */ +#define MMC_CONTEXT_READ_SINGLE_BLOCK 0x00000001U /*!< Read single block operation */ +#define MMC_CONTEXT_READ_MULTIPLE_BLOCK 0x00000002U /*!< Read multiple blocks operation */ +#define MMC_CONTEXT_WRITE_SINGLE_BLOCK 0x00000010U /*!< Write single block operation */ +#define MMC_CONTEXT_WRITE_MULTIPLE_BLOCK 0x00000020U /*!< Write multiple blocks operation */ +#define MMC_CONTEXT_IT 0x00000008U /*!< Process in Interrupt mode */ +#define MMC_CONTEXT_DMA 0x00000080U /*!< Process in DMA mode */ /** * @} @@ -344,8 +346,9 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc); /** @defgroup MMC_Exported_Constansts_Group4 MMC Memory Cards * @{ */ -#define MMC_HIGH_VOLTAGE_CARD ((uint32_t)0x00000000U) -#define MMC_DUAL_VOLTAGE_CARD ((uint32_t)0x00000001U) +#define MMC_LOW_CAPACITY_CARD 0x00000000U /*!< MMC Card Capacity <=2Gbytes */ +#define MMC_HIGH_CAPACITY_CARD 0x00000001U /*!< MMC Card Capacity >2Gbytes and <2Tbytes */ + /** * @} */ @@ -399,8 +402,8 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc); /** * @brief Enable the MMC device interrupt. - * @param __HANDLE__ MMC Handle - * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be enabled. + * @param __HANDLE__: MMC Handle + * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled. * This parameter can be one or a combination of the following values: * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt @@ -410,7 +413,7 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc); * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt - * @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt + * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt @@ -430,8 +433,8 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc); /** * @brief Disable the MMC device interrupt. - * @param __HANDLE__ MMC Handle - * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be disabled. + * @param __HANDLE__: MMC Handle + * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled. * This parameter can be one or a combination of the following values: * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt @@ -441,7 +444,7 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc); * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt - * @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt + * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt @@ -461,8 +464,8 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc); /** * @brief Check whether the specified MMC flag is set or not. - * @param __HANDLE__ MMC Handle - * @param __FLAG__ specifies the flag to check. + * @param __HANDLE__: MMC Handle + * @param __FLAG__: specifies the flag to check. * This parameter can be one of the following values: * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) @@ -472,7 +475,7 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc); * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed) * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required) - * @arg SDMMC_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) + * @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero) * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed) * @arg SDMMC_FLAG_CMDACT: Command transfer in progress * @arg SDMMC_FLAG_TXACT: Data transmit in progress @@ -492,8 +495,8 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc); /** * @brief Clear the MMC's pending flags. - * @param __HANDLE__ MMC Handle - * @param __FLAG__ specifies the flag to clear. + * @param __HANDLE__: MMC Handle + * @param __FLAG__: specifies the flag to clear. * This parameter can be one or a combination of the following values: * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) @@ -503,7 +506,7 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc); * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed) * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required) - * @arg SDMMC_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) + * @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero) * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed) * @arg SDMMC_FLAG_SDIOIT: SD I/O interrupt received * @retval None @@ -512,8 +515,8 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc); /** * @brief Check whether the specified MMC interrupt has occurred or not. - * @param __HANDLE__ MMC Handle - * @param __INTERRUPT__ specifies the SDMMC interrupt source to check. + * @param __HANDLE__: MMC Handle + * @param __INTERRUPT__: specifies the SDMMC interrupt source to check. * This parameter can be one of the following values: * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt @@ -523,7 +526,7 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc); * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt - * @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt + * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt @@ -537,14 +540,14 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc); * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt - * @retval The new state of SD IT (SET or RESET). + * @retval The new state of MMC IT (SET or RESET). */ #define __HAL_MMC_GET_IT(__HANDLE__, __INTERRUPT__) __SDMMC_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__)) /** * @brief Clear the MMC's interrupt pending bits. - * @param __HANDLE__ MMC Handle - * @param __INTERRUPT__ specifies the interrupt pending bit to clear. + * @param __HANDLE__: MMC Handle + * @param __INTERRUPT__: specifies the interrupt pending bit to clear. * This parameter can be one or a combination of the following values: * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt @@ -554,7 +557,12 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc); * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt - * @arg SDMMC_IT_DATAEND: Data end (data counter, SDMMC_DCOUNT, is zero) interrupt + * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt + * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt + * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt * @retval None */ @@ -577,6 +585,7 @@ HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc); HAL_StatusTypeDef HAL_MMC_DeInit (MMC_HandleTypeDef *hmmc); void HAL_MMC_MspInit(MMC_HandleTypeDef *hmmc); void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc); + /** * @} */ @@ -624,9 +633,9 @@ HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32 * @{ */ HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc); -HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID); -HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD); -HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo); +HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID); +HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD); +HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo); /** * @} */ @@ -725,12 +734,12 @@ HAL_StatusTypeDef HAL_MMC_Abort_IT(MMC_HandleTypeDef *hmmc); * @} */ - #ifdef __cplusplus } #endif +#endif /* SDMMC1 */ -#endif /* __STM32F7xx_HAL_MMC_H */ +#endif /* STM32F7xx_HAL_MMC_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pcd.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pcd.h index 4afcf4112f..650dfd5137 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pcd.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pcd.h @@ -96,16 +96,16 @@ typedef struct __PCD_HandleTypeDef typedef struct #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ { - PCD_TypeDef *Instance; /*!< Register base address */ - PCD_InitTypeDef Init; /*!< PCD required parameters */ - __IO uint8_t USB_Address; /*!< USB Address */ - PCD_EPTypeDef IN_ep[16]; /*!< IN endpoint parameters */ - PCD_EPTypeDef OUT_ep[16]; /*!< OUT endpoint parameters */ - HAL_LockTypeDef Lock; /*!< PCD peripheral status */ - __IO PCD_StateTypeDef State; /*!< PCD communication state */ - __IO uint32_t ErrorCode; /*!< PCD Error code */ - uint32_t Setup[12]; /*!< Setup packet buffer */ - PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */ + PCD_TypeDef *Instance; /*!< Register base address */ + PCD_InitTypeDef Init; /*!< PCD required parameters */ + __IO uint8_t USB_Address; /*!< USB Address */ + PCD_EPTypeDef IN_ep[16]; /*!< IN endpoint parameters */ + PCD_EPTypeDef OUT_ep[16]; /*!< OUT endpoint parameters */ + HAL_LockTypeDef Lock; /*!< PCD peripheral status */ + __IO PCD_StateTypeDef State; /*!< PCD communication state */ + __IO uint32_t ErrorCode; /*!< PCD Error code */ + uint32_t Setup[12]; /*!< Setup packet buffer */ + PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */ uint32_t BESL; @@ -148,9 +148,9 @@ typedef struct /** @defgroup PCD_Speed PCD Speed * @{ */ -#define PCD_SPEED_HIGH 0U -#define PCD_SPEED_HIGH_IN_FULL 1U -#define PCD_SPEED_FULL 2U +#define PCD_SPEED_HIGH USBD_HS_SPEED +#define PCD_SPEED_HIGH_IN_FULL USBD_HSINFS_SPEED +#define PCD_SPEED_FULL USBD_FS_SPEED /** * @} */ @@ -207,20 +207,20 @@ typedef struct #define __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_OTG_HS_WAKEUP_EXTI_LINE) #define __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (USB_OTG_HS_WAKEUP_EXTI_LINE) -#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE() \ - do { \ +#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE() \ + do { \ EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE); \ - EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE; \ + EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE; \ } while(0U) #define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_OTG_FS_WAKEUP_EXTI_LINE #define __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE) #define __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_OTG_FS_WAKEUP_EXTI_LINE) #define __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = USB_OTG_FS_WAKEUP_EXTI_LINE -#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE() \ - do { \ +#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE() \ + do { \ EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE); \ - EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE; \ + EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE; \ } while(0U) #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ @@ -256,7 +256,7 @@ typedef enum HAL_PCD_SUSPEND_CB_ID = 0x04, /*!< USB PCD Suspend callback ID */ HAL_PCD_RESUME_CB_ID = 0x05, /*!< USB PCD Resume callback ID */ HAL_PCD_CONNECT_CB_ID = 0x06, /*!< USB PCD Connect callback ID */ - HAL_PCD_DISCONNECT_CB_ID = 0x07, /*!< USB PCD Disconnect callback ID */ + HAL_PCD_DISCONNECT_CB_ID = 0x07, /*!< USB PCD Disconnect callback ID */ HAL_PCD_MSPINIT_CB_ID = 0x08, /*!< USB PCD MspInit callback ID */ HAL_PCD_MSPDEINIT_CB_ID = 0x09 /*!< USB PCD MspDeInit callback ID */ @@ -371,14 +371,6 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @{ */ #if defined (USB_OTG_FS) || defined (USB_OTG_HS) -#define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE 0x08U -#define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE 0x0CU -#define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE 0x10U - -#define USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE 0x08U -#define USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE 0x0CU -#define USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE 0x10U - #define USB_OTG_FS_WAKEUP_EXTI_LINE (0x1U << 18) /*!< USB FS EXTI Line WakeUp Interrupt */ #define USB_OTG_HS_WAKEUP_EXTI_LINE (0x1U << 20) /*!< USB HS EXTI Line WakeUp Interrupt */ #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_qspi.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_qspi.h index 70a3220d7f..8d7f520bf0 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_qspi.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_qspi.h @@ -12,14 +12,14 @@ * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F7xx_HAL_QSPI_H -#define __STM32F7xx_HAL_QSPI_H +#ifndef STM32F7xx_HAL_QSPI_H +#define STM32F7xx_HAL_QSPI_H #ifdef __cplusplus extern "C" { @@ -28,6 +28,8 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32f7xx_hal_def.h" +#if defined(QUADSPI) + /** @addtogroup STM32F7xx_HAL_Driver * @{ */ @@ -44,35 +46,27 @@ /** * @brief QSPI Init structure definition */ - typedef struct { uint32_t ClockPrescaler; /* Specifies the prescaler factor for generating clock based on the AHB clock. This parameter can be a number between 0 and 255 */ - uint32_t FifoThreshold; /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode) This parameter can be a value between 1 and 32 */ - uint32_t SampleShifting; /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode) This parameter can be a value of @ref QSPI_SampleShifting */ - uint32_t FlashSize; /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits required to address the flash memory. The flash capacity can be up to 4GB (addressed using 32 bits) in indirect mode, but the addressable space in memory-mapped mode is limited to 256MB This parameter can be a number between 0 and 31 */ - uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number of clock cycles which the chip select must remain high between commands. This parameter can be a value of @ref QSPI_ChipSelectHighTime */ - uint32_t ClockMode; /* Specifies the Clock Mode. It indicates the level that clock takes between commands. This parameter can be a value of @ref QSPI_ClockMode */ - uint32_t FlashID; /* Specifies the Flash which will be used, This parameter can be a value of @ref QSPI_Flash_Select */ - uint32_t DualFlash; /* Specifies the Dual Flash Mode State This parameter can be a value of @ref QSPI_DualFlash_Mode */ }QSPI_InitTypeDef; @@ -157,15 +151,15 @@ typedef struct This parameter can be a value of @ref QSPI_AlternateBytesMode */ uint32_t DataMode; /* Specifies the Data Mode (used for dummy cycles and data phases) This parameter can be a value of @ref QSPI_DataMode */ - uint32_t NbData; /* Specifies the number of data to transfer. + uint32_t NbData; /* Specifies the number of data to transfer. (This is the number of bytes) This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length until end of memory)*/ uint32_t DdrMode; /* Specifies the double data rate mode for address, alternate byte and data phase This parameter can be a value of @ref QSPI_DdrMode */ - uint32_t DdrHoldHalfCycle; /* Specifies the DDR hold half cycle. It delays the data output by one half of - system clock in DDR mode. + uint32_t DdrHoldHalfCycle; /* Specifies if the DDR hold is enabled. When enabled it delays the data + output by one half of system clock in DDR mode. This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */ - uint32_t SIOOMode; /* Specifies the send instruction only once mode + uint32_t SIOOMode; /* Specifies the send instruction only once mode This parameter can be a value of @ref QSPI_SIOOMode */ }QSPI_CommandTypeDef; @@ -195,7 +189,7 @@ typedef struct { uint32_t TimeOutPeriod; /* Specifies the number of clock to wait when the FIFO is full before to release the chip select. This parameter can be any value between 0 and 0xFFFF */ - uint32_t TimeOutActivation; /* Specifies if the time out counter is enabled to release the chip select. + uint32_t TimeOutActivation; /* Specifies if the timeout counter is enabled to release the chip select. This parameter can be a value of @ref QSPI_TimeOutActivation */ }QSPI_MemoryMappedTypeDef; @@ -233,14 +227,15 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi); /** @defgroup QSPI_Exported_Constants QSPI Exported Constants * @{ */ + /** @defgroup QSPI_ErrorCode QSPI Error Code * @{ */ -#define HAL_QSPI_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ -#define HAL_QSPI_ERROR_TIMEOUT ((uint32_t)0x00000001U) /*!< Timeout error */ -#define HAL_QSPI_ERROR_TRANSFER ((uint32_t)0x00000002U) /*!< Transfer error */ -#define HAL_QSPI_ERROR_DMA ((uint32_t)0x00000004U) /*!< DMA transfer error */ -#define HAL_QSPI_ERROR_INVALID_PARAM ((uint32_t)0x00000008U) /*!< Invalid parameters error */ +#define HAL_QSPI_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_QSPI_ERROR_TIMEOUT 0x00000001U /*!< Timeout error */ +#define HAL_QSPI_ERROR_TRANSFER 0x00000002U /*!< Transfer error */ +#define HAL_QSPI_ERROR_DMA 0x00000004U /*!< DMA transfer error */ +#define HAL_QSPI_ERROR_INVALID_PARAM 0x00000008U /*!< Invalid parameters error */ #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) #define HAL_QSPI_ERROR_INVALID_CALLBACK 0x00000010U /*!< Invalid callback error */ #endif @@ -251,23 +246,23 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi); /** @defgroup QSPI_SampleShifting QSPI Sample Shifting * @{ */ -#define QSPI_SAMPLE_SHIFTING_NONE ((uint32_t)0x00000000U) /*!State = HAL_QSPI_STATE_RESET) #endif -/** @brief Enable QSPI - * @param __HANDLE__ specifies the QSPI Handle. +/** @brief Enable the QSPI peripheral. + * @param __HANDLE__ : specifies the QSPI Handle. * @retval None */ #define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) -/** @brief Disable QSPI - * @param __HANDLE__ specifies the QSPI Handle. +/** @brief Disable the QSPI peripheral. + * @param __HANDLE__ : specifies the QSPI Handle. * @retval None */ #define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) -/** @brief Enables the specified QSPI interrupt. - * @param __HANDLE__ specifies the QSPI Handle. - * @param __INTERRUPT__ specifies the QSPI interrupt source to enable. +/** @brief Enable the specified QSPI interrupt. + * @param __HANDLE__ : specifies the QSPI Handle. + * @param __INTERRUPT__ : specifies the QSPI interrupt source to enable. * This parameter can be one of the following values: - * @arg QSPI_IT_TO: QSPI Time out interrupt + * @arg QSPI_IT_TO: QSPI Timeout interrupt * @arg QSPI_IT_SM: QSPI Status match interrupt * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt * @arg QSPI_IT_TC: QSPI Transfer complete interrupt @@ -501,9 +496,9 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi); #define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) -/** @brief Disables the specified QSPI interrupt. - * @param __HANDLE__ specifies the QSPI Handle. - * @param __INTERRUPT__ specifies the QSPI interrupt source to disable. +/** @brief Disable the specified QSPI interrupt. + * @param __HANDLE__ : specifies the QSPI Handle. + * @param __INTERRUPT__ : specifies the QSPI interrupt source to disable. * This parameter can be one of the following values: * @arg QSPI_IT_TO: QSPI Timeout interrupt * @arg QSPI_IT_SM: QSPI Status match interrupt @@ -514,11 +509,11 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi); */ #define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) -/** @brief Checks whether the specified QSPI interrupt source is enabled. - * @param __HANDLE__ specifies the QSPI Handle. - * @param __INTERRUPT__ specifies the QSPI interrupt source to check. +/** @brief Check whether the specified QSPI interrupt source is enabled or not. + * @param __HANDLE__ : specifies the QSPI Handle. + * @param __INTERRUPT__ : specifies the QSPI interrupt source to check. * This parameter can be one of the following values: - * @arg QSPI_IT_TO: QSPI Time out interrupt + * @arg QSPI_IT_TO: QSPI Timeout interrupt * @arg QSPI_IT_SM: QSPI Status match interrupt * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt * @arg QSPI_IT_TC: QSPI Transfer complete interrupt @@ -528,25 +523,25 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi); #define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__)) /** - * @brief Get the selected QSPI's flag status. - * @param __HANDLE__ specifies the QSPI Handle. - * @param __FLAG__ specifies the QSPI flag to check. + * @brief Check whether the selected QSPI flag is set or not. + * @param __HANDLE__ : specifies the QSPI Handle. + * @param __FLAG__ : specifies the QSPI flag to check. * This parameter can be one of the following values: * @arg QSPI_FLAG_BUSY: QSPI Busy flag - * @arg QSPI_FLAG_TO: QSPI Time out flag + * @arg QSPI_FLAG_TO: QSPI Timeout flag * @arg QSPI_FLAG_SM: QSPI Status match flag * @arg QSPI_FLAG_FT: QSPI FIFO threshold flag * @arg QSPI_FLAG_TC: QSPI Transfer complete flag * @arg QSPI_FLAG_TE: QSPI Transfer error flag * @retval None */ -#define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) (READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0) +#define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? SET : RESET) /** @brief Clears the specified QSPI's flag status. - * @param __HANDLE__ specifies the QSPI Handle. - * @param __FLAG__ specifies the QSPI clear register flag that needs to be set + * @param __HANDLE__ : specifies the QSPI Handle. + * @param __FLAG__ : specifies the QSPI clear register flag that needs to be set * This parameter can be one of the following values: - * @arg QSPI_FLAG_TO: QSPI Time out flag + * @arg QSPI_FLAG_TO: QSPI Timeout flag * @arg QSPI_FLAG_SM: QSPI Status match flag * @arg QSPI_FLAG_TC: QSPI Transfer complete flag * @arg QSPI_FLAG_TE: QSPI Transfer error flag @@ -597,13 +592,7 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_Co /* QSPI memory-mapped mode */ HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg); -/** - * @} - */ -/** @addtogroup QSPI_Exported_Functions_Group3 - * @{ - */ /* Callback functions in non-blocking modes ***********************************/ void HAL_QSPI_ErrorCallback (QSPI_HandleTypeDef *hqspi); void HAL_QSPI_AbortCpltCallback (QSPI_HandleTypeDef *hqspi); @@ -631,7 +620,7 @@ HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, * @} */ -/** @addtogroup QSPI_Exported_Functions_Group4 +/** @addtogroup QSPI_Exported_Functions_Group3 * @{ */ /* Peripheral Control and State functions ************************************/ @@ -642,6 +631,7 @@ HAL_StatusTypeDef HAL_QSPI_Abort_IT (QSPI_HandleTypeDef *hqspi); void HAL_QSPI_SetTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Timeout); HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold); uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi); +HAL_StatusTypeDef HAL_QSPI_SetFlashID (QSPI_HandleTypeDef *hqspi, uint32_t FlashID); /** * @} */ @@ -649,161 +639,100 @@ uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi); /** * @} */ +/* End of exported functions -------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ /** @defgroup QSPI_Private_Macros QSPI Private Macros * @{ */ -/** @defgroup QSPI_ClockPrescaler QSPI Clock Prescaler - * @{ - */ -#define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFF) -/** - * @} - */ - -/** @defgroup QSPI_FifoThreshold QSPI Fifo Threshold - * @{ - */ -#define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0) && ((THR) <= 32)) -/** - * @} - */ - -#define IS_QSPI_SSHIFT(SSHIFT) (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \ - ((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE)) - -/** @defgroup QSPI_FlashSize QSPI Flash Size - * @{ - */ -#define IS_QSPI_FLASH_SIZE(FSIZE) (((FSIZE) <= 31)) -/** - * @} - */ +#define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFU) -#define IS_QSPI_CS_HIGH_TIME(CSHTIME) (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \ - ((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \ - ((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \ - ((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \ - ((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \ - ((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \ - ((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \ - ((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE)) +#define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0U) && ((THR) <= 32U)) -#define IS_QSPI_CLOCK_MODE(CLKMODE) (((CLKMODE) == QSPI_CLOCK_MODE_0) || \ - ((CLKMODE) == QSPI_CLOCK_MODE_3)) +#define IS_QSPI_SSHIFT(SSHIFT) (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \ + ((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE)) -#define IS_QSPI_FLASH_ID(FLA) (((FLA) == QSPI_FLASH_ID_1) || \ - ((FLA) == QSPI_FLASH_ID_2)) +#define IS_QSPI_FLASH_SIZE(FSIZE) (((FSIZE) <= 31U)) -#define IS_QSPI_DUAL_FLASH_MODE(MODE) (((MODE) == QSPI_DUALFLASH_ENABLE) || \ - ((MODE) == QSPI_DUALFLASH_DISABLE)) +#define IS_QSPI_CS_HIGH_TIME(CSHTIME) (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \ + ((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \ + ((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \ + ((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \ + ((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \ + ((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \ + ((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \ + ((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE)) +#define IS_QSPI_CLOCK_MODE(CLKMODE) (((CLKMODE) == QSPI_CLOCK_MODE_0) || \ + ((CLKMODE) == QSPI_CLOCK_MODE_3)) -/** @defgroup QSPI_Instruction QSPI Instruction - * @{ - */ -#define IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFF) -/** - * @} - */ +#define IS_QSPI_FLASH_ID(FLASH_ID) (((FLASH_ID) == QSPI_FLASH_ID_1) || \ + ((FLASH_ID) == QSPI_FLASH_ID_2)) -#define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE) (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS) || \ - ((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \ - ((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \ - ((ADDR_SIZE) == QSPI_ADDRESS_32_BITS)) +#define IS_QSPI_DUAL_FLASH_MODE(MODE) (((MODE) == QSPI_DUALFLASH_ENABLE) || \ + ((MODE) == QSPI_DUALFLASH_DISABLE)) -#define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS) || \ - ((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \ - ((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \ - ((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS)) +#define IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFFU) +#define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE) (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS) || \ + ((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \ + ((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \ + ((ADDR_SIZE) == QSPI_ADDRESS_32_BITS)) -/** @defgroup QSPI_DummyCycles QSPI Dummy Cycles - * @{ - */ -#define IS_QSPI_DUMMY_CYCLES(DCY) ((DCY) <= 31) -/** - * @} - */ +#define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS) || \ + ((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \ + ((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \ + ((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS)) -#define IS_QSPI_INSTRUCTION_MODE(MODE) (((MODE) == QSPI_INSTRUCTION_NONE) || \ - ((MODE) == QSPI_INSTRUCTION_1_LINE) || \ - ((MODE) == QSPI_INSTRUCTION_2_LINES) || \ - ((MODE) == QSPI_INSTRUCTION_4_LINES)) +#define IS_QSPI_DUMMY_CYCLES(DCY) ((DCY) <= 31U) -#define IS_QSPI_ADDRESS_MODE(MODE) (((MODE) == QSPI_ADDRESS_NONE) || \ - ((MODE) == QSPI_ADDRESS_1_LINE) || \ - ((MODE) == QSPI_ADDRESS_2_LINES) || \ - ((MODE) == QSPI_ADDRESS_4_LINES)) +#define IS_QSPI_INSTRUCTION_MODE(MODE) (((MODE) == QSPI_INSTRUCTION_NONE) || \ + ((MODE) == QSPI_INSTRUCTION_1_LINE) || \ + ((MODE) == QSPI_INSTRUCTION_2_LINES) || \ + ((MODE) == QSPI_INSTRUCTION_4_LINES)) -#define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE) || \ - ((MODE) == QSPI_ALTERNATE_BYTES_1_LINE) || \ - ((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \ - ((MODE) == QSPI_ALTERNATE_BYTES_4_LINES)) +#define IS_QSPI_ADDRESS_MODE(MODE) (((MODE) == QSPI_ADDRESS_NONE) || \ + ((MODE) == QSPI_ADDRESS_1_LINE) || \ + ((MODE) == QSPI_ADDRESS_2_LINES) || \ + ((MODE) == QSPI_ADDRESS_4_LINES)) -#define IS_QSPI_DATA_MODE(MODE) (((MODE) == QSPI_DATA_NONE) || \ - ((MODE) == QSPI_DATA_1_LINE) || \ - ((MODE) == QSPI_DATA_2_LINES) || \ - ((MODE) == QSPI_DATA_4_LINES)) +#define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE) || \ + ((MODE) == QSPI_ALTERNATE_BYTES_1_LINE) || \ + ((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \ + ((MODE) == QSPI_ALTERNATE_BYTES_4_LINES)) -#define IS_QSPI_DDR_MODE(DDR_MODE) (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \ - ((DDR_MODE) == QSPI_DDR_MODE_ENABLE)) +#define IS_QSPI_DATA_MODE(MODE) (((MODE) == QSPI_DATA_NONE) || \ + ((MODE) == QSPI_DATA_1_LINE) || \ + ((MODE) == QSPI_DATA_2_LINES) || \ + ((MODE) == QSPI_DATA_4_LINES)) -#define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \ - ((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY)) +#define IS_QSPI_DDR_MODE(DDR_MODE) (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \ + ((DDR_MODE) == QSPI_DDR_MODE_ENABLE)) -#define IS_QSPI_SIOO_MODE(SIOO_MODE) (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \ - ((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD)) +#define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \ + ((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY)) -/** @defgroup QSPI_Interval QSPI Interval - * @{ - */ -#define IS_QSPI_INTERVAL(INTERVAL) ((INTERVAL) <= QUADSPI_PIR_INTERVAL) -/** - * @} - */ +#define IS_QSPI_SIOO_MODE(SIOO_MODE) (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \ + ((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD)) -/** @defgroup QSPI_StatusBytesSize QSPI Status Bytes Size - * @{ - */ -#define IS_QSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1) && ((SIZE) <= 4)) -/** - * @} - */ -#define IS_QSPI_MATCH_MODE(MODE) (((MODE) == QSPI_MATCH_MODE_AND) || \ - ((MODE) == QSPI_MATCH_MODE_OR)) +#define IS_QSPI_INTERVAL(INTERVAL) ((INTERVAL) <= QUADSPI_PIR_INTERVAL) -#define IS_QSPI_AUTOMATIC_STOP(APMS) (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \ - ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE)) +#define IS_QSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 4U)) -#define IS_QSPI_TIMEOUT_ACTIVATION(TCEN) (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \ - ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE)) +#define IS_QSPI_MATCH_MODE(MODE) (((MODE) == QSPI_MATCH_MODE_AND) || \ + ((MODE) == QSPI_MATCH_MODE_OR)) -/** @defgroup QSPI_TimeOutPeriod QSPI TimeOut Period - * @{ - */ -#define IS_QSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFF) -/** - * @} - */ +#define IS_QSPI_AUTOMATIC_STOP(APMS) (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \ + ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE)) -#define IS_QSPI_GET_FLAG(FLAG) (((FLAG) == QSPI_FLAG_BUSY) || \ - ((FLAG) == QSPI_FLAG_TO) || \ - ((FLAG) == QSPI_FLAG_SM) || \ - ((FLAG) == QSPI_FLAG_FT) || \ - ((FLAG) == QSPI_FLAG_TC) || \ - ((FLAG) == QSPI_FLAG_TE)) +#define IS_QSPI_TIMEOUT_ACTIVATION(TCEN) (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \ + ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE)) -#define IS_QSPI_IT(IT) ((((IT) & (uint32_t)0xFFE0FFFFU) == 0x00000000U) && ((IT) != 0x00000000U)) +#define IS_QSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFFU) /** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ -/** @defgroup QSPI_Private_Functions QSPI Private Functions - * @{ - */ +* @} +*/ +/* End of private macros -----------------------------------------------------*/ /** * @} @@ -813,14 +742,12 @@ uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi); * @} */ -/** - * @} - */ +#endif /* defined(QUADSPI) || defined(QUADSPI1) || defined(QUADSPI2) */ #ifdef __cplusplus } #endif -#endif /* __STM32F7xx_HAL_QSPI_H */ +#endif /* STM32F7xx_HAL_QSPI_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sai.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sai.h index 5e384b9370..3a32096dc4 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sai.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sai.h @@ -97,9 +97,10 @@ typedef struct uint32_t AudioFrequency; /*!< Specifies the audio frequency sampling. This parameter can be a value of @ref SAI_Audio_Frequency */ - uint32_t Mckdiv; /*!< Specifies the master clock divider, the parameter will be used if for - AudioFrequency the user choice - This parameter must be a number between Min_Data = 0 and Max_Data = 15 */ + uint32_t Mckdiv; /*!< Specifies the master clock divider. + This parameter must be a number between Min_Data = 0 and Max_Data = 15. + @note This parameter is used only if AudioFrequency is set to + SAI_AUDIO_FREQUENCY_MCKDIV otherwise it is internally computed. */ uint32_t MonoStereoMode; /*!< Specifies if the mono or stereo mode is selected. This parameter can be a value of @ref SAI_Mono_Stereo_Mode */ @@ -841,7 +842,7 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai); #define IS_SAI_BLOCK_FS_DEFINITION(DEFINITION) (((DEFINITION) == SAI_FS_STARTFRAME) || \ ((DEFINITION) == SAI_FS_CHANNEL_IDENTIFICATION)) -#define IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 15) +#define IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 15U) #define IS_SAI_BLOCK_FRAME_LENGTH(LENGTH) ((8 <= (LENGTH)) && ((LENGTH) <= 256)) diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h index 3762b8da25..bf9ded73b4 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h @@ -12,19 +12,21 @@ * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F7xx_HAL_SD_H -#define __STM32F7xx_HAL_SD_H +#ifndef STM32F7xx_HAL_SD_H +#define STM32F7xx_HAL_SD_H #ifdef __cplusplus extern "C" { #endif +#if defined(SDMMC1) + /* Includes ------------------------------------------------------------------*/ #include "stm32f7xx_ll_sdmmc.h" @@ -47,14 +49,14 @@ */ typedef enum { - HAL_SD_STATE_RESET = ((uint32_t)0x00000000U), /*!< SD not yet initialized or disabled */ - HAL_SD_STATE_READY = ((uint32_t)0x00000001U), /*!< SD initialized and ready for use */ - HAL_SD_STATE_TIMEOUT = ((uint32_t)0x00000002U), /*!< SD Timeout state */ - HAL_SD_STATE_BUSY = ((uint32_t)0x00000003U), /*!< SD process ongoing */ - HAL_SD_STATE_PROGRAMMING = ((uint32_t)0x00000004U), /*!< SD Programming State */ - HAL_SD_STATE_RECEIVING = ((uint32_t)0x00000005U), /*!< SD Receinving State */ - HAL_SD_STATE_TRANSFER = ((uint32_t)0x00000006U), /*!< SD Transfert State */ - HAL_SD_STATE_ERROR = ((uint32_t)0x0000000FU) /*!< SD is in error state */ + HAL_SD_STATE_RESET = 0x00000000U, /*!< SD not yet initialized or disabled */ + HAL_SD_STATE_READY = 0x00000001U, /*!< SD initialized and ready for use */ + HAL_SD_STATE_TIMEOUT = 0x00000002U, /*!< SD Timeout state */ + HAL_SD_STATE_BUSY = 0x00000003U, /*!< SD process ongoing */ + HAL_SD_STATE_PROGRAMMING = 0x00000004U, /*!< SD Programming State */ + HAL_SD_STATE_RECEIVING = 0x00000005U, /*!< SD Receiving State */ + HAL_SD_STATE_TRANSFER = 0x00000006U, /*!< SD Transfert State */ + HAL_SD_STATE_ERROR = 0x0000000FU /*!< SD is in error state */ }HAL_SD_StateTypeDef; /** * @} @@ -63,18 +65,17 @@ typedef enum /** @defgroup SD_Exported_Types_Group2 SD Card State enumeration structure * @{ */ -typedef enum -{ - HAL_SD_CARD_READY = ((uint32_t)0x00000001U), /*!< Card state is ready */ - HAL_SD_CARD_IDENTIFICATION = ((uint32_t)0x00000002U), /*!< Card is in identification state */ - HAL_SD_CARD_STANDBY = ((uint32_t)0x00000003U), /*!< Card is in standby state */ - HAL_SD_CARD_TRANSFER = ((uint32_t)0x00000004U), /*!< Card is in transfer state */ - HAL_SD_CARD_SENDING = ((uint32_t)0x00000005U), /*!< Card is sending an operation */ - HAL_SD_CARD_RECEIVING = ((uint32_t)0x00000006U), /*!< Card is receiving operation information */ - HAL_SD_CARD_PROGRAMMING = ((uint32_t)0x00000007U), /*!< Card is in programming state */ - HAL_SD_CARD_DISCONNECTED = ((uint32_t)0x00000008U), /*!< Card is disconnected */ - HAL_SD_CARD_ERROR = ((uint32_t)0x000000FFU) /*!< Card response Error */ -}HAL_SD_CardStateTypeDef; +typedef uint32_t HAL_SD_CardStateTypeDef; + +#define HAL_SD_CARD_READY 0x00000001U /*!< Card state is ready */ +#define HAL_SD_CARD_IDENTIFICATION 0x00000002U /*!< Card is in identification state */ +#define HAL_SD_CARD_STANDBY 0x00000003U /*!< Card is in standby state */ +#define HAL_SD_CARD_TRANSFER 0x00000004U /*!< Card is in transfer state */ +#define HAL_SD_CARD_SENDING 0x00000005U /*!< Card is sending an operation */ +#define HAL_SD_CARD_RECEIVING 0x00000006U /*!< Card is receiving operation information */ +#define HAL_SD_CARD_PROGRAMMING 0x00000007U /*!< Card is in programming state */ +#define HAL_SD_CARD_DISCONNECTED 0x00000008U /*!< Card is disconnected */ +#define HAL_SD_CARD_ERROR 0x000000FFU /*!< Card response Error */ /** * @} */ @@ -111,7 +112,11 @@ typedef struct /** * @brief SD handle Structure definition */ +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) typedef struct __SD_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ { SD_TypeDef *Instance; /*!< SD registers base address */ @@ -119,11 +124,11 @@ typedef struct __SD_HandleTypeDef HAL_LockTypeDef Lock; /*!< SD locking object */ - uint32_t *pTxBuffPtr; /*!< Pointer to SD Tx transfer Buffer */ + uint8_t *pTxBuffPtr; /*!< Pointer to SD Tx transfer Buffer */ uint32_t TxXferSize; /*!< SD Tx Transfer size */ - uint32_t *pRxBuffPtr; /*!< Pointer to SD Rx transfer Buffer */ + uint8_t *pRxBuffPtr; /*!< Pointer to SD Rx transfer Buffer */ uint32_t RxXferSize; /*!< SD Rx Transfer size */ @@ -133,17 +138,17 @@ typedef struct __SD_HandleTypeDef __IO uint32_t ErrorCode; /*!< SD Card Error codes */ - DMA_HandleTypeDef *hdmarx; /*!< SD Rx DMA handle parameters */ - DMA_HandleTypeDef *hdmatx; /*!< SD Tx DMA handle parameters */ + DMA_HandleTypeDef *hdmarx; /*!< SD Rx DMA handle parameters */ + HAL_SD_CardInfoTypeDef SdCard; /*!< SD Card information */ uint32_t CSD[4]; /*!< SD card specific data table */ uint32_t CID[4]; /*!< SD card identification number table */ -#if (USE_HAL_SD_REGISTER_CALLBACKS == 1) +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) void (* TxCpltCallback) (struct __SD_HandleTypeDef *hsd); void (* RxCpltCallback) (struct __SD_HandleTypeDef *hsd); void (* ErrorCallback) (struct __SD_HandleTypeDef *hsd); @@ -151,7 +156,7 @@ typedef struct __SD_HandleTypeDef void (* MspInitCallback) (struct __SD_HandleTypeDef *hsd); void (* MspDeInitCallback) (struct __SD_HandleTypeDef *hsd); -#endif +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ }SD_HandleTypeDef; /** @@ -192,7 +197,7 @@ typedef struct __IO uint8_t WriteBlockPaPartial; /*!< Partial blocks for write allowed */ __IO uint8_t Reserved3; /*!< Reserved */ __IO uint8_t ContentProtectAppli; /*!< Content protection application */ - __IO uint8_t FileFormatGrouop; /*!< File format group */ + __IO uint8_t FileFormatGroup; /*!< File format group */ __IO uint8_t CopyFlag; /*!< Copy flag (OTP) */ __IO uint8_t PermWrProtect; /*!< Permanent write protection */ __IO uint8_t TempWrProtect; /*!< Temporary write protection */ @@ -200,7 +205,6 @@ typedef struct __IO uint8_t ECC; /*!< ECC code */ __IO uint8_t CSD_CRC; /*!< CSD CRC */ __IO uint8_t Reserved4; /*!< Always 1 */ - }HAL_SD_CardCSDTypeDef; /** * @} @@ -248,7 +252,7 @@ typedef struct * @} */ -#if (USE_HAL_SD_REGISTER_CALLBACKS == 1) +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) /** @defgroup SD_Exported_Types_Group7 SD Callback ID enumeration definition * @{ */ @@ -273,7 +277,7 @@ typedef void (*pSD_CallbackTypeDef) (SD_HandleTypeDef *hsd); /** * @} */ -#endif +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ /** * @} */ @@ -283,7 +287,7 @@ typedef void (*pSD_CallbackTypeDef) (SD_HandleTypeDef *hsd); * @{ */ -#define BLOCKSIZE ((uint32_t)512U) /*!< Block size is 512 bytes */ +#define BLOCKSIZE 512U /*!< Block size is 512 bytes */ /** @defgroup SD_Exported_Constansts_Group1 SD Error status enumeration Structure definition * @{ @@ -325,10 +329,9 @@ typedef void (*pSD_CallbackTypeDef) (SD_HandleTypeDef *hsd); #define HAL_SD_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */ #define HAL_SD_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */ -#if (USE_HAL_SD_REGISTER_CALLBACKS == 1) +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) #define HAL_SD_ERROR_INVALID_CALLBACK SDMMC_ERROR_INVALID_PARAMETER /*!< Invalid callback error */ -#endif - +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ /** * @} */ @@ -336,13 +339,13 @@ typedef void (*pSD_CallbackTypeDef) (SD_HandleTypeDef *hsd); /** @defgroup SD_Exported_Constansts_Group2 SD context enumeration * @{ */ -#define SD_CONTEXT_NONE ((uint32_t)0x00000000U) /*!< None */ -#define SD_CONTEXT_READ_SINGLE_BLOCK ((uint32_t)0x00000001U) /*!< Read single block operation */ -#define SD_CONTEXT_READ_MULTIPLE_BLOCK ((uint32_t)0x00000002U) /*!< Read multiple blocks operation */ -#define SD_CONTEXT_WRITE_SINGLE_BLOCK ((uint32_t)0x00000010U) /*!< Write single block operation */ -#define SD_CONTEXT_WRITE_MULTIPLE_BLOCK ((uint32_t)0x00000020U) /*!< Write multiple blocks operation */ -#define SD_CONTEXT_IT ((uint32_t)0x00000008U) /*!< Process in Interrupt mode */ -#define SD_CONTEXT_DMA ((uint32_t)0x00000080U) /*!< Process in DMA mode */ +#define SD_CONTEXT_NONE 0x00000000U /*!< None */ +#define SD_CONTEXT_READ_SINGLE_BLOCK 0x00000001U /*!< Read single block operation */ +#define SD_CONTEXT_READ_MULTIPLE_BLOCK 0x00000002U /*!< Read multiple blocks operation */ +#define SD_CONTEXT_WRITE_SINGLE_BLOCK 0x00000010U /*!< Write single block operation */ +#define SD_CONTEXT_WRITE_MULTIPLE_BLOCK 0x00000020U /*!< Write multiple blocks operation */ +#define SD_CONTEXT_IT 0x00000008U /*!< Process in Interrupt mode */ +#define SD_CONTEXT_DMA 0x00000080U /*!< Process in DMA mode */ /** * @} @@ -351,9 +354,9 @@ typedef void (*pSD_CallbackTypeDef) (SD_HandleTypeDef *hsd); /** @defgroup SD_Exported_Constansts_Group3 SD Supported Memory Cards * @{ */ -#define CARD_SDSC ((uint32_t)0x00000000U) -#define CARD_SDHC_SDXC ((uint32_t)0x00000001U) -#define CARD_SECURED ((uint32_t)0x00000003U) +#define CARD_SDSC 0x00000000U /*!< SD Standard Capacity <2Go */ +#define CARD_SDHC_SDXC 0x00000001U /*!< SD High Capacity <32Go, SD Extended Capacity <2To */ +#define CARD_SECURED 0x00000003U /** * @} @@ -362,8 +365,8 @@ typedef void (*pSD_CallbackTypeDef) (SD_HandleTypeDef *hsd); /** @defgroup SD_Exported_Constansts_Group4 SD Supported Version * @{ */ -#define CARD_V1_X ((uint32_t)0x00000000U) -#define CARD_V2_X ((uint32_t)0x00000001U) +#define CARD_V1_X 0x00000000U +#define CARD_V2_X 0x00000001U /** * @} */ @@ -381,7 +384,7 @@ typedef void (*pSD_CallbackTypeDef) (SD_HandleTypeDef *hsd); * @param __HANDLE__ : SD handle. * @retval None */ -#if (USE_HAL_SD_REGISTER_CALLBACKS == 1) +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) #define __HAL_SD_RESET_HANDLE_STATE(__HANDLE__) do { \ (__HANDLE__)->State = HAL_SD_STATE_RESET; \ (__HANDLE__)->MspInitCallback = NULL; \ @@ -389,7 +392,7 @@ typedef void (*pSD_CallbackTypeDef) (SD_HandleTypeDef *hsd); } while(0) #else #define __HAL_SD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SD_STATE_RESET) -#endif +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ /** * @brief Enable the SD device. @@ -417,8 +420,8 @@ typedef void (*pSD_CallbackTypeDef) (SD_HandleTypeDef *hsd); /** * @brief Enable the SD device interrupt. - * @param __HANDLE__ SD Handle - * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be enabled. + * @param __HANDLE__: SD Handle + * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled. * This parameter can be one or a combination of the following values: * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt @@ -428,7 +431,7 @@ typedef void (*pSD_CallbackTypeDef) (SD_HandleTypeDef *hsd); * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt - * @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt + * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt @@ -441,15 +444,15 @@ typedef void (*pSD_CallbackTypeDef) (SD_HandleTypeDef *hsd); * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt - * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt + * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt * @retval None */ #define __HAL_SD_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__)) /** * @brief Disable the SD device interrupt. - * @param __HANDLE__ SD Handle - * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be disabled. + * @param __HANDLE__: SD Handle + * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled. * This parameter can be one or a combination of the following values: * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt @@ -459,7 +462,7 @@ typedef void (*pSD_CallbackTypeDef) (SD_HandleTypeDef *hsd); * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt - * @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt + * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt @@ -472,15 +475,15 @@ typedef void (*pSD_CallbackTypeDef) (SD_HandleTypeDef *hsd); * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt - * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt + * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt * @retval None */ #define __HAL_SD_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__)) /** * @brief Check whether the specified SD flag is set or not. - * @param __HANDLE__ SD Handle - * @param __FLAG__ specifies the flag to check. + * @param __HANDLE__: SD Handle + * @param __FLAG__: specifies the flag to check. * This parameter can be one of the following values: * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) @@ -490,7 +493,7 @@ typedef void (*pSD_CallbackTypeDef) (SD_HandleTypeDef *hsd); * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed) * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required) - * @arg SDMMC_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) + * @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero) * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed) * @arg SDMMC_FLAG_CMDACT: Command transfer in progress * @arg SDMMC_FLAG_TXACT: Data transmit in progress @@ -503,15 +506,15 @@ typedef void (*pSD_CallbackTypeDef) (SD_HandleTypeDef *hsd); * @arg SDMMC_FLAG_RXFIFOE: Receive FIFO empty * @arg SDMMC_FLAG_TXDAVL: Data available in transmit FIFO * @arg SDMMC_FLAG_RXDAVL: Data available in receive FIFO - * @arg SDMMC_FLAG_SDIOIT: SD I/O interrupt received + * @arg SDMMC_FLAG_SDIOIT: SDIO interrupt received * @retval The new state of SD FLAG (SET or RESET). */ #define __HAL_SD_GET_FLAG(__HANDLE__, __FLAG__) __SDMMC_GET_FLAG((__HANDLE__)->Instance, (__FLAG__)) /** * @brief Clear the SD's pending flags. - * @param __HANDLE__ SD Handle - * @param __FLAG__ specifies the flag to clear. + * @param __HANDLE__: SD Handle + * @param __FLAG__: specifies the flag to clear. * This parameter can be one or a combination of the following values: * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) @@ -521,17 +524,17 @@ typedef void (*pSD_CallbackTypeDef) (SD_HandleTypeDef *hsd); * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed) * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required) - * @arg SDMMC_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) + * @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero) * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed) - * @arg SDMMC_FLAG_SDIOIT: SD I/O interrupt received + * @arg SDMMC_FLAG_SDIOIT: SDIO interrupt received * @retval None */ #define __HAL_SD_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDMMC_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__)) /** * @brief Check whether the specified SD interrupt has occurred or not. - * @param __HANDLE__ SD Handle - * @param __INTERRUPT__ specifies the SDMMC interrupt source to check. + * @param __HANDLE__: SD Handle + * @param __INTERRUPT__: specifies the SDMMC interrupt source to check. * This parameter can be one of the following values: * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt @@ -541,7 +544,7 @@ typedef void (*pSD_CallbackTypeDef) (SD_HandleTypeDef *hsd); * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt - * @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt + * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt @@ -554,15 +557,15 @@ typedef void (*pSD_CallbackTypeDef) (SD_HandleTypeDef *hsd); * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt - * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt + * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt * @retval The new state of SD IT (SET or RESET). */ #define __HAL_SD_GET_IT(__HANDLE__, __INTERRUPT__) __SDMMC_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__)) /** * @brief Clear the SD's interrupt pending bits. - * @param __HANDLE__ SD Handle - * @param __INTERRUPT__ specifies the interrupt pending bit to clear. + * @param __HANDLE__: SD Handle + * @param __INTERRUPT__: specifies the interrupt pending bit to clear. * This parameter can be one or a combination of the following values: * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt @@ -572,8 +575,8 @@ typedef void (*pSD_CallbackTypeDef) (SD_HandleTypeDef *hsd); * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt - * @arg SDMMC_IT_DATAEND: Data end (data counter, SDMMC_DCOUNT, is zero) interrupt - * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt + * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt + * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt * @retval None */ #define __HAL_SD_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDMMC_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__)) @@ -621,11 +624,12 @@ void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd); void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd); void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd); -#if (USE_HAL_SD_REGISTER_CALLBACKS == 1) +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) /* SD callback registering/unregistering */ HAL_StatusTypeDef HAL_SD_RegisterCallback (SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackId, pSD_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_SD_UnRegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackId); -#endif +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ + /** * @} */ @@ -745,12 +749,13 @@ HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd); * @} */ +#endif /* SDMMC1 */ #ifdef __cplusplus } #endif -#endif /* __STM32F7xx_HAL_SD_H */ +#endif /* STM32F7xx_HAL_SD_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_smartcard.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_smartcard.h index 6d0ae01714..c14c584b89 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_smartcard.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_smartcard.h @@ -524,15 +524,15 @@ typedef enum */ #if USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1 #define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET; \ - (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ + (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET; \ + (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ } while(0U) #else #define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET; \ - (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET; \ + (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET; \ + (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET; \ } while(0U) #endif /*USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ @@ -540,11 +540,11 @@ typedef enum * @param __HANDLE__ specifies the SMARTCARD Handle. * @retval None */ -#define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__) \ - do{ \ - SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST); \ - SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_TXDATA_FLUSH_REQUEST); \ - } while(0U) +#define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__) \ + do{ \ + SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST); \ + SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_TXDATA_FLUSH_REQUEST); \ + } while(0U) /** @brief Clear the specified SMARTCARD pending flag. * @param __HANDLE__ specifies the SMARTCARD Handle. @@ -667,7 +667,8 @@ typedef enum * @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error) * @retval The new state of __INTERRUPT__ (SET or RESET). */ -#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR & ((uint32_t)0x01U << (((__INTERRUPT__) & SMARTCARD_ISR_MASK)>> SMARTCARD_ISR_POS))) != 0U) ? SET : RESET) +#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\ + & ((uint32_t)0x01U << (((__INTERRUPT__) & SMARTCARD_ISR_MASK)>> SMARTCARD_ISR_POS))) != 0U) ? SET : RESET) /** @brief Check whether the specified SmartCard interrupt source is enabled or not. * @param __HANDLE__ specifies the SMARTCARD Handle. @@ -685,8 +686,8 @@ typedef enum * @retval The new state of __INTERRUPT__ (SET or RESET). */ #define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 : \ - (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 0x02U)? (__HANDLE__)->Instance->CR2 : \ - (__HANDLE__)->Instance->CR3)) & ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__)) & SMARTCARD_IT_MASK))) != 0U) ? SET : RESET) + (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 0x02U)? (__HANDLE__)->Instance->CR2 : \ + (__HANDLE__)->Instance->CR3)) & ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__)) & SMARTCARD_IT_MASK))) != 0U) ? SET : RESET) /** @brief Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag. * @param __HANDLE__ specifies the SMARTCARD Handle. @@ -726,7 +727,8 @@ typedef enum * @param __HANDLE__ specifies the SMARTCARD Handle. * @retval None */ -#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT)) +#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3\ + &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT)) /** @brief Enable the USART associated to the SMARTCARD Handle. * @param __HANDLE__ specifies the SMARTCARD Handle. @@ -758,8 +760,8 @@ typedef enum do { \ if((__HANDLE__)->Instance == USART1) \ { \ - switch(__HAL_RCC_GET_USART1_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ case RCC_USART1CLKSOURCE_PCLK2: \ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK2; \ break; \ @@ -775,12 +777,12 @@ typedef enum default: \ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ else if((__HANDLE__)->Instance == USART2) \ { \ - switch(__HAL_RCC_GET_USART2_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_USART2_SOURCE()) \ + { \ case RCC_USART2CLKSOURCE_PCLK1: \ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \ break; \ @@ -796,12 +798,12 @@ typedef enum default: \ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ else if((__HANDLE__)->Instance == USART3) \ { \ - switch(__HAL_RCC_GET_USART3_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_USART3_SOURCE()) \ + { \ case RCC_USART3CLKSOURCE_PCLK1: \ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \ break; \ @@ -817,12 +819,12 @@ typedef enum default: \ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ else if((__HANDLE__)->Instance == USART6) \ { \ - switch(__HAL_RCC_GET_USART6_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_USART6_SOURCE()) \ + { \ case RCC_USART6CLKSOURCE_PCLK2: \ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK2; \ break; \ @@ -838,7 +840,7 @@ typedef enum default: \ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ else \ { \ @@ -905,7 +907,8 @@ typedef enum * @param __CPOL__ SMARTCARD frame polarity. * @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid) */ -#define IS_SMARTCARD_POLARITY(__CPOL__) (((__CPOL__) == SMARTCARD_POLARITY_LOW) || ((__CPOL__) == SMARTCARD_POLARITY_HIGH)) +#define IS_SMARTCARD_POLARITY(__CPOL__) (((__CPOL__) == SMARTCARD_POLARITY_LOW)\ + || ((__CPOL__) == SMARTCARD_POLARITY_HIGH)) /** @brief Ensure that SMARTCARD frame phase is valid. * @param __CPHA__ SMARTCARD frame phase. @@ -1034,8 +1037,10 @@ void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard); #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) /* Callbacks Register/UnRegister functions ***********************************/ -HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, HAL_SMARTCARD_CallbackIDTypeDef CallbackID); +HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, + HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, + HAL_SMARTCARD_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ /** @@ -1047,8 +1052,10 @@ HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsma * @{ */ -HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, + uint32_t Timeout); +HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, + uint32_t Timeout); HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size); diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_smartcard_ex.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_smartcard_ex.h index 061b0f4e82..ddae1b6eb1 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_smartcard_ex.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_smartcard_ex.h @@ -166,7 +166,7 @@ extern "C" { do { \ if (HAL_IS_BIT_CLR((__HANDLE__)->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXCOMPLETION)) \ { \ - (__HANDLE__)->AdvancedInit.TxCompletionIndication = SMARTCARD_TC; \ + (__HANDLE__)->AdvancedInit.TxCompletionIndication = SMARTCARD_TC; \ } \ else \ { \ @@ -243,15 +243,6 @@ HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef * @} */ -/** @addtogroup SMARTCARDEx_Exported_Functions_Group3 - * @{ - */ - -/* Peripheral Control functions ***********************************************/ - -/** - * @} - */ /** * @} diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h index d5cde2b1c4..9a14e0fae3 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h @@ -167,7 +167,7 @@ typedef struct This parameter can be a value of @ref TIM_Encoder_Mode */ uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ uint32_t IC1Selection; /*!< Specifies the input. This parameter can be a value of @ref TIM_Input_Capture_Selection */ @@ -179,7 +179,7 @@ typedef struct This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ uint32_t IC2Selection; /*!< Specifies the input. This parameter can be a value of @ref TIM_Input_Capture_Selection */ @@ -235,7 +235,12 @@ typedef struct uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */ uint32_t MasterSlaveMode; /*!< Master/slave mode selection - This parameter can be a value of @ref TIM_Master_Slave_Mode */ + This parameter can be a value of @ref TIM_Master_Slave_Mode + @note When the Master/slave mode is enabled, the effect of + an event on the trigger input (TRGI) is delayed to allow a + perfect synchronization between the current timer and its + slaves (through TRGO). It is not mandatory in case of timer + synchronization mode. */ } TIM_MasterConfigTypeDef; /** @@ -518,6 +523,15 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to * @} */ +/** @defgroup TIM_Update_Interrupt_Flag_Remap TIM Update Interrupt Flag Remap + * @{ + */ +#define TIM_UIFREMAP_DISABLE 0x00000000U /*!< Update interrupt flag remap disabled */ +#define TIM_UIFREMAP_ENABLE TIM_CR1_UIFREMAP /*!< Update interrupt flag remap enabled */ +/** + * @} + */ + /** @defgroup TIM_ClockDivision TIM Clock Division * @{ */ @@ -611,6 +625,15 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to * @} */ +/** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity + * @{ + */ +#define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Encoder input with rising edge polarity */ +#define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Encoder input with falling edge polarity */ +/** + * @} + */ + /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection * @{ */ @@ -1119,15 +1142,15 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to * @retval None */ #define __HAL_TIM_DISABLE(__HANDLE__) \ - do { \ - if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ - { \ - if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ - { \ - (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ - } \ - } \ - } while(0) + do { \ + if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ + { \ + if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ + { \ + (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ + } \ + } \ + } while(0) /** * @brief Disable the TIM main Output. @@ -1136,15 +1159,15 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled */ #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ - do { \ - if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ - { \ - if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ - { \ - (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \ - } \ - } \ - } while(0) + do { \ + if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ + { \ + if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ + { \ + (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \ + } \ + } \ + } while(0) /** * @brief Disable the TIM main Output. @@ -1279,7 +1302,8 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to * @arg TIM_IT_BREAK: Break interrupt * @retval The state of TIM_IT (SET or RESET). */ -#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) +#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \ + == (__INTERRUPT__)) ? SET : RESET) /** @brief Clear the TIM interrupt pending bits. * @param __HANDLE__ TIM handle @@ -1297,6 +1321,31 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to */ #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) +/** + * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31). + * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read in an atomic way. + * @param __HANDLE__ TIM handle. + * @retval None +mode. + */ +#define __HAL_TIM_UIFREMAP_ENABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 |= TIM_CR1_UIFREMAP)) + +/** + * @brief Disable update interrupt flag (UIF) remapping. + * @param __HANDLE__ TIM handle. + * @retval None +mode. + */ +#define __HAL_TIM_UIFREMAP_DISABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 &= ~TIM_CR1_UIFREMAP)) + +/** + * @brief Get update interrupt flag (UIF) copy status. + * @param __COUNTER__ Counter value. + * @retval The state of UIFCPY (TRUE or FALSE). +mode. + */ +#define __HAL_TIM_GET_UIFCPY(__COUNTER__) (((__COUNTER__) & (TIM_CNT_UIFCPY)) == (TIM_CNT_UIFCPY)) + /** * @brief Indicates whether or not the TIM Counter is used as downcounter. * @param __HANDLE__ TIM handle. @@ -1316,6 +1365,8 @@ mode. /** * @brief Set the TIM Counter Register value on runtime. + * Note Please check if the bit 31 of CNT register is used as UIF copy or not, this may affect the counter range in case of 32 bits counter TIM instance. + * Bit 31 of CNT can be enabled/disabled using __HAL_TIM_UIFREMAP_ENABLE()/__HAL_TIM_UIFREMAP_DISABLE() macros. * @param __HANDLE__ TIM handle. * @param __COUNTER__ specifies the Counter register new value. * @retval None @@ -1327,8 +1378,7 @@ mode. * @param __HANDLE__ TIM handle. * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT) */ -#define __HAL_TIM_GET_COUNTER(__HANDLE__) \ - ((__HANDLE__)->Instance->CNT) +#define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT) /** * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function. @@ -1337,18 +1387,17 @@ mode. * @retval None */ #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ - do{ \ - (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ - (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ - } while(0) + do{ \ + (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ + (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ + } while(0) /** * @brief Get the TIM Autoreload Register value on runtime. * @param __HANDLE__ TIM handle. * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR) */ -#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \ - ((__HANDLE__)->Instance->ARR) +#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR) /** * @brief Set the TIM Clock Division value on runtime without calling another time any Init function. @@ -1361,11 +1410,11 @@ mode. * @retval None */ #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ - do{ \ - (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \ - (__HANDLE__)->Instance->CR1 |= (__CKD__); \ - (__HANDLE__)->Init.ClockDivision = (__CKD__); \ - } while(0) + do{ \ + (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \ + (__HANDLE__)->Instance->CR1 |= (__CKD__); \ + (__HANDLE__)->Init.ClockDivision = (__CKD__); \ + } while(0) /** * @brief Get the TIM Clock Division value on runtime. @@ -1375,8 +1424,7 @@ mode. * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT */ -#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) \ - ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) +#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) /** * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function. @@ -1396,10 +1444,10 @@ mode. * @retval None */ #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \ - do{ \ - TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ - TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ - } while(0) + do{ \ + TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ + TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ + } while(0) /** * @brief Get the TIM Input Capture prescaler on runtime. @@ -1437,12 +1485,12 @@ mode. * @retval None */ #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ -(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\ - ((__HANDLE__)->Instance->CCR6 = (__COMPARE__))) + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\ + ((__HANDLE__)->Instance->CCR6 = (__COMPARE__))) /** * @brief Get the TIM Capture Compare Register value on runtime. @@ -1458,12 +1506,12 @@ mode. * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy) */ #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ -(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\ - ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\ - ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\ - ((__HANDLE__)->Instance->CCR6)) + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\ + ((__HANDLE__)->Instance->CCR6)) /** * @brief Set the TIM Output compare preload. @@ -1479,12 +1527,12 @@ mode. * @retval None */ #define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\ - ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE)) + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\ + ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE)) /** * @brief Reset the TIM Output compare preload. @@ -1500,12 +1548,62 @@ mode. * @retval None */ #define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC5PE) :\ - ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC6PE)) + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5PE) :\ + ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6PE)) + +/** + * @brief Enable fast mode for a given channel. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @note When fast mode is enabled an active edge on the trigger input acts + * like a compare match on CCx output. Delay to sample the trigger + * input and to activate CCx output is reduced to 3 clock cycles. + * @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode. + * @retval None + */ +#define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5FE) :\ + ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6FE)) + +/** + * @brief Disable fast mode for a given channel. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @note When fast mode is disabled CCx output behaves normally depending + * on counter and CCRx values even when the trigger is ON. The minimum + * delay to activate CCx output when an active edge occurs on the + * trigger input is 5 clock cycles. + * @retval None + */ +#define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE) :\ + ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE)) /** * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register. @@ -1515,8 +1613,7 @@ mode. * enabled) * @retval None */ -#define __HAL_TIM_URS_ENABLE(__HANDLE__) \ - ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS) +#define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS) /** * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register. @@ -1529,8 +1626,7 @@ mode. * _ Update generation through the slave mode controller * @retval None */ -#define __HAL_TIM_URS_DISABLE(__HANDLE__) \ - ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS) +#define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS) /** * @brief Set the TIM Capture x input polarity on runtime. @@ -1548,10 +1644,10 @@ mode. * @retval None */ #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ - do{ \ - TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ - TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ - }while(0) + do{ \ + TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ + TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ + }while(0) /** * @} @@ -1579,29 +1675,29 @@ mode. ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR)) #if defined(TIM_AF1_BKINE)&&defined(TIM_AF2_BKINE) -#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \ - ((__BASE__) == TIM_DMABASE_CR2) || \ - ((__BASE__) == TIM_DMABASE_SMCR) || \ - ((__BASE__) == TIM_DMABASE_DIER) || \ - ((__BASE__) == TIM_DMABASE_SR) || \ - ((__BASE__) == TIM_DMABASE_EGR) || \ - ((__BASE__) == TIM_DMABASE_CCMR1) || \ - ((__BASE__) == TIM_DMABASE_CCMR2) || \ - ((__BASE__) == TIM_DMABASE_CCER) || \ - ((__BASE__) == TIM_DMABASE_CNT) || \ - ((__BASE__) == TIM_DMABASE_PSC) || \ - ((__BASE__) == TIM_DMABASE_ARR) || \ - ((__BASE__) == TIM_DMABASE_RCR) || \ - ((__BASE__) == TIM_DMABASE_CCR1) || \ - ((__BASE__) == TIM_DMABASE_CCR2) || \ - ((__BASE__) == TIM_DMABASE_CCR3) || \ - ((__BASE__) == TIM_DMABASE_CCR4) || \ - ((__BASE__) == TIM_DMABASE_BDTR) || \ - ((__BASE__) == TIM_DMABASE_OR) || \ - ((__BASE__) == TIM_DMABASE_CCMR3) || \ - ((__BASE__) == TIM_DMABASE_CCR5) || \ - ((__BASE__) == TIM_DMABASE_CCR6) || \ - ((__BASE__) == TIM_DMABASE_AF1) || \ +#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \ + ((__BASE__) == TIM_DMABASE_CR2) || \ + ((__BASE__) == TIM_DMABASE_SMCR) || \ + ((__BASE__) == TIM_DMABASE_DIER) || \ + ((__BASE__) == TIM_DMABASE_SR) || \ + ((__BASE__) == TIM_DMABASE_EGR) || \ + ((__BASE__) == TIM_DMABASE_CCMR1) || \ + ((__BASE__) == TIM_DMABASE_CCMR2) || \ + ((__BASE__) == TIM_DMABASE_CCER) || \ + ((__BASE__) == TIM_DMABASE_CNT) || \ + ((__BASE__) == TIM_DMABASE_PSC) || \ + ((__BASE__) == TIM_DMABASE_ARR) || \ + ((__BASE__) == TIM_DMABASE_RCR) || \ + ((__BASE__) == TIM_DMABASE_CCR1) || \ + ((__BASE__) == TIM_DMABASE_CCR2) || \ + ((__BASE__) == TIM_DMABASE_CCR3) || \ + ((__BASE__) == TIM_DMABASE_CCR4) || \ + ((__BASE__) == TIM_DMABASE_BDTR) || \ + ((__BASE__) == TIM_DMABASE_OR) || \ + ((__BASE__) == TIM_DMABASE_CCMR3) || \ + ((__BASE__) == TIM_DMABASE_CCR5) || \ + ((__BASE__) == TIM_DMABASE_CCR6) || \ + ((__BASE__) == TIM_DMABASE_AF1) || \ ((__BASE__) == TIM_DMABASE_AF2)) #else #define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \ @@ -1636,6 +1732,9 @@ mode. ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \ ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3)) +#define IS_TIM_UIFREMAP_MODE(__MODE__) (((__MODE__) == TIM_UIFREMAP_DISABLE) || \ + ((__MODE__) == TIM_UIFREMAP_ENALE)) + #define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \ ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \ ((__DIV__) == TIM_CLOCKDIVISION_DIV4)) @@ -1658,6 +1757,9 @@ mode. #define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \ ((__STATE__) == TIM_OCNIDLESTATE_RESET)) +#define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || \ + ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING)) + #define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \ ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \ ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE)) @@ -1876,28 +1978,28 @@ mode. ((__TRIGGER__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER)) #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ -(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ - ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U))) + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ + ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U))) #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ -(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\ - ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC)) + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\ + ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC)) #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ -(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\ - ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U)))) + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\ + ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U)))) #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ -(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ - ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP))) + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ + ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP))) /** * @} @@ -2035,7 +2137,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, + uint32_t *pData2, uint16_t Length); HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); /** * @} @@ -2059,17 +2162,19 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel); -HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, + uint32_t OutputChannel, uint32_t InputChannel); +HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, + uint32_t Channel); HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig); HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); -HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ - uint32_t *BurstBuffer, uint32_t BurstLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); -HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ - uint32_t *BurstBuffer, uint32_t BurstLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); @@ -2095,7 +2200,8 @@ void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, pTIM_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, + pTIM_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ @@ -2125,8 +2231,8 @@ HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); /* Private functions----------------------------------------------------------*/ /** @defgroup TIM_Private_Functions TIM Private Functions -* @{ -*/ + * @{ + */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure); void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); @@ -2145,8 +2251,8 @@ void TIM_ResetCallback(TIM_HandleTypeDef *htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /** -* @} -*/ + * @} + */ /* End of private functions --------------------------------------------------*/ /** diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h index f0434c255e..2897aca4d7 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h @@ -201,9 +201,9 @@ TIMEx_BreakInputConfigTypeDef; */ /** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions - * @brief Timer Hall Sensor functions - * @{ - */ + * @brief Timer Hall Sensor functions + * @{ + */ /* Timer Hall Sensor functions **********************************************/ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig); HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim); @@ -225,9 +225,9 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim); */ /** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions - * @brief Timer Complementary Output Compare functions - * @{ - */ + * @brief Timer Complementary Output Compare functions + * @{ + */ /* Timer Complementary Output Compare functions *****************************/ /* Blocking mode: Polling */ HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); @@ -245,9 +245,9 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann */ /** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions - * @brief Timer Complementary PWM functions - * @{ - */ + * @brief Timer Complementary PWM functions + * @{ + */ /* Timer Complementary PWM functions ****************************************/ /* Blocking mode: Polling */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); @@ -264,9 +264,9 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan */ /** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions - * @brief Timer Complementary One Pulse functions - * @{ - */ + * @brief Timer Complementary One Pulse functions + * @{ + */ /* Timer Complementary One Pulse functions **********************************/ /* Blocking mode: Polling */ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); @@ -280,17 +280,23 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t */ /** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions - * @brief Peripheral Control functions - * @{ - */ + * @brief Peripheral Control functions + * @{ + */ /* Extended Control functions ************************************************/ -HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); -HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); -HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); -HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef *sMasterConfig); -HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig); +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource); +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource); +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource); +HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, + TIM_MasterConfigTypeDef *sMasterConfig); +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, + TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig); #if defined(TIM_BREAK_INPUT_SUPPORT) -HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput, TIMEx_BreakInputConfigTypeDef *sBreakInputConfig); +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput, + TIMEx_BreakInputConfigTypeDef *sBreakInputConfig); #endif /* TIM_BREAK_INPUT_SUPPORT */ HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels); HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap); @@ -327,7 +333,7 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim); /* End of exported functions -------------------------------------------------*/ /* Private functions----------------------------------------------------------*/ -/** @defgroup TIMEx_Private_Functions TIM Extended Private Functions +/** @addtogroup TIMEx_Private_Functions TIMEx Private Functions * @{ */ void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma); diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h index 689092d36c..eb186d6f5e 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h @@ -125,8 +125,6 @@ typedef struct This parameter can be a value of @ref UART_MSB_First. */ } UART_AdvFeatureInitTypeDef; - - /** * @brief HAL UART State definition * @note HAL UART State value is a combination of 2 different substates: gState and RxState (see @ref UART_State_Definition). @@ -206,10 +204,9 @@ typedef struct __UART_HandleTypeDef uint16_t Mask; /*!< UART Rx RDR register mask */ + void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */ - void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */ - - void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */ + void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */ DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */ @@ -313,8 +310,10 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer #define HAL_UART_ERROR_FE ((uint32_t)0x00000004U) /*!< Frame error */ #define HAL_UART_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */ #define HAL_UART_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */ +#define HAL_UART_ERROR_RTO ((uint32_t)0x00000020U) /*!< Receiver Timeout error */ + #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) -#define HAL_UART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U) /*!< Invalid Callback error */ +#define HAL_UART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */ #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ /** * @} @@ -400,11 +399,11 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @} */ -/** @defgroup UART_Receiver_TimeOut UART Receiver TimeOut +/** @defgroup UART_Receiver_Timeout UART Receiver Timeout * @{ */ -#define UART_RECEIVER_TIMEOUT_DISABLE 0x00000000U /*!< UART receiver timeout disable */ -#define UART_RECEIVER_TIMEOUT_ENABLE USART_CR2_RTOEN /*!< UART receiver timeout enable */ +#define UART_RECEIVER_TIMEOUT_DISABLE 0x00000000U /*!< UART Receiver Timeout disable */ +#define UART_RECEIVER_TIMEOUT_ENABLE USART_CR2_RTOEN /*!< UART Receiver Timeout enable */ /** * @} */ @@ -562,6 +561,17 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer /** * @} */ +#if defined(USART_CR1_UESM) + +/** @defgroup UART_Stop_Mode_Enable UART Advanced Feature Stop Mode Enable + * @{ + */ +#define UART_ADVFEATURE_STOPMODE_DISABLE 0x00000000U /*!< UART stop mode disable */ +#define UART_ADVFEATURE_STOPMODE_ENABLE USART_CR1_UESM /*!< UART stop mode enable */ +/** + * @} + */ +#endif /* USART_CR1_UESM */ /** @defgroup UART_Mute_Mode UART Advanced Feature Mute Mode Enable * @{ @@ -579,6 +589,18 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer /** * @} */ +#if defined(USART_CR1_UESM) + +/** @defgroup UART_WakeUp_from_Stop_Selection UART WakeUp From Stop Selection + * @{ + */ +#define UART_WAKEUP_ON_ADDRESS 0x00000000U /*!< UART wake-up on address */ +#define UART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< UART wake-up on start bit */ +#define UART_WAKEUP_ON_READDATA_NONEMPTY USART_CR3_WUS /*!< UART wake-up on receive data register not empty or RXFIFO is not empty */ +/** + * @} + */ +#endif /* USART_CR1_UESM */ /** @defgroup UART_DriverEnable_Polarity UART DriverEnable Polarity * @{ @@ -626,13 +648,20 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * - 0xXXXX : Flag mask in the ISR register * @{ */ +#if defined(USART_ISR_REACK) +#define UART_FLAG_REACK USART_ISR_REACK /*!< UART receive enable acknowledge flag */ +#endif /* USART_ISR_REACK */ #define UART_FLAG_TEACK USART_ISR_TEACK /*!< UART transmit enable acknowledge flag */ +#if defined(USART_CR1_UESM) +#define UART_FLAG_WUF USART_ISR_WUF /*!< UART wake-up from stop mode flag */ +#endif /* USART_CR1_UESM */ #define UART_FLAG_RWU USART_ISR_RWU /*!< UART receiver wake-up from mute mode flag */ #define UART_FLAG_SBKF USART_ISR_SBKF /*!< UART send break flag */ #define UART_FLAG_CMF USART_ISR_CMF /*!< UART character match flag */ #define UART_FLAG_BUSY USART_ISR_BUSY /*!< UART busy flag */ #define UART_FLAG_ABRF USART_ISR_ABRF /*!< UART auto Baud rate flag */ #define UART_FLAG_ABRE USART_ISR_ABRE /*!< UART auto Baud rate error */ +#define UART_FLAG_RTOF USART_ISR_RTOF /*!< UART receiver timeout flag */ #define UART_FLAG_CTS USART_ISR_CTS /*!< UART clear to send flag */ #define UART_FLAG_CTSIF USART_ISR_CTSIF /*!< UART clear to send interrupt flag */ #define UART_FLAG_LBDF USART_ISR_LBDF /*!< UART LIN break detection flag */ @@ -674,6 +703,10 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer #define UART_IT_LBD 0x0846U /*!< UART LIN break detection interruption */ #define UART_IT_CTS 0x096AU /*!< UART CTS interruption */ #define UART_IT_CM 0x112EU /*!< UART character match interruption */ +#if defined(USART_CR1_UESM) +#define UART_IT_WUF 0x1476U /*!< UART wake-up from stop mode interruption */ +#endif /* USART_CR1_UESM */ +#define UART_IT_RTO 0x0B3AU /*!< UART receiver timeout interruption */ #define UART_IT_ERR 0x0060U /*!< UART error interruption */ @@ -689,13 +722,17 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer */ #define UART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */ #define UART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */ -#define UART_CLEAR_NEF USART_ICR_NCF /*!< Noise Error detected Clear Flag */ +#define UART_CLEAR_NEF USART_ICR_NCF /*!< Noise Error detected Clear Flag */ #define UART_CLEAR_OREF USART_ICR_ORECF /*!< Overrun Error Clear Flag */ #define UART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */ #define UART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */ #define UART_CLEAR_LBDF USART_ICR_LBDCF /*!< LIN Break Detection Clear Flag */ #define UART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */ #define UART_CLEAR_CMF USART_ICR_CMCF /*!< Character Match Clear Flag */ +#if defined(USART_CR1_UESM) +#define UART_CLEAR_WUF USART_ICR_WUCF /*!< Wake Up from stop mode Clear Flag */ +#endif /* USART_CR1_UESM */ +#define UART_CLEAR_RTOF USART_ICR_RTOCF /*!< UART receiver timeout clear flag */ /** * @} */ @@ -734,9 +771,9 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer */ #define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) \ do{ \ - SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \ - SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \ - } while(0U) + SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \ + SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \ + } while(0U) /** @brief Clear the specified UART pending flag. * @param __HANDLE__ specifies the UART Handle. @@ -748,9 +785,13 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag + * @arg @ref UART_CLEAR_RTOF Receiver Timeout clear flag * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag * @arg @ref UART_CLEAR_CMF Character Match Clear Flag +#if defined(USART_CR1_UESM) + * @arg @ref UART_CLEAR_WUF Wake Up from stop mode Clear Flag +#endif * @retval None */ #define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) @@ -790,7 +831,13 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @param __HANDLE__ specifies the UART Handle. * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: +#if defined(USART_ISR_REACK) + * @arg @ref UART_FLAG_REACK Receive enable acknowledge flag +#endif * @arg @ref UART_FLAG_TEACK Transmit enable acknowledge flag + #if defined(USART_CR1_UESM) + * @arg @ref UART_FLAG_WUF Wake up from stop mode flag + #endif * @arg @ref UART_FLAG_RWU Receiver wake up flag (if the UART in mute mode) * @arg @ref UART_FLAG_SBKF Send Break flag * @arg @ref UART_FLAG_CMF Character match flag @@ -802,6 +849,7 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @arg @ref UART_FLAG_TXE Transmit data register empty flag * @arg @ref UART_FLAG_TC Transmission Complete flag * @arg @ref UART_FLAG_RXNE Receive data register not empty flag + * @arg @ref UART_FLAG_RTOF Receiver Timeout flag * @arg @ref UART_FLAG_IDLE Idle Line detection flag * @arg @ref UART_FLAG_ORE Overrun Error flag * @arg @ref UART_FLAG_NE Noise Error flag @@ -815,12 +863,16 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @param __HANDLE__ specifies the UART Handle. * @param __INTERRUPT__ specifies the UART interrupt source to enable. * This parameter can be one of the following values: +#if defined(USART_CR1_UESM) + * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt +#endif * @arg @ref UART_IT_CM Character match interrupt * @arg @ref UART_IT_CTS CTS change interrupt * @arg @ref UART_IT_LBD LIN Break detection interrupt * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt * @arg @ref UART_IT_TC Transmission complete interrupt * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref UART_IT_RTO Receive Timeout interrupt * @arg @ref UART_IT_IDLE Idle line detection interrupt * @arg @ref UART_IT_PE Parity Error interrupt * @arg @ref UART_IT_ERR Error interrupt (frame error, noise error, overrun error) @@ -835,12 +887,16 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @param __HANDLE__ specifies the UART Handle. * @param __INTERRUPT__ specifies the UART interrupt source to disable. * This parameter can be one of the following values: +#if defined(USART_CR1_UESM) + * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt +#endif * @arg @ref UART_IT_CM Character match interrupt * @arg @ref UART_IT_CTS CTS change interrupt * @arg @ref UART_IT_LBD LIN Break detection interrupt * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt * @arg @ref UART_IT_TC Transmission complete interrupt * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref UART_IT_RTO Receive Timeout interrupt * @arg @ref UART_IT_IDLE Idle line detection interrupt * @arg @ref UART_IT_PE Parity Error interrupt * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) @@ -854,37 +910,46 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @param __HANDLE__ specifies the UART Handle. * @param __INTERRUPT__ specifies the UART interrupt to check. * This parameter can be one of the following values: +#if defined(USART_CR1_UESM) + * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt +#endif * @arg @ref UART_IT_CM Character match interrupt * @arg @ref UART_IT_CTS CTS change interrupt * @arg @ref UART_IT_LBD LIN Break detection interrupt * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt * @arg @ref UART_IT_TC Transmission complete interrupt * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref UART_IT_RTO Receive Timeout interrupt * @arg @ref UART_IT_IDLE Idle line detection interrupt * @arg @ref UART_IT_PE Parity Error interrupt * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) * @retval The new state of __INTERRUPT__ (SET or RESET). */ -#define __HAL_UART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR & (1U << ((__INTERRUPT__)>> 8U))) != RESET) ? SET : RESET) +#define __HAL_UART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\ + & (1U << ((__INTERRUPT__)>> 8U))) != RESET) ? SET : RESET) /** @brief Check whether the specified UART interrupt source is enabled or not. * @param __HANDLE__ specifies the UART Handle. * @param __INTERRUPT__ specifies the UART interrupt source to check. * This parameter can be one of the following values: +#if defined(USART_CR1_UESM) + * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt +#endif * @arg @ref UART_IT_CM Character match interrupt * @arg @ref UART_IT_CTS CTS change interrupt * @arg @ref UART_IT_LBD LIN Break detection interrupt * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt * @arg @ref UART_IT_TC Transmission complete interrupt * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref UART_IT_RTO Receive Timeout interrupt * @arg @ref UART_IT_IDLE Idle line detection interrupt * @arg @ref UART_IT_PE Parity Error interrupt * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) * @retval The new state of __INTERRUPT__ (SET or RESET). */ #define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) ? (__HANDLE__)->Instance->CR1 : \ - (((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ? (__HANDLE__)->Instance->CR2 : \ - (__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__INTERRUPT__)) & UART_IT_MASK))) != RESET) ? SET : RESET) + (((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ? (__HANDLE__)->Instance->CR2 : \ + (__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__INTERRUPT__)) & UART_IT_MASK))) != RESET) ? SET : RESET) /** @brief Clear the specified UART ISR flag, in setting the proper ICR register flag. * @param __HANDLE__ specifies the UART Handle. @@ -896,10 +961,14 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @arg @ref UART_CLEAR_NEF Noise detected Clear Flag * @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag + * @arg @ref UART_CLEAR_RTOF Receiver timeout clear flag * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag * @arg @ref UART_CLEAR_CMF Character Match Clear Flag + #if defined(USART_CR1_UESM) + * @arg @ref UART_CLEAR_WUF Wake Up from stop mode Clear Flag +#endif * @retval None */ #define __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__)) @@ -1083,10 +1152,10 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @retval SET (__CONTROL__ is valid) or RESET (__CONTROL__ is invalid) */ #define IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)\ - (((__CONTROL__) == UART_HWCONTROL_NONE) || \ - ((__CONTROL__) == UART_HWCONTROL_RTS) || \ - ((__CONTROL__) == UART_HWCONTROL_CTS) || \ - ((__CONTROL__) == UART_HWCONTROL_RTS_CTS)) + (((__CONTROL__) == UART_HWCONTROL_NONE) || \ + ((__CONTROL__) == UART_HWCONTROL_RTS) || \ + ((__CONTROL__) == UART_HWCONTROL_CTS) || \ + ((__CONTROL__) == UART_HWCONTROL_RTS_CTS)) /** * @brief Ensure that UART communication mode is valid. @@ -1134,8 +1203,15 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @param __TIMEOUT__ UART receiver timeout setting. * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid) */ -#define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \ - ((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE)) +#define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \ + ((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE)) + +/** @brief Check the receiver timeout value. + * @note The maximum UART receiver timeout value is 0xFFFFFF. + * @param __TIMEOUTVALUE__ receiver timeout value. + * @retval Test result (TRUE or FALSE) + */ +#define IS_UART_RECEIVER_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFFU) /** * @brief Ensure that UART LIN state is valid. @@ -1275,6 +1351,16 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer #define IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \ ((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_ENABLE)) +#if defined(USART_CR1_UESM) +/** + * @brief Ensure that UART stop mode state is valid. + * @param __STOPMODE__ UART stop mode state. + * @retval SET (__STOPMODE__ is valid) or RESET (__STOPMODE__ is invalid) + */ +#define IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__) (((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_DISABLE) || \ + ((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_ENABLE)) + +#endif /* USART_CR1_UESM */ /** * @brief Ensure that UART mute mode state is valid. * @param __MUTE__ UART mute mode state. @@ -1282,6 +1368,17 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer */ #define IS_UART_MUTE_MODE(__MUTE__) (((__MUTE__) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \ ((__MUTE__) == UART_ADVFEATURE_MUTEMODE_ENABLE)) +#if defined(USART_CR1_UESM) + +/** + * @brief Ensure that UART wake-up selection is valid. + * @param __WAKE__ UART wake-up selection. + * @retval SET (__WAKE__ is valid) or RESET (__WAKE__ is invalid) + */ +#define IS_UART_WAKEUP_SELECTION(__WAKE__) (((__WAKE__) == UART_WAKEUP_ON_ADDRESS) || \ + ((__WAKE__) == UART_WAKEUP_ON_STARTBIT) || \ + ((__WAKE__) == UART_WAKEUP_ON_READDATA_NONEMPTY)) +#endif /* USART_CR1_UESM */ /** * @brief Ensure that UART driver enable polarity is valid. @@ -1320,7 +1417,8 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef *huart); /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, pUART_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, + pUART_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ @@ -1369,6 +1467,10 @@ void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart); */ /* Peripheral Control functions ************************************************/ +void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue); +HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart); + HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart); @@ -1405,7 +1507,8 @@ void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart); HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart); -HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout); +HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout); void UART_AdvFeatureConfig(UART_HandleTypeDef *huart); /** diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h index 3917016cae..e99d8d6846 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h @@ -41,7 +41,24 @@ extern "C" { * @{ */ +#if defined(USART_CR1_UESM) +/** + * @brief UART wake up from stop mode parameters + */ +typedef struct +{ + uint32_t WakeUpEvent; /*!< Specifies which event will activate the Wakeup from Stop mode flag (WUF). + This parameter can be a value of @ref UART_WakeUp_from_Stop_Selection. + If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must + be filled up. */ + + uint16_t AddressLength; /*!< Specifies whether the address is 4 or 7-bit long. + This parameter can be a value of @ref UARTEx_WakeUp_Address_Length. */ + uint8_t Address; /*!< UART/USART node address (7-bit long max). */ +} UART_WakeUpTypeDef; + +#endif /* USART_CR1_UESM */ /** * @} */ @@ -54,9 +71,9 @@ extern "C" { /** @defgroup UARTEx_Word_Length UARTEx Word Length * @{ */ -#define UART_WORDLENGTH_7B USART_CR1_M1 /*!< 7-bit long UART frame */ -#define UART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long UART frame */ -#define UART_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long UART frame */ +#define UART_WORDLENGTH_7B USART_CR1_M1 /*!< 7-bit long UART frame */ +#define UART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long UART frame */ +#define UART_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long UART frame */ /** * @} */ @@ -64,13 +81,12 @@ extern "C" { /** @defgroup UARTEx_WakeUp_Address_Length UARTEx WakeUp Address Length * @{ */ -#define UART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit long wake-up address */ -#define UART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit long wake-up address */ +#define UART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit long wake-up address */ +#define UART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit long wake-up address */ /** * @} */ - /** * @} */ @@ -86,7 +102,8 @@ extern "C" { */ /* Initialization and de-initialization functions ****************************/ -HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime); +HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, + uint32_t DeassertionTime); /** * @} @@ -96,6 +113,10 @@ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, * @{ */ +#if defined(USART_CR1_UESM) +void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart); + +#endif /* USART_CR1_UESM */ /** * @} @@ -106,8 +127,20 @@ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, */ /* Peripheral Control functions **********************************************/ +#if defined(USART_CR1_UESM) +HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection); +HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart); + +#endif/* USART_CR1_UESM */ +#if defined(USART_CR3_UCESM) +HAL_StatusTypeDef HAL_UARTEx_EnableClockStopMode(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UARTEx_DisableClockStopMode(UART_HandleTypeDef *huart); + +#endif /* USART_CR3_UCESM */ HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength); + /** * @} */ @@ -126,12 +159,12 @@ HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *hua * @param __CLOCKSOURCE__ output variable. * @retval UART clocking source, written in __CLOCKSOURCE__. */ -#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ +#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ if((__HANDLE__)->Instance == USART1) \ { \ - switch(__HAL_RCC_GET_USART1_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ case RCC_USART1CLKSOURCE_PCLK2: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \ break; \ @@ -147,12 +180,12 @@ HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *hua default: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ else if((__HANDLE__)->Instance == USART2) \ { \ - switch(__HAL_RCC_GET_USART2_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_USART2_SOURCE()) \ + { \ case RCC_USART2CLKSOURCE_PCLK1: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ break; \ @@ -168,12 +201,12 @@ HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *hua default: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ else if((__HANDLE__)->Instance == USART3) \ { \ - switch(__HAL_RCC_GET_USART3_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_USART3_SOURCE()) \ + { \ case RCC_USART3CLKSOURCE_PCLK1: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ break; \ @@ -189,12 +222,12 @@ HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *hua default: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ else if((__HANDLE__)->Instance == UART4) \ { \ - switch(__HAL_RCC_GET_UART4_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_UART4_SOURCE()) \ + { \ case RCC_UART4CLKSOURCE_PCLK1: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ break; \ @@ -210,12 +243,12 @@ HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *hua default: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ else if ((__HANDLE__)->Instance == UART5) \ { \ - switch(__HAL_RCC_GET_UART5_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_UART5_SOURCE()) \ + { \ case RCC_UART5CLKSOURCE_PCLK1: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ break; \ @@ -231,12 +264,12 @@ HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *hua default: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ else if((__HANDLE__)->Instance == USART6) \ { \ - switch(__HAL_RCC_GET_USART6_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_USART6_SOURCE()) \ + { \ case RCC_USART6CLKSOURCE_PCLK2: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \ break; \ @@ -252,12 +285,12 @@ HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *hua default: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ else if ((__HANDLE__)->Instance == UART7) \ { \ - switch(__HAL_RCC_GET_UART7_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_UART7_SOURCE()) \ + { \ case RCC_UART7CLKSOURCE_PCLK1: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ break; \ @@ -273,12 +306,12 @@ HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *hua default: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ else if ((__HANDLE__)->Instance == UART8) \ { \ - switch(__HAL_RCC_GET_UART8_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_UART8_SOURCE()) \ + { \ case RCC_UART8CLKSOURCE_PCLK1: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ break; \ @@ -294,7 +327,7 @@ HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *hua default: \ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ else \ { \ @@ -313,44 +346,44 @@ HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *hua */ #define UART_MASK_COMPUTATION(__HANDLE__) \ do { \ - if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \ - { \ - if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ - { \ + if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \ + { \ + if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ + { \ (__HANDLE__)->Mask = 0x01FFU ; \ - } \ - else \ - { \ + } \ + else \ + { \ (__HANDLE__)->Mask = 0x00FFU ; \ - } \ - } \ - else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \ - { \ - if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ - { \ + } \ + } \ + else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \ + { \ + if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ + { \ (__HANDLE__)->Mask = 0x00FFU ; \ - } \ - else \ - { \ + } \ + else \ + { \ (__HANDLE__)->Mask = 0x007FU ; \ - } \ - } \ - else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B) \ - { \ - if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ - { \ + } \ + } \ + else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B) \ + { \ + if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ + { \ (__HANDLE__)->Mask = 0x007FU ; \ - } \ - else \ - { \ + } \ + else \ + { \ (__HANDLE__)->Mask = 0x003FU ; \ - } \ - } \ - else \ - { \ - (__HANDLE__)->Mask = 0x0000U; \ - } \ -} while(0U) + } \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x0000U; \ + } \ + } while(0U) /** * @brief Ensure that UART frame length is valid. @@ -369,7 +402,6 @@ HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *hua #define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \ ((__ADDRESS__) == UART_ADDRESS_DETECT_7B)) - /** * @} */ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_usart.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_usart.h index 9f615f3962..4707dfd80b 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_usart.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_usart.h @@ -209,6 +209,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin #if (USE_HAL_USART_REGISTER_CALLBACKS == 1) #define HAL_USART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */ #endif /* USE_HAL_USART_REGISTER_CALLBACKS */ +#define HAL_USART_ERROR_RTO ((uint32_t)0x00000080U) /*!< Receiver Timeout error */ /** * @} */ @@ -304,9 +305,11 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin * - 0xXXXX : Flag mask in the ISR register * @{ */ +#define USART_FLAG_REACK USART_ISR_REACK /*!< USART receive enable acknowledge flag */ #define USART_FLAG_TEACK USART_ISR_TEACK /*!< USART transmit enable acknowledge flag */ #define USART_FLAG_BUSY USART_ISR_BUSY /*!< USART busy flag */ #define USART_FLAG_TXE USART_ISR_TXE /*!< USART transmit data register empty */ +#define USART_FLAG_RTOF USART_ISR_RTOF /*!< USART receiver timeout flag */ #define USART_FLAG_TC USART_ISR_TC /*!< USART transmission complete */ #define USART_FLAG_RXNE USART_ISR_RXNE /*!< USART read data register not empty */ #define USART_FLAG_IDLE USART_ISR_IDLE /*!< USART idle flag */ @@ -348,10 +351,11 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin */ #define USART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */ #define USART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */ -#define USART_CLEAR_NEF USART_ICR_NCF /*!< Noise Error detected Clear Flag */ +#define USART_CLEAR_NEF USART_ICR_NCF /*!< Noise Error detected Clear Flag */ #define USART_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */ #define USART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */ #define USART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */ +#define USART_CLEAR_RTOF USART_ICR_RTOCF /*!< USART receiver timeout clear flag */ /** * @} */ @@ -383,10 +387,10 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin */ #if (USE_HAL_USART_REGISTER_CALLBACKS == 1) #define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_USART_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0U) + (__HANDLE__)->State = HAL_USART_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0U) #else #define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET) #endif /* USE_HAL_USART_REGISTER_CALLBACKS */ @@ -395,11 +399,13 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin * @param __HANDLE__ specifies the USART Handle * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: + * @arg @ref USART_FLAG_REACK Receive enable acknowledge flag * @arg @ref USART_FLAG_TEACK Transmit enable acknowledge flag * @arg @ref USART_FLAG_BUSY Busy flag * @arg @ref USART_FLAG_TXE Transmit data register empty flag * @arg @ref USART_FLAG_TC Transmission Complete flag * @arg @ref USART_FLAG_RXNE Receive data register not empty flag + * @arg @ref USART_FLAG_RTOF Receiver Timeout flag * @arg @ref USART_FLAG_IDLE Idle Line detection flag * @arg @ref USART_FLAG_ORE OverRun Error flag * @arg @ref USART_FLAG_NE Noise Error flag @@ -419,6 +425,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin * @arg @ref USART_CLEAR_OREF Overrun Error Clear Flag * @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag * @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag + * @arg @ref USART_CLEAR_RTOF Receiver Timeout clear flag * @retval None */ #define __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) @@ -502,7 +509,8 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin * @arg @ref USART_IT_PE Parity Error interrupt * @retval The new state of __INTERRUPT__ (SET or RESET). */ -#define __HAL_USART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR & ((uint32_t)0x01U << (((__INTERRUPT__) & USART_ISR_MASK)>> USART_ISR_POS))) != 0U) ? SET : RESET) +#define __HAL_USART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\ + & ((uint32_t)0x01U << (((__INTERRUPT__) & USART_ISR_MASK)>> USART_ISR_POS))) != 0U) ? SET : RESET) /** @brief Check whether the specified USART interrupt source is enabled or not. * @param __HANDLE__ specifies the USART Handle. @@ -519,8 +527,8 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin * @retval The new state of __INTERRUPT__ (SET or RESET). */ #define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x01U) ? (__HANDLE__)->Instance->CR1 : \ - (((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x02U) ? (__HANDLE__)->Instance->CR2 : \ - (__HANDLE__)->Instance->CR3)) & (0x01U << (((uint16_t)(__INTERRUPT__)) & USART_IT_MASK))) != 0U) ? SET : RESET) + (((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x02U) ? (__HANDLE__)->Instance->CR2 : \ + (__HANDLE__)->Instance->CR3)) & (0x01U << (((uint16_t)(__INTERRUPT__)) & USART_IT_MASK))) != 0U) ? SET : RESET) /** @brief Clear the specified USART ISR flag, in setting the proper ICR register flag. @@ -533,6 +541,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin * @arg @ref USART_CLEAR_NEF Noise detected Clear Flag * @arg @ref USART_CLEAR_OREF Overrun Error Clear Flag * @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag + * @arg @ref USART_CLEAR_RTOF Receiver timeout clear flag * @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag * @retval None */ @@ -598,8 +607,8 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin do { \ if((__HANDLE__)->Instance == USART1) \ { \ - switch(__HAL_RCC_GET_USART1_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ case RCC_USART1CLKSOURCE_PCLK2: \ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK2; \ break; \ @@ -615,12 +624,12 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin default: \ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ else if((__HANDLE__)->Instance == USART2) \ { \ - switch(__HAL_RCC_GET_USART2_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_USART2_SOURCE()) \ + { \ case RCC_USART2CLKSOURCE_PCLK1: \ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \ break; \ @@ -636,12 +645,12 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin default: \ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ else if((__HANDLE__)->Instance == USART3) \ { \ - switch(__HAL_RCC_GET_USART3_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_USART3_SOURCE()) \ + { \ case RCC_USART3CLKSOURCE_PCLK1: \ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \ break; \ @@ -657,12 +666,12 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin default: \ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ else if((__HANDLE__)->Instance == USART6) \ { \ - switch(__HAL_RCC_GET_USART6_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_USART6_SOURCE()) \ + { \ case RCC_USART6CLKSOURCE_PCLK2: \ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK2; \ break; \ @@ -678,7 +687,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin default: \ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ else \ { \ @@ -789,7 +798,8 @@ void HAL_USART_MspDeInit(USART_HandleTypeDef *husart); /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_USART_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID, pUSART_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID, + pUSART_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_USART_REGISTER_CALLBACKS */ @@ -804,13 +814,16 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_ /* IO operation functions *****************************************************/ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size); HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size); -HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); +HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size); HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size); HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size); -HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); +HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size); HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart); HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart); HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart); diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_usart_ex.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_usart_ex.h index e8dc9a9c56..47abbf4dd4 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_usart_ex.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_usart_ex.h @@ -46,14 +46,13 @@ extern "C" { * @{ */ #define USART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1) /*!< 7-bit long USART frame */ -#define USART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long USART frame */ +#define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */ #define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) /*!< 9-bit long USART frame */ /** * @} */ - /** * @} */ @@ -74,45 +73,44 @@ extern "C" { */ #define USART_MASK_COMPUTATION(__HANDLE__) \ do { \ - if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B) \ - { \ - if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \ - { \ + if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B) \ + { \ + if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \ + { \ (__HANDLE__)->Mask = 0x01FFU; \ - } \ - else \ - { \ + } \ + else \ + { \ (__HANDLE__)->Mask = 0x00FFU; \ - } \ - } \ - else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B) \ - { \ - if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \ - { \ + } \ + } \ + else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B) \ + { \ + if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \ + { \ (__HANDLE__)->Mask = 0x00FFU; \ - } \ - else \ - { \ + } \ + else \ + { \ (__HANDLE__)->Mask = 0x007FU; \ - } \ - } \ - else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_7B) \ - { \ - if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \ - { \ + } \ + } \ + else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_7B) \ + { \ + if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \ + { \ (__HANDLE__)->Mask = 0x007FU; \ - } \ - else \ - { \ + } \ + else \ + { \ (__HANDLE__)->Mask = 0x003FU; \ - } \ - } \ - else \ - { \ - (__HANDLE__)->Mask = 0x0000U; \ - } \ -} while(0U) - + } \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x0000U; \ + } \ + } while(0U) /** * @brief Ensure that USART frame length is valid. diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_wwdg.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_wwdg.h index f6ccb4ee11..c0ce8e4cc4 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_wwdg.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_wwdg.h @@ -22,7 +22,7 @@ #define STM32F7xx_HAL_WWDG_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -89,12 +89,12 @@ typedef enum { HAL_WWDG_EWI_CB_ID = 0x00u, /*!< WWDG EWI callback ID */ HAL_WWDG_MSPINIT_CB_ID = 0x01u, /*!< WWDG MspInit callback ID */ -}HAL_WWDG_CallbackIDTypeDef; +} HAL_WWDG_CallbackIDTypeDef; /** * @brief HAL WWDG Callback pointer definition */ -typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef * hppp); /*!< pointer to a WWDG common callback functions */ +typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef *hppp); /*!< pointer to a WWDG common callback functions */ #endif /** @@ -239,7 +239,8 @@ typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef * hppp); /*!< pointer t * @arg WWDG_IT_EWI: Early Wakeup Interrupt * @retval state of __INTERRUPT__ (TRUE or FALSE). */ -#define __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR & (__INTERRUPT__)) == (__INTERRUPT__)) +#define __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR\ + & (__INTERRUPT__)) == (__INTERRUPT__)) /** * @} @@ -294,6 +295,6 @@ void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef *hwwdg); } #endif -#endif /* __STM32F7xx_HAL_WWDG_H */ +#endif /* STM32F7xx_HAL_WWDG_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_adc.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_adc.h index 3216dfb3ca..78ee0aef96 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_adc.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_adc.h @@ -255,11 +255,11 @@ extern "C" { #define ADC_TR_HT_BITOFFSET_POS (16U) /* Value equivalent to POSITION_VAL(ADC_TR_HT) */ /* ADC internal channels related definitions */ /* Internal voltage reference VrefInt */ -#define VREFINT_CAL_ADDR ((uint16_t*) (0x1FF0F44A)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */ +#define VREFINT_CAL_ADDR VREFINT_CAL_ADDR_CMSIS /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */ #define VREFINT_CAL_VREF ( 3300U) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */ /* Temperature sensor */ -#define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FF0F44C)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32F7, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */ -#define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FF0F44E)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32F7, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */ +#define TEMPSENSOR_CAL1_ADDR TEMPSENSOR_CAL1_ADDR_CMSIS /* Internal temperature sensor, address of parameter TS_CAL1: On STM32F7, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */ +#define TEMPSENSOR_CAL2_ADDR TEMPSENSOR_CAL2_ADDR_CMSIS /* Internal temperature sensor, address of parameter TS_CAL2: On STM32F7, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */ #define TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */ #define TEMPSENSOR_CAL2_TEMP (( int32_t) 110) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */ #define TEMPSENSOR_CAL_VREFANALOG ( 3300U) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_lptim.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_lptim.h index 1a54084f0c..03baa9158c 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_lptim.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_lptim.h @@ -18,8 +18,8 @@ */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F7xx_LL_LPTIM_H -#define __STM32F7xx_LL_LPTIM_H +#ifndef STM32F7xx_LL_LPTIM_H +#define STM32F7xx_LL_LPTIM_H #ifdef __cplusplus extern "C" { @@ -31,6 +31,7 @@ extern "C" { /** @addtogroup STM32F7xx_LL_Driver * @{ */ + #if defined (LPTIM1) /** @defgroup LPTIM_LL LPTIM @@ -127,8 +128,8 @@ typedef struct /** @defgroup LPTIM_LL_EC_OPERATING_MODE Operating Mode * @{ */ -#define LL_LPTIM_OPERATING_MODE_CONTINUOUS LPTIM_CR_CNTSTRT /*!__REG__, (__VALUE__)) +#define LL_LPTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__)) /** * @brief Read a value in LPTIM register @@ -289,7 +289,7 @@ typedef struct * @param __REG__ Register to be read * @retval Register value */ -#define LL_LPTIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +#define LL_LPTIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__) /** * @} */ @@ -298,12 +298,25 @@ typedef struct * @} */ - /* Exported functions --------------------------------------------------------*/ /** @defgroup LPTIM_LL_Exported_Functions LPTIM Exported Functions * @{ */ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup LPTIM_LL_EF_Init Initialisation and deinitialisation functions + * @{ + */ + +ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef *LPTIMx); +void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct); +ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, LL_LPTIM_InitTypeDef *LPTIM_InitStruct); +void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx); +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + /** @defgroup LPTIM_LL_EF_LPTIM_Configuration LPTIM Configuration * @{ */ @@ -321,17 +334,6 @@ __STATIC_INLINE void LL_LPTIM_Enable(LPTIM_TypeDef *LPTIMx) SET_BIT(LPTIMx->CR, LPTIM_CR_ENABLE); } -/** - * @brief Disable the LPTIM instance - * @rmtoll CR ENABLE LL_LPTIM_Disable - * @param LPTIMx Low-Power Timer instance - * @retval None - */ -__STATIC_INLINE void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx) -{ - CLEAR_BIT(LPTIMx->CR, LPTIM_CR_ENABLE); -} - /** * @brief Indicates whether the LPTIM instance is enabled. * @rmtoll CR ENABLE LL_LPTIM_IsEnabled @@ -340,7 +342,7 @@ __STATIC_INLINE void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(LPTIM_TypeDef *LPTIMx) { - return (READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == (LPTIM_CR_ENABLE)); + return (((READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == LPTIM_CR_ENABLE) ? 1UL : 0UL)); } /** @@ -361,7 +363,6 @@ __STATIC_INLINE void LL_LPTIM_StartCounter(LPTIM_TypeDef *LPTIMx, uint32_t Opera MODIFY_REG(LPTIMx->CR, LPTIM_CR_CNTSTRT | LPTIM_CR_SNGSTRT, OperatingMode); } - /** * @brief Set the LPTIM registers update mode (enable/disable register preload) * @note This function must be called when the LPTIM instance is disabled. @@ -395,7 +396,7 @@ __STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(LPTIM_TypeDef *LPTIMx) * @note The LPTIMx_ARR register content must only be modified when the LPTIM is enabled * @note After a write to the LPTIMx_ARR register a new write operation to the * same register can only be performed when the previous write operation - * is completed. Any successive write before the ARROK flag be set, will + * is completed. Any successive write before the ARROK flag is set, will * lead to unpredictable results. * @note autoreload value be strictly greater than the compare value. * @rmtoll ARR ARR LL_LPTIM_SetAutoReload @@ -423,7 +424,7 @@ __STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload(LPTIM_TypeDef *LPTIMx) * @brief Set the compare value * @note After a write to the LPTIMx_CMP register a new write operation to the * same register can only be performed when the previous write operation - * is completed. Any successive write before the CMPOK flag be set, will + * is completed. Any successive write before the CMPOK flag is set, will * lead to unpredictable results. * @rmtoll CMP CMP LL_LPTIM_SetCompare * @param LPTIMx Low-Power Timer instance @@ -609,7 +610,6 @@ __STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler(LPTIM_TypeDef *LPTIMx) return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRESC)); } - /** * @} */ @@ -657,7 +657,7 @@ __STATIC_INLINE void LL_LPTIM_DisableTimeout(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(LPTIM_TypeDef *LPTIMx) { - return (READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == (LPTIM_CFGR_TIMOUT)); + return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == LPTIM_CFGR_TIMOUT) ? 1UL : 0UL)); } /** @@ -920,7 +920,7 @@ __STATIC_INLINE void LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(LPTIM_TypeDef *LPTIMx) { - return (READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == (LPTIM_CFGR_ENC)); + return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == LPTIM_CFGR_ENC) ? 1UL : 0UL)); } /** @@ -950,7 +950,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFLAG_CMPM(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPM(LPTIM_TypeDef *LPTIMx) { - return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPM) == (LPTIM_ISR_CMPM)); + return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPM) == LPTIM_ISR_CMPM) ? 1UL : 0UL)); } /** @@ -972,7 +972,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFLAG_ARRM(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(LPTIM_TypeDef *LPTIMx) { - return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == (LPTIM_ISR_ARRM)); + return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == LPTIM_ISR_ARRM) ? 1UL : 0UL)); } /** @@ -994,7 +994,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx) { - return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == (LPTIM_ISR_EXTTRIG)); + return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == LPTIM_ISR_EXTTRIG) ? 1UL : 0UL)); } /** @@ -1009,14 +1009,14 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_CMPOK(LPTIM_TypeDef *LPTIMx) } /** - * @brief Informs application whether the APB bus write operation to the LPTIMx_CMP register has been successfully completed; If so, a new one can be initiated. + * @brief Informs application whether the APB bus write operation to the LPTIMx_CMP register has been successfully completed. If so, a new one can be initiated. * @rmtoll ISR CMPOK LL_LPTIM_IsActiveFlag_CMPOK * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPOK(LPTIM_TypeDef *LPTIMx) { - return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPOK) == (LPTIM_ISR_CMPOK)); + return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPOK) == LPTIM_ISR_CMPOK) ? 1UL : 0UL)); } /** @@ -1031,14 +1031,14 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef *LPTIMx) } /** - * @brief Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully completed; If so, a new one can be initiated. + * @brief Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully completed. If so, a new one can be initiated. * @rmtoll ISR ARROK LL_LPTIM_IsActiveFlag_ARROK * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(LPTIM_TypeDef *LPTIMx) { - return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == (LPTIM_ISR_ARROK)); + return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == LPTIM_ISR_ARROK) ? 1UL : 0UL)); } /** @@ -1060,7 +1060,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(LPTIM_TypeDef *LPTIMx) { - return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == (LPTIM_ISR_UP)); + return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == LPTIM_ISR_UP) ? 1UL : 0UL)); } /** @@ -1082,7 +1082,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(LPTIM_TypeDef *LPTIMx) { - return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == (LPTIM_ISR_DOWN)); + return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == LPTIM_ISR_DOWN) ? 1UL : 0UL)); } /** @@ -1123,7 +1123,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_CMPM(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPM(LPTIM_TypeDef *LPTIMx) { - return (READ_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE) == (LPTIM_IER_CMPMIE)); + return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE) == LPTIM_IER_CMPMIE) ? 1UL : 0UL)); } /** @@ -1156,7 +1156,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(LPTIM_TypeDef *LPTIMx) { - return (READ_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE) == (LPTIM_IER_ARRMIE)); + return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE) == LPTIM_IER_ARRMIE) ? 1UL : 0UL)); } /** @@ -1189,7 +1189,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(LPTIM_TypeDef *LPTIMx) { - return (READ_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE) == (LPTIM_IER_EXTTRIGIE)); + return (((READ_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE) == LPTIM_IER_EXTTRIGIE) ? 1UL : 0UL)); } /** @@ -1222,7 +1222,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_CMPOK(LPTIM_TypeDef *LPTIMx) */ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPOK(LPTIM_TypeDef *LPTIMx) { - return (READ_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE) == (LPTIM_IER_CMPOKIE)); + return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE) == LPTIM_IER_CMPOKIE) ? 1UL : 0UL)); } /** @@ -1251,11 +1251,11 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef *LPTIMx) * @brief Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled. * @rmtoll IER ARROKIE LL_LPTIM_IsEnabledIT_ARROK * @param LPTIMx Low-Power Timer instance - * @retval State of bit (1 or 0). + * @retval State of bit(1 or 0). */ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(LPTIM_TypeDef *LPTIMx) { - return (READ_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE) == (LPTIM_IER_ARROKIE)); + return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE) == LPTIM_IER_ARROKIE) ? 1UL : 0UL)); } /** @@ -1284,11 +1284,11 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_UP(LPTIM_TypeDef *LPTIMx) * @brief Indicates whether the direction change to up interrupt (UPIE) is enabled. * @rmtoll IER UPIE LL_LPTIM_IsEnabledIT_UP * @param LPTIMx Low-Power Timer instance - * @retval State of bit (1 or 0). + * @retval State of bit(1 or 0). */ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(LPTIM_TypeDef *LPTIMx) { - return (READ_BIT(LPTIMx->IER, LPTIM_IER_UPIE) == (LPTIM_IER_UPIE)); + return (((READ_BIT(LPTIMx->IER, LPTIM_IER_UPIE) == LPTIM_IER_UPIE) ? 1UL : 0UL)); } /** @@ -1317,30 +1317,17 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef *LPTIMx) * @brief Indicates whether the direction change to down interrupt (DOWNIE) is enabled. * @rmtoll IER DOWNIE LL_LPTIM_IsEnabledIT_DOWN * @param LPTIMx Low-Power Timer instance - * @retval State of bit (1 or 0). + * @retval State of bit(1 or 0). */ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(LPTIM_TypeDef *LPTIMx) { - return (READ_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE) == (LPTIM_IER_DOWNIE)); + return ((READ_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE) == LPTIM_IER_DOWNIE) ? 1UL : 0UL); } /** * @} */ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup LPTIM_LL_EF_Init Initialisation and deinitialisation functions - * @{ - */ - -ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef *LPTIMx); -void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct); -ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, LL_LPTIM_InitTypeDef *LPTIM_InitStruct); -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - /** * @} */ @@ -1359,6 +1346,6 @@ ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, LL_LPTIM_InitTypeDef *LPTIM_Ini } #endif -#endif /* __STM32F7xx_LL_LPTIM_H */ +#endif /* STM32F7xx_LL_LPTIM_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h index 43fd0d7b5a..88fe9fa033 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h @@ -12,19 +12,21 @@ * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F7xx_LL_SDMMC_H -#define __STM32F7xx_LL_SDMMC_H +#ifndef STM32F7xx_LL_SDMMC_H +#define STM32F7xx_LL_SDMMC_H #ifdef __cplusplus extern "C" { #endif +#if defined(SDMMC1) + /* Includes ------------------------------------------------------------------*/ #include "stm32f7xx_hal_def.h" @@ -127,205 +129,206 @@ typedef struct /** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants * @{ */ -#define SDMMC_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ -#define SDMMC_ERROR_CMD_CRC_FAIL ((uint32_t)0x00000001U) /*!< Command response received (but CRC check failed) */ -#define SDMMC_ERROR_DATA_CRC_FAIL ((uint32_t)0x00000002U) /*!< Data block sent/received (CRC check failed) */ -#define SDMMC_ERROR_CMD_RSP_TIMEOUT ((uint32_t)0x00000004U) /*!< Command response timeout */ -#define SDMMC_ERROR_DATA_TIMEOUT ((uint32_t)0x00000008U) /*!< Data timeout */ -#define SDMMC_ERROR_TX_UNDERRUN ((uint32_t)0x00000010U) /*!< Transmit FIFO underrun */ -#define SDMMC_ERROR_RX_OVERRUN ((uint32_t)0x00000020U) /*!< Receive FIFO overrun */ -#define SDMMC_ERROR_ADDR_MISALIGNED ((uint32_t)0x00000040U) /*!< Misaligned address */ -#define SDMMC_ERROR_BLOCK_LEN_ERR ((uint32_t)0x00000080U) /*!< Transferred block length is not allowed for the card or the +#define SDMMC_ERROR_NONE 0x00000000U /*!< No error */ +#define SDMMC_ERROR_CMD_CRC_FAIL 0x00000001U /*!< Command response received (but CRC check failed) */ +#define SDMMC_ERROR_DATA_CRC_FAIL 0x00000002U /*!< Data block sent/received (CRC check failed) */ +#define SDMMC_ERROR_CMD_RSP_TIMEOUT 0x00000004U /*!< Command response timeout */ +#define SDMMC_ERROR_DATA_TIMEOUT 0x00000008U /*!< Data timeout */ +#define SDMMC_ERROR_TX_UNDERRUN 0x00000010U /*!< Transmit FIFO underrun */ +#define SDMMC_ERROR_RX_OVERRUN 0x00000020U /*!< Receive FIFO overrun */ +#define SDMMC_ERROR_ADDR_MISALIGNED 0x00000040U /*!< Misaligned address */ +#define SDMMC_ERROR_BLOCK_LEN_ERR 0x00000080U /*!< Transferred block length is not allowed for the card or the number of transferred bytes does not match the block length */ -#define SDMMC_ERROR_ERASE_SEQ_ERR ((uint32_t)0x00000100U) /*!< An error in the sequence of erase command occurs */ -#define SDMMC_ERROR_BAD_ERASE_PARAM ((uint32_t)0x00000200U) /*!< An invalid selection for erase groups */ -#define SDMMC_ERROR_WRITE_PROT_VIOLATION ((uint32_t)0x00000400U) /*!< Attempt to program a write protect block */ -#define SDMMC_ERROR_LOCK_UNLOCK_FAILED ((uint32_t)0x00000800U) /*!< Sequence or password error has been detected in unlock +#define SDMMC_ERROR_ERASE_SEQ_ERR 0x00000100U /*!< An error in the sequence of erase command occurs */ +#define SDMMC_ERROR_BAD_ERASE_PARAM 0x00000200U /*!< An invalid selection for erase groups */ +#define SDMMC_ERROR_WRITE_PROT_VIOLATION 0x00000400U /*!< Attempt to program a write protect block */ +#define SDMMC_ERROR_LOCK_UNLOCK_FAILED 0x00000800U /*!< Sequence or password error has been detected in unlock command or if there was an attempt to access a locked card */ -#define SDMMC_ERROR_COM_CRC_FAILED ((uint32_t)0x00001000U) /*!< CRC check of the previous command failed */ -#define SDMMC_ERROR_ILLEGAL_CMD ((uint32_t)0x00002000U) /*!< Command is not legal for the card state */ -#define SDMMC_ERROR_CARD_ECC_FAILED ((uint32_t)0x00004000U) /*!< Card internal ECC was applied but failed to correct the data */ -#define SDMMC_ERROR_CC_ERR ((uint32_t)0x00008000U) /*!< Internal card controller error */ -#define SDMMC_ERROR_GENERAL_UNKNOWN_ERR ((uint32_t)0x00010000U) /*!< General or unknown error */ -#define SDMMC_ERROR_STREAM_READ_UNDERRUN ((uint32_t)0x00020000U) /*!< The card could not sustain data reading in stream rmode */ -#define SDMMC_ERROR_STREAM_WRITE_OVERRUN ((uint32_t)0x00040000U) /*!< The card could not sustain data programming in stream mode */ -#define SDMMC_ERROR_CID_CSD_OVERWRITE ((uint32_t)0x00080000U) /*!< CID/CSD overwrite error */ -#define SDMMC_ERROR_WP_ERASE_SKIP ((uint32_t)0x00100000U) /*!< Only partial address space was erased */ -#define SDMMC_ERROR_CARD_ECC_DISABLED ((uint32_t)0x00200000U) /*!< Command has been executed without using internal ECC */ -#define SDMMC_ERROR_ERASE_RESET ((uint32_t)0x00400000U) /*!< Erase sequence was cleared before executing because an out +#define SDMMC_ERROR_COM_CRC_FAILED 0x00001000U /*!< CRC check of the previous command failed */ +#define SDMMC_ERROR_ILLEGAL_CMD 0x00002000U /*!< Command is not legal for the card state */ +#define SDMMC_ERROR_CARD_ECC_FAILED 0x00004000U /*!< Card internal ECC was applied but failed to correct the data */ +#define SDMMC_ERROR_CC_ERR 0x00008000U /*!< Internal card controller error */ +#define SDMMC_ERROR_GENERAL_UNKNOWN_ERR 0x00010000U /*!< General or unknown error */ +#define SDMMC_ERROR_STREAM_READ_UNDERRUN 0x00020000U /*!< The card could not sustain data reading in stream rmode */ +#define SDMMC_ERROR_STREAM_WRITE_OVERRUN 0x00040000U /*!< The card could not sustain data programming in stream mode */ +#define SDMMC_ERROR_CID_CSD_OVERWRITE 0x00080000U /*!< CID/CSD overwrite error */ +#define SDMMC_ERROR_WP_ERASE_SKIP 0x00100000U /*!< Only partial address space was erased */ +#define SDMMC_ERROR_CARD_ECC_DISABLED 0x00200000U /*!< Command has been executed without using internal ECC */ +#define SDMMC_ERROR_ERASE_RESET 0x00400000U /*!< Erase sequence was cleared before executing because an out of erase sequence command was received */ -#define SDMMC_ERROR_AKE_SEQ_ERR ((uint32_t)0x00800000U) /*!< Error in sequence of authentication */ -#define SDMMC_ERROR_INVALID_VOLTRANGE ((uint32_t)0x01000000U) /*!< Error in case of invalid voltage range */ -#define SDMMC_ERROR_ADDR_OUT_OF_RANGE ((uint32_t)0x02000000U) /*!< Error when addressed block is out of range */ -#define SDMMC_ERROR_REQUEST_NOT_APPLICABLE ((uint32_t)0x04000000U) /*!< Error when command request is not applicable */ -#define SDMMC_ERROR_INVALID_PARAMETER ((uint32_t)0x08000000U) /*!< the used parameter is not valid */ -#define SDMMC_ERROR_UNSUPPORTED_FEATURE ((uint32_t)0x10000000U) /*!< Error when feature is not insupported */ -#define SDMMC_ERROR_BUSY ((uint32_t)0x20000000U) /*!< Error when transfer process is busy */ -#define SDMMC_ERROR_DMA ((uint32_t)0x40000000U) /*!< Error while DMA transfer */ -#define SDMMC_ERROR_TIMEOUT ((uint32_t)0x80000000U) /*!< Timeout error */ +#define SDMMC_ERROR_AKE_SEQ_ERR 0x00800000U /*!< Error in sequence of authentication */ +#define SDMMC_ERROR_INVALID_VOLTRANGE 0x01000000U /*!< Error in case of invalid voltage range */ +#define SDMMC_ERROR_ADDR_OUT_OF_RANGE 0x02000000U /*!< Error when addressed block is out of range */ +#define SDMMC_ERROR_REQUEST_NOT_APPLICABLE 0x04000000U /*!< Error when command request is not applicable */ +#define SDMMC_ERROR_INVALID_PARAMETER 0x08000000U /*!< the used parameter is not valid */ +#define SDMMC_ERROR_UNSUPPORTED_FEATURE 0x10000000U /*!< Error when feature is not insupported */ +#define SDMMC_ERROR_BUSY 0x20000000U /*!< Error when transfer process is busy */ +#define SDMMC_ERROR_DMA 0x40000000U /*!< Error while DMA transfer */ +#define SDMMC_ERROR_TIMEOUT 0x80000000U /*!< Timeout error */ /** * @brief SDMMC Commands Index */ -#define SDMMC_CMD_GO_IDLE_STATE ((uint8_t)0U) /*!< Resets the SD memory card. */ -#define SDMMC_CMD_SEND_OP_COND ((uint8_t)1U) /*!< Sends host capacity support information and activates the card's initialization process. */ -#define SDMMC_CMD_ALL_SEND_CID ((uint8_t)2U) /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */ -#define SDMMC_CMD_SET_REL_ADDR ((uint8_t)3U) /*!< Asks the card to publish a new relative address (RCA). */ -#define SDMMC_CMD_SET_DSR ((uint8_t)4U) /*!< Programs the DSR of all cards. */ -#define SDMMC_CMD_SDMMC_SEN_OP_COND ((uint8_t)5U) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its - operating condition register (OCR) content in the response on the CMD line. */ -#define SDMMC_CMD_HS_SWITCH ((uint8_t)6U) /*!< Checks switchable function (mode 0) and switch card function (mode 1). */ -#define SDMMC_CMD_SEL_DESEL_CARD ((uint8_t)7U) /*!< Selects the card by its own relative address and gets deselected by any other address */ -#define SDMMC_CMD_HS_SEND_EXT_CSD ((uint8_t)8U) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information - and asks the card whether card supports voltage. */ -#define SDMMC_CMD_SEND_CSD ((uint8_t)9U) /*!< Addressed card sends its card specific data (CSD) on the CMD line. */ -#define SDMMC_CMD_SEND_CID ((uint8_t)10U) /*!< Addressed card sends its card identification (CID) on the CMD line. */ -#define SDMMC_CMD_READ_DAT_UNTIL_STOP ((uint8_t)11U) /*!< SD card doesn't support it. */ -#define SDMMC_CMD_STOP_TRANSMISSION ((uint8_t)12U) /*!< Forces the card to stop transmission. */ -#define SDMMC_CMD_SEND_STATUS ((uint8_t)13U) /*!< Addressed card sends its status register. */ -#define SDMMC_CMD_HS_BUSTEST_READ ((uint8_t)14U) /*!< Reserved */ -#define SDMMC_CMD_GO_INACTIVE_STATE ((uint8_t)15U) /*!< Sends an addressed card into the inactive state. */ -#define SDMMC_CMD_SET_BLOCKLEN ((uint8_t)16U) /*!< Sets the block length (in bytes for SDSC) for all following block commands +#define SDMMC_CMD_GO_IDLE_STATE 0U /*!< Resets the SD memory card. */ +#define SDMMC_CMD_SEND_OP_COND 1U /*!< Sends host capacity support information and activates the card's initialization process. */ +#define SDMMC_CMD_ALL_SEND_CID 2U /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */ +#define SDMMC_CMD_SET_REL_ADDR 3U /*!< Asks the card to publish a new relative address (RCA). */ +#define SDMMC_CMD_SET_DSR 4U /*!< Programs the DSR of all cards. */ +#define SDMMC_CMD_SDMMC_SEN_OP_COND 5U /*!< Sends host capacity support information (HCS) and asks the accessed card to send its + operating condition register (OCR) content in the response on the CMD line. */ +#define SDMMC_CMD_HS_SWITCH 6U /*!< Checks switchable function (mode 0) and switch card function (mode 1). */ +#define SDMMC_CMD_SEL_DESEL_CARD 7U /*!< Selects the card by its own relative address and gets deselected by any other address */ +#define SDMMC_CMD_HS_SEND_EXT_CSD 8U /*!< Sends SD Memory Card interface condition, which includes host supply voltage information + and asks the card whether card supports voltage. */ +#define SDMMC_CMD_SEND_CSD 9U /*!< Addressed card sends its card specific data (CSD) on the CMD line. */ +#define SDMMC_CMD_SEND_CID 10U /*!< Addressed card sends its card identification (CID) on the CMD line. */ +#define SDMMC_CMD_READ_DAT_UNTIL_STOP 11U /*!< SD card doesn't support it. */ +#define SDMMC_CMD_STOP_TRANSMISSION 12U /*!< Forces the card to stop transmission. */ +#define SDMMC_CMD_SEND_STATUS 13U /*!< Addressed card sends its status register. */ +#define SDMMC_CMD_HS_BUSTEST_READ 14U /*!< Reserved */ +#define SDMMC_CMD_GO_INACTIVE_STATE 15U /*!< Sends an addressed card into the inactive state. */ +#define SDMMC_CMD_SET_BLOCKLEN 16U /*!< Sets the block length (in bytes for SDSC) for all following block commands (read, write, lock). Default block length is fixed to 512 Bytes. Not effective for SDHS and SDXC. */ -#define SDMMC_CMD_READ_SINGLE_BLOCK ((uint8_t)17U) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of +#define SDMMC_CMD_READ_SINGLE_BLOCK 17U /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of fixed 512 bytes in case of SDHC and SDXC. */ -#define SDMMC_CMD_READ_MULT_BLOCK ((uint8_t)18U) /*!< Continuously transfers data blocks from card to host until interrupted by +#define SDMMC_CMD_READ_MULT_BLOCK 18U /*!< Continuously transfers data blocks from card to host until interrupted by STOP_TRANSMISSION command. */ -#define SDMMC_CMD_HS_BUSTEST_WRITE ((uint8_t)19U) /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */ -#define SDMMC_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20U) /*!< Speed class control command. */ -#define SDMMC_CMD_SET_BLOCK_COUNT ((uint8_t)23U) /*!< Specify block count for CMD18 and CMD25. */ -#define SDMMC_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24U) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of +#define SDMMC_CMD_HS_BUSTEST_WRITE 19U /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */ +#define SDMMC_CMD_WRITE_DAT_UNTIL_STOP 20U /*!< Speed class control command. */ +#define SDMMC_CMD_SET_BLOCK_COUNT 23U /*!< Specify block count for CMD18 and CMD25. */ +#define SDMMC_CMD_WRITE_SINGLE_BLOCK 24U /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of fixed 512 bytes in case of SDHC and SDXC. */ -#define SDMMC_CMD_WRITE_MULT_BLOCK ((uint8_t)25U) /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */ -#define SDMMC_CMD_PROG_CID ((uint8_t)26U) /*!< Reserved for manufacturers. */ -#define SDMMC_CMD_PROG_CSD ((uint8_t)27U) /*!< Programming of the programmable bits of the CSD. */ -#define SDMMC_CMD_SET_WRITE_PROT ((uint8_t)28U) /*!< Sets the write protection bit of the addressed group. */ -#define SDMMC_CMD_CLR_WRITE_PROT ((uint8_t)29U) /*!< Clears the write protection bit of the addressed group. */ -#define SDMMC_CMD_SEND_WRITE_PROT ((uint8_t)30U) /*!< Asks the card to send the status of the write protection bits. */ -#define SDMMC_CMD_SD_ERASE_GRP_START ((uint8_t)32U) /*!< Sets the address of the first write block to be erased. (For SD card only). */ -#define SDMMC_CMD_SD_ERASE_GRP_END ((uint8_t)33U) /*!< Sets the address of the last write block of the continuous range to be erased. */ -#define SDMMC_CMD_ERASE_GRP_START ((uint8_t)35U) /*!< Sets the address of the first write block to be erased. Reserved for each command +#define SDMMC_CMD_WRITE_MULT_BLOCK 25U /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */ +#define SDMMC_CMD_PROG_CID 26U /*!< Reserved for manufacturers. */ +#define SDMMC_CMD_PROG_CSD 27U /*!< Programming of the programmable bits of the CSD. */ +#define SDMMC_CMD_SET_WRITE_PROT 28U /*!< Sets the write protection bit of the addressed group. */ +#define SDMMC_CMD_CLR_WRITE_PROT 29U /*!< Clears the write protection bit of the addressed group. */ +#define SDMMC_CMD_SEND_WRITE_PROT 30U /*!< Asks the card to send the status of the write protection bits. */ +#define SDMMC_CMD_SD_ERASE_GRP_START 32U /*!< Sets the address of the first write block to be erased. (For SD card only). */ +#define SDMMC_CMD_SD_ERASE_GRP_END 33U /*!< Sets the address of the last write block of the continuous range to be erased. */ +#define SDMMC_CMD_ERASE_GRP_START 35U /*!< Sets the address of the first write block to be erased. Reserved for each command system set by switch function command (CMD6). */ -#define SDMMC_CMD_ERASE_GRP_END ((uint8_t)36U) /*!< Sets the address of the last write block of the continuous range to be erased. +#define SDMMC_CMD_ERASE_GRP_END 36U /*!< Sets the address of the last write block of the continuous range to be erased. Reserved for each command system set by switch function command (CMD6). */ -#define SDMMC_CMD_ERASE ((uint8_t)38U) /*!< Reserved for SD security applications. */ -#define SDMMC_CMD_FAST_IO ((uint8_t)39U) /*!< SD card doesn't support it (Reserved). */ -#define SDMMC_CMD_GO_IRQ_STATE ((uint8_t)40U) /*!< SD card doesn't support it (Reserved). */ -#define SDMMC_CMD_LOCK_UNLOCK ((uint8_t)42U) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by +#define SDMMC_CMD_ERASE 38U /*!< Reserved for SD security applications. */ +#define SDMMC_CMD_FAST_IO 39U /*!< SD card doesn't support it (Reserved). */ +#define SDMMC_CMD_GO_IRQ_STATE 40U /*!< SD card doesn't support it (Reserved). */ +#define SDMMC_CMD_LOCK_UNLOCK 42U /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by the SET_BLOCK_LEN command. */ -#define SDMMC_CMD_APP_CMD ((uint8_t)55U) /*!< Indicates to the card that the next command is an application specific command rather +#define SDMMC_CMD_APP_CMD 55U /*!< Indicates to the card that the next command is an application specific command rather than a standard command. */ -#define SDMMC_CMD_GEN_CMD ((uint8_t)56U) /*!< Used either to transfer a data block to the card or to get a data block from the card +#define SDMMC_CMD_GEN_CMD 56U /*!< Used either to transfer a data block to the card or to get a data block from the card for general purpose/application specific commands. */ -#define SDMMC_CMD_NO_CMD ((uint8_t)64U) /*!< No command */ +#define SDMMC_CMD_NO_CMD 64U /*!< No command */ /** * @brief Following commands are SD Card Specific commands. * SDMMC_APP_CMD should be sent before sending these commands. */ -#define SDMMC_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6U) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus +#define SDMMC_CMD_APP_SD_SET_BUSWIDTH 6U /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus widths are given in SCR register. */ -#define SDMMC_CMD_SD_APP_STATUS ((uint8_t)13U) /*!< (ACMD13) Sends the SD status. */ -#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22U) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with +#define SDMMC_CMD_SD_APP_STATUS 13U /*!< (ACMD13) Sends the SD status. */ +#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS 22U /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with 32bit+CRC data block. */ -#define SDMMC_CMD_SD_APP_OP_COND ((uint8_t)41U) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to +#define SDMMC_CMD_SD_APP_OP_COND 41U /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to send its operating condition register (OCR) content in the response on the CMD line. */ -#define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42U) /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */ -#define SDMMC_CMD_SD_APP_SEND_SCR ((uint8_t)51U) /*!< Reads the SD Configuration Register (SCR). */ -#define SDMMC_CMD_SDMMC_RW_DIRECT ((uint8_t)52U) /*!< For SD I/O card only, reserved for security specification. */ -#define SDMMC_CMD_SDMMC_RW_EXTENDED ((uint8_t)53U) /*!< For SD I/O card only, reserved for security specification. */ +#define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT 42U /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */ +#define SDMMC_CMD_SD_APP_SEND_SCR 51U /*!< Reads the SD Configuration Register (SCR). */ +#define SDMMC_CMD_SDMMC_RW_DIRECT 52U /*!< For SD I/O card only, reserved for security specification. */ +#define SDMMC_CMD_SDMMC_RW_EXTENDED 53U /*!< For SD I/O card only, reserved for security specification. */ /** * @brief Following commands are SD Card Specific security commands. * SDMMC_CMD_APP_CMD should be sent before sending these commands. */ -#define SDMMC_CMD_SD_APP_GET_MKB ((uint8_t)43U) -#define SDMMC_CMD_SD_APP_GET_MID ((uint8_t)44U) -#define SDMMC_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45U) -#define SDMMC_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46U) -#define SDMMC_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47U) -#define SDMMC_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48U) -#define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18U) -#define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25U) -#define SDMMC_CMD_SD_APP_SECURE_ERASE ((uint8_t)38U) -#define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49U) -#define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48U) +#define SDMMC_CMD_SD_APP_GET_MKB 43U +#define SDMMC_CMD_SD_APP_GET_MID 44U +#define SDMMC_CMD_SD_APP_SET_CER_RN1 45U +#define SDMMC_CMD_SD_APP_GET_CER_RN2 46U +#define SDMMC_CMD_SD_APP_SET_CER_RES2 47U +#define SDMMC_CMD_SD_APP_GET_CER_RES1 48U +#define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK 18U +#define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK 25U +#define SDMMC_CMD_SD_APP_SECURE_ERASE 38U +#define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA 49U +#define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB 48U /** * @brief Masks for errors Card Status R1 (OCR Register) */ -#define SDMMC_OCR_ADDR_OUT_OF_RANGE ((uint32_t)0x80000000U) -#define SDMMC_OCR_ADDR_MISALIGNED ((uint32_t)0x40000000U) -#define SDMMC_OCR_BLOCK_LEN_ERR ((uint32_t)0x20000000U) -#define SDMMC_OCR_ERASE_SEQ_ERR ((uint32_t)0x10000000U) -#define SDMMC_OCR_BAD_ERASE_PARAM ((uint32_t)0x08000000U) -#define SDMMC_OCR_WRITE_PROT_VIOLATION ((uint32_t)0x04000000U) -#define SDMMC_OCR_LOCK_UNLOCK_FAILED ((uint32_t)0x01000000U) -#define SDMMC_OCR_COM_CRC_FAILED ((uint32_t)0x00800000U) -#define SDMMC_OCR_ILLEGAL_CMD ((uint32_t)0x00400000U) -#define SDMMC_OCR_CARD_ECC_FAILED ((uint32_t)0x00200000U) -#define SDMMC_OCR_CC_ERROR ((uint32_t)0x00100000U) -#define SDMMC_OCR_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00080000U) -#define SDMMC_OCR_STREAM_READ_UNDERRUN ((uint32_t)0x00040000U) -#define SDMMC_OCR_STREAM_WRITE_OVERRUN ((uint32_t)0x00020000U) -#define SDMMC_OCR_CID_CSD_OVERWRITE ((uint32_t)0x00010000U) -#define SDMMC_OCR_WP_ERASE_SKIP ((uint32_t)0x00008000U) -#define SDMMC_OCR_CARD_ECC_DISABLED ((uint32_t)0x00004000U) -#define SDMMC_OCR_ERASE_RESET ((uint32_t)0x00002000U) -#define SDMMC_OCR_AKE_SEQ_ERROR ((uint32_t)0x00000008U) -#define SDMMC_OCR_ERRORBITS ((uint32_t)0xFDFFE008U) +#define SDMMC_OCR_ADDR_OUT_OF_RANGE 0x80000000U +#define SDMMC_OCR_ADDR_MISALIGNED 0x40000000U +#define SDMMC_OCR_BLOCK_LEN_ERR 0x20000000U +#define SDMMC_OCR_ERASE_SEQ_ERR 0x10000000U +#define SDMMC_OCR_BAD_ERASE_PARAM 0x08000000U +#define SDMMC_OCR_WRITE_PROT_VIOLATION 0x04000000U +#define SDMMC_OCR_LOCK_UNLOCK_FAILED 0x01000000U +#define SDMMC_OCR_COM_CRC_FAILED 0x00800000U +#define SDMMC_OCR_ILLEGAL_CMD 0x00400000U +#define SDMMC_OCR_CARD_ECC_FAILED 0x00200000U +#define SDMMC_OCR_CC_ERROR 0x00100000U +#define SDMMC_OCR_GENERAL_UNKNOWN_ERROR 0x00080000U +#define SDMMC_OCR_STREAM_READ_UNDERRUN 0x00040000U +#define SDMMC_OCR_STREAM_WRITE_OVERRUN 0x00020000U +#define SDMMC_OCR_CID_CSD_OVERWRITE 0x00010000U +#define SDMMC_OCR_WP_ERASE_SKIP 0x00008000U +#define SDMMC_OCR_CARD_ECC_DISABLED 0x00004000U +#define SDMMC_OCR_ERASE_RESET 0x00002000U +#define SDMMC_OCR_AKE_SEQ_ERROR 0x00000008U +#define SDMMC_OCR_ERRORBITS 0xFDFFE008U /** * @brief Masks for R6 Response */ -#define SDMMC_R6_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00002000U) -#define SDMMC_R6_ILLEGAL_CMD ((uint32_t)0x00004000U) -#define SDMMC_R6_COM_CRC_FAILED ((uint32_t)0x00008000U) +#define SDMMC_R6_GENERAL_UNKNOWN_ERROR 0x00002000U +#define SDMMC_R6_ILLEGAL_CMD 0x00004000U +#define SDMMC_R6_COM_CRC_FAILED 0x00008000U -#define SDMMC_VOLTAGE_WINDOW_SD ((uint32_t)0x80100000U) -#define SDMMC_HIGH_CAPACITY ((uint32_t)0x40000000U) -#define SDMMC_STD_CAPACITY ((uint32_t)0x00000000U) -#define SDMMC_CHECK_PATTERN ((uint32_t)0x000001AAU) +#define SDMMC_VOLTAGE_WINDOW_SD 0x80100000U +#define SDMMC_HIGH_CAPACITY 0x40000000U +#define SDMMC_STD_CAPACITY 0x00000000U +#define SDMMC_CHECK_PATTERN 0x000001AAU +#define SD_SWITCH_1_8V_CAPACITY 0x01000000U -#define SDMMC_MAX_VOLT_TRIAL ((uint32_t)0x0000FFFFU) +#define SDMMC_MAX_VOLT_TRIAL 0x0000FFFFU -#define SDMMC_MAX_TRIAL ((uint32_t)0x0000FFFFU) +#define SDMMC_MAX_TRIAL 0x0000FFFFU -#define SDMMC_ALLZERO ((uint32_t)0x00000000U) +#define SDMMC_ALLZERO 0x00000000U -#define SDMMC_WIDE_BUS_SUPPORT ((uint32_t)0x00040000U) -#define SDMMC_SINGLE_BUS_SUPPORT ((uint32_t)0x00010000U) -#define SDMMC_CARD_LOCKED ((uint32_t)0x02000000U) +#define SDMMC_WIDE_BUS_SUPPORT 0x00040000U +#define SDMMC_SINGLE_BUS_SUPPORT 0x00010000U +#define SDMMC_CARD_LOCKED 0x02000000U -#define SDMMC_DATATIMEOUT ((uint32_t)0xFFFFFFFFU) +#define SDMMC_DATATIMEOUT 0xFFFFFFFFU -#define SDMMC_0TO7BITS ((uint32_t)0x000000FFU) -#define SDMMC_8TO15BITS ((uint32_t)0x0000FF00U) -#define SDMMC_16TO23BITS ((uint32_t)0x00FF0000U) -#define SDMMC_24TO31BITS ((uint32_t)0xFF000000U) -#define SDMMC_MAX_DATA_LENGTH ((uint32_t)0x01FFFFFFU) +#define SDMMC_0TO7BITS 0x000000FFU +#define SDMMC_8TO15BITS 0x0000FF00U +#define SDMMC_16TO23BITS 0x00FF0000U +#define SDMMC_24TO31BITS 0xFF000000U +#define SDMMC_MAX_DATA_LENGTH 0x01FFFFFFU -#define SDMMC_HALFFIFO ((uint32_t)0x00000008U) -#define SDMMC_HALFFIFOBYTES ((uint32_t)0x00000020U) +#define SDMMC_HALFFIFO 0x00000008U +#define SDMMC_HALFFIFOBYTES 0x00000020U /** * @brief Command Class supported */ -#define SDMMC_CCCC_ERASE ((uint32_t)0x00000020U) - -#define SDMMC_CMDTIMEOUT ((uint32_t)5000U) /* Command send and response timeout */ -#define SDMMC_MAXERASETIMEOUT ((uint32_t)63000U) /* Max erase Timeout 63 s */ +#define SDMMC_CCCC_ERASE 0x00000020U +#define SDMMC_CMDTIMEOUT 5000U /* Command send and response timeout */ +#define SDMMC_MAXERASETIMEOUT 63000U /* Max erase Timeout 63 s */ +#define SDMMC_STOPTRANSFERTIMEOUT 100000000U /* Timeout for STOP TRANSMISSION command */ /** @defgroup SDMMC_LL_Clock_Edge Clock Edge * @{ */ -#define SDMMC_CLOCK_EDGE_RISING ((uint32_t)0x00000000U) +#define SDMMC_CLOCK_EDGE_RISING 0x00000000U #define SDMMC_CLOCK_EDGE_FALLING SDMMC_CLKCR_NEGEDGE #define IS_SDMMC_CLOCK_EDGE(EDGE) (((EDGE) == SDMMC_CLOCK_EDGE_RISING) || \ - ((EDGE) == SDMMC_CLOCK_EDGE_FALLING)) + ((EDGE) == SDMMC_CLOCK_EDGE_FALLING)) /** * @} */ @@ -333,11 +336,11 @@ typedef struct /** @defgroup SDMMC_LL_Clock_Bypass Clock Bypass * @{ */ -#define SDMMC_CLOCK_BYPASS_DISABLE ((uint32_t)0x00000000U) +#define SDMMC_CLOCK_BYPASS_DISABLE 0x00000000U #define SDMMC_CLOCK_BYPASS_ENABLE SDMMC_CLKCR_BYPASS #define IS_SDMMC_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDMMC_CLOCK_BYPASS_DISABLE) || \ - ((BYPASS) == SDMMC_CLOCK_BYPASS_ENABLE)) + ((BYPASS) == SDMMC_CLOCK_BYPASS_ENABLE)) /** * @} */ @@ -345,11 +348,11 @@ typedef struct /** @defgroup SDMMC_LL_Clock_Power_Save Clock Power Saving * @{ */ -#define SDMMC_CLOCK_POWER_SAVE_DISABLE ((uint32_t)0x00000000U) +#define SDMMC_CLOCK_POWER_SAVE_DISABLE 0x00000000U #define SDMMC_CLOCK_POWER_SAVE_ENABLE SDMMC_CLKCR_PWRSAV #define IS_SDMMC_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDMMC_CLOCK_POWER_SAVE_DISABLE) || \ - ((SAVE) == SDMMC_CLOCK_POWER_SAVE_ENABLE)) + ((SAVE) == SDMMC_CLOCK_POWER_SAVE_ENABLE)) /** * @} */ @@ -357,13 +360,13 @@ typedef struct /** @defgroup SDMMC_LL_Bus_Wide Bus Width * @{ */ -#define SDMMC_BUS_WIDE_1B ((uint32_t)0x00000000U) +#define SDMMC_BUS_WIDE_1B 0x00000000U #define SDMMC_BUS_WIDE_4B SDMMC_CLKCR_WIDBUS_0 #define SDMMC_BUS_WIDE_8B SDMMC_CLKCR_WIDBUS_1 #define IS_SDMMC_BUS_WIDE(WIDE) (((WIDE) == SDMMC_BUS_WIDE_1B) || \ - ((WIDE) == SDMMC_BUS_WIDE_4B) || \ - ((WIDE) == SDMMC_BUS_WIDE_8B)) + ((WIDE) == SDMMC_BUS_WIDE_4B) || \ + ((WIDE) == SDMMC_BUS_WIDE_8B)) /** * @} */ @@ -371,11 +374,11 @@ typedef struct /** @defgroup SDMMC_LL_Hardware_Flow_Control Hardware Flow Control * @{ */ -#define SDMMC_HARDWARE_FLOW_CONTROL_DISABLE ((uint32_t)0x00000000U) +#define SDMMC_HARDWARE_FLOW_CONTROL_DISABLE 0x00000000U #define SDMMC_HARDWARE_FLOW_CONTROL_ENABLE SDMMC_CLKCR_HWFC_EN #define IS_SDMMC_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_DISABLE) || \ - ((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_ENABLE)) + ((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_ENABLE)) /** * @} */ @@ -383,7 +386,7 @@ typedef struct /** @defgroup SDMMC_LL_Clock_Division Clock Division * @{ */ -#define IS_SDMMC_CLKDIV(DIV) ((DIV) <= 0xFF) +#define IS_SDMMC_CLKDIV(DIV) ((DIV) <= 0xFFU) /** * @} */ @@ -391,7 +394,7 @@ typedef struct /** @defgroup SDMMC_LL_Command_Index Command Index * @{ */ -#define IS_SDMMC_CMD_INDEX(INDEX) ((INDEX) < 0x40) +#define IS_SDMMC_CMD_INDEX(INDEX) ((INDEX) < 0x40U) /** * @} */ @@ -399,13 +402,13 @@ typedef struct /** @defgroup SDMMC_LL_Response_Type Response Type * @{ */ -#define SDMMC_RESPONSE_NO ((uint32_t)0x00000000U) +#define SDMMC_RESPONSE_NO 0x00000000U #define SDMMC_RESPONSE_SHORT SDMMC_CMD_WAITRESP_0 #define SDMMC_RESPONSE_LONG SDMMC_CMD_WAITRESP #define IS_SDMMC_RESPONSE(RESPONSE) (((RESPONSE) == SDMMC_RESPONSE_NO) || \ - ((RESPONSE) == SDMMC_RESPONSE_SHORT) || \ - ((RESPONSE) == SDMMC_RESPONSE_LONG)) + ((RESPONSE) == SDMMC_RESPONSE_SHORT) || \ + ((RESPONSE) == SDMMC_RESPONSE_LONG)) /** * @} */ @@ -413,13 +416,13 @@ typedef struct /** @defgroup SDMMC_LL_Wait_Interrupt_State Wait Interrupt * @{ */ -#define SDMMC_WAIT_NO ((uint32_t)0x00000000U) +#define SDMMC_WAIT_NO 0x00000000U #define SDMMC_WAIT_IT SDMMC_CMD_WAITINT #define SDMMC_WAIT_PEND SDMMC_CMD_WAITPEND #define IS_SDMMC_WAIT(WAIT) (((WAIT) == SDMMC_WAIT_NO) || \ - ((WAIT) == SDMMC_WAIT_IT) || \ - ((WAIT) == SDMMC_WAIT_PEND)) + ((WAIT) == SDMMC_WAIT_IT) || \ + ((WAIT) == SDMMC_WAIT_PEND)) /** * @} */ @@ -427,11 +430,11 @@ typedef struct /** @defgroup SDMMC_LL_CPSM_State CPSM State * @{ */ -#define SDMMC_CPSM_DISABLE ((uint32_t)0x00000000U) +#define SDMMC_CPSM_DISABLE 0x00000000U #define SDMMC_CPSM_ENABLE SDMMC_CMD_CPSMEN #define IS_SDMMC_CPSM(CPSM) (((CPSM) == SDMMC_CPSM_DISABLE) || \ - ((CPSM) == SDMMC_CPSM_ENABLE)) + ((CPSM) == SDMMC_CPSM_ENABLE)) /** * @} */ @@ -439,15 +442,15 @@ typedef struct /** @defgroup SDMMC_LL_Response_Registers Response Register * @{ */ -#define SDMMC_RESP1 ((uint32_t)0x00000000U) -#define SDMMC_RESP2 ((uint32_t)0x00000004U) -#define SDMMC_RESP3 ((uint32_t)0x00000008U) -#define SDMMC_RESP4 ((uint32_t)0x0000000C) +#define SDMMC_RESP1 0x00000000U +#define SDMMC_RESP2 0x00000004U +#define SDMMC_RESP3 0x00000008U +#define SDMMC_RESP4 0x0000000CU #define IS_SDMMC_RESP(RESP) (((RESP) == SDMMC_RESP1) || \ - ((RESP) == SDMMC_RESP2) || \ - ((RESP) == SDMMC_RESP3) || \ - ((RESP) == SDMMC_RESP4)) + ((RESP) == SDMMC_RESP2) || \ + ((RESP) == SDMMC_RESP3) || \ + ((RESP) == SDMMC_RESP4)) /** * @} */ @@ -455,7 +458,7 @@ typedef struct /** @defgroup SDMMC_LL_Data_Length Data Lenght * @{ */ -#define IS_SDMMC_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF) +#define IS_SDMMC_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFFU) /** * @} */ @@ -463,7 +466,7 @@ typedef struct /** @defgroup SDMMC_LL_Data_Block_Size Data Block Size * @{ */ -#define SDMMC_DATABLOCK_SIZE_1B ((uint32_t)0x00000000U) +#define SDMMC_DATABLOCK_SIZE_1B 0x00000000U #define SDMMC_DATABLOCK_SIZE_2B SDMMC_DCTRL_DBLOCKSIZE_0 #define SDMMC_DATABLOCK_SIZE_4B SDMMC_DCTRL_DBLOCKSIZE_1 #define SDMMC_DATABLOCK_SIZE_8B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1) @@ -480,20 +483,20 @@ typedef struct #define SDMMC_DATABLOCK_SIZE_16384B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3) #define IS_SDMMC_BLOCK_SIZE(SIZE) (((SIZE) == SDMMC_DATABLOCK_SIZE_1B) || \ - ((SIZE) == SDMMC_DATABLOCK_SIZE_2B) || \ - ((SIZE) == SDMMC_DATABLOCK_SIZE_4B) || \ - ((SIZE) == SDMMC_DATABLOCK_SIZE_8B) || \ - ((SIZE) == SDMMC_DATABLOCK_SIZE_16B) || \ - ((SIZE) == SDMMC_DATABLOCK_SIZE_32B) || \ - ((SIZE) == SDMMC_DATABLOCK_SIZE_64B) || \ - ((SIZE) == SDMMC_DATABLOCK_SIZE_128B) || \ - ((SIZE) == SDMMC_DATABLOCK_SIZE_256B) || \ - ((SIZE) == SDMMC_DATABLOCK_SIZE_512B) || \ - ((SIZE) == SDMMC_DATABLOCK_SIZE_1024B) || \ - ((SIZE) == SDMMC_DATABLOCK_SIZE_2048B) || \ - ((SIZE) == SDMMC_DATABLOCK_SIZE_4096B) || \ - ((SIZE) == SDMMC_DATABLOCK_SIZE_8192B) || \ - ((SIZE) == SDMMC_DATABLOCK_SIZE_16384B)) + ((SIZE) == SDMMC_DATABLOCK_SIZE_2B) || \ + ((SIZE) == SDMMC_DATABLOCK_SIZE_4B) || \ + ((SIZE) == SDMMC_DATABLOCK_SIZE_8B) || \ + ((SIZE) == SDMMC_DATABLOCK_SIZE_16B) || \ + ((SIZE) == SDMMC_DATABLOCK_SIZE_32B) || \ + ((SIZE) == SDMMC_DATABLOCK_SIZE_64B) || \ + ((SIZE) == SDMMC_DATABLOCK_SIZE_128B) || \ + ((SIZE) == SDMMC_DATABLOCK_SIZE_256B) || \ + ((SIZE) == SDMMC_DATABLOCK_SIZE_512B) || \ + ((SIZE) == SDMMC_DATABLOCK_SIZE_1024B) || \ + ((SIZE) == SDMMC_DATABLOCK_SIZE_2048B) || \ + ((SIZE) == SDMMC_DATABLOCK_SIZE_4096B) || \ + ((SIZE) == SDMMC_DATABLOCK_SIZE_8192B) || \ + ((SIZE) == SDMMC_DATABLOCK_SIZE_16384B)) /** * @} */ @@ -501,11 +504,11 @@ typedef struct /** @defgroup SDMMC_LL_Transfer_Direction Transfer Direction * @{ */ -#define SDMMC_TRANSFER_DIR_TO_CARD ((uint32_t)0x00000000U) -#define SDMMC_TRANSFER_DIR_TO_SDMMC SDMMC_DCTRL_DTDIR +#define SDMMC_TRANSFER_DIR_TO_CARD 0x00000000U +#define SDMMC_TRANSFER_DIR_TO_SDMMC SDMMC_DCTRL_DTDIR #define IS_SDMMC_TRANSFER_DIR(DIR) (((DIR) == SDMMC_TRANSFER_DIR_TO_CARD) || \ - ((DIR) == SDMMC_TRANSFER_DIR_TO_SDMMC)) + ((DIR) == SDMMC_TRANSFER_DIR_TO_SDMMC)) /** * @} */ @@ -513,11 +516,11 @@ typedef struct /** @defgroup SDMMC_LL_Transfer_Type Transfer Type * @{ */ -#define SDMMC_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000U) +#define SDMMC_TRANSFER_MODE_BLOCK 0x00000000U #define SDMMC_TRANSFER_MODE_STREAM SDMMC_DCTRL_DTMODE #define IS_SDMMC_TRANSFER_MODE(MODE) (((MODE) == SDMMC_TRANSFER_MODE_BLOCK) || \ - ((MODE) == SDMMC_TRANSFER_MODE_STREAM)) + ((MODE) == SDMMC_TRANSFER_MODE_STREAM)) /** * @} */ @@ -525,11 +528,11 @@ typedef struct /** @defgroup SDMMC_LL_DPSM_State DPSM State * @{ */ -#define SDMMC_DPSM_DISABLE ((uint32_t)0x00000000U) +#define SDMMC_DPSM_DISABLE 0x00000000U #define SDMMC_DPSM_ENABLE SDMMC_DCTRL_DTEN #define IS_SDMMC_DPSM(DPSM) (((DPSM) == SDMMC_DPSM_DISABLE) ||\ - ((DPSM) == SDMMC_DPSM_ENABLE)) + ((DPSM) == SDMMC_DPSM_ENABLE)) /** * @} */ @@ -537,11 +540,11 @@ typedef struct /** @defgroup SDMMC_LL_Read_Wait_Mode Read Wait Mode * @{ */ -#define SDMMC_READ_WAIT_MODE_DATA2 ((uint32_t)0x00000000U) +#define SDMMC_READ_WAIT_MODE_DATA2 0x00000000U #define SDMMC_READ_WAIT_MODE_CLK (SDMMC_DCTRL_RWMOD) #define IS_SDMMC_READWAIT_MODE(MODE) (((MODE) == SDMMC_READ_WAIT_MODE_CLK) || \ - ((MODE) == SDMMC_READ_WAIT_MODE_DATA2)) + ((MODE) == SDMMC_READ_WAIT_MODE_DATA2)) /** * @} */ @@ -549,28 +552,28 @@ typedef struct /** @defgroup SDMMC_LL_Interrupt_sources Interrupt Sources * @{ */ -#define SDMMC_IT_CCRCFAIL SDMMC_STA_CCRCFAIL -#define SDMMC_IT_DCRCFAIL SDMMC_STA_DCRCFAIL -#define SDMMC_IT_CTIMEOUT SDMMC_STA_CTIMEOUT -#define SDMMC_IT_DTIMEOUT SDMMC_STA_DTIMEOUT -#define SDMMC_IT_TXUNDERR SDMMC_STA_TXUNDERR -#define SDMMC_IT_RXOVERR SDMMC_STA_RXOVERR -#define SDMMC_IT_CMDREND SDMMC_STA_CMDREND -#define SDMMC_IT_CMDSENT SDMMC_STA_CMDSENT -#define SDMMC_IT_DATAEND SDMMC_STA_DATAEND -#define SDMMC_IT_DBCKEND SDMMC_STA_DBCKEND -#define SDMMC_IT_CMDACT SDMMC_STA_CMDACT -#define SDMMC_IT_TXACT SDMMC_STA_TXACT -#define SDMMC_IT_RXACT SDMMC_STA_RXACT -#define SDMMC_IT_TXFIFOHE SDMMC_STA_TXFIFOHE -#define SDMMC_IT_RXFIFOHF SDMMC_STA_RXFIFOHF -#define SDMMC_IT_TXFIFOF SDMMC_STA_TXFIFOF -#define SDMMC_IT_RXFIFOF SDMMC_STA_RXFIFOF -#define SDMMC_IT_TXFIFOE SDMMC_STA_TXFIFOE -#define SDMMC_IT_RXFIFOE SDMMC_STA_RXFIFOE -#define SDMMC_IT_TXDAVL SDMMC_STA_TXDAVL -#define SDMMC_IT_RXDAVL SDMMC_STA_RXDAVL -#define SDMMC_IT_SDIOIT SDMMC_STA_SDIOIT +#define SDMMC_IT_CCRCFAIL SDMMC_MASK_CCRCFAILIE +#define SDMMC_IT_DCRCFAIL SDMMC_MASK_DCRCFAILIE +#define SDMMC_IT_CTIMEOUT SDMMC_MASK_CTIMEOUTIE +#define SDMMC_IT_DTIMEOUT SDMMC_MASK_DTIMEOUTIE +#define SDMMC_IT_TXUNDERR SDMMC_MASK_TXUNDERRIE +#define SDMMC_IT_RXOVERR SDMMC_MASK_RXOVERRIE +#define SDMMC_IT_CMDREND SDMMC_MASK_CMDRENDIE +#define SDMMC_IT_CMDSENT SDMMC_MASK_CMDSENTIE +#define SDMMC_IT_DATAEND SDMMC_MASK_DATAENDIE +#define SDMMC_IT_DBCKEND SDMMC_MASK_DBCKENDIE +#define SDMMC_IT_CMDACT SDMMC_MASK_CMDACTIE +#define SDMMC_IT_TXACT SDMMC_MASK_TXACTIE +#define SDMMC_IT_RXACT SDMMC_MASK_RXACTIE +#define SDMMC_IT_TXFIFOHE SDMMC_MASK_TXFIFOHEIE +#define SDMMC_IT_RXFIFOHF SDMMC_MASK_RXFIFOHFIE +#define SDMMC_IT_TXFIFOF SDMMC_MASK_TXFIFOFIE +#define SDMMC_IT_RXFIFOF SDMMC_MASK_RXFIFOFIE +#define SDMMC_IT_TXFIFOE SDMMC_MASK_TXFIFOEIE +#define SDMMC_IT_RXFIFOE SDMMC_MASK_RXFIFOEIE +#define SDMMC_IT_TXDAVL SDMMC_MASK_TXDAVLIE +#define SDMMC_IT_RXDAVL SDMMC_MASK_RXDAVLIE +#define SDMMC_IT_SDIOIT SDMMC_MASK_SDIOITIE /** * @} */ @@ -603,7 +606,13 @@ typedef struct #define SDMMC_STATIC_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_CTIMEOUT |\ SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_RXOVERR |\ SDMMC_FLAG_CMDREND | SDMMC_FLAG_CMDSENT | SDMMC_FLAG_DATAEND |\ - SDMMC_FLAG_DBCKEND)) + SDMMC_FLAG_DBCKEND | SDMMC_FLAG_SDIOIT)) + +#define SDMMC_STATIC_CMD_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CTIMEOUT | SDMMC_FLAG_CMDREND |\ + SDMMC_FLAG_CMDSENT)) + +#define SDMMC_STATIC_DATA_FLAGS ((uint32_t)(SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR |\ + SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DATAEND | SDMMC_FLAG_DBCKEND)) /** * @} */ @@ -640,11 +649,10 @@ typedef struct SDMMC_CMD_CPSMEN | SDMMC_CMD_SDIOSUSPEND)) /* SDMMC Initialization Frequency (400KHz max) */ -#define SDMMC_INIT_CLK_DIV ((uint8_t)0x76) +#define SDMMC_INIT_CLK_DIV ((uint8_t)0x76) /* 48MHz / (SDMMC_INIT_CLK_DIV + 2) < 400KHz */ /* SDMMC Data Transfer Frequency (25MHz max) */ -#define SDMMC_TRANSFER_CLK_DIV ((uint8_t)0x0) - +#define SDMMC_TRANSFER_CLK_DIV ((uint8_t)0x0) /* 48MHz / (SDMMC_TRANSFER_CLK_DIV + 2) < 25MHz */ /** * @} */ @@ -656,35 +664,36 @@ typedef struct /** * @brief Enable the SDMMC device. - * @param __INSTANCE__ SDMMC Instance + * @param __INSTANCE__: SDMMC Instance * @retval None */ #define __SDMMC_ENABLE(__INSTANCE__) ((__INSTANCE__)->CLKCR |= SDMMC_CLKCR_CLKEN) /** * @brief Disable the SDMMC device. - * @param __INSTANCE__ SDMMC Instance + * @param __INSTANCE__: SDMMC Instance * @retval None */ #define __SDMMC_DISABLE(__INSTANCE__) ((__INSTANCE__)->CLKCR &= ~SDMMC_CLKCR_CLKEN) /** * @brief Enable the SDMMC DMA transfer. - * @param __INSTANCE__ SDMMC Instance + * @param __INSTANCE__: SDMMC Instance * @retval None */ #define __SDMMC_DMA_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_DMAEN) + /** * @brief Disable the SDMMC DMA transfer. - * @param __INSTANCE__ SDMMC Instance + * @param __INSTANCE__: SDMMC Instance * @retval None */ #define __SDMMC_DMA_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_DMAEN) /** * @brief Enable the SDMMC device interrupt. - * @param __INSTANCE__ Pointer to SDMMC register base - * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be enabled. + * @param __INSTANCE__ : Pointer to SDMMC register base + * @param __INTERRUPT__ : specifies the SDMMC interrupt sources to be enabled. * This parameter can be one or a combination of the following values: * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt @@ -694,7 +703,7 @@ typedef struct * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt - * @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt + * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt @@ -707,15 +716,15 @@ typedef struct * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt - * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt + * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt * @retval None */ #define __SDMMC_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK |= (__INTERRUPT__)) /** * @brief Disable the SDMMC device interrupt. - * @param __INSTANCE__ Pointer to SDMMC register base - * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be disabled. + * @param __INSTANCE__ : Pointer to SDMMC register base + * @param __INTERRUPT__ : specifies the SDMMC interrupt sources to be disabled. * This parameter can be one or a combination of the following values: * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt @@ -725,7 +734,7 @@ typedef struct * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt - * @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt + * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt @@ -738,15 +747,15 @@ typedef struct * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt - * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt + * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt * @retval None */ #define __SDMMC_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__)) /** * @brief Checks whether the specified SDMMC flag is set or not. - * @param __INSTANCE__ Pointer to SDMMC register base - * @param __FLAG__ specifies the flag to check. + * @param __INSTANCE__ : Pointer to SDMMC register base + * @param __FLAG__: specifies the flag to check. * This parameter can be one of the following values: * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) @@ -756,7 +765,7 @@ typedef struct * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed) * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required) - * @arg SDMMC_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) + * @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero) * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed) * @arg SDMMC_FLAG_CMDACT: Command transfer in progress * @arg SDMMC_FLAG_TXACT: Data transmit in progress @@ -769,16 +778,16 @@ typedef struct * @arg SDMMC_FLAG_RXFIFOE: Receive FIFO empty * @arg SDMMC_FLAG_TXDAVL: Data available in transmit FIFO * @arg SDMMC_FLAG_RXDAVL: Data available in receive FIFO - * @arg SDMMC_FLAG_SDMMCIT: SD I/O interrupt received + * @arg SDMMC_FLAG_SDIOIT: SDIO interrupt received * @retval The new state of SDMMC_FLAG (SET or RESET). */ -#define __SDMMC_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != RESET) +#define __SDMMC_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != 0U) /** * @brief Clears the SDMMC pending flags. - * @param __INSTANCE__ Pointer to SDMMC register base - * @param __FLAG__ specifies the flag to clear. + * @param __INSTANCE__ : Pointer to SDMMC register base + * @param __FLAG__: specifies the flag to clear. * This parameter can be one or a combination of the following values: * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) @@ -788,17 +797,17 @@ typedef struct * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed) * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required) - * @arg SDMMC_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) + * @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero) * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed) - * @arg SDMMC_FLAG_SDMMCIT: SD I/O interrupt received + * @arg SDMMC_FLAG_SDIOIT: SDIO interrupt received * @retval None */ #define __SDMMC_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__)) /** * @brief Checks whether the specified SDMMC interrupt has occurred or not. - * @param __INSTANCE__ Pointer to SDMMC register base - * @param __INTERRUPT__ specifies the SDMMC interrupt source to check. + * @param __INSTANCE__ : Pointer to SDMMC register base + * @param __INTERRUPT__: specifies the SDMMC interrupt source to check. * This parameter can be one of the following values: * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt @@ -808,7 +817,7 @@ typedef struct * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt - * @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt + * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt @@ -821,15 +830,15 @@ typedef struct * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt - * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt + * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt * @retval The new state of SDMMC_IT (SET or RESET). */ #define __SDMMC_GET_IT (__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__)) /** * @brief Clears the SDMMC's interrupt pending bits. - * @param __INSTANCE__ Pointer to SDMMC register base - * @param __INTERRUPT__ specifies the interrupt pending bit to clear. + * @param __INSTANCE__ : Pointer to SDMMC register base + * @param __INTERRUPT__: specifies the interrupt pending bit to clear. * This parameter can be one or a combination of the following values: * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt @@ -839,64 +848,64 @@ typedef struct * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt - * @arg SDMMC_IT_DATAEND: Data end (data counter, SDMMC_DCOUNT, is zero) interrupt - * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt + * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt + * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt * @retval None */ #define __SDMMC_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__)) /** * @brief Enable Start the SD I/O Read Wait operation. - * @param __INSTANCE__ Pointer to SDMMC register base + * @param __INSTANCE__ : Pointer to SDMMC register base * @retval None */ #define __SDMMC_START_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTART) /** * @brief Disable Start the SD I/O Read Wait operations. - * @param __INSTANCE__ Pointer to SDMMC register base + * @param __INSTANCE__ : Pointer to SDMMC register base * @retval None */ #define __SDMMC_START_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTART) /** * @brief Enable Start the SD I/O Read Wait operation. - * @param __INSTANCE__ Pointer to SDMMC register base + * @param __INSTANCE__ : Pointer to SDMMC register base * @retval None */ #define __SDMMC_STOP_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTOP) /** * @brief Disable Stop the SD I/O Read Wait operations. - * @param __INSTANCE__ Pointer to SDMMC register base + * @param __INSTANCE__ : Pointer to SDMMC register base * @retval None */ #define __SDMMC_STOP_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTOP) /** * @brief Enable the SD I/O Mode Operation. - * @param __INSTANCE__ Pointer to SDMMC register base + * @param __INSTANCE__ : Pointer to SDMMC register base * @retval None */ #define __SDMMC_OPERATION_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_SDIOEN) /** * @brief Disable the SD I/O Mode Operation. - * @param __INSTANCE__ Pointer to SDMMC register base + * @param __INSTANCE__ : Pointer to SDMMC register base * @retval None */ #define __SDMMC_OPERATION_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_SDIOEN) /** * @brief Enable the SD I/O Suspend command sending. - * @param __INSTANCE__ Pointer to SDMMC register base + * @param __INSTANCE__ : Pointer to SDMMC register base * @retval None */ #define __SDMMC_SUSPEND_CMD_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_SDIOSUSPEND) /** * @brief Disable the SD I/O Suspend command sending. - * @param __INSTANCE__ Pointer to SDMMC register base + * @param __INSTANCE__ : Pointer to SDMMC register base * @retval None */ #define __SDMMC_SUSPEND_CMD_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_SDIOSUSPEND) @@ -970,7 +979,7 @@ uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint64_t Addr); uint32_t SDMMC_CmdGoIdleState(SDMMC_TypeDef *SDMMCx); uint32_t SDMMC_CmdOperCond(SDMMC_TypeDef *SDMMCx); uint32_t SDMMC_CmdAppCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument); -uint32_t SDMMC_CmdAppOperCommand(SDMMC_TypeDef *SDMMCx, uint32_t SdType); +uint32_t SDMMC_CmdAppOperCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument); uint32_t SDMMC_CmdBusWidth(SDMMC_TypeDef *SDMMCx, uint32_t BusWidth); uint32_t SDMMC_CmdSendSCR(SDMMC_TypeDef *SDMMCx); uint32_t SDMMC_CmdSendCID(SDMMC_TypeDef *SDMMCx); @@ -997,10 +1006,12 @@ uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument); * @} */ +#endif /* SDMMC1 */ + #ifdef __cplusplus } #endif -#endif /* __STM32F7xx_LL_SDMMC_H */ +#endif /* STM32F7xx_LL_SDMMC_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h index 6e8df28327..cdbde05b72 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h @@ -121,17 +121,7 @@ static const uint8_t SHIFT_TAB_OISx[] = #define TIM_POSITION_BRK_SOURCE (POSITION_VAL(Source) & 0x1FUL) /* Generic bit definitions for TIMx_AF1 register */ -#define TIMx_AF1_BKINE TIM1_AF1_BKINE /*!< BRK BKINE input enable */ -#if defined(DFSDM1_Channel0) -#define TIMx_AF1_BKDFBKE TIM1_AF1_BKDFBKE /*!< BRK DFSDM1_BREAK[0] enable */ -#endif /* DFSDM1_Channel0 */ #define TIMx_AF1_BKINP TIM1_AF1_BKINP /*!< BRK BKIN input polarity */ -/* Generic bit definitions for TIMx_AF2 register */ -#define TIMx_AF2_BK2INE TIM1_AF2_BK2INE /*!< BRK B2KINE input enable */ -#if defined(DFSDM1_Channel0) -#define TIMx_AF2_BK2DFBKE TIM1_AF2_BK2DFBKE /*!< BRK DFSDM_BREAK[0] enable */ -#endif /* DFSDM1_Channel0 */ -#define TIMx_AF2_BK2INP TIM1_AF2_BK2INP /*!< BRK BK2IN input polarity */ #endif /* TIM_BREAK_INPUT_SUPPORT */ /* Remap mask definitions */ @@ -176,14 +166,14 @@ static const uint8_t SHIFT_TAB_OISx[] = * @retval none */ #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \ -(((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\ -((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\ -((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\ -((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\ -((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\ -((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\ -((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\ -((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U) + (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U) /** @brief Calculate the deadtime sampling period(in ps). * @param __TIMCLK__ timer input clock frequency (in Hz). @@ -194,9 +184,9 @@ static const uint8_t SHIFT_TAB_OISx[] = * @retval none */ #define TIM_CALC_DTS(__TIMCLK__, __CKD__) \ - (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \ - ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \ - ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U))) + (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \ + ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \ + ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U))) /** * @} */ @@ -235,13 +225,14 @@ typedef struct This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/ - uint8_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter + uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter reaches zero, an update event is generated and counting restarts from the RCR value (N). This means in PWM mode that (N+1) corresponds to: - the number of PWM periods in edge-aligned mode - the number of half PWM period in center-aligned mode - This parameter must be a number between 0x00 and 0xFF. + GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. + Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/ } LL_TIM_InitTypeDef; @@ -1157,7 +1148,7 @@ typedef struct * @retval UIF status bit */ #define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \ - (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos) + (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos) /** * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration. @@ -1171,11 +1162,11 @@ typedef struct * @retval DTG[0:7] */ #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \ - ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \ - (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\ - (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\ - (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\ - 0U) + ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \ + (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\ + (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\ + (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\ + 0U) /** * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency. @@ -1185,7 +1176,7 @@ typedef struct * @retval Prescaler value (between Min_Data=0 and Max_Data=65535) */ #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \ - (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)(((__TIMCLK__)/(__CNTCLK__)) - 1U) : 0U) + (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)(((__TIMCLK__)/(__CNTCLK__)) - 1U) : 0U) /** * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency. @@ -1196,7 +1187,7 @@ typedef struct * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) */ #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \ - ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U) + ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U) /** * @brief HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay. @@ -1207,8 +1198,8 @@ typedef struct * @retval Compare value (between Min_Data=0 and Max_Data=65535) */ #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \ -((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \ - / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U)))) + ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \ + / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U)))) /** * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode). @@ -1220,8 +1211,8 @@ typedef struct * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) */ #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \ - ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \ - + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__)))) + ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \ + + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__)))) /** * @brief HELPER macro retrieving the ratio of the input capture prescaler @@ -1234,7 +1225,7 @@ typedef struct * @retval Input capture prescaler ratio (1, 2, 4 or 8) */ #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \ - ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos))) + ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos))) /** @@ -1383,7 +1374,7 @@ __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx) /** * @brief Set the timer counter counting mode. - * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to + * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to * check whether or not the counter mode selection feature is supported * by a timer instance. * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) @@ -1407,7 +1398,7 @@ __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMo /** * @brief Get actual counter mode. - * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to + * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to * check whether or not the counter mode selection feature is supported * by a timer instance. * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n @@ -1444,7 +1435,7 @@ __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx) */ __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx) { - CLEAR_BIT(TIMx->CR1,TIM_CR1_ARPE); + CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE); } /** @@ -1460,7 +1451,7 @@ __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx) /** * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters. - * @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check * whether or not the clock division feature is supported by the timer * instance. * @rmtoll CR1 CKD LL_TIM_SetClockDivision @@ -1478,7 +1469,7 @@ __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDi /** * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters. - * @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check * whether or not the clock division feature is supported by the timer * instance. * @rmtoll CR1 CKD LL_TIM_GetClockDivision @@ -1495,7 +1486,7 @@ __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx) /** * @brief Set the counter value. - * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a 32 bits counter. * @rmtoll CNT CNT LL_TIM_SetCounter * @param TIMx Timer instance @@ -1509,7 +1500,7 @@ __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter) /** * @brief Get the counter value. - * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a 32 bits counter. * @rmtoll CNT CNT LL_TIM_GetCounter * @param TIMx Timer instance @@ -1563,7 +1554,7 @@ __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx) /** * @brief Set the auto-reload value. * @note The counter is blocked while the auto-reload value is null. - * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a 32 bits counter. * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter * @rmtoll ARR ARR LL_TIM_SetAutoReload @@ -1579,7 +1570,7 @@ __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload /** * @brief Get the auto-reload value. * @rmtoll ARR ARR LL_TIM_GetAutoReload - * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a 32 bits counter. * @param TIMx Timer instance * @retval Auto-reload value @@ -1592,11 +1583,11 @@ __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx) /** * @brief Set the repetition counter value. * @note For advanced timer instances RepetitionCounter can be up to 65535. - * @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a repetition counter. * @rmtoll RCR REP LL_TIM_SetRepetitionCounter * @param TIMx Timer instance - * @param RepetitionCounter between Min_Data=0 and Max_Data=255 + * @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer. * @retval None */ __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter) @@ -1606,7 +1597,7 @@ __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t Rep /** * @brief Get the repetition counter value. - * @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a repetition counter. * @rmtoll RCR REP LL_TIM_GetRepetitionCounter * @param TIMx Timer instance @@ -1640,6 +1631,16 @@ __STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx) CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP); } +/** + * @brief Indicate whether update interrupt flag (UIF) copy is set. + * @param Counter Counter value + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(uint32_t Counter) +{ + return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL); +} + /** * @} */ @@ -1652,7 +1653,7 @@ __STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx) * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written, * they are updated only when a commutation event (COM) occurs. * @note Only on channels that have a complementary output. - * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check * whether or not a timer instance is able to generate a commutation event. * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload * @param TIMx Timer instance @@ -1665,7 +1666,7 @@ __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx) /** * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload. - * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check * whether or not a timer instance is able to generate a commutation event. * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload * @param TIMx Timer instance @@ -1678,7 +1679,7 @@ __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx) /** * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM). - * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check * whether or not a timer instance is able to generate a commutation event. * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate * @param TIMx Timer instance @@ -1722,7 +1723,7 @@ __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx) /** * @brief Set the lock level to freeze the * configuration of several capture/compare parameters. - * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not * the lock mechanism is supported by a timer instance. * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel * @param TIMx Timer instance @@ -2024,7 +2025,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Chann /** * @brief Set the IDLE state of an output channel * @note This function is significant only for the timer instances - * supporting the break feature. Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) + * supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx) * can be used to check whether or not a timer instance provides * a break input. * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n @@ -2248,7 +2249,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t /** * @brief Enable clearing the output channel on an external event. * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode. - * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether + * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether * or not a timer instance can clear the OCxREF signal on an external event. * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n * CCMR1 OC2CE LL_TIM_OC_EnableClear\n @@ -2275,7 +2276,7 @@ __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel) /** * @brief Disable clearing the output channel on an external event. - * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether + * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether * or not a timer instance can clear the OCxREF signal on an external event. * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n * CCMR1 OC2CE LL_TIM_OC_DisableClear\n @@ -2304,7 +2305,7 @@ __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel) * @brief Indicates clearing the output channel on an external event is enabled for the output channel. * @note This function enables clearing the output channel on an external event. * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode. - * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether + * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether * or not a timer instance can clear the OCxREF signal on an external event. * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n @@ -2332,7 +2333,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Ch /** * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of the Ocx and OCxN signals). - * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not * dead-time insertion feature is supported by a timer instance. * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime @@ -2348,9 +2349,9 @@ __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime) /** * @brief Set compare value for output channel 1 (TIMx_CCR1). * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. - * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a 32 bits counter. - * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not * output channel 1 is supported by a timer instance. * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1 * @param TIMx Timer instance @@ -2365,9 +2366,9 @@ __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t Compare /** * @brief Set compare value for output channel 2 (TIMx_CCR2). * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. - * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a 32 bits counter. - * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not * output channel 2 is supported by a timer instance. * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2 * @param TIMx Timer instance @@ -2382,9 +2383,9 @@ __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t Compare /** * @brief Set compare value for output channel 3 (TIMx_CCR3). * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. - * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a 32 bits counter. - * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not * output channel is supported by a timer instance. * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3 * @param TIMx Timer instance @@ -2399,9 +2400,9 @@ __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t Compare /** * @brief Set compare value for output channel 4 (TIMx_CCR4). * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. - * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a 32 bits counter. - * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not * output channel 4 is supported by a timer instance. * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4 * @param TIMx Timer instance @@ -2415,7 +2416,7 @@ __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t Compare /** * @brief Set compare value for output channel 5 (TIMx_CCR5). - * @note Macro @ref IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not * output channel 5 is supported by a timer instance. * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5 * @param TIMx Timer instance @@ -2429,7 +2430,7 @@ __STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t Compare /** * @brief Set compare value for output channel 6 (TIMx_CCR6). - * @note Macro @ref IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not * output channel 6 is supported by a timer instance. * @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6 * @param TIMx Timer instance @@ -2444,9 +2445,9 @@ __STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t Compare /** * @brief Get compare value (TIMx_CCR1) set for output channel 1. * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. - * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a 32 bits counter. - * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not * output channel 1 is supported by a timer instance. * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1 * @param TIMx Timer instance @@ -2460,9 +2461,9 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx) /** * @brief Get compare value (TIMx_CCR2) set for output channel 2. * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. - * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a 32 bits counter. - * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not * output channel 2 is supported by a timer instance. * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2 * @param TIMx Timer instance @@ -2476,9 +2477,9 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx) /** * @brief Get compare value (TIMx_CCR3) set for output channel 3. * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. - * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a 32 bits counter. - * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not * output channel 3 is supported by a timer instance. * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3 * @param TIMx Timer instance @@ -2492,9 +2493,9 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx) /** * @brief Get compare value (TIMx_CCR4) set for output channel 4. * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. - * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a 32 bits counter. - * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not * output channel 4 is supported by a timer instance. * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4 * @param TIMx Timer instance @@ -2507,7 +2508,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx) /** * @brief Get compare value (TIMx_CCR5) set for output channel 5. - * @note Macro @ref IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not * output channel 5 is supported by a timer instance. * @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5 * @param TIMx Timer instance @@ -2520,7 +2521,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(TIM_TypeDef *TIMx) /** * @brief Get compare value (TIMx_CCR6) set for output channel 6. - * @note Macro @ref IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not * output channel 6 is supported by a timer instance. * @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6 * @param TIMx Timer instance @@ -2533,7 +2534,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(TIM_TypeDef *TIMx) /** * @brief Select on which reference signal the OC5REF is combined to. - * @note Macro @ref IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports the combined 3-phase PWM mode. * @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n @@ -2837,7 +2838,7 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Chann /** * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination). - * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides an XOR input. * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination * @param TIMx Timer instance @@ -2850,7 +2851,7 @@ __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx) /** * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input. - * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides an XOR input. * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination * @param TIMx Timer instance @@ -2863,7 +2864,7 @@ __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx) /** * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input. - * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides an XOR input. * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination * @param TIMx Timer instance @@ -2877,9 +2878,9 @@ __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx) /** * @brief Get captured value for input channel 1. * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. - * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a 32 bits counter. - * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not * input channel 1 is supported by a timer instance. * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1 * @param TIMx Timer instance @@ -2893,9 +2894,9 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx) /** * @brief Get captured value for input channel 2. * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. - * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a 32 bits counter. - * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not * input channel 2 is supported by a timer instance. * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2 * @param TIMx Timer instance @@ -2909,9 +2910,9 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx) /** * @brief Get captured value for input channel 3. * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. - * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a 32 bits counter. - * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not * input channel 3 is supported by a timer instance. * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3 * @param TIMx Timer instance @@ -2925,9 +2926,9 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx) /** * @brief Get captured value for input channel 4. * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. - * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a 32 bits counter. - * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not * input channel 4 is supported by a timer instance. * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4 * @param TIMx Timer instance @@ -2948,7 +2949,7 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx) /** * @brief Enable external clock mode 2. * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal. - * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports external clock mode2. * @rmtoll SMCR ECE LL_TIM_EnableExternalClock * @param TIMx Timer instance @@ -2961,7 +2962,7 @@ __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx) /** * @brief Disable external clock mode 2. - * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports external clock mode2. * @rmtoll SMCR ECE LL_TIM_DisableExternalClock * @param TIMx Timer instance @@ -2974,7 +2975,7 @@ __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx) /** * @brief Indicate whether external clock mode 2 is enabled. - * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports external clock mode2. * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock * @param TIMx Timer instance @@ -2991,9 +2992,9 @@ __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx) * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput() * function. This timer input must be configured by calling * the @ref LL_TIM_IC_Config() function. - * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports external clock mode1. - * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports external clock mode2. * @rmtoll SMCR SMS LL_TIM_SetClockSource\n * SMCR ECE LL_TIM_SetClockSource @@ -3011,7 +3012,7 @@ __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSour /** * @brief Set the encoder interface mode. - * @note Macro @ref IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports the encoder mode. * @rmtoll SMCR SMS LL_TIM_SetEncoderMode * @param TIMx Timer instance @@ -3035,7 +3036,7 @@ __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMo */ /** * @brief Set the trigger output (TRGO) used for timer synchronization . - * @note Macro @ref IS_TIM_MASTER_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance can operate as a master timer. * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput * @param TIMx Timer instance @@ -3057,7 +3058,7 @@ __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSy /** * @brief Set the trigger output 2 (TRGO2) used for ADC synchronization . - * @note Macro @ref IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check * whether or not a timer instance can be used for ADC synchronization. * @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2 * @param TIMx Timer Instance @@ -3087,7 +3088,7 @@ __STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSyn /** * @brief Set the synchronization mode of a slave timer. - * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not * a timer instance can operate as a slave timer. * @rmtoll SMCR SMS LL_TIM_SetSlaveMode * @param TIMx Timer instance @@ -3106,7 +3107,7 @@ __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode) /** * @brief Set the selects the trigger input to be used to synchronize the counter. - * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not * a timer instance can operate as a slave timer. * @rmtoll SMCR TS LL_TIM_SetTriggerInput * @param TIMx Timer instance @@ -3128,7 +3129,7 @@ __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerI /** * @brief Enable the Master/Slave mode. - * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not * a timer instance can operate as a slave timer. * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode * @param TIMx Timer instance @@ -3141,7 +3142,7 @@ __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx) /** * @brief Disable the Master/Slave mode. - * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not * a timer instance can operate as a slave timer. * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode * @param TIMx Timer instance @@ -3154,7 +3155,7 @@ __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx) /** * @brief Indicates whether the Master/Slave mode is enabled. - * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not * a timer instance can operate as a slave timer. * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode * @param TIMx Timer instance @@ -3167,7 +3168,7 @@ __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx) /** * @brief Configure the external trigger (ETR) input. - * @note Macro @ref IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides an external trigger input. * @rmtoll SMCR ETP LL_TIM_ConfigETR\n * SMCR ETPS LL_TIM_ConfigETR\n @@ -3215,7 +3216,7 @@ __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, u */ /** * @brief Enable the break function. - * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a break input. * @rmtoll BDTR BKE LL_TIM_EnableBRK * @param TIMx Timer instance @@ -3230,7 +3231,7 @@ __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx) * @brief Disable the break function. * @rmtoll BDTR BKE LL_TIM_DisableBRK * @param TIMx Timer instance - * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a break input. * @retval None */ @@ -3241,7 +3242,7 @@ __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx) /** * @brief Configure the break input. - * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a break input. * @rmtoll BDTR BKP LL_TIM_ConfigBRK\n * BDTR BKF LL_TIM_ConfigBRK @@ -3268,14 +3269,15 @@ __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx) * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8 * @retval None */ -__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter) +__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, + uint32_t BreakFilter) { MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF, BreakPolarity | BreakFilter); } /** * @brief Enable the break 2 function. - * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a second break input. * @rmtoll BDTR BK2E LL_TIM_EnableBRK2 * @param TIMx Timer instance @@ -3288,7 +3290,7 @@ __STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx) /** * @brief Disable the break 2 function. - * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a second break input. * @rmtoll BDTR BK2E LL_TIM_DisableBRK2 * @param TIMx Timer instance @@ -3301,7 +3303,7 @@ __STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx) /** * @brief Configure the break 2 input. - * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a second break input. * @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n * BDTR BK2F LL_TIM_ConfigBRK2 @@ -3335,7 +3337,7 @@ __STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarit /** * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes. - * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a break input. * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n * BDTR OSSR LL_TIM_SetOffStates @@ -3355,7 +3357,7 @@ __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdl /** * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active). - * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a break input. * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput * @param TIMx Timer instance @@ -3368,7 +3370,7 @@ __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx) /** * @brief Disable automatic output (MOE can be set only by software). - * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a break input. * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput * @param TIMx Timer instance @@ -3381,7 +3383,7 @@ __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx) /** * @brief Indicate whether automatic output is enabled. - * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a break input. * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput * @param TIMx Timer instance @@ -3396,7 +3398,7 @@ __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx) * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register). * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by * software and is reset in case of break or break2 event - * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a break input. * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs * @param TIMx Timer instance @@ -3411,7 +3413,7 @@ __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx) * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register). * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by * software and is reset in case of break or break2 event. - * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a break input. * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs * @param TIMx Timer instance @@ -3424,7 +3426,7 @@ __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx) /** * @brief Indicates whether outputs are enabled. - * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a break input. * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs * @param TIMx Timer instance @@ -3438,7 +3440,7 @@ __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx) #if defined(TIM_BREAK_INPUT_SUPPORT) /** * @brief Enable the signals connected to the designated timer break input. - * @note Macro @ref IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether + * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether * or not a timer instance allows for break input selection. * @rmtoll AF1 BKINE LL_TIM_EnableBreakInputSource\n * AF1 BKDFBKE LL_TIM_EnableBreakInputSource\n @@ -3461,7 +3463,7 @@ __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t B /** * @brief Disable the signals connected to the designated timer break input. - * @note Macro @ref IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether + * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether * or not a timer instance allows for break input selection. * @rmtoll AF1 BKINE LL_TIM_DisableBreakInputSource\n * AF1 BKDFBKE LL_TIM_DisableBreakInputSource\n @@ -3484,7 +3486,7 @@ __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t /** * @brief Set the polarity of the break signal for the timer break input. - * @note Macro @ref IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether + * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether * or not a timer instance allows for break input selection. * @rmtoll AF1 BKINE LL_TIM_SetBreakInputSourcePolarity\n * AF1 BKDFBKE LL_TIM_SetBreakInputSourcePolarity\n @@ -3518,7 +3520,7 @@ __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint3 */ /** * @brief Configures the timer DMA burst feature. - * @note Macro @ref IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or + * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or * not a timer instance supports the DMA burst mode. * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n * DCR DBA LL_TIM_ConfigDMABurst @@ -3584,7 +3586,7 @@ __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstB */ /** * @brief Remap TIM inputs (input channel, internal/external triggers). - * @note Macro @ref IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not * a some timer inputs can be remapped. * @rmtoll TIM2_OR ITR1_RMP LL_TIM_SetRemap\n * TIM5_OR TI4_RMP LL_TIM_SetRemap\n diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h index df5db5ea4a..5a89688ee7 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h @@ -42,13 +42,6 @@ extern "C" { /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ -/** @defgroup USART_LL_Private_Constants USART Private Constants - * @{ - */ -/** - * @} - */ - /* Private macros ------------------------------------------------------------*/ #if defined(USE_FULL_LL_DRIVER) /** @defgroup USART_LL_Private_Macros USART Private Macros @@ -156,18 +149,21 @@ typedef struct */ #define LL_USART_ICR_PECF USART_ICR_PECF /*!< Parity error flag */ #define LL_USART_ICR_FECF USART_ICR_FECF /*!< Framing error flag */ -#define LL_USART_ICR_NCF USART_ICR_NCF /*!< Noise error detected flag */ +#define LL_USART_ICR_NCF USART_ICR_NCF /*!< Noise error detected flag */ #define LL_USART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error flag */ #define LL_USART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected flag */ #define LL_USART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete flag */ #if defined(USART_TCBGT_SUPPORT) #define LL_USART_ICR_TCBGTCF USART_ICR_TCBGTCF /*!< Transmission completed before guard time flag */ -#endif +#endif /* USART_TCBGT_SUPPORT */ #define LL_USART_ICR_LBDCF USART_ICR_LBDCF /*!< LIN break detection flag */ #define LL_USART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS flag */ #define LL_USART_ICR_RTOCF USART_ICR_RTOCF /*!< Receiver timeout flag */ #define LL_USART_ICR_EOBCF USART_ICR_EOBCF /*!< End of block flag */ #define LL_USART_ICR_CMCF USART_ICR_CMCF /*!< Character match flag */ +#if defined(USART_CR1_UESM) +#define LL_USART_ICR_WUCF USART_ICR_WUCF /*!< Wakeup from Stop mode flag */ +#endif /* USART_CR1_UESM */ /** * @} */ @@ -195,10 +191,16 @@ typedef struct #define LL_USART_ISR_CMF USART_ISR_CMF /*!< Character match flag */ #define LL_USART_ISR_SBKF USART_ISR_SBKF /*!< Send break flag */ #define LL_USART_ISR_RWU USART_ISR_RWU /*!< Receiver wakeup from Mute mode flag */ +#if defined(USART_CR1_UESM) +#define LL_USART_ISR_WUF USART_ISR_WUF /*!< Wakeup from Stop mode flag */ +#endif /* USART_CR1_UESM */ #define LL_USART_ISR_TEACK USART_ISR_TEACK /*!< Transmit enable acknowledge flag */ +#if defined(USART_ISR_REACK) +#define LL_USART_ISR_REACK USART_ISR_REACK /*!< Receive enable acknowledge flag */ +#endif /* USART_ISR_REACK */ #if defined(USART_TCBGT_SUPPORT) #define LL_USART_ISR_TCBGT USART_ISR_TCBGT /*!< Transmission complete before guard time completion flag */ -#endif +#endif /* USART_TCBGT_SUPPORT */ /** * @} */ @@ -218,9 +220,12 @@ typedef struct #define LL_USART_CR2_LBDIE USART_CR2_LBDIE /*!< LIN break detection interrupt enable */ #define LL_USART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */ #define LL_USART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */ +#if defined(USART_CR1_UESM) +#define LL_USART_CR3_WUFIE USART_CR3_WUFIE /*!< Wakeup from Stop mode interrupt enable */ +#endif /* USART_CR1_UESM */ #if defined(USART_TCBGT_SUPPORT) #define LL_USART_CR3_TCBGTIE USART_CR3_TCBGTIE /*!< Transmission complete before guard time interrupt enable */ -#endif +#endif /* USART_TCBGT_SUPPORT */ /** * @} */ @@ -400,6 +405,18 @@ typedef struct * @} */ +#if defined(USART_CR1_UESM) +/** @defgroup USART_LL_EC_WAKEUP_ON Wakeup Activation + * @{ + */ +#define LL_USART_WAKEUP_ON_ADDRESS 0x00000000U /*!< Wake up active on address match */ +#define LL_USART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< Wake up active on Start bit detection */ +#define LL_USART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1) /*!< Wake up active on RXNE */ +/** + * @} + */ + +#endif /* USART_CR1_UESM */ /** @defgroup USART_LL_EC_IRDA_POWER IrDA Power * @{ */ @@ -480,7 +497,8 @@ typedef struct * @param __BAUDRATE__ Baud rate value to achieve * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case */ -#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) ((((__PERIPHCLK__)*2U) + ((__BAUDRATE__)/2U))/(__BAUDRATE__)) +#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) ((((__PERIPHCLK__)*2U)\ + + ((__BAUDRATE__)/2U))/(__BAUDRATE__)) /** * @brief Compute USARTDIV value according to Peripheral Clock and @@ -545,6 +563,87 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabled(USART_TypeDef *USARTx) return ((READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL); } +#if defined(USART_CR1_UESM) +/** + * @brief USART enabled in STOP Mode. + * @note When this function is enabled, USART is able to wake up the MCU from Stop mode, provided that + * USART clock selection is HSI or LSE in RCC. + * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the USARTx instance. + * @rmtoll CR1 UESM LL_USART_EnableInStopMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableInStopMode(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR1, USART_CR1_UESM); +} + +/** + * @brief USART disabled in STOP Mode. + * @note When this function is disabled, USART is not able to wake up the MCU from Stop mode + * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the USARTx instance. + * @rmtoll CR1 UESM LL_USART_DisableInStopMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableInStopMode(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR1, USART_CR1_UESM); +} + +/** + * @brief Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not) + * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the USARTx instance. + * @rmtoll CR1 UESM LL_USART_IsEnabledInStopMode + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL); +} + +#if defined(USART_CR3_UCESM) +/** + * @brief USART Clock enabled in STOP Mode + * @note When this function is called, USART Clock is enabled while in STOP mode + * @rmtoll CR3 UCESM LL_USART_EnableClockInStopMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableClockInStopMode(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_UCESM); +} + +/** + * @brief USART clock disabled in STOP Mode + * @note When this function is called, USART Clock is disabled while in STOP mode + * @rmtoll CR3 UCESM LL_USART_DisableClockInStopMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableClockInStopMode(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_UCESM); +} + +/** + * @brief Indicate if USART clock is enabled in STOP Mode + * @rmtoll CR3 UCESM LL_USART_IsClockEnabledInStopMode + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsClockEnabledInStopMode(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR3, USART_CR3_UCESM) == (USART_CR3_UCESM)); +} + +#endif /* USART_CR3_UCESM */ +#endif /* USART_CR1_UESM*/ /** * @brief Receiver Enable (Receiver is enabled and begins searching for a start bit) * @rmtoll CR1 RE LL_USART_EnableDirectionRx @@ -1461,6 +1560,41 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(USART_TypeDef *USARTx) return ((READ_BIT(USARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL); } +#if defined(USART_CR1_UESM) +/** + * @brief Select event type for Wake UP Interrupt Flag (WUS[1:0] bits) + * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the USARTx instance. + * @rmtoll CR3 WUS LL_USART_SetWKUPType + * @param USARTx USART Instance + * @param Type This parameter can be one of the following values: + * @arg @ref LL_USART_WAKEUP_ON_ADDRESS + * @arg @ref LL_USART_WAKEUP_ON_STARTBIT + * @arg @ref LL_USART_WAKEUP_ON_RXNE + * @retval None + */ +__STATIC_INLINE void LL_USART_SetWKUPType(USART_TypeDef *USARTx, uint32_t Type) +{ + MODIFY_REG(USARTx->CR3, USART_CR3_WUS, Type); +} + +/** + * @brief Return event type for Wake UP Interrupt Flag (WUS[1:0] bits) + * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the USARTx instance. + * @rmtoll CR3 WUS LL_USART_GetWKUPType + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_WAKEUP_ON_ADDRESS + * @arg @ref LL_USART_WAKEUP_ON_STARTBIT + * @arg @ref LL_USART_WAKEUP_ON_RXNE + */ +__STATIC_INLINE uint32_t LL_USART_GetWKUPType(USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_WUS)); +} + +#endif /* USART_CR1_UESM */ /** * @brief Configure USART BRR register for achieving expected Baud Rate value. * @note Compute and set USARTDIV value in BRR Register (full BRR content) @@ -1480,7 +1614,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(USART_TypeDef *USARTx) __STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling, uint32_t BaudRate) { - register uint32_t usartdiv; + uint32_t usartdiv; register uint32_t brrtemp; if (OverSampling == LL_USART_OVERSAMPLING_8) @@ -2161,7 +2295,8 @@ __STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx) { /* In Asynchronous mode, the following bits must be kept cleared: - LINEN, CLKEN bits in the USART_CR2 register, - - SCEN, IREN and HDSEL bits in the USART_CR3 register.*/ + - SCEN, IREN and HDSEL bits in the USART_CR3 register. + */ CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL)); } @@ -2197,7 +2332,8 @@ __STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx) { /* In Synchronous mode, the following bits must be kept cleared: - LINEN bit in the USART_CR2 register, - - SCEN, IREN and HDSEL bits in the USART_CR3 register.*/ + - SCEN, IREN and HDSEL bits in the USART_CR3 register. + */ CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN)); CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL)); /* set the UART/USART in Synchronous mode */ @@ -2237,7 +2373,8 @@ __STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx) { /* In LIN mode, the following bits must be kept cleared: - STOP and CLKEN bits in the USART_CR2 register, - - IREN, SCEN and HDSEL bits in the USART_CR3 register.*/ + - IREN, SCEN and HDSEL bits in the USART_CR3 register. + */ CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP)); CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL)); /* Set the UART/USART in LIN mode */ @@ -2275,7 +2412,8 @@ __STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx) { /* In Half Duplex mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - - SCEN and IREN bits in the USART_CR3 register.*/ + - SCEN and IREN bits in the USART_CR3 register. + */ CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN)); /* set the UART/USART in Half Duplex mode */ @@ -2315,7 +2453,8 @@ __STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx) { /* In Smartcard mode, the following bits must be kept cleared: - LINEN bit in the USART_CR2 register, - - IREN and HDSEL bits in the USART_CR3 register.*/ + - IREN and HDSEL bits in the USART_CR3 register. + */ CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN)); CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL)); /* Configure Stop bits to 1.5 bits */ @@ -2358,7 +2497,8 @@ __STATIC_INLINE void LL_USART_ConfigIrdaMode(USART_TypeDef *USARTx) { /* In IRDA mode, the following bits must be kept cleared: - LINEN, STOP and CLKEN bits in the USART_CR2 register, - - SCEN and HDSEL bits in the USART_CR3 register.*/ + - SCEN and HDSEL bits in the USART_CR3 register. + */ CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP)); CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL)); /* set the UART/USART in IRDA mode */ @@ -2396,7 +2536,8 @@ __STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx) { /* In Multi Processor mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - - IREN, SCEN and HDSEL bits in the USART_CR3 register.*/ + - IREN, SCEN and HDSEL bits in the USART_CR3 register. + */ CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); } @@ -2630,6 +2771,21 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(USART_TypeDef *USARTx) return ((READ_BIT(USARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL); } +#if defined(USART_CR1_UESM) +/** + * @brief Check if the USART Wake Up from stop mode Flag is set or not + * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the USARTx instance. + * @rmtoll ISR WUF LL_USART_IsActiveFlag_WKUP + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP(USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL); +} + +#endif /* USART_CR1_UESM */ /** * @brief Check if the USART Transmit Enable Acknowledge Flag is set or not * @rmtoll ISR TEACK LL_USART_IsActiveFlag_TEACK @@ -2641,6 +2797,19 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(USART_TypeDef *USARTx) return ((READ_BIT(USARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL); } +#if defined(USART_ISR_REACK) +/** + * @brief Check if the USART Receive Enable Acknowledge Flag is set or not + * @rmtoll ISR REACK LL_USART_IsActiveFlag_REACK + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL); +} + +#endif/* USART_ISR_REACK */ #if defined(USART_TCBGT_SUPPORT) /* Function available only on devices supporting Transmit Complete before Guard Time feature */ /** @@ -2653,8 +2822,8 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT(USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_TCBGT) == (USART_ISR_TCBGT)) ? 1UL : 0UL); } -#endif +#endif /* USART_TCBGT_SUPPORT */ /** * @brief Clear Parity Error Flag * @rmtoll ICR PECF LL_USART_ClearFlag_PE @@ -2733,7 +2902,7 @@ __STATIC_INLINE void LL_USART_ClearFlag_TCBGT(USART_TypeDef *USARTx) { WRITE_REG(USARTx->ICR, USART_ICR_TCBGTCF); } -#endif +#endif /* USART_TCBGT_SUPPORT */ /** * @brief Clear LIN Break Detection Flag @@ -2796,6 +2965,21 @@ __STATIC_INLINE void LL_USART_ClearFlag_CM(USART_TypeDef *USARTx) WRITE_REG(USARTx->ICR, USART_ICR_CMCF); } +#if defined(USART_CR1_UESM) +/** + * @brief Clear Wake Up from stop mode Flag + * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the USARTx instance. + * @rmtoll ICR WUCF LL_USART_ClearFlag_WKUP + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_WKUP(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_WUCF); +} + +#endif /* USART_CR1_UESM */ /** * @} */ @@ -2935,6 +3119,21 @@ __STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx) SET_BIT(USARTx->CR3, USART_CR3_CTSIE); } +#if defined(USART_CR1_UESM) +/** + * @brief Enable Wake Up from Stop Mode Interrupt + * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the USARTx instance. + * @rmtoll CR3 WUFIE LL_USART_EnableIT_WKUP + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_WKUP(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_WUFIE); +} + +#endif /* USART_CR1_UESM */ #if defined(USART_TCBGT_SUPPORT) /* Function available only on devices supporting Transmit Complete before Guard Time feature */ /** @@ -2949,7 +3148,7 @@ __STATIC_INLINE void LL_USART_EnableIT_TCBGT(USART_TypeDef *USARTx) { SET_BIT(USARTx->CR3, USART_CR3_TCBGTIE); } -#endif +#endif /* USART_TCBGT_SUPPORT */ /** * @brief Disable IDLE Interrupt @@ -3082,6 +3281,21 @@ __STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx) CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE); } +#if defined(USART_CR1_UESM) +/** + * @brief Disable Wake Up from Stop Mode Interrupt + * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the USARTx instance. + * @rmtoll CR3 WUFIE LL_USART_DisableIT_WKUP + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_WKUP(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_WUFIE); +} + +#endif /* USART_CR1_UESM */ #if defined(USART_TCBGT_SUPPORT) /* Function available only on devices supporting Transmit Complete before Guard Time feature */ /** @@ -3096,7 +3310,7 @@ __STATIC_INLINE void LL_USART_DisableIT_TCBGT(USART_TypeDef *USARTx) { CLEAR_BIT(USARTx->CR3, USART_CR3_TCBGTIE); } -#endif +#endif /* USART_TCBGT_SUPPORT */ /** * @brief Check if the USART IDLE Interrupt source is enabled or disabled. @@ -3225,6 +3439,21 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(USART_TypeDef *USARTx) return ((READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL); } +#if defined(USART_CR1_UESM) +/** + * @brief Check if the USART Wake Up from Stop Mode Interrupt is enabled or disabled. + * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the USARTx instance. + * @rmtoll CR3 WUFIE LL_USART_IsEnabledIT_WKUP + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP(USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL); +} + +#endif /* USART_CR1_UESM */ #if defined(USART_TCBGT_SUPPORT) /* Function available only on devices supporting Transmit Complete before Guard Time feature */ /** @@ -3239,7 +3468,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT(USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR3, USART_CR3_TCBGTIE) == (USART_CR3_TCBGTIE)) ? 1UL : 0UL); } -#endif +#endif /* USART_TCBGT_SUPPORT */ /** * @} @@ -3365,12 +3594,12 @@ __STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx, uint32_t if (Direction == LL_USART_DMA_REG_DATA_TRANSMIT) { /* return address of TDR register */ - data_reg_addr = (uint32_t) & (USARTx->TDR); + data_reg_addr = (uint32_t) &(USARTx->TDR); } else { /* return address of RDR register */ - data_reg_addr = (uint32_t) & (USARTx->RDR); + data_reg_addr = (uint32_t) &(USARTx->RDR); } return data_reg_addr; @@ -3392,7 +3621,7 @@ __STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx, uint32_t */ __STATIC_INLINE uint8_t LL_USART_ReceiveData8(USART_TypeDef *USARTx) { - return (uint8_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR)); + return (uint8_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR) & 0xFFU); } /** diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usb.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usb.h index d53f10ccc3..6d3769c88b 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usb.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usb.h @@ -155,7 +155,7 @@ typedef struct typedef struct { - uint8_t dev_addr ; /*!< USB device address. + uint8_t dev_addr; /*!< USB device address. This parameter must be a number between Min_Data = 1 and Max_Data = 255 */ uint8_t ch_num; /*!< Host channel number. @@ -199,10 +199,10 @@ typedef struct uint32_t ErrCnt; /*!< Host channel error count.*/ - USB_OTG_URBStateTypeDef urb_state; /*!< URB state. + USB_OTG_URBStateTypeDef urb_state; /*!< URB state. This parameter can be any value of @ref USB_OTG_URBStateTypeDef */ - USB_OTG_HCStateTypeDef state; /*!< Host Channel state. + USB_OTG_HCStateTypeDef state; /*!< Host Channel state. This parameter can be any value of @ref USB_OTG_HCStateTypeDef */ } USB_OTG_HCTypeDef; #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ @@ -234,6 +234,18 @@ typedef struct * @} */ +/** @defgroup USB_LL Device Speed + * @{ + */ +#define USBD_HS_SPEED 0U +#define USBD_HSINFS_SPEED 1U +#define USBH_HS_SPEED 0U +#define USBD_FS_SPEED 2U +#define USBH_FSLS_SPEED 1U +/** + * @} + */ + /** @defgroup USB_LL_Core_Speed USB Low Layer Core Speed * @{ */ @@ -252,7 +264,7 @@ typedef struct #define USB_OTG_HS_EMBEDDED_PHY 3U #if !defined (USB_HS_PHYC_TUNE_VALUE) -#define USB_HS_PHYC_TUNE_VALUE 0x00000F13U /*!< Value of USB HS PHY Tune */ +#define USB_HS_PHYC_TUNE_VALUE 0x00000F13U /*!< Value of USB HS PHY Tune */ #endif /* USB_HS_PHYC_TUNE_VALUE */ /** * @} @@ -262,11 +274,11 @@ typedef struct * @{ */ #ifndef USBD_HS_TRDT_VALUE -#define USBD_HS_TRDT_VALUE 9U +#define USBD_HS_TRDT_VALUE 9U #endif /* USBD_HS_TRDT_VALUE */ #ifndef USBD_FS_TRDT_VALUE -#define USBD_FS_TRDT_VALUE 5U -#define USBD_DEFAULT_TRDT_VALUE 9U +#define USBD_FS_TRDT_VALUE 5U +#define USBD_DEFAULT_TRDT_VALUE 9U #endif /* USBD_HS_TRDT_VALUE */ /** * @} @@ -275,9 +287,9 @@ typedef struct /** @defgroup USB_LL_Core_MPS USB Low Layer Core MPS * @{ */ -#define USB_OTG_HS_MAX_PACKET_SIZE 512U -#define USB_OTG_FS_MAX_PACKET_SIZE 64U -#define USB_OTG_MAX_EP0_SIZE 64U +#define USB_OTG_HS_MAX_PACKET_SIZE 512U +#define USB_OTG_FS_MAX_PACKET_SIZE 64U +#define USB_OTG_MAX_EP0_SIZE 64U /** * @} */ @@ -287,7 +299,6 @@ typedef struct */ #define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ (0U << 1) #define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ (1U << 1) -#define DSTS_ENUMSPD_LS_PHY_6MHZ (2U << 1) #define DSTS_ENUMSPD_FS_PHY_48MHZ (3U << 1) /** * @} @@ -397,7 +408,7 @@ typedef struct #define USBPHYC ((USBPHYC_GlobalTypeDef *)((uint32_t )USB_PHY_HS_CONTROLLER_BASE)) #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ -#define EP_ADDR_MSK 0xFU +#define EP_ADDR_MSK 0xFU /** * @} */ @@ -462,13 +473,9 @@ HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx); HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state); uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef *USBx); uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, - uint8_t ch_num, - uint8_t epnum, - uint8_t dev_address, - uint8_t speed, - uint8_t ep_type, - uint16_t mps); +HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, + uint8_t epnum, uint8_t dev_address, uint8_t speed, + uint8_t ep_type, uint16_t mps); HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma); uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx); HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num); diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_wwdg.h b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_wwdg.h index 620a524374..16616303da 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_wwdg.h +++ b/system/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_wwdg.h @@ -58,8 +58,8 @@ extern "C" { */ /** @defgroup WWDG_LL_EC_PRESCALER PRESCALER -* @{ -*/ + * @{ + */ #define LL_WWDG_PRESCALER_1 0x00000000u /*!< WWDG counter clock = (PCLK1/4096)/1 */ #define LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */ #define LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */ @@ -175,7 +175,7 @@ __STATIC_INLINE uint32_t LL_WWDG_GetCounter(WWDG_TypeDef *WWDGx) * @arg @ref LL_WWDG_PRESCALER_2 * @arg @ref LL_WWDG_PRESCALER_4 * @arg @ref LL_WWDG_PRESCALER_8 -* @retval None + * @retval None */ __STATIC_INLINE void LL_WWDG_SetPrescaler(WWDG_TypeDef *WWDGx, uint32_t Prescaler) { @@ -314,6 +314,6 @@ __STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(WWDG_TypeDef *WWDGx) } #endif -#endif /* __STM32F7xx_LL_WWDG_H */ +#endif /* STM32F7xx_LL_WWDG_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Release_Notes.html b/system/Drivers/STM32F7xx_HAL_Driver/Release_Notes.html index 8835d889c2..2608ed26ec 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Release_Notes.html +++ b/system/Drivers/STM32F7xx_HAL_Driver/Release_Notes.html @@ -652,7 +652,8 @@ {margin-bottom:0in;} --> - + +

     

    @@ -673,7 +674,7 @@

    Copyright 2017 STMicroelectronics

    -

    +
    -

    Update History -

    V1.2.7/ 08-February-2019

    +

    Update History +

    V1.2.8/ 13-February-2020

    +

    Main Changes

    +
    • General updates to fix known defects and enhancements implementation
    • HAL/LL GPIO update
      • Update GPIO + initialization sequence to avoid unwanted pulse on GPIO Pin's
    • HAL I2C update
      • Update + HAL_I2C_EV_IRQHandler() API to fix I2C send break issue 
        • Add + additional check on hi2c->hdmatx, + hdmatx->XferCpltCallback, hi2c->hdmarx, + hdmarx->XferCpltCallback in I2C_Master_SB() API to + avoid enabling DMA request when IT mode is used.
      • Update + HAL_I2C_ER_IRQHandler() API to fix acknowledge failure issue with + I2C memory IT processes
        •  Add stop + condition generation when NACK occurs.
      • Update HAL_I2C_Init() + API to force software reset before setting new I2C configuration
      • Update + HAL I2C processes to report ErrorCode when wrong I2C start condition + occurs
        •  Add + new ErrorCode define: HAL_I2C_WRONG_START
        •  Set ErrorCode + parameter in I2C handle to HAL_I2C_WRONG_START
      • Update I2C_DMAXferCplt(), + I2C_DMAError() and I2C_DMAAbort() APIs to fix hardfault issue when hdmatx + and hdmarx parameters in i2c handle aren't initialized (NULL pointer).
        • Add + additional check on hi2c->hdmtx and hi2c->hdmarx before + resetting DMA Tx/Rx complete callback
    + +
    • HAL ADC Update
      • Add "ADC_INTERNAL_NONE" channel to disable the VBAT & TSVREFE channel.
    • HAL DCMI update
      • Add DCMI_SyncUnmaskTypeDef structure and HAL_DCMI_ConfigSyncUnmask() API to manage embedded synchronization delimiters unmasks
    • HAL EXTI update
      • General update to enhance HAL EXTI driver robustness 
        • Add additional assert check on EXTI config lines
        • Update to compute EXTI line mask before read/write access to EXTI registers
      • Update EXTI callbacks management to be compliant with reference manual: only one PR register for rising and falling interrupts.
        • Update +parameters in EXTI_HandleTypeDef structure: merge HAL EXTI +RisingCallback and FallingCallback in only one PendingCallback.
        • Remove HAL_EXTI_RISING_CB_ID and HAL_EXTI_FALLING_CB_ID values from EXTI_CallbackIDTypeDef enumeration.
      • Update HAL_EXTI_IRQHandler() API to serve interrupts correctly.
        • Update to compute EXTI line mask before handle EXTI interrupt.
      • Update to support GPIO port interrupts:
        • Add new "GPIOSel" parameter in EXTI_ConfigTypeDef structure
    • HAL HASH update
      • Null pointer on handler "hhash" is now checked before accessing structure member "hhash->Init.DataType" in the following API:
        • HAL_HASH_Init()
      • Following interrupt-based +APIs have been added. Interrupt mode could allow the MCU to enter +"Sleep" mode while a data block is being processed. Please refer to the +"##### How to use this driver #####" section for details about their +use.
        • HAL_HASH_SHA1_Accmlt_IT()
        • HAL_HASH_MD5_Accmlt_IT()
        • HAL_HASHEx_SHA224_Accmlt_IT()
        • HAL_HASHEx_SHA256_Accmlt_IT()
      • Following aliases have been added (just for clarity sake) as they shall be used at the end of the computation of a multi-buffers message and not at the start:
        • HAL_HASH_SHA1_Accmlt_End() to be used instead of HAL_HASH_SHA1_Start()
        • HAL_HASH_MD5_Accmlt_End() to be used instead of HAL_HASH_MD5_Start()
        • HAL_HASH_SHA1_Accmlt_End_IT() to be used instead of HAL_HASH_SHA1_Start_IT()
        • HAL_HASH_MD5_Accmlt_End_IT() to be used instead of HAL_HASH_MD5_Start_IT()
        • HAL_HASHEx_SHA224_Accmlt_End() to be used instead of HAL_HASHEx_SHA224_Start()
        • HAL_HASHEx_SHA256_Accmlt_End() to be used instead of HAL_HASHEx_SHA256_Start()
        • HAL_HASHEx_SHA224_Accmlt_End_IT() to be used instead of HAL_HASHEx_SHA224_Start_IT()
        • HAL_HASHEx_SHA256_Accmlt_End_IT() to be used instead of HAL_HASHEx_SHA256_Start_IT()
      • MISRAC-2012 +rule R.5.1 (identifiers shall be distinct in the first 31 characters) +constrained the naming of the above listed aliases (e.g. +HAL_HASHEx_SHA256_Accmlt_End() could not be named HAL_HASHEx_SHA256_Accumulate_End(). Otherwise the name would have conflicted with HAL_HASHEx_SHA256_Accumulate_End_IT()). In order to have aligned names following APIs have been renamed:
        • HAL_HASH_MD5_Accumulate() renamed HAL_HASH_MD5_Accmlt()
        • HAL_HASH_SHA1_Accumulate() renamed HAL_HASH_SHA1_Accmlt()
        • HAL_HASHEx_SHA224_Accumulate() renamed HAL_HASHEx_SHA224_Accmlt()
        • HAL_HASHEx_SHA256_Accumulate() renamed HAL_HASHEx_SHA256_Accmlt()
      • HASH handler state is no more reset to HAL_HASH_STATE_READY once DMA has been started in the following APIs:
        • HAL_HASH_MD5_Start_DMA()
        • HAL_HMAC_MD5_Start_DMA()
        • HAL_HASH_SHA1_Start_DMA()
        • HAL_HMAC_SHA1_Start_DMA()
      • HASH phase state is now set to HAL_HASH_PHASE_READY once the digest has been read in the following APIs:
        • HASH_IT()
        • HMAC_Processing()
        • HASH_Start()
        • HASH_Finish()
      • Case of a large buffer scattered around in memory each piece of which is not necessarily a multiple of 4 bytes in length.
        • In +section "##### How to use this driver #####", sub-section "*** Remarks +on message length ***" added to provide recommendations to follow in +such case.
        • No modification of the driver as the root-cause is at design-level.
    • HAL SDMMC update
      • Fix typo in "FileFormatGroup" parameter in the HAL_MMC_CardCSDTypeDef and HAL_SD_CardCSDTypeDef structures.
      • Fix an improve handle state and error management
      • Rename the defined MMC card capacity type to be more meaningful:
        • Update MMC_HIGH_VOLTAGE_CARD to MMC LOW_CAPACITY_CARD
        • Update MMC_DUAL_VOLTAGE_CRAD to MMC_HIGH_CAPACITY_CARD
    • HAL QSPI update
      • Remove Lock mechanism from HAL_QSPI_Init() and HAL_QSPI_DeInit() APIs
    • HAL LPTIM update
      • Add a polling mechanism to check on LPTIM_FLAG_XXOK flags in different API 
        • Add LPTIM_WaitForFlag() API to wait for flag set.
        • Perform new checks on HAL_LPTIM_STATE_TIMEOUT.
      • Workaround to fix MCU slack in sleep mode
        • Update __HAL_LPTIM_DISABLE () macro used to disable LPTIM HW instance
          • Remove the LPTIM_CR_ENABLE bit clear.
          • Add a new API  LPTIM_Disable() defined in  hal_lptim.c
      • Update __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) macro by adding a specific .... when using callback register
      • __HAL_LPTIM_ENABLE
      • Remove usseless check on LPTIM2 in the LL driver since F7 support only one instance of LPTIM.
      • Update the  LL_LPTIM_DISABLE() API used to disable LPTIM HW instance
        • Move API definition to ll_lptim.c
    • HAL TIM update
      • Add new macros to enable and disable the fast mode when using the one pulse mode to output a waveform with a minimum delay
        • __HAL_TIM_ENABLE_OCxFAST() and __HAL_TIM_DISABLE_OCxFAST().
      • Update Encoder interface mode to keep TIM_CCER_CCxNP bits low
        • Add TIM_ENCODERINPUTPOLARITY_RISING and TIM_ENCODERINPUTPOLARITY_FALLING definitions to determine encoder input polarity.
        • Add IS_TIM_ENCODERINPUT_POLARITY() macro to check the encoder input polarity.
        • Update HAL_TIM_Encoder_Init() API 
          • Replace IS_TIM_IC_POLARITY() macro by IS_TIM_ENCODERINPUT_POLARITY() macro.
      • Correct wrong + instance parameter check in encoder mode
        • Replace + IS_TIM_CC2_INSTANCE by IS_TIM_ENCODER_INTERFACE_INSTANCE in encoder + interface : 
          • HAL_TIM_Encoder_Start()
          • HAL_TIM_Encoder_Stop()
          • HAL_TIM_Encoder_Start_IT()
          • HAL_TIM_Encoder_Stop_IT()
        • Replace + IS_TIM_DMA_CC_INSTANCE by IS_TIM_ENCODER_INTERFACE_INSTANCE in encoder + interface in DMA mode : 
          • HAL_TIM_Encoder_Start_DMA()
          • HAL_TIM_Encoder_Stop_DMA()
    + +
      • Update + HAL_TIMEx_MasterConfigSynchronization() API to avoid functional errors + and assert fails when using some TIM instances as input trigger.
        • Replace IS_TIM_SYNCHRO_INSTANCE() + macro by IS_TIM_MASTER_INSTANCE() macro. 
        • Add IS_TIM_SLAVE_INSTANCE() + macro to check on TIM_SMCR_MSM bit.
      • Provide new + API to set and clear UIFREMAP
        • Add new + definition for TIM Update Interrupt Flag Remap
          • TIM_UIFREMAP_DISABLE
          • TIM_UIFREMAP_ENABLE
        • Add new macro + in HAL driver to enable and desable the  Update Interrupt Flag + Remap
          •  __HAL_TIM_UIFREMAP_ENABLE()
          • __HAL_TIM_UIFREMAP_DISABLE()/__HAL_TIM_GET_UIFCPY + macro
        • Add new + mecanism to check whether the update interrupt flag (UIF) copy is + set or not 
          • Add the + __HAL_TIM_GET_UIFCPY() macro in the HAL driver
          • Add + LL_TIM_IsActiveUIFCPY() API in the LL driver
        • Add new macro + to check on the Update Interrupt Flag Remap mode
          • IS_TIM_UIFREMAP_MODE()
      • Remove usseless + define in the LL driver 
        • TIMx_AF1_BKINE + / TIMx_AF1_BKDFBKE /  TIMx_AF2_BK2INE /  TIMx_AF2_BK2DFBKE / +  TIMx_AF2_BK2INP
    • HAL SMARTCARD update
      • Update SMARTCARD_SetConfig() API.
        • Split HAL_RCC_GetPCLK1Freq() and +HAL_RCC_GetPCLK2Freq() macros from the BRR calculation.
    • HAL IRDA update
      • Update IRDA_SetConfig() API 
        • Split HAL_RCC_GetPCLK1Freq() and +HAL_RCC_GetPCLK2Freq() macros from the IRDA_DIV_SAMPLING16() macro.
      • Update some API desciption
        • HAL_IRDA_Transmit() / HAL_IRDA_Transmit_IT()
        • HAL_IRDA_Receive() / HAL_IRDA_Receive_IT()
        • HAL_IRDA_Transmit_DMA() / HAL_IRDA_Receive_DMA()
    • HAL RCC update
      • Update the HAL_RCC_ClockConfig() and HAL_RCC_DeInit() API to don't overwrite the custom tick priority
      • Update HAL_RCC_OscConfig() API to don't return HAL_ERROR if request repeats the current PLL configuration
    • HAL/LL USART update
      • Add support to the Receiver Timeout Interrupt in the +HAL_USART_IRQHandler
      • Update some API desciption 
        • + +

          HAL_USART_Transmit() / HAL_USART_Transmit_IT() 

        • + + + +

          HAL_USART_Receive() / HAL_USART_Receive_IT() 

        • + +

          HAL_USART_TransmitReceive() / HAL_USART_TransmitReceive_IT() 

        • HAL_USART_Transmit_DMA() / HAL_USART_Receive_DMA() / HAL_USART_TransmitReceive_DMA()

      • Update USART_SetConfig() API 
      • Split HAL_RCC_GetPCLK1Freq() and +HAL_RCC_GetPCLK2Freq() macros from the USART_DIV_SAMPLING8() macro
      • Support Stop Mode functionalities in the USART +driver  
      • Add  definition of USART_ISR_REACK USART,  +receive enable acknowledge flag in the HAL driver
      • Add new flag definition in the LL driver 
        • + + + +

          LL_USART_ICR_WUCF  Wakeup from Stop mode flag 

        • + +

          LL_USART_ISR_WUF Wakeup from Stop mode flag 

        • + +

          LL_USART_ISR_REACK Receive enable acknowledge flag 

        • LL_USART_CR3_WUFIE Wakeup from Stop mode interrupt enable

      • Add new definition of the different event which +activates the wakeup from Stop mode flag
        • LL_ USART_WAKEUP_ON_ADDRESS
        • + +

          LL_USART_WAKEUP_ON_STARTBIT

        • + +

          LL_USART_WAKEUP_ON_RXNE

      • + +

        Add new API in LL driver to support stop mode

        • + + + +

          LL_USART_EnableInStopMode() to enable the USART in stop mode

        • + +

          LL_USART_DisableInStopMode() to disable the USART in stop mode

        • + +

          LL_USART_IsEnabledInStopMode() to check if the USART is enabled or not +in the stop mode

        • + +

          LL_USART_EnableClockInStopMode() to enable the USART clock in the stop +mode

        • + +

          LL_USART_DisableClockInStopMode() to disable the USART clock in the stop +mode

        • LL_USART_IsClockEnabledInStopMode() to check whether USART clock are +enabled or not in the stop mode

      • + +

        Add new API in LL driver to manage event relisted to Wake UP Interrupt +Flag

        • + + + +

          LL_USART_SetWKUPType() to select the event type for Wake UP Interrupt +Flag

        • + +

          LL_USART_GetWKUPType() to get  the event type for Wake UP Interrupt +Flag

        • + +

          LL_USART_IsActiveFlag_WKUP() to Check if the USART Wake Up from stop +mode Flag is set or not

        • + +

          LL_USART_IsActiveFlag_REACK() to Check if the USART Receive Enable +Acknowledge Flag is set or not

        • LL_USART_ClearFlag_WKUP() Clear Wake Up from stop mode Flag

      • + +

        Add new API in LL driver to manage wake up from stop interruption

        • + + + +

          LL_USART_EnableIT_WKUP() to Enable Wake Up from Stop Mode Interrupt

        • + +

          LL_USART_DisableIT_WKUP() to Disable Wake Up from Stop Mode Interrupt

        • LL_USART_IsEnabledIT_WKUP() to Check if the USART Wake Up from Stop Mode +Interrupt is enabled or not

    • HAL/LL USB update
      •  Add handling USB host babble error interrupt
      •  Fix Enabling ULPI interface for platforms that integrates USB HS PHY
      •  Fix Host data toggling for IN Iso transfers
      •  Ensure to disable USB EP during endpoint deactivation
    +

    V1.2.7/ 08-February-2019

    Main Changes

    • General updates to fix known defects and enhancements implementation
      • @@ -875,11 +1006,11 @@

      -

      V1.2.6 / 29-June-2018

      Main Changes

      • Update to support STM32F730xx and STM32F750xx value lines
      • HAL DMA update
        • DMA_CHANNEL_8 to DMA_CHANNEL_15 are also defined in case of STM32F730xx (same features as STM32F733xx line)
      • HAL FLASH update
        • Add support of STM32F730xx with 4 FLash sectors of 16KB each.
        • Add support of STM32F750xx with 2 FLash sectors of 32KB each.
      • HAL GPIO update
        • Add support of STM32F730xx value line : same features as STM32F733xx line
        • Add support of STM32F750xx value line : same features as STM32F756xx line
      • HAL RCC update
        • Add support of STM32F730xx value line : same features as STM32F733xx line
        • Add support of STM32F750xx value line : same features as STM32F756xx line

      V1.2.5 / 02-February-2018

      +

      V1.2.6 / 29-June-2018

      Main Changes

      • Update to support STM32F730xx and STM32F750xx value lines
      • HAL DMA update
        • DMA_CHANNEL_8 to DMA_CHANNEL_15 are also defined in case of STM32F730xx (same features as STM32F733xx line)
      • HAL FLASH update
        • Add support of STM32F730xx with 4 FLash sectors of 16KB each.
        • Add support of STM32F750xx with 2 FLash sectors of 32KB each.
      • HAL GPIO update
        • Add support of STM32F730xx value line : same features as STM32F733xx line
        • Add support of STM32F750xx value line : same features as STM32F756xx line
      • HAL RCC update
        • Add support of STM32F730xx value line : same features as STM32F733xx line
        • Add support of STM32F750xx value line : same features as STM32F756xx line

      V1.2.5 / 02-February-2018

      Main Changes

      • General updates to fix known defects and enhancements implementation
      • HAL update
        • Add new macro to get variable aligned on 32-bytes, required for cache maintenance purpose
        • Update UNUSED() macro implementation to avoid GCC warning
          • The warning is detected when the UNUSED() macro is called from C++ file
      • HAL SAI update
        • Update HAL_SAI_DMAStop() and HAL_SAI_Abort() process to fix the lock/unlock audio issue
      • HAL PWR update
        • Update HAL_PWR_EnterSLEEPMode() and HAL_PWR_EnterSTOPMode() APIs to ensure -that all instructions finished before entering STOP mode.
      • HAL HCD update
        • Add new callback to be used to handle usb device connection/disconnection
          • HAL_HCD_PortEnabled_Callback()
          • HAL_HCD_PortDisabled_Callback()
        • Update to prevent reactivate host interrrupt channel

      V1.2.4 / 22-December-2017

      +that all instructions finished before entering STOP mode.
  • HAL HCD update
    • Add new callback to be used to handle usb device connection/disconnection
      • HAL_HCD_PortEnabled_Callback()
      • HAL_HCD_PortDisabled_Callback()
    • Update to prevent reactivate host interrrupt channel

    V1.2.4 / 22-December-2017

    Main Changes

    • General updates to fix known defects and enhancements implementation
    • The following changes done on the HAL drivers require an update on the application code based on older HAL versions
      • Rework of HAL CAN driver (compatibility break) 
        • A new HAL CAN driver has been redesigned with new APIs, to bypass @@ -917,14 +1048,14 @@

        • Add checks for HSI, PLL and PLLI2S  ready before modifying RCC CFGR registers
        • Clear all interrupt flags
        • Initialize systick interrupt period
  • HAL DMA update
    • Add clean of callbacks in HAL_DMA_DeInit() API
    • Fix wrong DMA_FLAG_FEIFO_4 and DMA_FLAGDMAEIFO_4 defines values 
  • HAL I2C update
    • Update Interface APIs headers to remove confusing message about device address
    • Update I2C_WaitOnRXNEFlagUntilTimeout() to resolve a race condition between STOPF and RXNE Flags
    • Update I2C_TransferConfig() to fix wrong bit management
  • LL USART update
    • Add assert macros to check USART BaudRate register
  • HAL ETH update
    • Do{..} While(0) insured in multi statement macros :
      • __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() 
      • __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER()
  • HAL FLASH update
    • HAL_FLASH_Unlock() update to return state error when the FLASH is already unlocked
  • HAL GPIO update
    • Add missing define of GPIO_PIN_2 in GPIOK_PIN_AVAILABLE list
  • HAL PCD update
    • Do{..} While(0)  insured in multi statement macros
  • LL UTILS update
    • stm32f7xx_ll_utils.h : Update LL_GetPackageType command to return uint32_t instead of uint16_t
  • HAL TIM update
    • stm32f7xx_hal_tim_ex.c : Update HAL_TIMEx_ConfigBreakDeadTime API to avoid to block timer behavior when
      remains in the state HAL_TIM_STATE_BUSY.
    •  stm32f7xx_hal_tim.h : 
      • Fix __HAL_TIM_SET_PRESCALER() macro
      • Fix typos in some exported macros description 
  • LL FMC update
    • HAL_SDRAM_SendCommand() API: Remove the timeout check
  • HAL NAND update
    • Fix wrong check for NAND status
    -

    V1.2.3 / 25-August-2017

    +

    V1.2.3 / 25-August-2017

    Main Changes

    • General updates to fix known defects and enhancements implementation
    • Remove Date and Version from header files
    • Update HAL drivers to refer to the new CMSIS bit position defines instead of usage the POSITION_VAL() macro
    • HAL CAN update
      • Add missing unlock in HAL_CAN_Receive_IT() process
    • HAL DCMI update
      • HAL DCMI driver clean-up: remove non referenced callback APIs: HAL_DCMI_VsyncCallback() and HAL_DCMI_HsyncCallback()
    • HAL DFSDM update
      • Fix cast issue on APIs that return signed integer value (uint32_t) 
    • HAL DMA update
      • HAL DMA driver clean-up: remove non referenced callback APIs: HAL_DMA_CleanCallbacks()
    • HAL FLASH update
      • FLASH_Program_DoubleWord() API: Replace 64-bit accesses with 2 double words operations
    • HAL Generic update
      • Update assert_param() macro definition to be in line with stm32_ll_utils.c driver
    • HAL GPIO update
      • GPIOK_PIN_AVAILABLE() assert macro update to allow possibility to configure GPIO_PIN_2
    • HAL LTDC update
      • Rename HAL_LTDC_LineEvenCallback() API to HAL_LTDC_LineEventCallback()
    • HAL PCD update
      • Update HAL_PCD_IRQHandler() API to fix transfer issues when USB HS is used with DMA enabled
    • HAL RCC update
      • Update HAL_RCC_GetOscConfig() API to:
        • set PLLR in the RCC_OscInitStruct
        • check on null pointer
      • Update HAL_RCC_ClockConfig() API to:
        • check on null pointer
        • optimize code size by updating the handling method of the SWS bits
        • update to use  __HAL_FLASH_GET_LATENCY() flash macro instead of using direct register access to LATENCY bits in FLASH ACR register.
    • HAL SAI update
      • Update HAL_SAI_DMAStop() API to flush fifo after disabling SAI
    • HAL TIM update
      • Update HAL_TIMEx_ConfigBreakInput() API to support BKINP/BKIN2P polarity bits.
    • LL DMA update
      • Update SET_BIT() access to LIFCR and HIFCR registers by WRITE_REG() to avoid -read access that is not allowed when clearing DMA flags
    • LL I2C update
      • Update LL_I2C_Init() API to avoid enabling own address1 when OwnAddress1 parameter value in the I2C_InitStruct is equal to 0.
    • LL TIM update
      • Update LL_TIM_EnableUpdateEvent() API to clear UDIS bit in CR1 register instead of setting it.
      • Update LL_TIM_DisableUpdateEvent() API to set UDIS bit in CR1 register instead of clearing it.
    • LL USB update
      • Update USB_EP0StartXfer() API to fix transfer issues when USB HS is used with DMA enabled

    V1.2.2 / 14-April-2017

    +read access that is not allowed when clearing DMA flags
  • LL I2C update
    • Update LL_I2C_Init() API to avoid enabling own address1 when OwnAddress1 parameter value in the I2C_InitStruct is equal to 0.
  • LL TIM update
    • Update LL_TIM_EnableUpdateEvent() API to clear UDIS bit in CR1 register instead of setting it.
    • Update LL_TIM_DisableUpdateEvent() API to set UDIS bit in CR1 register instead of clearing it.
  • LL USB update
    • Update USB_EP0StartXfer() API to fix transfer issues when USB HS is used with DMA enabled

    V1.2.2 / 14-April-2017

    Main Changes

    • General updates to fix known defects and enhancements implementation
    • HAL CAN update
      • Add @@ -933,12 +1064,12 @@

        Fix message lost issue with specific sequence of transmit requests.

      • Handle transmission failure with error callback, when NART is enabled.
      • Add __HAL_CAN_CANCEL_TRANSMIT() call to abort transmission when - timeout is reached

    V1.2.1 / 24-March-2017

    + timeout is reached

    V1.2.1 / 24-March-2017

    Main Changes

    • Update CHM UserManuals to support LL drivers
    • General updates to fix known defects and enhancements implementation
    • HAL DMA update
      • Update HAL_DMA_Init() function to adjust the compatibility check between FIFO threshold and burst configuration
    • HAL MMC update
      • Update HAL_MMC_InitCard() function with proper initialization sequence adding a delay after MMC clock enable
      • Update MMC_DMAError() function ignore DMA FIFO error as not impacting the data transfer
    • HAL SD update
      • Update HAL_SD_InitCard() function with proper initialization sequence adding a delay after SD clock enable
      • Update SD_DMAError() function ignore DMA FIFO error as not impacting the data transfer
    • HAL NAND update
      • Update HAL_NAND_Address_Inc() function implementation for proper plane number check
    • LL SDMMC update
      • Update SDMMC_DATATIMEOUT value with appropriate value needed by reading and writing operations of SD and MMC cards
    • LL RTC update
      • LL_RTC_TIME_Get() and LL_RTC_DATE_Get() inline macros optimization
    • LL ADC update
      • Fix wrong ADC group injected sequence configuration
        • LL_ADC_INJ_SetSequencerRanks() and LL_ADC_INJ_GetSequencerRanks() API's update to take in -consideration the ADC number of conversions
        • Update the defined values for ADC group injected seqencer ranks 

    V1.2.0 / 30-December-2016

    +consideration the ADC number of conversions
  • Update the defined values for ADC group injected seqencer ranks 

    • V1.2.0 / 30-December-2016

    Main Changes

    • Official release to add the support of STM32F722xx, STM32F723xx, STM32F732xx and STM32F733xx devices
    • Add Low Layer drivers allowing performance and footprint optimization
      • Low Layer drivers APIs provide register level programming: require deep @@ -948,9 +1079,9 @@

        Low Layer drivers APIs are implemented as static inline function in new Inc/stm32f7xx_ll_ppp.h files for PPP peripherals, there is no configuration file and each stm32f7xx_ll_ppp.h file must be included in user code.

    • General updates to fix known defects and enhancements implementation
    • Add new HAL MMC and SMBUS drivers
    • HAL Cortex update
      • Move HAL_MPU_Disable() and HAL_MPU_Enable() from stm32f7xx_hal_cortex.h to stm32f7xx_hal_cortex.c
      • Clear the whole MPU control register in HAL_MPU_Disable() API
    • HAL CRYP update
      • Add support of AES
    • HAL DMA update
      • Add a check on DMA stream instance in HAL_DMA_DeInit() API
    • HAL ETH update 
      • Fix wrong definitions in driver header file stm32f7_hal_eth.h
    • HAL FLASH update
      • Support OTP program operation
      • Add the support of PCROP feature
      • Update the clearing of error flags
    • HAL I2C update
      • Align driver source code with other STM32 families
    • HAL JPEG update 
      • Update the output data management when HAL_JPEG_Pause() is performed during the last data sending
    • HAL RCC update
      • Enable PWR only if necessary for LSE configuration in HAL_RCC_OscConfig() API
      • Rename RCC_LPTIM1CLKSOURCE_PCLK define to RCC_LPTIM1CLKSOURCE_PCLK1
      • Rename RCC_DFSDM1CLKSOURCE_PCLK define to RCC_DFSDM1CLKSOURCE_PCLK2
    • HAL SPI update
      • Clear RX FIFO at the end of each transaction
    • HAL UART update
      • Remove USART_CR2_LINEN bit clearing when initializing in synchronous mode
    • HAL USB update
      • Add support of embedded USB PHY Controller
      • Add support of Battery Charging Detector (BCD) feature
    • LL SDMMC update
      • Add new SDMMC_CmdSDEraseStartAdd, SDMMC_CmdSDEraseEndAdd, SDMMC_CmdOpCondition and SDMMC_CmdSwitch functions
    • LL USB update
      • Update PENA bit clearing in OTG_HPRT0 register
    • The following changes done on the HAL drivers require an update on the -application code based on older HAL versions
      • HAL SD update
        • Overall rework of the driver for a more efficient implementation
          • Modify initialization API and structures
          • Modify Read / Write sequences: separate transfer process and SD Cards state management 
          • Adding interrupt mode for Read / Write operations
          • Update the HAL_SD_IRQHandler function by optimizing the management of interrupt errors
        • Refer to the following example to identify the changes: BSP example and USB_Device/MSC_Standalone application
      • HAL TIM update
        • Add new AutoReloadPreload field in TIM_Base_InitTypeDef structure
        • Refer to the TIM examples to identify the changes 
      • HAL NAND update
        • Modify NAND_AddressTypeDef, NAND_DeviceConfigTypeDef and NAND_HandleTypeDef structures fields
        • Add new HAL_NAND_ConfigDevice API

    V1.1.1 / 01-July-2016

    +application code based on older HAL versions
    • HAL SD update
      • Overall rework of the driver for a more efficient implementation
        • Modify initialization API and structures
        • Modify Read / Write sequences: separate transfer process and SD Cards state management 
        • Adding interrupt mode for Read / Write operations
        • Update the HAL_SD_IRQHandler function by optimizing the management of interrupt errors
      • Refer to the following example to identify the changes: BSP example and USB_Device/MSC_Standalone application
    • HAL TIM update
      • Add new AutoReloadPreload field in TIM_Base_InitTypeDef structure
      • Refer to the TIM examples to identify the changes 
    • HAL NAND update
      • Modify NAND_AddressTypeDef, NAND_DeviceConfigTypeDef and NAND_HandleTypeDef structures fields
      • Add new HAL_NAND_ConfigDevice API

    V1.1.1 / 01-July-2016

    Main -Changes

    • HAL DMA update 
      • Update HAL_DMA_PollForTransfer() function implementation to avoid early TIMEOUT error.
    • HAL JPEG update
      • Update HAL_JPEG_ConfigEncoding() function to properly set the ImageHeight and ImageWidth
    • HAL SPI update
      • Update SPI_DMATransmitReceiveCplt() function to properly handle the CRC and avoid conditional statement duplication

    V1.1.0 / 22-April-2016

    +Changes

    • HAL DMA update 
      • Update HAL_DMA_PollForTransfer() function implementation to avoid early TIMEOUT error.
    • HAL JPEG update
      • Update HAL_JPEG_ConfigEncoding() function to properly set the ImageHeight and ImageWidth
    • HAL SPI update
      • Update SPI_DMATransmitReceiveCplt() function to properly handle the CRC and avoid conditional statement duplication

    V1.1.0 / 22-April-2016

    Main Changes

    • Official release to add the support of STM32F765xx, STM32F767xx, STM32F768xx, STM32F769xx, STM32F777xx, STM32F778xx and STM32F779xx devices
    • General updates to fix known defects and enhancements implementation
    • Add new HAL drivers for DFSDM, DSI, JPEG and MDIOS peripherals
    • Enhance HAL delay and timebase implementation
      • Add new @@ -1150,12 +1281,12 @@

      • Add the management of SPI peripheral errors during DMA process. This requires the following updates in the user application:
        • Configure and enable the SPI IRQ in HAL_SPI_MspInit() function
        • In stm32f7xx_it.c file, SPI_IRQHandler() function: add a call to HAL_SPI_IRQHandler() function
        • Add and customize the Error Callback API: HAL_SPI_ErrorCallback()
        • Refer to the following example which describe the changes: SPI_FullDuplex_ComDMA

  • HAL TIM update 
    • Update HAL_TIM_ConfigOCrefClear() function for proper configuration of the SMCR register
    • Add new function HAL_TIMEx_ConfigBreakInput() to configure the break input source
  • HAL UART, USART, SMARTCARD and IRDA (referenced as PPP here below) update -
    • Update Polling management:
      • The user Timeout value must be estimated for the overall process duration: the Timeout measurement is cumulative
    • Update DMA process:
      • Update the management of PPP peripheral errors during DMA process. This requires the following updates in user application:
        • Configure and enable the PPP IRQ in HAL_PPP_MspInit() function
        • In stm32f7xx_it.c file, PPP_IRQHandler() function: add a call to HAL_PPP_IRQHandler() function
        • Add and customize the Error Callback API: HAL_PPP_ErrorCallback()
    • HAL WWDG update 
      • Overall rework of the driver for more efficient implementation
        • Remove the following APIs:
          • HAL_WWDG_Start()
          • HAL_WWDG_Start_IT()
          • HAL_WWDG_MspDeInit()
          • HAL_WWDG_GetState()
        • Update implementation:
          • HAL_WWDG_Init()
            • A new parameter in the Init Structure: EWIMode
          • HAL_WWDG_MspInit()
          • HAL_WWDG_Refresh() 
            • This function insures the reload of the counter
            • The "counter" parameter has been removed
          • HAL_WWDG_IRQHandler()
          • HAL_WWDG_EarlyWakeupCallback() is the new prototype of HAL_WWDG_WakeupCallback()
      • Refer to the following example to identify the changes: WWDG_Example

    V1.0.4 / 09-December-2015

    +
    • Update Polling management:
      • The user Timeout value must be estimated for the overall process duration: the Timeout measurement is cumulative
    • Update DMA process:
      • Update the management of PPP peripheral errors during DMA process. This requires the following updates in user application:
        • Configure and enable the PPP IRQ in HAL_PPP_MspInit() function
        • In stm32f7xx_it.c file, PPP_IRQHandler() function: add a call to HAL_PPP_IRQHandler() function
        • Add and customize the Error Callback API: HAL_PPP_ErrorCallback()
    • HAL WWDG update 
      • Overall rework of the driver for more efficient implementation
        • Remove the following APIs:
          • HAL_WWDG_Start()
          • HAL_WWDG_Start_IT()
          • HAL_WWDG_MspDeInit()
          • HAL_WWDG_GetState()
        • Update implementation:
          • HAL_WWDG_Init()
            • A new parameter in the Init Structure: EWIMode
          • HAL_WWDG_MspInit()
          • HAL_WWDG_Refresh() 
            • This function insures the reload of the counter
            • The "counter" parameter has been removed
          • HAL_WWDG_IRQHandler()
          • HAL_WWDG_EarlyWakeupCallback() is the new prototype of HAL_WWDG_WakeupCallback()
      • Refer to the following example to identify the changes: WWDG_Example

    V1.0.4 / 09-December-2015

    Main Changes

    • HAL Generic update
      • Update HAL weak empty callbacks to prevent unused argument compilation warnings with some compilers by calling the following line: -
        • UNUSED(hppp);
    • HAL ETH update 
      • Update HAL_ETH_Init() function to add timeout on the Software reset management

    V1.0.3 / 13-November-2015

    +
    • UNUSED(hppp);
  • HAL ETH update 
    • Update HAL_ETH_Init() function to add timeout on the Software reset management

    V1.0.3 / 13-November-2015

    Main Changes

    • General updates to fix known defects and enhancements implementation
    • One change done on the HAL CRYP requires an update on @@ -1169,7 +1300,7 @@

      HAL CORTEX update

      • Remove duplication -for __HAL_CORTEX_SYSTICKCLK_CONFIG() macro
    • HAL CRYP update
      • Update HAL_CRYP_DESECB_Decrypt() API to fix the inverted pPlainData and pCypherData parameters issue
    • HAL FLASH update
      • Update OB_IWDG_STOP_ACTIVE definition
      • Update OB_RDP_LEVEL_x definition by proper values
      • Update FLASH_MassErase() function to consider the voltage range parameter in the mass erase configuration
    • HAL RCC update
      • update values for LSE Drive capability defines
      • update PLLN min value 50 instead of 100
      • add RCC_PLLI2SP_DIVx defines for PLLI2SP clock divider
      • Update __HAL_RCC_USB_OTG_FS_CLK_DISABLE() macro to remove the disable of the SYSCFG 
      • Update HAL_RCCEx_GetPeriphCLKFreq() function for proper SAI clock configuration
    • HAL SAI update
      • update for proper management of the external synchronization input selection
        • update of HAL_SAI_Init () funciton
        • update definition of SAI_Block_SyncExt and SAI_Block_Synchronization groups
      • update SAI_SLOTACTIVE_X  defines values
      • update HAL_SAI_Init() function for proper companding mode management
      • update SAI_Transmit_ITxxBit() functions to add the check on transfer counter before writing new data to SAIx_DR registers
      • update SAI_FillFifo() function to avoid issue when the number of data to transmit is smaller than the FIFO size
      • update HAL_SAI_EnableRxMuteMode() function for proper mute management
      • update SAI_InitPCM() function to support 24bits configuration
    • HAL SD update
      • update HAL_SD_Get_CardInfo() to properly support high capacity cards
    • HAL SPDIFRX update
      • update SPDIFRX_DMARxCplt() function implementation to check on circular mode before disabling the DMA
    • HAL TIM update
      • Update HAL_TIM_ConfigClockSource() function implementation for proper parameters check
    • HAL UART update
      • Update __HAL_UART_CLEAR_IT macro for proper functionning 
    • ll FMC update
      • add FMC_PAGE_SIZE_512 define
    • ll SDMMC update
      • update SDMMC_SetSDMMCReadWaitMode() function for proper functionning

    V1.0.2 / 21-September-2015

    +for __HAL_CORTEX_SYSTICKCLK_CONFIG() macro
  • HAL CRYP update
    • Update HAL_CRYP_DESECB_Decrypt() API to fix the inverted pPlainData and pCypherData parameters issue
  • HAL FLASH update
    • Update OB_IWDG_STOP_ACTIVE definition
    • Update OB_RDP_LEVEL_x definition by proper values
    • Update FLASH_MassErase() function to consider the voltage range parameter in the mass erase configuration
  • HAL RCC update
    • update values for LSE Drive capability defines
    • update PLLN min value 50 instead of 100
    • add RCC_PLLI2SP_DIVx defines for PLLI2SP clock divider
    • Update __HAL_RCC_USB_OTG_FS_CLK_DISABLE() macro to remove the disable of the SYSCFG 
    • Update HAL_RCCEx_GetPeriphCLKFreq() function for proper SAI clock configuration
  • HAL SAI update
    • update for proper management of the external synchronization input selection
      • update of HAL_SAI_Init () funciton
      • update definition of SAI_Block_SyncExt and SAI_Block_Synchronization groups
    • update SAI_SLOTACTIVE_X  defines values
    • update HAL_SAI_Init() function for proper companding mode management
    • update SAI_Transmit_ITxxBit() functions to add the check on transfer counter before writing new data to SAIx_DR registers
    • update SAI_FillFifo() function to avoid issue when the number of data to transmit is smaller than the FIFO size
    • update HAL_SAI_EnableRxMuteMode() function for proper mute management
    • update SAI_InitPCM() function to support 24bits configuration
  • HAL SD update
    • update HAL_SD_Get_CardInfo() to properly support high capacity cards
  • HAL SPDIFRX update
    • update SPDIFRX_DMARxCplt() function implementation to check on circular mode before disabling the DMA
  • HAL TIM update
    • Update HAL_TIM_ConfigClockSource() function implementation for proper parameters check
  • HAL UART update
    • Update __HAL_UART_CLEAR_IT macro for proper functionning 
  • ll FMC update
    • add FMC_PAGE_SIZE_512 define
  • ll SDMMC update
    • update SDMMC_SetSDMMCReadWaitMode() function for proper functionning

    V1.0.2 / 21-September-2015

    Main Changes

    • HAL Generic update
      • stm32f7xx_hal.conf_template.h: update HSE_STARTUP_TIMEOUT
      • stm32f7xx_hal_def.h: update the quotation marks used in #error"USE_RTOS should be 0 in the current HAL release"
    • HAL DMA update
      • Overall driver update for code optimization
        • add @@ -1201,7 +1332,7 @@

          HAL RCC update

          • update values for LSE Drive capability defines
          • update PLLN/PLLI2SN/PLLSAI VCO min value 100MHz instead of 192MHz
          • add __HAL_RCC_MCO1_CONFIG() and __HAL_RCC_MCO2_CONFIG() macros
          • update HAL_RCCEx_PeriphCLKConfig() function to reset the Backup domain only if the RTC Clock source selection is modified 
        • HAL TIM update
          • update the implementation of __HAL_TIM_SET_COMPARE() macro
          • remove useless assert() in HAL_TIM_PWM_ConfigChannel(), TIM_OC2_SetConfig() and HAL_TIM_PWM_ConfigChannel() functions
        • HAL CAN update
          • add the clear flag ERRI bit in HAL_CAN_IRQHandler()
        • HAL I2S update
          • update I2S HAL_I2S_Transmit() API to keep the check on busy flag only for the slave
        • HAL QSPI update
          • Add __HAL_QSPI_CLEAR_FLAG() before QSPI_Config()
        • HAL UART update
          • Remove enabling of ERR IT source and PE source from HAL_UART_Transmit_IT() and remove the corresponding disabling ERR/PE IT from UART_EndTransmit_IT()
        • HAL PCD update 
          • Clean status phase received interrupt when DMA mode enabled 
        • HAL HCD update
          • Update to use local -variable in USB Host channel re-activation
        • ll FMC update
          • update the define FMC Write FIFO Disable/Enable: FMC_WRITE_FIFO_DISABLE and FMC_WRITE_FIFO_ENABLE
          • remove return HAL_ERROR from FMC_SDRAM_SendCommand() function

        V1.0.1 / 25-June-2015

        +variable in USB Host channel re-activation
    • ll FMC update
      • update the define FMC Write FIFO Disable/Enable: FMC_WRITE_FIFO_DISABLE and FMC_WRITE_FIFO_ENABLE
      • remove return HAL_ERROR from FMC_SDRAM_SendCommand() function

    V1.0.1 / 25-June-2015

    Main Changes

    • General updates to fix known defects and enhancements implementation
    • HAL CRC update
      • update __HAL_CRC_SET_IDR() macro implementation to use WRITE_REG() instead of MODIFY_REG()
    • HAL CEC update
      • update timeout management in HAL_CEC_Transmit() and HAL_CEC_Receive() functions
    • HAL Cortex update
      • update HAL_MPU_ConfigRegion() function to be misra compliant
    • HAL ETH update
      • Remove @@ -1227,12 +1358,12 @@

        Update to use local variable in USB Host channel re-activation

    -

    V1.0.0 / 12-May-2015

    +

    V1.0.0 / 12-May-2015

    Main Changes

    • First official release for STM32F756xx/746xx/745xx devices
    -

    License

    +

    License

    Redistribution and use in source and binary forms, with or without diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/Legacy/stm32f7xx_hal_can.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/Legacy/stm32f7xx_hal_can.c index 598ab0825a..22fbc27acb 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/Legacy/stm32f7xx_hal_can.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/Legacy/stm32f7xx_hal_can.c @@ -83,13 +83,29 @@ ****************************************************************************** * @attention * - *

    © Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

    + *

    © COPYRIGHT(c) 2017 STMicroelectronics

    * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** */ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c index 44e336f36b..1f076aa8b9 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c @@ -50,11 +50,11 @@ * @{ */ /** - * @brief STM32F7xx HAL Driver version number V1.2.7 + * @brief STM32F7xx HAL Driver version number V1.2.8 */ #define __STM32F7xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */ #define __STM32F7xx_HAL_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */ -#define __STM32F7xx_HAL_VERSION_SUB2 (0x07) /*!< [15:8] sub2 version */ +#define __STM32F7xx_HAL_VERSION_SUB2 (0x08) /*!< [15:8] sub2 version */ #define __STM32F7xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32F7xx_HAL_VERSION ((__STM32F7xx_HAL_VERSION_MAIN << 24)\ |(__STM32F7xx_HAL_VERSION_SUB1 << 16)\ @@ -319,14 +319,26 @@ uint32_t HAL_GetTickPrio(void) HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq) { HAL_StatusTypeDef status = HAL_OK; + HAL_TickFreqTypeDef prevTickFreq; + assert_param(IS_TICKFREQ(Freq)); if (uwTickFreq != Freq) { + /* Back up uwTickFreq frequency */ + prevTickFreq = uwTickFreq; + + /* Update uwTickFreq global variable used by HAL_InitTick() */ uwTickFreq = Freq; /* Apply the new tick Freq */ status = HAL_InitTick(uwTickPrio); + + if (status != HAL_OK) + { + /* Restore previous tick frequency */ + uwTickFreq = prevTickFreq; + } } return status; diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c index d71292189f..2b57088cbd 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c @@ -131,6 +131,7 @@ *** Callback functions *** ============================== + [..] (@) Callback functions must be implemented in user program: (+@) HAL_ADC_ErrorCallback() (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog) @@ -1632,22 +1633,22 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf /* Process locked */ __HAL_LOCK(hadc); - /* if ADC_Channel_10 ... ADC_Channel_18 is selected */ - if (sConfig->Channel > ADC_CHANNEL_9) - { - /* Clear the old sample time */ - hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel); - - if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) - { - /* Set the new sample time */ - hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, ADC_CHANNEL_18); - } - else - { - /* Set the new sample time */ - hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel); - } + /* if ADC_Channel_10 ... ADC_Channel_18 is selected */ + if ((sConfig->Channel > ADC_CHANNEL_9) && (sConfig->Channel != ADC_INTERNAL_NONE)) + { + /* Clear the old sample time */ + hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel); + + if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) + { + /* Set the new sample time */ + hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, ADC_CHANNEL_18); + } + else + { + /* Set the new sample time */ + hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel); + } } else /* ADC_Channel include in ADC_Channel_[0..9] */ { @@ -1686,6 +1687,13 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf hadc->Instance->SQR1 |= ADC_SQR1_RK(sConfig->Channel, sConfig->Rank); } + /* if no internal channel selected */ + if ((hadc->Instance == ADC1) && (sConfig->Channel == ADC_INTERNAL_NONE)) + { + /* Disable the VBAT & TSVREFE channel*/ + ADC->CCR &= ~(ADC_CCR_VBATE | ADC_CCR_TSVREFE); + } + /* if ADC1 Channel_18 is selected enable VBAT Channel */ if ((hadc->Instance == ADC1) && (sConfig->Channel == ADC_CHANNEL_VBAT)) { diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c index 0cf31b9a7f..7fa5917efc 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c @@ -58,18 +58,6 @@ add his own code by customization of function pointer HAL_ADCEx_InjectedErrorCallback (+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop_IT() - - *** DMA mode IO operation *** - ============================== - [..] - (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart_DMA(), at this stage the user specify the length - of data to be transferred at each end of conversion - (+) At The end of data transfer ba HAL_ADCEx_InjectedConvCpltCallback() function is executed and user can - add his own code by customization of function pointer HAL_ADCEx_InjectedConvCpltCallback - (+) In case of transfer Error, HAL_ADCEx_InjectedErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_ADCEx_InjectedErrorCallback - (+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop_DMA() - *** Multi mode ADCs Regular channels configuration *** ====================================================== [..] diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_can.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_can.c index a45b2a521f..954f5ce3c7 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_can.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_can.c @@ -1556,7 +1556,7 @@ HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, { pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos; } - pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_RTR_Pos; + pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR); pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos; pHeader->FilterMatchIndex = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_FMI_Pos; pHeader->Timestamp = (CAN_RDT0R_TIME & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_TIME_Pos; diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cryp.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cryp.c index 4e6524ff41..6aabd17639 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cryp.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cryp.c @@ -64,6 +64,12 @@ (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral. + (#)To process a single message with consecutive calls to HAL_CRYP_Encrypt() or HAL_CRYP_Decrypt() + without having to configure again the Key or the Initialization Vector between each API call, + the field KeyIVConfigSkip of the initialization structure must be set to CRYP_KEYIVCONFIG_ONCE. + Same is true for consecutive calls of HAL_CRYP_Encrypt_IT(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt_DMA() + or HAL_CRYP_Decrypt_DMA(). + [..] The cryptographic processor supports following standards: (#) The data encryption standard (DES) and Triple-DES (TDES) supported only by CRYP1 IP: @@ -295,7 +301,7 @@ #define CRYP_OPERATINGMODE_DECRYPT CRYP_CR_ALGODIR /*!< Decryption */ #endif /* End CRYP or AES */ - /* CTR1 information to use in CCM algorithm */ +/* CTR1 information to use in CCM algorithm */ #define CRYP_CCM_CTR1_0 0x07FFFFFFU #define CRYP_CCM_CTR1_1 0xFFFFFF00U #define CRYP_CCM_CTR1_2 0x00000001U @@ -350,7 +356,7 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp); static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcryp); static void CRYP_Workaround(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp); -static HAL_StatusTypeDef CRYP_AESGCM_Process_IT (CRYP_HandleTypeDef *hcryp); +static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp); static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp); @@ -386,8 +392,8 @@ static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t T /** @defgroup CRYP_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions. - * + * @brief Initialization and Configuration functions. + * @verbatim ======================================================================================== ##### Initialization, de-initialization and Set and Get configuration functions ##### @@ -424,7 +430,7 @@ static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t T HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp) { /* Check the CRYP handle allocation */ - if(hcryp == NULL) + if (hcryp == NULL) { return HAL_ERROR; } @@ -433,9 +439,10 @@ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp) assert_param(IS_CRYP_KEYSIZE(hcryp->Init.KeySize)); assert_param(IS_CRYP_DATATYPE(hcryp->Init.DataType)); assert_param(IS_CRYP_ALGORITHM(hcryp->Init.Algorithm)); + assert_param(IS_CRYP_INIT(hcryp->Init.KeyIVConfigSkip)); - #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) - if(hcryp->State == HAL_CRYP_STATE_RESET) +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) + if (hcryp->State == HAL_CRYP_STATE_RESET) { /* Allocate lock resource and initialize it */ hcryp->Lock = HAL_UNLOCKED; @@ -444,7 +451,7 @@ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp) hcryp->OutCpltCallback = HAL_CRYP_OutCpltCallback; /* Legacy weak OutCpltCallback */ hcryp->ErrorCallback = HAL_CRYP_ErrorCallback; /* Legacy weak ErrorCallback */ - if(hcryp->MspInitCallback == NULL) + if (hcryp->MspInitCallback == NULL) { hcryp->MspInitCallback = HAL_CRYP_MspInit; /* Legacy weak MspInit */ } @@ -453,7 +460,7 @@ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp) hcryp->MspInitCallback(hcryp); } #else - if(hcryp->State == HAL_CRYP_STATE_RESET) + if (hcryp->State == HAL_CRYP_STATE_RESET) { /* Allocate lock resource and initialize it */ hcryp->Lock = HAL_UNLOCKED; @@ -461,16 +468,18 @@ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp) /* Init the low level hardware */ HAL_CRYP_MspInit(hcryp); } - #endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */ +#endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */ /* Set the key size(This bit field is don�t care in the DES or TDES modes) data type and Algorithm */ #if defined (CRYP) - MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE|CRYP_CR_KEYSIZE|CRYP_CR_ALGOMODE, hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm); + MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE | CRYP_CR_KEYSIZE | CRYP_CR_ALGOMODE, + hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm); #else /*AES*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE|AES_CR_KEYSIZE|AES_CR_CHMOD, hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm); + MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD, + hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm); #endif /* End AES or CRYP*/ @@ -492,11 +501,11 @@ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp) * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp) { /* Check the CRYP handle allocation */ - if(hcryp == NULL) + if (hcryp == NULL) { return HAL_ERROR; } @@ -507,14 +516,14 @@ HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp) /* Reset CrypInCount and CrypOutCount */ hcryp->CrypInCount = 0; hcryp->CrypOutCount = 0; - hcryp->CrypHeaderCount =0; + hcryp->CrypHeaderCount = 0; /* Disable the CRYP peripheral clock */ __HAL_CRYP_DISABLE(hcryp); #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) - if(hcryp->MspDeInitCallback == NULL) + if (hcryp->MspDeInitCallback == NULL) { hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit; /* Legacy weak MspDeInit */ } @@ -546,10 +555,10 @@ HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp) * the configuration information for CRYP module * @retval HAL status */ -HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf ) +HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf) { /* Check the CRYP handle allocation */ - if((hcryp == NULL)|| (pConf == NULL) ) + if ((hcryp == NULL) || (pConf == NULL)) { return HAL_ERROR; } @@ -559,7 +568,7 @@ HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeD assert_param(IS_CRYP_DATATYPE(pConf->DataType)); assert_param(IS_CRYP_ALGORITHM(pConf->Algorithm)); - if(hcryp->State == HAL_CRYP_STATE_READY) + if (hcryp->State == HAL_CRYP_STATE_READY) { /* Change the CRYP state */ hcryp->State = HAL_CRYP_STATE_BUSY; @@ -581,13 +590,15 @@ HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeD /* Set the key size(This bit field is don�t care in the DES or TDES modes) data type, AlgoMode and operating mode*/ #if defined (CRYP) - MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE|CRYP_CR_KEYSIZE|CRYP_CR_ALGOMODE, hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm); + MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE | CRYP_CR_KEYSIZE | CRYP_CR_ALGOMODE, + hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm); #else /*AES*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE|AES_CR_KEYSIZE|AES_CR_CHMOD, hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm); + MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD, + hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm); /*clear error flags*/ - __HAL_CRYP_CLEAR_FLAG(hcryp,CRYP_ERR_CLEAR); + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_ERR_CLEAR); #endif /* End AES or CRYP */ @@ -624,15 +635,15 @@ HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeD * the configuration information for CRYP module * @retval HAL status */ -HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf ) +HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf) { /* Check the CRYP handle allocation */ - if((hcryp == NULL)|| (pConf == NULL) ) + if ((hcryp == NULL) || (pConf == NULL)) { return HAL_ERROR; } - if(hcryp->State == HAL_CRYP_STATE_READY) + if (hcryp->State == HAL_CRYP_STATE_READY) { /* Change the CRYP state */ hcryp->State = HAL_CRYP_STATE_BUSY; @@ -717,11 +728,12 @@ __weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp) * @param pCallback pointer to the Callback function * @retval status */ -HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID, pCRYP_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID, + pCRYP_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; - if(pCallback == NULL) + if (pCallback == NULL) { /* Update the error code */ hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK; @@ -731,56 +743,56 @@ HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_ /* Process locked */ __HAL_LOCK(hcryp); - if(hcryp->State == HAL_CRYP_STATE_READY) + if (hcryp->State == HAL_CRYP_STATE_READY) { switch (CallbackID) { - case HAL_CRYP_INPUT_COMPLETE_CB_ID : - hcryp->InCpltCallback = pCallback; - break; + case HAL_CRYP_INPUT_COMPLETE_CB_ID : + hcryp->InCpltCallback = pCallback; + break; - case HAL_CRYP_OUTPUT_COMPLETE_CB_ID : - hcryp->OutCpltCallback = pCallback; - break; + case HAL_CRYP_OUTPUT_COMPLETE_CB_ID : + hcryp->OutCpltCallback = pCallback; + break; - case HAL_CRYP_ERROR_CB_ID : - hcryp->ErrorCallback = pCallback; - break; + case HAL_CRYP_ERROR_CB_ID : + hcryp->ErrorCallback = pCallback; + break; - case HAL_CRYP_MSPINIT_CB_ID : - hcryp->MspInitCallback = pCallback; - break; + case HAL_CRYP_MSPINIT_CB_ID : + hcryp->MspInitCallback = pCallback; + break; - case HAL_CRYP_MSPDEINIT_CB_ID : - hcryp->MspDeInitCallback = pCallback; - break; + case HAL_CRYP_MSPDEINIT_CB_ID : + hcryp->MspDeInitCallback = pCallback; + break; - default : - /* Update the error code */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - break; + default : + /* Update the error code */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; } } - else if(hcryp->State == HAL_CRYP_STATE_RESET) + else if (hcryp->State == HAL_CRYP_STATE_RESET) { switch (CallbackID) { - case HAL_CRYP_MSPINIT_CB_ID : - hcryp->MspInitCallback = pCallback; - break; + case HAL_CRYP_MSPINIT_CB_ID : + hcryp->MspInitCallback = pCallback; + break; - case HAL_CRYP_MSPDEINIT_CB_ID : - hcryp->MspDeInitCallback = pCallback; - break; + case HAL_CRYP_MSPDEINIT_CB_ID : + hcryp->MspDeInitCallback = pCallback; + break; - default : - /* Update the error code */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - break; + default : + /* Update the error code */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; } } else @@ -817,56 +829,56 @@ HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRY /* Process locked */ __HAL_LOCK(hcryp); - if(hcryp->State == HAL_CRYP_STATE_READY) + if (hcryp->State == HAL_CRYP_STATE_READY) { switch (CallbackID) { - case HAL_CRYP_INPUT_COMPLETE_CB_ID : - hcryp->InCpltCallback = HAL_CRYP_InCpltCallback; /* Legacy weak InCpltCallback */ - break; + case HAL_CRYP_INPUT_COMPLETE_CB_ID : + hcryp->InCpltCallback = HAL_CRYP_InCpltCallback; /* Legacy weak InCpltCallback */ + break; - case HAL_CRYP_OUTPUT_COMPLETE_CB_ID : - hcryp->OutCpltCallback = HAL_CRYP_OutCpltCallback; /* Legacy weak OutCpltCallback */ - break; + case HAL_CRYP_OUTPUT_COMPLETE_CB_ID : + hcryp->OutCpltCallback = HAL_CRYP_OutCpltCallback; /* Legacy weak OutCpltCallback */ + break; - case HAL_CRYP_ERROR_CB_ID : - hcryp->ErrorCallback = HAL_CRYP_ErrorCallback; /* Legacy weak ErrorCallback */ - break; + case HAL_CRYP_ERROR_CB_ID : + hcryp->ErrorCallback = HAL_CRYP_ErrorCallback; /* Legacy weak ErrorCallback */ + break; - case HAL_CRYP_MSPINIT_CB_ID : - hcryp->MspInitCallback = HAL_CRYP_MspInit; - break; + case HAL_CRYP_MSPINIT_CB_ID : + hcryp->MspInitCallback = HAL_CRYP_MspInit; + break; - case HAL_CRYP_MSPDEINIT_CB_ID : - hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit; - break; + case HAL_CRYP_MSPDEINIT_CB_ID : + hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit; + break; - default : - /* Update the error code */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - break; + default : + /* Update the error code */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; } } - else if(hcryp->State == HAL_CRYP_STATE_RESET) + else if (hcryp->State == HAL_CRYP_STATE_RESET) { switch (CallbackID) { - case HAL_CRYP_MSPINIT_CB_ID : - hcryp->MspInitCallback = HAL_CRYP_MspInit; - break; + case HAL_CRYP_MSPINIT_CB_ID : + hcryp->MspInitCallback = HAL_CRYP_MspInit; + break; - case HAL_CRYP_MSPDEINIT_CB_ID : - hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit; - break; + case HAL_CRYP_MSPDEINIT_CB_ID : + hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit; + break; - default : - /* Update the error code */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - break; + default : + /* Update the error code */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; } } else @@ -888,8 +900,8 @@ HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRY */ /** @defgroup CRYP_Exported_Functions_Group2 Encrypt Decrypt functions - * @brief processing functions. - * + * @brief processing functions. + * @verbatim ============================================================================== ##### Encrypt Decrypt functions ##### @@ -927,12 +939,13 @@ HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRY * @param Timeout: Specify Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout) +HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, + uint32_t Timeout) { uint32_t algo; HAL_StatusTypeDef status; - if(hcryp->State == HAL_CRYP_STATE_READY) + if (hcryp->State == HAL_CRYP_STATE_READY) { /* Change state Busy */ hcryp->State = HAL_CRYP_STATE_BUSY; @@ -963,65 +976,69 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, u /* algo get algorithm selected */ algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE; - switch(algo) + switch (algo) { - case CRYP_DES_ECB: - case CRYP_DES_CBC: - case CRYP_TDES_ECB: - case CRYP_TDES_CBC: + case CRYP_DES_ECB: + case CRYP_DES_CBC: + case CRYP_TDES_ECB: + case CRYP_TDES_CBC: - /*Set Key */ - hcryp->Instance->K1LR = *(uint32_t*)(hcryp->Init.pKey); - hcryp->Instance->K1RR = *(uint32_t*)(hcryp->Init.pKey+1); - if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC)) - { - hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey+2); - hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+3); - hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+4); - hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+5); - } + /*Set Key */ + hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey); + hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1); + if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC)) + { + hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2); + hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3); + hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4); + hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5); + } - /*Set Initialization Vector (IV)*/ - if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC)) - { - hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect); - hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1); - } + /*Set Initialization Vector (IV)*/ + if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC)) + { + hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect); + hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1); + } - /* Flush FIFO */ - HAL_CRYP_FIFO_FLUSH(hcryp); + /* Flush FIFO */ + HAL_CRYP_FIFO_FLUSH(hcryp); - /* Set the phase */ - hcryp->Phase = CRYP_PHASE_PROCESS; + /* Set the phase */ + hcryp->Phase = CRYP_PHASE_PROCESS; - /* Statrt DES/TDES encryption process */ - status = CRYP_TDES_Process(hcryp,Timeout); - break; + /* Statrt DES/TDES encryption process */ + status = CRYP_TDES_Process(hcryp, Timeout); + break; - case CRYP_AES_ECB: - case CRYP_AES_CBC: - case CRYP_AES_CTR: + case CRYP_AES_ECB: + case CRYP_AES_CBC: + case CRYP_AES_CTR: - /* AES encryption */ - status = CRYP_AES_Encrypt(hcryp, Timeout); - break; + /* AES encryption */ + status = CRYP_AES_Encrypt(hcryp, Timeout); + break; - case CRYP_AES_GCM: + case CRYP_AES_GCM: - /* AES GCM encryption */ - status = CRYP_AESGCM_Process(hcryp, Timeout); + /* AES GCM encryption */ + status = CRYP_AESGCM_Process(hcryp, Timeout); - break; + break; - case CRYP_AES_CCM: + case CRYP_AES_CCM: - /* AES CCM encryption */ - status = CRYP_AESCCM_Process(hcryp,Timeout); - break; + /* AES CCM encryption */ + status = CRYP_AESCCM_Process(hcryp, Timeout); + break; - default: - hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; - return HAL_ERROR; + default: + hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; + /* Change the CRYP peripheral state */ + hcryp->State = HAL_CRYP_STATE_READY; + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; } #else /*AES*/ @@ -1032,32 +1049,36 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, u /* algo get algorithm selected */ algo = hcryp->Instance->CR & AES_CR_CHMOD; - switch(algo) + switch (algo) { - case CRYP_AES_ECB: - case CRYP_AES_CBC: - case CRYP_AES_CTR: + case CRYP_AES_ECB: + case CRYP_AES_CBC: + case CRYP_AES_CTR: - /* AES encryption */ - status = CRYP_AES_Encrypt(hcryp, Timeout); - break; + /* AES encryption */ + status = CRYP_AES_Encrypt(hcryp, Timeout); + break; - case CRYP_AES_GCM_GMAC: + case CRYP_AES_GCM_GMAC: - /* AES GCM encryption */ - status = CRYP_AESGCM_Process (hcryp,Timeout) ; - break; + /* AES GCM encryption */ + status = CRYP_AESGCM_Process(hcryp, Timeout) ; + break; - case CRYP_AES_CCM: + case CRYP_AES_CCM: - /* AES CCM encryption */ - status = CRYP_AESCCM_Process(hcryp,Timeout); - break; + /* AES CCM encryption */ + status = CRYP_AESCCM_Process(hcryp, Timeout); + break; - default: - hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; - return HAL_ERROR; + default: + hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; + /* Change the CRYP peripheral state */ + hcryp->State = HAL_CRYP_STATE_READY; + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; } #endif /*end AES or CRYP */ @@ -1091,12 +1112,13 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, u * @param Timeout: Specify Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout) +HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, + uint32_t Timeout) { HAL_StatusTypeDef status; uint32_t algo; - if(hcryp->State == HAL_CRYP_STATE_READY) + if (hcryp->State == HAL_CRYP_STATE_READY) { /* Change state Busy */ hcryp->State = HAL_CRYP_STATE_BUSY; @@ -1128,65 +1150,69 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, u /* algo get algorithm selected */ algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE; - switch(algo) + switch (algo) { - case CRYP_DES_ECB: - case CRYP_DES_CBC: - case CRYP_TDES_ECB: - case CRYP_TDES_CBC: + case CRYP_DES_ECB: + case CRYP_DES_CBC: + case CRYP_TDES_ECB: + case CRYP_TDES_CBC: - /*Set Key */ - hcryp->Instance->K1LR = *(uint32_t*)(hcryp->Init.pKey); - hcryp->Instance->K1RR = *(uint32_t*)(hcryp->Init.pKey+1); - if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC)) - { - hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey+2); - hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+3); - hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+4); - hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+5); - } + /*Set Key */ + hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey); + hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1); + if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC)) + { + hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2); + hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3); + hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4); + hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5); + } - /*Set Initialization Vector (IV)*/ - if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC)) - { - hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect); - hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1); - } + /*Set Initialization Vector (IV)*/ + if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC)) + { + hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect); + hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1); + } - /* Flush FIFO */ - HAL_CRYP_FIFO_FLUSH(hcryp); + /* Flush FIFO */ + HAL_CRYP_FIFO_FLUSH(hcryp); - /* Set the phase */ - hcryp->Phase = CRYP_PHASE_PROCESS; + /* Set the phase */ + hcryp->Phase = CRYP_PHASE_PROCESS; - /* Start DES/TDES decryption process */ - status = CRYP_TDES_Process(hcryp, Timeout); + /* Start DES/TDES decryption process */ + status = CRYP_TDES_Process(hcryp, Timeout); - break; + break; - case CRYP_AES_ECB: - case CRYP_AES_CBC: - case CRYP_AES_CTR: + case CRYP_AES_ECB: + case CRYP_AES_CBC: + case CRYP_AES_CTR: - /* AES decryption */ - status = CRYP_AES_Decrypt(hcryp, Timeout); - break; + /* AES decryption */ + status = CRYP_AES_Decrypt(hcryp, Timeout); + break; - case CRYP_AES_GCM: + case CRYP_AES_GCM: - /* AES GCM decryption */ - status = CRYP_AESGCM_Process (hcryp, Timeout) ; - break; + /* AES GCM decryption */ + status = CRYP_AESGCM_Process(hcryp, Timeout) ; + break; - case CRYP_AES_CCM: + case CRYP_AES_CCM: - /* AES CCM decryption */ - status = CRYP_AESCCM_Process(hcryp, Timeout); - break; + /* AES CCM decryption */ + status = CRYP_AESCCM_Process(hcryp, Timeout); + break; - default: - hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; - return HAL_ERROR; + default: + hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; + /* Change the CRYP peripheral state */ + hcryp->State = HAL_CRYP_STATE_READY; + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; } #else /*AES*/ @@ -1197,32 +1223,36 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, u /* algo get algorithm selected */ algo = hcryp->Instance->CR & AES_CR_CHMOD; - switch(algo) + switch (algo) { - case CRYP_AES_ECB: - case CRYP_AES_CBC: - case CRYP_AES_CTR: + case CRYP_AES_ECB: + case CRYP_AES_CBC: + case CRYP_AES_CTR: - /* AES decryption */ - status = CRYP_AES_Decrypt(hcryp, Timeout); - break; + /* AES decryption */ + status = CRYP_AES_Decrypt(hcryp, Timeout); + break; - case CRYP_AES_GCM_GMAC: + case CRYP_AES_GCM_GMAC: - /* AES GCM decryption */ - status = CRYP_AESGCM_Process (hcryp, Timeout) ; - break; + /* AES GCM decryption */ + status = CRYP_AESGCM_Process(hcryp, Timeout) ; + break; - case CRYP_AES_CCM: + case CRYP_AES_CCM: - /* AES CCM decryption */ - status = CRYP_AESCCM_Process(hcryp, Timeout); - break; + /* AES CCM decryption */ + status = CRYP_AESCCM_Process(hcryp, Timeout); + break; - default: - hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; - return HAL_ERROR; + default: + hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; + /* Change the CRYP peripheral state */ + hcryp->State = HAL_CRYP_STATE_READY; + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; } #endif /* End AES or CRYP */ @@ -1260,7 +1290,7 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input uint32_t algo; HAL_StatusTypeDef status = HAL_OK; - if(hcryp->State == HAL_CRYP_STATE_READY) + if (hcryp->State == HAL_CRYP_STATE_READY) { /* Change state Busy */ hcryp->State = HAL_CRYP_STATE_BUSY; @@ -1292,64 +1322,68 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input /* algo get algorithm selected */ algo = (hcryp->Instance->CR & CRYP_CR_ALGOMODE); - switch(algo) + switch (algo) { - case CRYP_DES_ECB: - case CRYP_DES_CBC: - case CRYP_TDES_ECB: - case CRYP_TDES_CBC: + case CRYP_DES_ECB: + case CRYP_DES_CBC: + case CRYP_TDES_ECB: + case CRYP_TDES_CBC: - /*Set Key */ - hcryp->Instance->K1LR = *(uint32_t*)(hcryp->Init.pKey); - hcryp->Instance->K1RR = *(uint32_t*)(hcryp->Init.pKey+1); - if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC)) - { - hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey+2); - hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+3); - hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+4); - hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+5); - } - /* Set the Initialization Vector*/ - if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC)) - { - hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect); - hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1); - } + /*Set Key */ + hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey); + hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1); + if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC)) + { + hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2); + hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3); + hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4); + hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5); + } + /* Set the Initialization Vector*/ + if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC)) + { + hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect); + hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1); + } - /* Flush FIFO */ - HAL_CRYP_FIFO_FLUSH(hcryp); + /* Flush FIFO */ + HAL_CRYP_FIFO_FLUSH(hcryp); - /* Set the phase */ - hcryp->Phase = CRYP_PHASE_PROCESS; + /* Set the phase */ + hcryp->Phase = CRYP_PHASE_PROCESS; - /* Enable interrupts */ - __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI); + /* Enable interrupts */ + __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI); - /* Enable CRYP to start DES/TDES process*/ - __HAL_CRYP_ENABLE(hcryp); - break; + /* Enable CRYP to start DES/TDES process*/ + __HAL_CRYP_ENABLE(hcryp); + break; - case CRYP_AES_ECB: - case CRYP_AES_CBC: - case CRYP_AES_CTR: + case CRYP_AES_ECB: + case CRYP_AES_CBC: + case CRYP_AES_CTR: - status = CRYP_AES_Encrypt_IT(hcryp); - break; + status = CRYP_AES_Encrypt_IT(hcryp); + break; - case CRYP_AES_GCM: + case CRYP_AES_GCM: - status = CRYP_AESGCM_Process_IT (hcryp) ; - break; + status = CRYP_AESGCM_Process_IT(hcryp) ; + break; - case CRYP_AES_CCM: + case CRYP_AES_CCM: - status = CRYP_AESCCM_Process_IT(hcryp); - break; + status = CRYP_AESCCM_Process_IT(hcryp); + break; - default: - hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; - status = HAL_ERROR; - break; + default: + hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; + /* Change the CRYP peripheral state */ + hcryp->State = HAL_CRYP_STATE_READY; + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + status = HAL_ERROR; + break; } #else /* AES */ @@ -1360,32 +1394,36 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input /* algo get algorithm selected */ algo = hcryp->Instance->CR & AES_CR_CHMOD; - switch(algo) + switch (algo) { - case CRYP_AES_ECB: - case CRYP_AES_CBC: - case CRYP_AES_CTR: + case CRYP_AES_ECB: + case CRYP_AES_CBC: + case CRYP_AES_CTR: - /* AES encryption */ - status = CRYP_AES_Encrypt_IT(hcryp); - break; + /* AES encryption */ + status = CRYP_AES_Encrypt_IT(hcryp); + break; - case CRYP_AES_GCM_GMAC: + case CRYP_AES_GCM_GMAC: - /* AES GCM encryption */ - status = CRYP_AESGCM_Process_IT (hcryp) ; - break; + /* AES GCM encryption */ + status = CRYP_AESGCM_Process_IT(hcryp) ; + break; - case CRYP_AES_CCM: + case CRYP_AES_CCM: - /* AES CCM encryption */ - status = CRYP_AESCCM_Process_IT(hcryp); - break; + /* AES CCM encryption */ + status = CRYP_AESCCM_Process_IT(hcryp); + break; - default: - hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; - status = HAL_ERROR; - break; + default: + hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; + /* Change the CRYP peripheral state */ + hcryp->State = HAL_CRYP_STATE_READY; + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + status = HAL_ERROR; + break; } #endif /*end AES or CRYP*/ @@ -1415,7 +1453,7 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input uint32_t algo; HAL_StatusTypeDef status = HAL_OK; - if(hcryp->State == HAL_CRYP_STATE_READY) + if (hcryp->State == HAL_CRYP_STATE_READY) { /* Change state Busy */ hcryp->State = HAL_CRYP_STATE_BUSY; @@ -1442,73 +1480,77 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input #if defined (CRYP) /* Set decryption operating mode*/ - MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR,CRYP_OPERATINGMODE_DECRYPT); + MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_DECRYPT); /* algo get algorithm selected */ algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE; - switch(algo) + switch (algo) { - case CRYP_DES_ECB: - case CRYP_DES_CBC: - case CRYP_TDES_ECB: - case CRYP_TDES_CBC: + case CRYP_DES_ECB: + case CRYP_DES_CBC: + case CRYP_TDES_ECB: + case CRYP_TDES_CBC: - /*Set Key */ - hcryp->Instance->K1LR = *(uint32_t*)(hcryp->Init.pKey); - hcryp->Instance->K1RR = *(uint32_t*)(hcryp->Init.pKey+1); - if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC)) - { - hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey+2); - hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+3); - hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+4); - hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+5); - } + /*Set Key */ + hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey); + hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1); + if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC)) + { + hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2); + hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3); + hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4); + hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5); + } - /* Set the Initialization Vector*/ - if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC)) - { - hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect); - hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1); - } - /* Flush FIFO */ - HAL_CRYP_FIFO_FLUSH(hcryp); + /* Set the Initialization Vector*/ + if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC)) + { + hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect); + hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1); + } + /* Flush FIFO */ + HAL_CRYP_FIFO_FLUSH(hcryp); - /* Set the phase */ - hcryp->Phase = CRYP_PHASE_PROCESS; + /* Set the phase */ + hcryp->Phase = CRYP_PHASE_PROCESS; - /* Enable interrupts */ - __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI); + /* Enable interrupts */ + __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI); - /* Enable CRYP and start DES/TDES process*/ - __HAL_CRYP_ENABLE(hcryp); + /* Enable CRYP and start DES/TDES process*/ + __HAL_CRYP_ENABLE(hcryp); - break; + break; - case CRYP_AES_ECB: - case CRYP_AES_CBC: - case CRYP_AES_CTR: + case CRYP_AES_ECB: + case CRYP_AES_CBC: + case CRYP_AES_CTR: - /* AES decryption */ - status = CRYP_AES_Decrypt_IT(hcryp); - break; + /* AES decryption */ + status = CRYP_AES_Decrypt_IT(hcryp); + break; - case CRYP_AES_GCM: + case CRYP_AES_GCM: - /* AES GCM decryption */ - status = CRYP_AESGCM_Process_IT (hcryp) ; - break; + /* AES GCM decryption */ + status = CRYP_AESGCM_Process_IT(hcryp) ; + break; - case CRYP_AES_CCM: + case CRYP_AES_CCM: - /* AES CCMdecryption */ - status = CRYP_AESCCM_Process_IT(hcryp); - break; + /* AES CCMdecryption */ + status = CRYP_AESCCM_Process_IT(hcryp); + break; - default: - hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; - status = HAL_ERROR; - break; + default: + hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; + /* Change the CRYP peripheral state */ + hcryp->State = HAL_CRYP_STATE_READY; + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + status = HAL_ERROR; + break; } #else /*AES*/ @@ -1519,32 +1561,36 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input /* algo get algorithm selected */ algo = hcryp->Instance->CR & AES_CR_CHMOD; - switch(algo) + switch (algo) { - case CRYP_AES_ECB: - case CRYP_AES_CBC: - case CRYP_AES_CTR: + case CRYP_AES_ECB: + case CRYP_AES_CBC: + case CRYP_AES_CTR: - /* AES decryption */ - status = CRYP_AES_Decrypt_IT(hcryp); - break; + /* AES decryption */ + status = CRYP_AES_Decrypt_IT(hcryp); + break; - case CRYP_AES_GCM_GMAC: + case CRYP_AES_GCM_GMAC: - /* AES GCM decryption */ - status = CRYP_AESGCM_Process_IT (hcryp) ; - break; + /* AES GCM decryption */ + status = CRYP_AESGCM_Process_IT(hcryp) ; + break; - case CRYP_AES_CCM: + case CRYP_AES_CCM: - /* AES CCM decryption */ - status = CRYP_AESCCM_Process_IT(hcryp); - break; + /* AES CCM decryption */ + status = CRYP_AESCCM_Process_IT(hcryp); + break; - default: - hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; - status = HAL_ERROR; - break; + default: + hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; + /* Change the CRYP peripheral state */ + hcryp->State = HAL_CRYP_STATE_READY; + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + status = HAL_ERROR; + break; } #endif /* End AES or CRYP */ @@ -1573,8 +1619,9 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Inpu { uint32_t algo; HAL_StatusTypeDef status = HAL_OK; + uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ - if(hcryp->State == HAL_CRYP_STATE_READY) + if (hcryp->State == HAL_CRYP_STATE_READY) { /* Change state Busy */ hcryp->State = HAL_CRYP_STATE_BUSY; @@ -1606,77 +1653,104 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Inpu /* algo get algorithm selected */ algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE; - switch(algo) + switch (algo) { - case CRYP_DES_ECB: - case CRYP_DES_CBC: - case CRYP_TDES_ECB: - case CRYP_TDES_CBC: + case CRYP_DES_ECB: + case CRYP_DES_CBC: + case CRYP_TDES_ECB: + case CRYP_TDES_CBC: - /*Set Key */ - hcryp->Instance->K1LR = *(uint32_t*)(hcryp->Init.pKey); - hcryp->Instance->K1RR = *(uint32_t*)(hcryp->Init.pKey+1); - if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC)) - { - hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey+2); - hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+3); - hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+4); - hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+5); - } + /*Set Key */ + hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey); + hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1); + if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC)) + { + hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2); + hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3); + hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4); + hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5); + } - /* Set the Initialization Vector*/ - if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC)) - { - hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect); - hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1); - } + /* Set the Initialization Vector*/ + if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC)) + { + hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect); + hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1); + } - /* Flush FIFO */ - HAL_CRYP_FIFO_FLUSH(hcryp); + /* Flush FIFO */ + HAL_CRYP_FIFO_FLUSH(hcryp); - /* Set the phase */ - hcryp->Phase = CRYP_PHASE_PROCESS; + /* Set the phase */ + hcryp->Phase = CRYP_PHASE_PROCESS; - /* Start DMA process transfer for DES/TDES */ - CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), ((uint16_t)(hcryp->Size)/4U), (uint32_t)(hcryp->pCrypOutBuffPtr)); - break; + /* Start DMA process transfer for DES/TDES */ + CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), ((uint16_t)(hcryp->Size) / 4U), + (uint32_t)(hcryp->pCrypOutBuffPtr)); + break; - case CRYP_AES_ECB: - case CRYP_AES_CBC: - case CRYP_AES_CTR: + case CRYP_AES_ECB: + case CRYP_AES_CBC: + case CRYP_AES_CTR: - /* Set the Key*/ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); + if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) + { + if (hcryp->KeyIVConfig == 1U) + { + /* If the Key and IV configuration has to be done only once + and if it has already been done, skip it */ + DoKeyIVConfig = 0U; + } + else + { + /* If the Key and IV configuration has to be done only once + and if it has not been done already, do it and set KeyIVConfig + to keep track it won't have to be done again next time */ + hcryp->KeyIVConfig = 1U; + } + } - /* Set the Initialization Vector IV */ - if (hcryp->Init.Algorithm != CRYP_AES_ECB) - { - hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect); - hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1); - hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2); - hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3); - } - /* Set the phase */ - hcryp->Phase = CRYP_PHASE_PROCESS; + if (DoKeyIVConfig == 1U) + { + /* Set the Key*/ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); - /* Start DMA process transfer for AES */ - CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), ((uint16_t)(hcryp->Size)/4U), (uint32_t)(hcryp->pCrypOutBuffPtr)); - break; + /* Set the Initialization Vector*/ + if (hcryp->Init.Algorithm != CRYP_AES_ECB) + { + hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect); + hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1U); + hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2U); + hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3U); + } + } /* if (DoKeyIVConfig == 1U) */ - case CRYP_AES_GCM: - /* AES GCM encryption */ - status = CRYP_AESGCM_Process_DMA (hcryp) ; - break; + /* Set the phase */ + hcryp->Phase = CRYP_PHASE_PROCESS; - case CRYP_AES_CCM: - /* AES CCM encryption */ - status = CRYP_AESCCM_Process_DMA(hcryp); - break; + /* Start DMA process transfer for AES */ + CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), ((uint16_t)(hcryp->Size) / 4U), + (uint32_t)(hcryp->pCrypOutBuffPtr)); + break; - default: - hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; - status = HAL_ERROR; - break; + case CRYP_AES_GCM: + /* AES GCM encryption */ + status = CRYP_AESGCM_Process_DMA(hcryp) ; + break; + + case CRYP_AES_CCM: + /* AES CCM encryption */ + status = CRYP_AESCCM_Process_DMA(hcryp); + break; + + default: + hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; + /* Change the CRYP peripheral state */ + hcryp->State = HAL_CRYP_STATE_READY; + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + status = HAL_ERROR; + break; } #else /*AES*/ @@ -1686,46 +1760,69 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Inpu /* algo get algorithm selected */ algo = hcryp->Instance->CR & AES_CR_CHMOD; - switch(algo) + switch (algo) { - case CRYP_AES_ECB: - case CRYP_AES_CBC: - case CRYP_AES_CTR: - - /* Set the Key*/ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); - - /* Set the Initialization Vector*/ - if (hcryp->Init.Algorithm != CRYP_AES_ECB) - { - hcryp->Instance->IVR3 = *(uint32_t*)(hcryp->Init.pInitVect); - hcryp->Instance->IVR2 = *(uint32_t*)(hcryp->Init.pInitVect+1); - hcryp->Instance->IVR1 = *(uint32_t*)(hcryp->Init.pInitVect+2); - hcryp->Instance->IVR0 = *(uint32_t*)(hcryp->Init.pInitVect+3); - } - - /* Set the phase */ - hcryp->Phase = CRYP_PHASE_PROCESS; - - /* Start DMA process transfer for AES */ - CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), (hcryp->Size/4U), (uint32_t)(hcryp->pCrypOutBuffPtr)); - break; + case CRYP_AES_ECB: + case CRYP_AES_CBC: + case CRYP_AES_CTR: - case CRYP_AES_GCM_GMAC: - /* AES GCM encryption */ - status = CRYP_AESGCM_Process_DMA (hcryp) ; - break; + if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) + { + if (hcryp->KeyIVConfig == 1U) + { + /* If the Key and IV configuration has to be done only once + and if it has already been done, skip it */ + DoKeyIVConfig = 0U; + } + else + { + /* If the Key and IV configuration has to be done only once + and if it has not been done already, do it and set KeyIVConfig + to keep track it won't have to be done again next time */ + hcryp->KeyIVConfig = 1U; + } + } - case CRYP_AES_CCM: - /* AES CCM encryption */ - status = CRYP_AESCCM_Process_DMA(hcryp); - break; + if (DoKeyIVConfig == 1U) + { + /* Set the Key*/ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); - default: - hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; - status = HAL_ERROR; - break; + /* Set the Initialization Vector*/ + if (hcryp->Init.Algorithm != CRYP_AES_ECB) + { + hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect); + hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1); + hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2); + hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3); + } + } /* if (DoKeyIVConfig == 1U) */ + /* Set the phase */ + hcryp->Phase = CRYP_PHASE_PROCESS; + + /* Start DMA process transfer for AES */ + CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), (uint32_t)(hcryp->pCrypOutBuffPtr)); + break; + + case CRYP_AES_GCM_GMAC: + /* AES GCM encryption */ + status = CRYP_AESGCM_Process_DMA(hcryp) ; + break; + + case CRYP_AES_CCM: + /* AES CCM encryption */ + status = CRYP_AESCCM_Process_DMA(hcryp); + break; + + default: + hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; + /* Change the CRYP peripheral state */ + hcryp->State = HAL_CRYP_STATE_READY; + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + status = HAL_ERROR; + break; } #endif /* End AES or CRYP */ @@ -1755,7 +1852,7 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Inpu uint32_t algo; HAL_StatusTypeDef status = HAL_OK; - if(hcryp->State == HAL_CRYP_STATE_READY) + if (hcryp->State == HAL_CRYP_STATE_READY) { /* Change state Busy */ @@ -1788,63 +1885,68 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Inpu /* algo get algorithm selected */ algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE; - switch(algo) + switch (algo) { - case CRYP_DES_ECB: - case CRYP_DES_CBC: - case CRYP_TDES_ECB: - case CRYP_TDES_CBC: + case CRYP_DES_ECB: + case CRYP_DES_CBC: + case CRYP_TDES_ECB: + case CRYP_TDES_CBC: - /*Set Key */ - hcryp->Instance->K1LR = *(uint32_t*)(hcryp->Init.pKey); - hcryp->Instance->K1RR = *(uint32_t*)(hcryp->Init.pKey+1); - if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC)) - { - hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey+2); - hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+3); - hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+4); - hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+5); - } + /*Set Key */ + hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey); + hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1); + if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC)) + { + hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2); + hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3); + hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4); + hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5); + } - /* Set the Initialization Vector*/ - if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC)) - { - hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect); - hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1); - } + /* Set the Initialization Vector*/ + if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC)) + { + hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect); + hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1); + } - /* Flush FIFO */ - HAL_CRYP_FIFO_FLUSH(hcryp); + /* Flush FIFO */ + HAL_CRYP_FIFO_FLUSH(hcryp); - /* Set the phase */ - hcryp->Phase = CRYP_PHASE_PROCESS; + /* Set the phase */ + hcryp->Phase = CRYP_PHASE_PROCESS; - /* Start DMA process transfer for DES/TDES */ - CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), ((uint16_t)(hcryp->Size)/4U), (uint32_t)(hcryp->pCrypOutBuffPtr)); - break; + /* Start DMA process transfer for DES/TDES */ + CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), ((uint16_t)(hcryp->Size) / 4U), + (uint32_t)(hcryp->pCrypOutBuffPtr)); + break; - case CRYP_AES_ECB: - case CRYP_AES_CBC: - case CRYP_AES_CTR: + case CRYP_AES_ECB: + case CRYP_AES_CBC: + case CRYP_AES_CTR: - /* AES decryption */ - status = CRYP_AES_Decrypt_DMA(hcryp); - break; + /* AES decryption */ + status = CRYP_AES_Decrypt_DMA(hcryp); + break; - case CRYP_AES_GCM: - /* AES GCM decryption */ - status = CRYP_AESGCM_Process_DMA (hcryp) ; - break; + case CRYP_AES_GCM: + /* AES GCM decryption */ + status = CRYP_AESGCM_Process_DMA(hcryp) ; + break; - case CRYP_AES_CCM: - /* AES CCM decryption */ - status = CRYP_AESCCM_Process_DMA(hcryp); - break; + case CRYP_AES_CCM: + /* AES CCM decryption */ + status = CRYP_AESCCM_Process_DMA(hcryp); + break; - default: - hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; - status = HAL_ERROR; - break; + default: + hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; + /* Change the CRYP peripheral state */ + hcryp->State = HAL_CRYP_STATE_READY; + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + status = HAL_ERROR; + break; } #else /*AES*/ @@ -1855,31 +1957,35 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Inpu /* algo get algorithm selected */ algo = hcryp->Instance->CR & AES_CR_CHMOD; - switch(algo) + switch (algo) { - case CRYP_AES_ECB: - case CRYP_AES_CBC: - case CRYP_AES_CTR: + case CRYP_AES_ECB: + case CRYP_AES_CBC: + case CRYP_AES_CTR: - /* AES decryption */ - status = CRYP_AES_Decrypt_DMA(hcryp); - break; + /* AES decryption */ + status = CRYP_AES_Decrypt_DMA(hcryp); + break; - case CRYP_AES_GCM_GMAC: - /* AES GCM decryption */ - status = CRYP_AESGCM_Process_DMA (hcryp) ; - break; + case CRYP_AES_GCM_GMAC: + /* AES GCM decryption */ + status = CRYP_AESGCM_Process_DMA(hcryp) ; + break; - case CRYP_AES_CCM: - /* AES CCM decryption */ - status = CRYP_AESCCM_Process_DMA(hcryp); - break; + case CRYP_AES_CCM: + /* AES CCM decryption */ + status = CRYP_AESCCM_Process_DMA(hcryp); + break; - default: - hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; - status = HAL_ERROR; - break; + default: + hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; + /* Change the CRYP peripheral state */ + hcryp->State = HAL_CRYP_STATE_READY; + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + status = HAL_ERROR; + break; } #endif /* End AES or CRYP */ } @@ -1899,8 +2005,8 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Inpu */ /** @defgroup CRYP_Exported_Functions_Group3 CRYP IRQ handler management - * @brief CRYP IRQ handler. - * + * @brief CRYP IRQ handler. + * @verbatim ============================================================================== ##### CRYP IRQ handler management ##### @@ -1927,21 +2033,25 @@ void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp) #if defined (CRYP) - if((__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI) != 0x0U) || (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI) != 0x0U)) + uint32_t itstatus = hcryp->Instance->MISR; + + if ((itstatus & (CRYP_IT_INI | CRYP_IT_OUTI)) != 0U) { - if ((hcryp->Init.Algorithm == CRYP_DES_ECB)|| (hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC)) + if ((hcryp->Init.Algorithm == CRYP_DES_ECB) || (hcryp->Init.Algorithm == CRYP_DES_CBC) + || (hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC)) { CRYP_TDES_IT(hcryp); /* DES or TDES*/ } - else if((hcryp->Init.Algorithm == CRYP_AES_ECB) || (hcryp->Init.Algorithm == CRYP_AES_CBC) || (hcryp->Init.Algorithm == CRYP_AES_CTR)) + else if ((hcryp->Init.Algorithm == CRYP_AES_ECB) || (hcryp->Init.Algorithm == CRYP_AES_CBC) + || (hcryp->Init.Algorithm == CRYP_AES_CTR)) { CRYP_AES_IT(hcryp); /*AES*/ } - else if((hcryp->Init.Algorithm == CRYP_AES_GCM) ||(hcryp->Init.Algorithm == CRYP_CR_ALGOMODE_AES_CCM) ) + else if ((hcryp->Init.Algorithm == CRYP_AES_GCM) || (hcryp->Init.Algorithm == CRYP_CR_ALGOMODE_AES_CCM)) { /* if header phase */ - if ((hcryp->Instance->CR & CRYP_PHASE_HEADER) == CRYP_PHASE_HEADER ) + if ((hcryp->Instance->CR & CRYP_PHASE_HEADER) == CRYP_PHASE_HEADER) { CRYP_GCMCCM_SetHeaderPhase_IT(hcryp); } @@ -1958,52 +2068,55 @@ void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp) } #else /*AES*/ - if((__HAL_CRYP_GET_FLAG(hcryp,CRYP_IT_CCF) != 0x0U) && (__HAL_CRYP_GET_IT_SOURCE(hcryp,CRYP_IT_CCFIE) != 0x0U)) + if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_IT_CCF) != RESET) { + if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_CCFIE) != RESET) + { - /* Clear computation complete flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp,CRYP_CCF_CLEAR); + /* Clear computation complete flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - if(hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC) - { + if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC) + { - /* if header phase */ - if ((hcryp->Instance->CR & CRYP_PHASE_HEADER) == CRYP_PHASE_HEADER ) + /* if header phase */ + if ((hcryp->Instance->CR & CRYP_PHASE_HEADER) == CRYP_PHASE_HEADER) + { + CRYP_GCMCCM_SetHeaderPhase_IT(hcryp); + } + else /* if payload phase */ + { + CRYP_GCMCCM_SetPayloadPhase_IT(hcryp); + } + } + else if (hcryp->Init.Algorithm == CRYP_AES_CCM) { - CRYP_GCMCCM_SetHeaderPhase_IT(hcryp); + /* if header phase */ + if (hcryp->Init.HeaderSize >= hcryp->CrypHeaderCount) + { + CRYP_GCMCCM_SetHeaderPhase_IT(hcryp); + } + else /* if payload phase */ + { + CRYP_GCMCCM_SetPayloadPhase_IT(hcryp); + } } - else /* if payload phase */ + else /* AES Algorithm ECB,CBC or CTR*/ { - CRYP_GCMCCM_SetPayloadPhase_IT(hcryp); + CRYP_AES_IT(hcryp); } } - else if(hcryp->Init.Algorithm == CRYP_AES_CCM) - { - /* if header phase */ - if (hcryp->Init.HeaderSize >= hcryp->CrypHeaderCount ) - { - CRYP_GCMCCM_SetHeaderPhase_IT(hcryp); - } - else /* if payload phase */ - { - CRYP_GCMCCM_SetPayloadPhase_IT(hcryp); - } - } - else /* AES Algorithm ECB,CBC or CTR*/ - { - CRYP_AES_IT(hcryp); - } - } - /* Check if error occurred */ - if (__HAL_CRYP_GET_IT_SOURCE(hcryp,CRYP_IT_ERRIE) != RESET) - { - /* If write Error occurred */ - if (__HAL_CRYP_GET_FLAG(hcryp,CRYP_IT_WRERR) != RESET) + } + /* Check if error occurred */ + if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_ERRIE) != RESET) + { + /* If write Error occurred */ + if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_IT_WRERR) != RESET) { hcryp->ErrorCode |= HAL_CRYP_ERROR_WRITE; } /* If read Error occurred */ - if (__HAL_CRYP_GET_FLAG(hcryp,CRYP_IT_RDERR) != RESET) + if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_IT_RDERR) != RESET) { hcryp->ErrorCode |= HAL_CRYP_ERROR_READ; } @@ -2071,7 +2184,7 @@ __weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp) * the configuration information for CRYP module. * @retval None */ - __weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp) +__weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp) { /* Prevent unused argument(s) compilation warning */ UNUSED(hcryp); @@ -2089,7 +2202,7 @@ __weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp) * @{ */ - #if defined (CRYP) +#if defined (CRYP) /** * @brief Encryption in ECB/CBC Algorithm with DES/TDES standard. @@ -2100,9 +2213,10 @@ __weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp) */ static HAL_StatusTypeDef CRYP_TDES_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) { - uint32_t temp; /* Temporary CrypOutBuff */ + uint32_t temp[2]; /* Temporary CrypOutBuff */ uint16_t incount; /* Temporary CrypInCount Value */ uint16_t outcount; /* Temporary CrypOutCount Value */ + uint32_t i; /* Enable CRYP */ __HAL_CRYP_ENABLE(hcryp); @@ -2110,22 +2224,22 @@ static HAL_StatusTypeDef CRYP_TDES_Process(CRYP_HandleTypeDef *hcryp, uint32_t T outcount = hcryp->CrypOutCount; /*Start processing*/ - while((hcryp->CrypInCount < (hcryp->Size/4U)) && (outcount < (hcryp->Size/4U))) + while ((hcryp->CrypInCount < (hcryp->Size / 4U)) && (outcount < (hcryp->Size / 4U))) { /* Temporary CrypInCount Value */ incount = hcryp->CrypInCount; /* Write plain data and get cipher data */ - if(((hcryp->Instance->SR & CRYP_FLAG_IFNF ) != 0x0U) && (incount < (hcryp->Size/4U))) + if (((hcryp->Instance->SR & CRYP_FLAG_IFNF) != 0x0U) && (incount < (hcryp->Size / 4U))) { /* Write the input block in the IN FIFO */ - hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; } /* Wait for OFNE flag to be raised */ - if(CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK) + if (CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK) { /* Disable the CRYP peripheral clock */ __HAL_CRYP_DISABLE(hcryp); @@ -2148,15 +2262,20 @@ static HAL_StatusTypeDef CRYP_TDES_Process(CRYP_HandleTypeDef *hcryp, uint32_t T /*Temporary CrypOutCount Value*/ outcount = hcryp->CrypOutCount; - if(((hcryp->Instance->SR & CRYP_FLAG_OFNE ) != 0x0U) && (outcount < (hcryp->Size/4U))) + if (((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U) && (outcount < (hcryp->Size / 4U))) { /* Read the output block from the Output FIFO and put them in temporary Buffer then get CrypOutBuff from temporary buffer */ - temp = hcryp->Instance->DOUT; - *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp; - hcryp->CrypOutCount++; - temp = hcryp->Instance->DOUT; - *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp; - hcryp->CrypOutCount++; + for (i = 0U; i < 2U; i++) + { + temp[i] = hcryp->Instance->DOUT; + } + i = 0U; + while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 2U)) + { + *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i]; + hcryp->CrypOutCount++; + i++; + } } /*Temporary CrypOutCount Value*/ outcount = hcryp->CrypOutCount; @@ -2180,63 +2299,74 @@ static HAL_StatusTypeDef CRYP_TDES_Process(CRYP_HandleTypeDef *hcryp, uint32_t T */ static void CRYP_TDES_IT(CRYP_HandleTypeDef *hcryp) { - uint32_t temp; /* Temporary CrypOutBuff */ + uint32_t temp[2]; /* Temporary CrypOutBuff */ + uint32_t i; - if(hcryp->State == HAL_CRYP_STATE_BUSY) + if (hcryp->State == HAL_CRYP_STATE_BUSY) { - if((__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI) != 0x0U) && (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_INRIS) != 0x0U)) - + if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI) != 0x0U) { - /* Write input block in the IN FIFO */ - hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); - hcryp->CrypInCount++; - hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); - hcryp->CrypInCount++; - - if(hcryp->CrypInCount == ((uint16_t)(hcryp->Size)/4U)) + if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_INRIS) != 0x0U) { - /* Disable interruption */ - __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI); - /* Call the input data transfer complete callback */ + /* Write input block in the IN FIFO */ + hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + + if (hcryp->CrypInCount == ((uint16_t)(hcryp->Size) / 4U)) + { + /* Disable interruption */ + __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI); + /* Call the input data transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) - /*Call registered Input complete callback*/ - hcryp->InCpltCallback(hcryp); + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); #else - /*Call legacy weak Input complete callback*/ - HAL_CRYP_InCpltCallback(hcryp); + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } } } - if((__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI) != 0x0U)&& (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_OUTRIS) != 0x0U)) + if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI) != 0x0U) { - /* Read the output block from the Output FIFO and put them in temporary Buffer then get CrypOutBuff from temporary buffer */ - temp = hcryp->Instance->DOUT; - *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp; - hcryp->CrypOutCount++; - temp = hcryp->Instance->DOUT; - *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp; - hcryp->CrypOutCount++; - if(hcryp->CrypOutCount == ((uint16_t)(hcryp->Size)/4U)) + if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_OUTRIS) != 0x0U) { - /* Disable interruption */ - __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI); + /* Read the output block from the Output FIFO and put them in temporary Buffer then get CrypOutBuff from temporary buffer */ + for (i = 0U; i < 2U; i++) + { + temp[i] = hcryp->Instance->DOUT; + } + i = 0U; + while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 2U)) + { + *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i]; + hcryp->CrypOutCount++; + i++; + } + if (hcryp->CrypOutCount == ((uint16_t)(hcryp->Size) / 4U)) + { + /* Disable interruption */ + __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI); - /* Disable CRYP */ - __HAL_CRYP_DISABLE(hcryp); + /* Disable CRYP */ + __HAL_CRYP_DISABLE(hcryp); - /* Process unlocked */ - __HAL_UNLOCK(hcryp); + /* Process unlocked */ + __HAL_UNLOCK(hcryp); - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_READY; - /* Call output transfer complete callback */ + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_READY; + /* Call output transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) - /*Call registered Output complete callback*/ - hcryp->OutCpltCallback(hcryp); + /*Call registered Output complete callback*/ + hcryp->OutCpltCallback(hcryp); #else - /*Call legacy weak Output complete callback*/ - HAL_CRYP_OutCpltCallback(hcryp); + /*Call legacy weak Output complete callback*/ + HAL_CRYP_OutCpltCallback(hcryp); #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } } } } @@ -2267,25 +2397,47 @@ static void CRYP_TDES_IT(CRYP_HandleTypeDef *hcryp) static HAL_StatusTypeDef CRYP_AES_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) { uint16_t outcount; /* Temporary CrypOutCount Value */ + uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ - /* Set the Key*/ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); + if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) + { + if (hcryp->KeyIVConfig == 1U) + { + /* If the Key and IV configuration has to be done only once + and if it has already been done, skip it */ + DoKeyIVConfig = 0U; + } + else + { + /* If the Key and IV configuration has to be done only once + and if it has not been done already, do it and set KeyIVConfig + to keep track it won't have to be done again next time */ + hcryp->KeyIVConfig = 1U; + } + } - if (hcryp->Init.Algorithm != CRYP_AES_ECB) + if (DoKeyIVConfig == 1U) { - /* Set the Initialization Vector*/ + + /* Set the Key*/ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + + if (hcryp->Init.Algorithm != CRYP_AES_ECB) + { + /* Set the Initialization Vector*/ #if defined (AES) - hcryp->Instance->IVR3 = *(uint32_t*)(hcryp->Init.pInitVect); - hcryp->Instance->IVR2 = *(uint32_t*)(hcryp->Init.pInitVect+1); - hcryp->Instance->IVR1 = *(uint32_t*)(hcryp->Init.pInitVect+2); - hcryp->Instance->IVR0 = *(uint32_t*)(hcryp->Init.pInitVect+3); + hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect); + hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1); + hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2); + hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3); #else /* CRYP */ - hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect); - hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1); - hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2); - hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3); + hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect); + hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1); + hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2); + hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3); #endif /* End AES or CRYP */ - } + } + } /* if (DoKeyIVConfig == 1U) */ /* Set the phase */ hcryp->Phase = CRYP_PHASE_PROCESS; @@ -2296,10 +2448,10 @@ static HAL_StatusTypeDef CRYP_AES_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t Ti /*Temporary CrypOutCount Value*/ outcount = hcryp->CrypOutCount; - while((hcryp->CrypInCount < (hcryp->Size/4U)) && (outcount < (hcryp->Size/4U))) + while ((hcryp->CrypInCount < (hcryp->Size / 4U)) && (outcount < (hcryp->Size / 4U))) { /* Write plain Ddta and get cipher data */ - CRYP_AES_ProcessData(hcryp,Timeout); + CRYP_AES_ProcessData(hcryp, Timeout); /*Temporary CrypOutCount Value*/ outcount = hcryp->CrypOutCount; } @@ -2322,47 +2474,69 @@ static HAL_StatusTypeDef CRYP_AES_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t Ti */ static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp) { + uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ - /* Set the Key*/ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); + if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) + { + if (hcryp->KeyIVConfig == 1U) + { + /* If the Key and IV configuration has to be done only once + and if it has already been done, skip it */ + DoKeyIVConfig = 0U; + } + else + { + /* If the Key and IV configuration has to be done only once + and if it has not been done already, do it and set KeyIVConfig + to keep track it won't have to be done again next time */ + hcryp->KeyIVConfig = 1U; + } + } - if (hcryp->Init.Algorithm != CRYP_AES_ECB) + if (DoKeyIVConfig == 1U) { - /* Set the Initialization Vector*/ + /* Set the Key*/ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + + if (hcryp->Init.Algorithm != CRYP_AES_ECB) + { + /* Set the Initialization Vector*/ #if defined (AES) - hcryp->Instance->IVR3 = *(uint32_t*)(hcryp->Init.pInitVect); - hcryp->Instance->IVR2 = *(uint32_t*)(hcryp->Init.pInitVect+1); - hcryp->Instance->IVR1 = *(uint32_t*)(hcryp->Init.pInitVect+2); - hcryp->Instance->IVR0 = *(uint32_t*)(hcryp->Init.pInitVect+3); + hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect); + hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1); + hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2); + hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3); #else /* CRYP */ - hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect); - hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1); - hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2); - hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3); + hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect); + hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1); + hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2); + hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3); #endif /* End AES or CRYP */ - } + } + } /* if (DoKeyIVConfig == 1U) */ + /* Set the phase */ hcryp->Phase = CRYP_PHASE_PROCESS; - if(hcryp->Size != 0U) + if (hcryp->Size != 0U) { #if defined (AES) /* Enable computation complete flag and error interrupts */ - __HAL_CRYP_ENABLE_IT(hcryp,CRYP_IT_CCFIE | CRYP_IT_ERRIE); + __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE); /* Enable CRYP */ __HAL_CRYP_ENABLE(hcryp); /* Write the input block in the IN FIFO */ - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; #else /* CRYP */ @@ -2394,18 +2568,76 @@ static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp) * @param Timeout: Specify Timeout value * @retval HAL status */ -static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout ) +static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) { uint16_t outcount; /* Temporary CrypOutCount Value */ + uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ - /* Key preparation for ECB/CBC */ - if (hcryp->Init.Algorithm != CRYP_AES_CTR) + if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) { -#if defined (AES) - if (hcryp->AutoKeyDerivation == DISABLE)/*Mode 2 Key preparation*/ + if (hcryp->KeyIVConfig == 1U) + { + /* If the Key and IV configuration has to be done only once + and if it has already been done, skip it */ + DoKeyIVConfig = 0U; + } + else + { + /* If the Key and IV configuration has to be done only once + and if it has not been done already, do it and set KeyIVConfig + to keep track it won't have to be done again next time */ + hcryp->KeyIVConfig = 1U; + } + } + + if (DoKeyIVConfig == 1U) + { + /* Key preparation for ECB/CBC */ + if (hcryp->Init.Algorithm != CRYP_AES_CTR) { - /* Set key preparation for decryption operating mode*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION); +#if defined (AES) + if (hcryp->AutoKeyDerivation == DISABLE)/*Mode 2 Key preparation*/ + { + /* Set key preparation for decryption operating mode*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION); + + /* Set the Key*/ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + + /* Enable CRYP */ + __HAL_CRYP_ENABLE(hcryp); + + /* Wait for CCF flag to be raised */ + if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state & error code*/ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + /* Clear CCF Flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); + + /* Return to decryption operating mode(Mode 3)*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); + } + else /*Mode 4 : decryption & Key preparation*/ + { + /* Set the Key*/ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + + /* Set decryption & Key preparation operating mode*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT); + } +#else /* CRYP */ + /* change ALGOMODE to key preparation for decryption*/ + MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_CR_ALGOMODE_AES_KEY); /* Set the Key*/ CRYP_SetKey(hcryp, hcryp->Init.KeySize); @@ -2413,13 +2645,13 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Ti /* Enable CRYP */ __HAL_CRYP_ENABLE(hcryp); - /* Wait for CCF flag to be raised */ - if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + /* Wait for BUSY flag to be raised */ + if (CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK) { /* Disable the CRYP peripheral clock */ __HAL_CRYP_DISABLE(hcryp); - /* Change state & error code*/ + /* Change state */ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; hcryp->State = HAL_CRYP_STATE_READY; @@ -2427,71 +2659,34 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Ti __HAL_UNLOCK(hcryp); return HAL_ERROR; } - /* Clear CCF Flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); + /* Turn back to ALGOMODE of the configuration */ + MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm); - /* Return to decryption operating mode(Mode 3)*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); +#endif /* End AES or CRYP */ } - else /*Mode 4 : decryption & Key preparation*/ + else /*Algorithm CTR */ { /* Set the Key*/ CRYP_SetKey(hcryp, hcryp->Init.KeySize); - - /* Set decryption & Key preparation operating mode*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT); } -#else /* CRYP */ - /* change ALGOMODE to key preparation for decryption*/ - MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_CR_ALGOMODE_AES_KEY ); - - /* Set the Key*/ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); - - /* Enable CRYP */ - __HAL_CRYP_ENABLE(hcryp); - /* Wait for BUSY flag to be raised */ - if(CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK) + /* Set IV */ + if (hcryp->Init.Algorithm != CRYP_AES_ECB) { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); - - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - /* Turn back to ALGOMODE of the configuration */ - MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm ); - -#endif /* End AES or CRYP */ - } - else /*Algorithm CTR */ - { - /* Set the Key*/ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); - } - - /* Set IV */ - if (hcryp->Init.Algorithm != CRYP_AES_ECB) - { - /* Set the Initialization Vector*/ + /* Set the Initialization Vector*/ #if defined (AES) - hcryp->Instance->IVR3 = *(uint32_t*)(hcryp->Init.pInitVect); - hcryp->Instance->IVR2 = *(uint32_t*)(hcryp->Init.pInitVect+1); - hcryp->Instance->IVR1 = *(uint32_t*)(hcryp->Init.pInitVect+2); - hcryp->Instance->IVR0 = *(uint32_t*)(hcryp->Init.pInitVect+3); + hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect); + hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1); + hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2); + hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3); #else /* CRYP */ - hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect); - hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1); - hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2); - hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3); + hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect); + hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1); + hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2); + hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3); #endif /* End AES or CRYP */ - } + } + } /* if (DoKeyIVConfig == 1U) */ /* Set the phase */ hcryp->Phase = CRYP_PHASE_PROCESS; @@ -2501,10 +2696,10 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Ti /*Temporary CrypOutCount Value*/ outcount = hcryp->CrypOutCount; - while((hcryp->CrypInCount < (hcryp->Size/4U)) && (outcount < (hcryp->Size/4U))) + while ((hcryp->CrypInCount < (hcryp->Size / 4U)) && (outcount < (hcryp->Size / 4U))) { /* Write plain data and get cipher data */ - CRYP_AES_ProcessData(hcryp,Timeout); + CRYP_AES_ProcessData(hcryp, Timeout); /*Temporary CrypOutCount Value*/ outcount = hcryp->CrypOutCount; } @@ -2527,15 +2722,80 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Ti static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp) { __IO uint32_t count = 0U; + uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ - /* Key preparation for ECB/CBC */ - if (hcryp->Init.Algorithm != CRYP_AES_CTR) + if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) { -#if defined (AES) - if (hcryp->AutoKeyDerivation == DISABLE)/*Mode 2 Key preparation*/ + if (hcryp->KeyIVConfig == 1U) + { + /* If the Key and IV configuration has to be done only once + and if it has already been done, skip it */ + DoKeyIVConfig = 0U; + } + else + { + /* If the Key and IV configuration has to be done only once + and if it has not been done already, do it and set KeyIVConfig + to keep track it won't have to be done again next time */ + hcryp->KeyIVConfig = 1U; + } + } + + if (DoKeyIVConfig == 1U) + { + /* Key preparation for ECB/CBC */ + if (hcryp->Init.Algorithm != CRYP_AES_CTR) { - /* Set key preparation for decryption operating mode*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION); +#if defined (AES) + if (hcryp->AutoKeyDerivation == DISABLE)/*Mode 2 Key preparation*/ + { + /* Set key preparation for decryption operating mode*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION); + + /* Set the Key*/ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + + /* Enable CRYP */ + __HAL_CRYP_ENABLE(hcryp); + + /* Wait for CCF flag to be raised */ + count = CRYP_TIMEOUT_KEYPREPARATION; + do + { + count-- ; + if (count == 0U) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + + /* Clear CCF Flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); + + /* Return to decryption operating mode(Mode 3)*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); + } + else /*Mode 4 : decryption & key preparation*/ + { + /* Set the Key*/ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + + /* Set decryption & key preparation operating mode*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT); + } +#else /* CRYP */ + + /* change ALGOMODE to key preparation for decryption*/ + MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_CR_ALGOMODE_AES_KEY); /* Set the Key*/ CRYP_SetKey(hcryp, hcryp->Init.KeySize); @@ -2543,16 +2803,13 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp) /* Enable CRYP */ __HAL_CRYP_ENABLE(hcryp); - /* Wait for CCF flag to be raised */ + /* Wait for BUSY flag to be raised */ count = CRYP_TIMEOUT_KEYPREPARATION; do { count-- ; - if(count == 0U) + if (count == 0U) { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); - /* Change state */ hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; hcryp->State = HAL_CRYP_STATE_READY; @@ -2561,101 +2818,59 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp) __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } - while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + } while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY)); - /* Clear CCF Flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); + /* Turn back to ALGOMODE of the configuration */ + MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm); - /* Return to decryption operating mode(Mode 3)*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); +#endif /* End AES or CRYP */ } - else /*Mode 4 : decryption & key preparation*/ + + else /*Algorithm CTR */ { /* Set the Key*/ CRYP_SetKey(hcryp, hcryp->Init.KeySize); - - /* Set decryption & key preparation operating mode*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT); } -#else /* CRYP */ - - /* change ALGOMODE to key preparation for decryption*/ - MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_CR_ALGOMODE_AES_KEY ); - - /* Set the Key*/ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); - - /* Enable CRYP */ - __HAL_CRYP_ENABLE(hcryp); - /* Wait for BUSY flag to be raised */ - count = CRYP_TIMEOUT_KEYPREPARATION; - do + /* Set IV */ + if (hcryp->Init.Algorithm != CRYP_AES_ECB) { - count-- ; - if(count == 0U) - { - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - } - while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY)); - - /* Turn back to ALGOMODE of the configuration */ - MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm ); - -#endif /* End AES or CRYP */ - } - - else /*Algorithm CTR */ - { - /* Set the Key*/ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); - } - - /* Set IV */ - if (hcryp->Init.Algorithm != CRYP_AES_ECB) - { - /* Set the Initialization Vector*/ + /* Set the Initialization Vector*/ #if defined (AES) - hcryp->Instance->IVR3 = *(uint32_t*)(hcryp->Init.pInitVect); - hcryp->Instance->IVR2 = *(uint32_t*)(hcryp->Init.pInitVect+1); - hcryp->Instance->IVR1 = *(uint32_t*)(hcryp->Init.pInitVect+2); - hcryp->Instance->IVR0 = *(uint32_t*)(hcryp->Init.pInitVect+3); + hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect); + hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1); + hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2); + hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3); #else /* CRYP */ - hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect); - hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1); - hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2); - hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3); + hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect); + hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1); + hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2); + hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3); #endif /* End AES or CRYP */ - } + } + } /* if (DoKeyIVConfig == 1U) */ + /* Set the phase */ hcryp->Phase = CRYP_PHASE_PROCESS; - if(hcryp->Size != 0U) + if (hcryp->Size != 0U) { #if defined (AES) /* Enable computation complete flag and error interrupts */ - __HAL_CRYP_ENABLE_IT(hcryp,CRYP_IT_CCFIE | CRYP_IT_ERRIE); + __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE); /* Enable CRYP */ __HAL_CRYP_ENABLE(hcryp); /* Write the input block in the IN FIFO */ - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; #else /* CRYP */ @@ -2689,28 +2904,91 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp) static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp) { __IO uint32_t count = 0U; + uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ - /* Key preparation for ECB/CBC */ - if (hcryp->Init.Algorithm != CRYP_AES_CTR) + if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) { -#if defined (AES) - if (hcryp->AutoKeyDerivation == DISABLE)/*Mode 2 key preparation*/ + if (hcryp->KeyIVConfig == 1U) { - /* Set key preparation for decryption operating mode*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION); - - /* Set the Key*/ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); - - /* Enable CRYP */ - __HAL_CRYP_ENABLE(hcryp); - - /* Wait for CCF flag to be raised */ + /* If the Key and IV configuration has to be done only once + and if it has already been done, skip it */ + DoKeyIVConfig = 0U; + } + else + { + /* If the Key and IV configuration has to be done only once + and if it has not been done already, do it and set KeyIVConfig + to keep track it won't have to be done again next time */ + hcryp->KeyIVConfig = 1U; + } + } + if (DoKeyIVConfig == 1U) + { + /* Key preparation for ECB/CBC */ + if (hcryp->Init.Algorithm != CRYP_AES_CTR) + { +#if defined (AES) + if (hcryp->AutoKeyDerivation == DISABLE)/*Mode 2 key preparation*/ + { + /* Set key preparation for decryption operating mode*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION); + + /* Set the Key*/ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + + /* Enable CRYP */ + __HAL_CRYP_ENABLE(hcryp); + + /* Wait for CCF flag to be raised */ + count = CRYP_TIMEOUT_KEYPREPARATION; + do + { + count-- ; + if (count == 0U) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + + /* Clear CCF Flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); + + /* Return to decryption operating mode(Mode 3)*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); + } + else /*Mode 4 : decryption & key preparation*/ + { + /* Set the Key*/ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + + /* Set decryption & Key preparation operating mode*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT); + } +#else /* CRYP */ + /* change ALGOMODE to key preparation for decryption*/ + MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_CR_ALGOMODE_AES_KEY); + + /* Set the Key*/ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + + /* Enable CRYP */ + __HAL_CRYP_ENABLE(hcryp); + + /* Wait for BUSY flag to be raised */ count = CRYP_TIMEOUT_KEYPREPARATION; do { count-- ; - if(count == 0U) + if (count == 0U) { /* Disable the CRYP peripheral clock */ __HAL_CRYP_DISABLE(hcryp); @@ -2723,87 +3001,43 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp) __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } - while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + } while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY)); - /* Clear CCF Flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); + /* Turn back to ALGOMODE of the configuration */ + MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm); - /* Return to decryption operating mode(Mode 3)*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); +#endif /* End AES or CRYP */ } - else /*Mode 4 : decryption & key preparation*/ + else /*Algorithm CTR */ { /* Set the Key*/ CRYP_SetKey(hcryp, hcryp->Init.KeySize); - - /* Set decryption & Key preparation operating mode*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT); } -#else /* CRYP */ - /* change ALGOMODE to key preparation for decryption*/ - MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_CR_ALGOMODE_AES_KEY ); - - /* Set the Key*/ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); - - /* Enable CRYP */ - __HAL_CRYP_ENABLE(hcryp); - /* Wait for BUSY flag to be raised */ - count = CRYP_TIMEOUT_KEYPREPARATION; - do + if (hcryp->Init.Algorithm != CRYP_AES_ECB) { - count-- ; - if(count == 0U) - { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); - - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - } - while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY)); - - /* Turn back to ALGOMODE of the configuration */ - MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm ); - -#endif /* End AES or CRYP */ - } - else /*Algorithm CTR */ - { - /* Set the Key*/ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); - } - - if (hcryp->Init.Algorithm != CRYP_AES_ECB) - { - /* Set the Initialization Vector*/ + /* Set the Initialization Vector*/ #if defined (AES) - hcryp->Instance->IVR3 = *(uint32_t*)(hcryp->Init.pInitVect); - hcryp->Instance->IVR2 = *(uint32_t*)(hcryp->Init.pInitVect+1); - hcryp->Instance->IVR1 = *(uint32_t*)(hcryp->Init.pInitVect+2); - hcryp->Instance->IVR0 = *(uint32_t*)(hcryp->Init.pInitVect+3); + hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect); + hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1); + hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2); + hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3); #else /* CRYP */ - hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect); - hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1); - hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2); - hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3); + hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect); + hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1); + hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2); + hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3); #endif /* End AES or CRYP */ - } + } + } /* if (DoKeyIVConfig == 1U) */ + /* Set the phase */ hcryp->Phase = CRYP_PHASE_PROCESS; - if(hcryp->Size != 0U) + if (hcryp->Size != 0U) { /* Set the input and output addresses and start DMA transfer */ - CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), (hcryp->Size/4U), (uint32_t)(hcryp->pCrypOutBuffPtr)); + CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), (uint32_t)(hcryp->pCrypOutBuffPtr)); } else { @@ -2826,7 +3060,7 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp) */ static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma) { - CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Disable the DMA transfer for input FIFO request by resetting the DIEN bit in the DMACR register */ @@ -2837,10 +3071,10 @@ static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma) CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAINEN); /* TinyAES2, No output on CCM AES, unlock should be done when input data process complete */ - if((hcryp->Init.Algorithm & CRYP_AES_CCM) == CRYP_AES_CCM) + if ((hcryp->Init.Algorithm & CRYP_AES_CCM) == CRYP_AES_CCM) { /* Clear CCF flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp,CRYP_CCF_CLEAR); + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); /* Change the CRYP state to ready */ hcryp->State = HAL_CRYP_STATE_READY; @@ -2867,7 +3101,7 @@ static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma) */ static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma) { - CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Disable the DMA transfer for output FIFO request by resetting the DOEN bit in the DMACR register */ @@ -2875,7 +3109,7 @@ static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma) #if defined (CRYP) hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DOEN); - if((hcryp->Init.Algorithm & CRYP_AES_GCM) != CRYP_AES_GCM) + if ((hcryp->Init.Algorithm & CRYP_AES_GCM) != CRYP_AES_GCM) { /* Disable CRYP (not allowed in GCM)*/ __HAL_CRYP_DISABLE(hcryp); @@ -2885,9 +3119,9 @@ static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma) CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAOUTEN); /* Clear CCF flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp,CRYP_CCF_CLEAR); + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - if((hcryp->Init.Algorithm & CRYP_AES_GCM_GMAC) != CRYP_AES_GCM_GMAC) + if ((hcryp->Init.Algorithm & CRYP_AES_GCM_GMAC) != CRYP_AES_GCM_GMAC) { /* Disable CRYP (not allowed in GCM)*/ __HAL_CRYP_DISABLE(hcryp); @@ -2916,10 +3150,10 @@ static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma) */ static void CRYP_DMAError(DMA_HandleTypeDef *hdma) { - CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Change the CRYP peripheral state */ - hcryp->State= HAL_CRYP_STATE_READY; + hcryp->State = HAL_CRYP_STATE_READY; /* DMA error code field */ hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA; @@ -2927,7 +3161,7 @@ static void CRYP_DMAError(DMA_HandleTypeDef *hdma) #if defined (AES) /* Clear CCF flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp,CRYP_CCF_CLEAR); + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); #endif /* AES */ @@ -2970,7 +3204,7 @@ static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uin __HAL_CRYP_ENABLE(hcryp); /* Enable the input DMA Stream */ - if ( HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DIN, Size)!=HAL_OK) + if (HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DIN, Size) != HAL_OK) { /* DMA error code field */ hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA; @@ -2985,7 +3219,7 @@ static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uin #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } /* Enable the output DMA Stream */ - if (HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUT, outputaddr, Size)!=HAL_OK) + if (HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUT, outputaddr, Size) != HAL_OK) { /* DMA error code field */ hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA; @@ -3004,14 +3238,15 @@ static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uin #else /* AES */ - if(((hcryp->Init.Algorithm & CRYP_AES_GCM_GMAC) != CRYP_AES_GCM_GMAC) && ((hcryp->Init.Algorithm & CRYP_AES_CCM) != CRYP_AES_CCM)) + if (((hcryp->Init.Algorithm & CRYP_AES_GCM_GMAC) != CRYP_AES_GCM_GMAC) + && ((hcryp->Init.Algorithm & CRYP_AES_CCM) != CRYP_AES_CCM)) { /* Enable CRYP (not allowed in GCM & CCM)*/ __HAL_CRYP_ENABLE(hcryp); } /* Enable the DMA input stream */ - if (HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DINR, Size)!=HAL_OK) + if (HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DINR, Size) != HAL_OK) { /* DMA error code field */ hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA; @@ -3026,7 +3261,7 @@ static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uin #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } /* Enable the DMA output stream */ - if (HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUTR, outputaddr, Size)!=HAL_OK) + if (HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUTR, outputaddr, Size) != HAL_OK) { /* DMA error code field */ hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA; @@ -3040,12 +3275,12 @@ static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uin HAL_CRYP_ErrorCallback(hcryp); #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } - /*AES2v1.1.1 : CCM authentication : no init phase, only header and final phase */ + /*AES2v1.1.1 : CCM authentication : no init phase, only header and final phase */ /* Enable In and Out DMA requests */ - if((hcryp->Init.Algorithm & CRYP_AES_CCM) == CRYP_AES_CCM) + if ((hcryp->Init.Algorithm & CRYP_AES_CCM) == CRYP_AES_CCM) { /* Enable only In DMA requests for CCM*/ - SET_BIT(hcryp->Instance->CR, (AES_CR_DMAINEN )); + SET_BIT(hcryp->Instance->CR, (AES_CR_DMAINEN)); } else { @@ -3065,7 +3300,8 @@ static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uin static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) { - uint32_t temp; /* Temporary CrypOutBuff */ + uint32_t temp[4]; /* Temporary CrypOutBuff */ + uint32_t i; #if defined (CRYP) uint16_t incount; /* Temporary CrypInCount Value */ uint16_t outcount; /* Temporary CrypOutCount Value */ @@ -3076,21 +3312,21 @@ static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) /*Temporary CrypOutCount Value*/ incount = hcryp->CrypInCount; - if(((hcryp->Instance->SR & CRYP_FLAG_IFNF ) != 0x0U) && (incount < (hcryp->Size/4U))) + if (((hcryp->Instance->SR & CRYP_FLAG_IFNF) != 0x0U) && (incount < (hcryp->Size / 4U))) { /* Write the input block in the IN FIFO */ - hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; } /* Wait for OFNE flag to be raised */ - if(CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK) + if (CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK) { /* Disable the CRYP peripheral clock */ __HAL_CRYP_DISABLE(hcryp); @@ -3113,37 +3349,36 @@ static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) /*Temporary CrypOutCount Value*/ outcount = hcryp->CrypOutCount; - if(((hcryp->Instance->SR & CRYP_FLAG_OFNE ) != 0x0U) && (outcount < (hcryp->Size/4U))) + if (((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U) && (outcount < (hcryp->Size / 4U))) { /* Read the output block from the Output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */ - temp = hcryp->Instance->DOUT; - *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp; - hcryp->CrypOutCount++; - temp = hcryp->Instance->DOUT; - *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp; - hcryp->CrypOutCount++; - temp = hcryp->Instance->DOUT; - *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp; - hcryp->CrypOutCount++; - temp = hcryp->Instance->DOUT; - *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp; - hcryp->CrypOutCount++; + for (i = 0U; i < 4U; i++) + { + temp[i] = hcryp->Instance->DOUT; + } + i = 0U; + while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 4U)) + { + *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i]; + hcryp->CrypOutCount++; + i++; + } } #else /* AES */ /* Write the input block in the IN FIFO */ - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; /* Wait for CCF flag to be raised */ - if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) { /* Disable the CRYP peripheral clock */ __HAL_CRYP_DISABLE(hcryp); @@ -3167,19 +3402,17 @@ static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/ - temp = hcryp->Instance->DOUTR; - *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) =temp; - hcryp->CrypOutCount++; - temp = hcryp->Instance->DOUTR; - *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) =temp; - hcryp->CrypOutCount++; - temp = hcryp->Instance->DOUTR; - *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp; - hcryp->CrypOutCount++; - temp = hcryp->Instance->DOUTR; - *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp; - hcryp->CrypOutCount++; - + for (i = 0U; i < 4U; i++) + { + temp[i] = hcryp->Instance->DOUTR; + } + i = 0U; + while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (i < 4U)) + { + *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i]; + hcryp->CrypOutCount++; + i++; + } #endif /* End AES or CRYP */ } @@ -3193,30 +3426,31 @@ static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) */ static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp) { - uint32_t temp; /* Temporary CrypOutBuff */ + uint32_t temp[4]; /* Temporary CrypOutBuff */ + uint32_t i; #if defined (CRYP) uint16_t incount; /* Temporary CrypInCount Value */ uint16_t outcount; /* Temporary CrypOutCount Value */ #endif - if(hcryp->State == HAL_CRYP_STATE_BUSY) + if (hcryp->State == HAL_CRYP_STATE_BUSY) { #if defined (CRYP) /*Temporary CrypOutCount Value*/ incount = hcryp->CrypInCount; - if(((hcryp->Instance->SR & CRYP_FLAG_IFNF ) != 0x0U) && (incount < (hcryp->Size/4U))) + if (((hcryp->Instance->SR & CRYP_FLAG_IFNF) != 0x0U) && (incount < (hcryp->Size / 4U))) { /* Write the input block in the IN FIFO */ - hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - if(hcryp->CrypInCount == ((uint16_t)(hcryp->Size)/4U)) + if (hcryp->CrypInCount == ((uint16_t)(hcryp->Size) / 4U)) { /* Disable interrupts */ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI); @@ -3234,22 +3468,21 @@ static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp) /*Temporary CrypOutCount Value*/ outcount = hcryp->CrypOutCount; - if(((hcryp->Instance->SR & CRYP_FLAG_OFNE ) != 0x0U) && (outcount < (hcryp->Size/4U))) + if (((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U) && (outcount < (hcryp->Size / 4U))) { /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */ - temp = hcryp->Instance->DOUT; - *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp; - hcryp->CrypOutCount++; - temp = hcryp->Instance->DOUT; - *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp; - hcryp->CrypOutCount++; - temp = hcryp->Instance->DOUT; - *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp; - hcryp->CrypOutCount++; - temp = hcryp->Instance->DOUT; - *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp; - hcryp->CrypOutCount++; - if(hcryp->CrypOutCount == ((uint16_t)(hcryp->Size)/4U)) + for (i = 0U; i < 4U; i++) + { + temp[i] = hcryp->Instance->DOUT; + } + i = 0U; + while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 4U)) + { + *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i]; + hcryp->CrypOutCount++; + i++; + } + if (hcryp->CrypOutCount == ((uint16_t)(hcryp->Size) / 4U)) { /* Disable interrupts */ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI); @@ -3263,13 +3496,13 @@ static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp) /* Process unlocked */ __HAL_UNLOCK(hcryp); - /* Call Output transfer complete callback */ + /* Call Output transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) - /*Call registered Output complete callback*/ - hcryp->OutCpltCallback(hcryp); + /*Call registered Output complete callback*/ + hcryp->OutCpltCallback(hcryp); #else - /*Call legacy weak Output complete callback*/ - HAL_CRYP_OutCpltCallback(hcryp); + /*Call legacy weak Output complete callback*/ + HAL_CRYP_OutCpltCallback(hcryp); #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } } @@ -3277,23 +3510,22 @@ static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp) #else /*AES*/ /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/ - temp = hcryp->Instance->DOUTR; - *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) =temp; - hcryp->CrypOutCount++; - temp = hcryp->Instance->DOUTR; - *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) =temp; - hcryp->CrypOutCount++; - temp = hcryp->Instance->DOUTR; - *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp; - hcryp->CrypOutCount++; - temp = hcryp->Instance->DOUTR; - *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp; - hcryp->CrypOutCount++; + for (i = 0U; i < 4U; i++) + { + temp[i] = hcryp->Instance->DOUTR; + } + i = 0U; + while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (i < 4U)) + { + *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i]; + hcryp->CrypOutCount++; + i++; + } - if(hcryp->CrypOutCount == (hcryp->Size/4U)) + if (hcryp->CrypOutCount == (hcryp->Size / 4U)) { /* Disable Computation Complete flag and errors interrupts */ - __HAL_CRYP_DISABLE_IT(hcryp,CRYP_IT_CCFIE|CRYP_IT_ERRIE); + __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE); /* Change the CRYP state */ hcryp->State = HAL_CRYP_STATE_READY; @@ -3316,16 +3548,16 @@ static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp) else { /* Write the input block in the IN FIFO */ - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - if(hcryp->CrypInCount == (hcryp->Size/4U)) + if (hcryp->CrypInCount == (hcryp->Size / 4U)) { /* Call Input transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) @@ -3365,58 +3597,58 @@ static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint32_t KeySize) { #if defined (CRYP) - switch(KeySize) - { - case CRYP_KEYSIZE_256B: - hcryp->Instance->K0LR = *(uint32_t*)(hcryp->Init.pKey); - hcryp->Instance->K0RR = *(uint32_t*)(hcryp->Init.pKey+1); - hcryp->Instance->K1LR = *(uint32_t*)(hcryp->Init.pKey+2); - hcryp->Instance->K1RR = *(uint32_t*)(hcryp->Init.pKey+3); - hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey+4); - hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+5); - hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+6); - hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+7); - break; - case CRYP_KEYSIZE_192B: - hcryp->Instance->K1LR = *(uint32_t*)(hcryp->Init.pKey); - hcryp->Instance->K1RR = *(uint32_t*)(hcryp->Init.pKey+1); - hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey+2); - hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+3); - hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+4); - hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+5); - break; - case CRYP_KEYSIZE_128B: - hcryp->Instance->K2LR = *(uint32_t*)(hcryp->Init.pKey); - hcryp->Instance->K2RR = *(uint32_t*)(hcryp->Init.pKey+1); - hcryp->Instance->K3LR = *(uint32_t*)(hcryp->Init.pKey+2); - hcryp->Instance->K3RR = *(uint32_t*)(hcryp->Init.pKey+3); - - break; - default: - break; + switch (KeySize) + { + case CRYP_KEYSIZE_256B: + hcryp->Instance->K0LR = *(uint32_t *)(hcryp->Init.pKey); + hcryp->Instance->K0RR = *(uint32_t *)(hcryp->Init.pKey + 1); + hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey + 2); + hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 3); + hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 4); + hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 5); + hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 6); + hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 7); + break; + case CRYP_KEYSIZE_192B: + hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey); + hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1); + hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2); + hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3); + hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4); + hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5); + break; + case CRYP_KEYSIZE_128B: + hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey); + hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 1); + hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 2); + hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 3); + + break; + default: + break; } #else /*AES*/ - switch(KeySize) - { - case CRYP_KEYSIZE_256B: - hcryp->Instance->KEYR7 =*(uint32_t*)(hcryp->Init.pKey); - hcryp->Instance->KEYR6 =*(uint32_t*)(hcryp->Init.pKey+1); - hcryp->Instance->KEYR5 =*(uint32_t*)(hcryp->Init.pKey+2); - hcryp->Instance->KEYR4 =*(uint32_t*)(hcryp->Init.pKey+3); - hcryp->Instance->KEYR3 =*(uint32_t*)(hcryp->Init.pKey+4); - hcryp->Instance->KEYR2 =*(uint32_t*)(hcryp->Init.pKey+5); - hcryp->Instance->KEYR1 =*(uint32_t*)(hcryp->Init.pKey+6); - hcryp->Instance->KEYR0 =*(uint32_t*)(hcryp->Init.pKey+7); - break; - case CRYP_KEYSIZE_128B: - hcryp->Instance->KEYR3 =*(uint32_t*)(hcryp->Init.pKey); - hcryp->Instance->KEYR2 =*(uint32_t*)(hcryp->Init.pKey+1); - hcryp->Instance->KEYR1 =*(uint32_t*)(hcryp->Init.pKey+2); - hcryp->Instance->KEYR0 =*(uint32_t*)(hcryp->Init.pKey+3); - - break; - default: - break; + switch (KeySize) + { + case CRYP_KEYSIZE_256B: + hcryp->Instance->KEYR7 = *(uint32_t *)(hcryp->Init.pKey); + hcryp->Instance->KEYR6 = *(uint32_t *)(hcryp->Init.pKey + 1); + hcryp->Instance->KEYR5 = *(uint32_t *)(hcryp->Init.pKey + 2); + hcryp->Instance->KEYR4 = *(uint32_t *)(hcryp->Init.pKey + 3); + hcryp->Instance->KEYR3 = *(uint32_t *)(hcryp->Init.pKey + 4); + hcryp->Instance->KEYR2 = *(uint32_t *)(hcryp->Init.pKey + 5); + hcryp->Instance->KEYR1 = *(uint32_t *)(hcryp->Init.pKey + 6); + hcryp->Instance->KEYR0 = *(uint32_t *)(hcryp->Init.pKey + 7); + break; + case CRYP_KEYSIZE_128B: + hcryp->Instance->KEYR3 = *(uint32_t *)(hcryp->Init.pKey); + hcryp->Instance->KEYR2 = *(uint32_t *)(hcryp->Init.pKey + 1); + hcryp->Instance->KEYR1 = *(uint32_t *)(hcryp->Init.pKey + 2); + hcryp->Instance->KEYR0 = *(uint32_t *)(hcryp->Init.pKey + 3); + + break; + default: + break; } #endif /* End AES or CRYP */ } @@ -3432,121 +3664,148 @@ static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint32_t KeySize) static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) { uint32_t tickstart; - uint32_t wordsize = (uint32_t)(hcryp->Size)/4U ; + uint32_t wordsize = (uint32_t)(hcryp->Size) / 4U ; uint16_t outcount; /* Temporary CrypOutCount Value */ + uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ - /* Reset CrypHeaderCount */ - hcryp->CrypHeaderCount = 0U; + if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) + { + if (hcryp->KeyIVConfig == 1U) + { + /* If the Key and IV configuration has to be done only once + and if it has already been done, skip it */ + DoKeyIVConfig = 0U; + hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */ + } + else + { + /* If the Key and IV configuration has to be done only once + and if it has not been done already, do it and set KeyIVConfig + to keep track it won't have to be done again next time */ + hcryp->KeyIVConfig = 1U; + hcryp->SizesSum = hcryp->Size; /* Merely store payload length */ + } + } + else + { + hcryp->SizesSum = hcryp->Size; + } + + if (DoKeyIVConfig == 1U) + { + /* Reset CrypHeaderCount */ + hcryp->CrypHeaderCount = 0U; - /****************************** Init phase **********************************/ + /****************************** Init phase **********************************/ - CRYP_SET_PHASE(hcryp,CRYP_PHASE_INIT); + CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT); - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); + /* Set the key */ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); #if defined(CRYP) - /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/ - hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect); - hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1); - hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2); - hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3); + /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/ + hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect); + hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1); + hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2); + hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3); - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); - /* Get tick */ - tickstart = HAL_GetTick(); + /* Get tick */ + tickstart = HAL_GetTick(); - /*Wait for the CRYPEN bit to be cleared*/ - while((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + /*Wait for the CRYPEN bit to be cleared*/ + while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN) { - if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U)) + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } } } - } #else /* AES */ - /* Workaround 1 : only AES. - Datatype configuration must be 32 bits during Init phase. Only, after Init, and before re - enabling the IP, datatype different from 32 bits can be configured.*/ - /* Select DATATYPE 32 */ - MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, CRYP_DATATYPE_32B); - - /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/ - hcryp->Instance->IVR3 = *(uint32_t*)(hcryp->Init.pInitVect); - hcryp->Instance->IVR2 = *(uint32_t*)(hcryp->Init.pInitVect+1); - hcryp->Instance->IVR1 = *(uint32_t*)(hcryp->Init.pInitVect+2); - hcryp->Instance->IVR0 = *(uint32_t*)(hcryp->Init.pInitVect+3); - - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); + /* Workaround 1 : only AES. + Datatype configuration must be 32 bits during Init phase. Only, after Init, and before re + enabling the IP, datatype different from 32 bits can be configured.*/ + /* Select DATATYPE 32 */ + MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, CRYP_DATATYPE_32B); + + /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/ + hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect); + hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1); + hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2); + hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3); - /* just wait for hash computation */ - if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) - { - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); - /* Process unlocked & return error */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - /* Clear CCF flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); + /* just wait for hash computation */ + if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + { + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked & return error */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + /* Clear CCF flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); #endif /* End AES or CRYP */ - /************************ Header phase *************************************/ + /************************ Header phase *************************************/ - if(CRYP_GCMCCM_SetHeaderPhase(hcryp, Timeout) != HAL_OK) - { - return HAL_ERROR; - } + if (CRYP_GCMCCM_SetHeaderPhase(hcryp, Timeout) != HAL_OK) + { + return HAL_ERROR; + } - /*************************Payload phase ************************************/ + /*************************Payload phase ************************************/ - /* Set the phase */ - hcryp->Phase = CRYP_PHASE_PROCESS; + /* Set the phase */ + hcryp->Phase = CRYP_PHASE_PROCESS; #if defined(CRYP) - /* Disable the CRYP peripheral */ - __HAL_CRYP_DISABLE(hcryp); + /* Disable the CRYP peripheral */ + __HAL_CRYP_DISABLE(hcryp); - /* Select payload phase once the header phase is performed */ - CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); + /* Select payload phase once the header phase is performed */ + CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); #else /* AES */ - /* Select payload phase once the header phase is performed */ - CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); + /* Select payload phase once the header phase is performed */ + CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); #endif /* End AES or CRYP */ + } /* if (DoKeyIVConfig == 1U) */ if ((hcryp->Size % 16U) != 0U) { /* recalculate wordsize */ - wordsize = ((wordsize/4U)*4U) ; + wordsize = ((wordsize / 4U) * 4U) ; } /* Get tick */ @@ -3555,18 +3814,18 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t outcount = hcryp->CrypOutCount; /* Write input data and get output Data */ - while((hcryp->CrypInCount < wordsize) && (outcount < wordsize)) + while ((hcryp->CrypInCount < wordsize) && (outcount < wordsize)) { /* Write plain data and get cipher data */ - CRYP_AES_ProcessData(hcryp,Timeout); + CRYP_AES_ProcessData(hcryp, Timeout); /*Temporary CrypOutCount Value*/ outcount = hcryp->CrypOutCount; /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { /* Disable the CRYP peripheral clock */ __HAL_CRYP_DISABLE(hcryp); @@ -3587,7 +3846,7 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t /* Workaround 2 : CRYP1 & AES generates correct TAG for GCM mode only when input block size is multiple of 128 bits. If lthe size of the last block of payload is inferior to 128 bits, when GCM encryption is selected, then the TAG message will be wrong.*/ - CRYP_Workaround(hcryp,Timeout); + CRYP_Workaround(hcryp, Timeout); } /* Return function status */ @@ -3603,245 +3862,271 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp) { __IO uint32_t count = 0U; + uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ #if defined(AES) uint32_t loopcounter; uint32_t lastwordsize; uint32_t npblb; #endif /* AES */ - /* Reset CrypHeaderCount */ - hcryp->CrypHeaderCount =0U; + if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) + { + if (hcryp->KeyIVConfig == 1U) + { + /* If the Key and IV configuration has to be done only once + and if it has already been done, skip it */ + DoKeyIVConfig = 0U; + hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */ + } + else + { + /* If the Key and IV configuration has to be done only once + and if it has not been done already, do it and set KeyIVConfig + to keep track it won't have to be done again next time */ + hcryp->KeyIVConfig = 1U; + hcryp->SizesSum = hcryp->Size; /* Merely store payload length */ + } + } + else + { + hcryp->SizesSum = hcryp->Size; + } + + /* Configure Key, IV and process message (header and payload) */ + if (DoKeyIVConfig == 1U) + { + /* Reset CrypHeaderCount */ + hcryp->CrypHeaderCount = 0U; - /******************************* Init phase *********************************/ + /******************************* Init phase *********************************/ - CRYP_SET_PHASE(hcryp,CRYP_PHASE_INIT); + CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT); - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); + /* Set the key */ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); #if defined(CRYP) - /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/ - hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect); - hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1); - hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2); - hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3); + /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/ + hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect); + hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1); + hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2); + hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3); - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); - /*Wait for the CRYPEN bit to be cleared*/ - count = CRYP_TIMEOUT_GCMCCMINITPHASE; - do - { - count-- ; - if(count == 0U) + /*Wait for the CRYPEN bit to be cleared*/ + count = CRYP_TIMEOUT_GCMCCMINITPHASE; + do { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); + count-- ; + if (count == 0U) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - } - while((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN); + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN); #else /* AES */ - /* Workaround 1 : only AES - Datatype configuration must be 32 bits during INIT phase. Only, after INIT, and before re - enabling the IP, datatype different from 32 bits can be configured.*/ - /* Select DATATYPE 32 */ - MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, CRYP_DATATYPE_32B); + /* Workaround 1 : only AES + Datatype configuration must be 32 bits during INIT phase. Only, after INIT, and before re + enabling the IP, datatype different from 32 bits can be configured.*/ + /* Select DATATYPE 32 */ + MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, CRYP_DATATYPE_32B); - /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/ - hcryp->Instance->IVR3 = *(uint32_t*)(hcryp->Init.pInitVect); - hcryp->Instance->IVR2 = *(uint32_t*)(hcryp->Init.pInitVect+1); - hcryp->Instance->IVR1 = *(uint32_t*)(hcryp->Init.pInitVect+2); - hcryp->Instance->IVR0 = *(uint32_t*)(hcryp->Init.pInitVect+3); + /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/ + hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect); + hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1); + hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2); + hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3); - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); - /* just wait for hash computation */ - count = CRYP_TIMEOUT_GCMCCMINITPHASE; - do - { - count-- ; - if(count == 0U) + /* just wait for hash computation */ + count = CRYP_TIMEOUT_GCMCCMINITPHASE; + do { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); + count-- ; + if (count == 0U) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - } - while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); - /* Clear CCF flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); + /* Clear CCF flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); #endif /* End AES or CRYP */ - /***************************** Header phase *********************************/ + /***************************** Header phase *********************************/ #if defined(CRYP) - /* Select header phase */ - CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); + /* Select header phase */ + CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); - /* Enable interrupts */ - __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI); + /* Enable interrupts */ + __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI); - /* Enable CRYP */ - __HAL_CRYP_ENABLE(hcryp); + /* Enable CRYP */ + __HAL_CRYP_ENABLE(hcryp); #else /* AES */ - /* Workaround 1: only AES , before re-enabling the IP, datatype can be configured*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType); + /* Workaround 1: only AES , before re-enabling the IP, datatype can be configured*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType); - /* Select header phase */ - CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); + /* Select header phase */ + CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); - /* Enable computation complete flag and error interrupts */ - __HAL_CRYP_ENABLE_IT(hcryp,CRYP_IT_CCFIE | CRYP_IT_ERRIE); + /* Enable computation complete flag and error interrupts */ + __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE); - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); - if(hcryp->Init.HeaderSize == 0U) /*header phase is skipped*/ - { - /* Set the phase */ - hcryp->Phase = CRYP_PHASE_PROCESS; + if (hcryp->Init.HeaderSize == 0U) /*header phase is skipped*/ + { + /* Set the phase */ + hcryp->Phase = CRYP_PHASE_PROCESS; - /* Select payload phase once the header phase is performed */ - MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_PAYLOAD); + /* Select payload phase once the header phase is performed */ + MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_PAYLOAD); - /* Write the payload Input block in the IN FIFO */ - if(hcryp->Size == 0U) - { - /* Disable interrupts */ - __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE| CRYP_IT_ERRIE); + /* Write the payload Input block in the IN FIFO */ + if (hcryp->Size == 0U) + { + /* Disable interrupts */ + __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE); - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_READY; + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_READY; - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - } - else if (hcryp->Size >= 16U) - { - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); - hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); - hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); - hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); - hcryp->CrypInCount++; - if(hcryp->CrypInCount == ( hcryp->Size/4U)) + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + } + else if (hcryp->Size >= 16U) { - /* Call Input transfer complete callback */ + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + if (hcryp->CrypInCount == (hcryp->Size / 4U)) + { + /* Call Input transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) - /*Call registered Input complete callback*/ - hcryp->InCpltCallback(hcryp); + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); #else - /*Call legacy weak Input complete callback*/ - HAL_CRYP_InCpltCallback(hcryp); + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } } - } - else /* Size < 16Bytes : first block is the last block*/ - { - /* Workaround not implemented*/ - /* Size should be %4 otherwise Tag will be incorrectly generated for GCM Encryption: - Workaround is implemented in polling mode, so if last block of - payload <128bit don't use CRYP_Encrypt_IT otherwise TAG is incorrectly generated for GCM Encryption. */ + else /* Size < 16Bytes : first block is the last block*/ + { + /* Workaround not implemented*/ + /* Size should be %4 otherwise Tag will be incorrectly generated for GCM Encryption: + Workaround is implemented in polling mode, so if last block of + payload <128bit don't use CRYP_Encrypt_IT otherwise TAG is incorrectly generated for GCM Encryption. */ - /* Compute the number of padding bytes in last block of payload */ - npblb = 16U- (uint32_t)(hcryp->Size); + /* Compute the number of padding bytes in last block of payload */ + npblb = 16U - (uint32_t)(hcryp->Size); - /* Number of valid words (lastwordsize) in last block */ - if ((npblb % 4U) ==0U) - { - lastwordsize = (16U-npblb)/4U; - } - else - { - lastwordsize = ((16U-npblb)/4U) +1U; - } + /* Number of valid words (lastwordsize) in last block */ + if ((npblb % 4U) == 0U) + { + lastwordsize = (16U - npblb) / 4U; + } + else + { + lastwordsize = ((16U - npblb) / 4U) + 1U; + } - /* last block optionally pad the data with zeros*/ - for(loopcounter = 0U; loopcounter < lastwordsize ; loopcounter++) + /* last block optionally pad the data with zeros*/ + for (loopcounter = 0U; loopcounter < lastwordsize ; loopcounter++) + { + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + } + while (loopcounter < 4U) + { + /* pad the data with zeros to have a complete block */ + hcryp->Instance->DINR = 0x0U; + loopcounter++; + } + } + } + else if ((hcryp->Init.HeaderSize) < 4U) + { + for (loopcounter = 0U; loopcounter < hcryp->Init.HeaderSize ; loopcounter++) { - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); - hcryp->CrypInCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; } - while(loopcounter < 4U ) + while (loopcounter < 4U) { /* pad the data with zeros to have a complete block */ hcryp->Instance->DINR = 0x0U; loopcounter++; } - } - } - else if ((hcryp->Init.HeaderSize) < 4U) - { - for(loopcounter = 0U; loopcounter < hcryp->Init.HeaderSize ; loopcounter++) - { - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - } - while(loopcounter < 4U ) - { - /* pad the data with zeros to have a complete block */ - hcryp->Instance->DINR = 0x0U; - loopcounter++; - } - /* Set the phase */ - hcryp->Phase = CRYP_PHASE_PROCESS; + /* Set the phase */ + hcryp->Phase = CRYP_PHASE_PROCESS; - /* Select payload phase once the header phase is performed */ - CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); + /* Select payload phase once the header phase is performed */ + CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); - /* Call Input transfer complete callback */ + /* Call Input transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) - /*Call registered Input complete callback*/ - hcryp->InCpltCallback(hcryp); + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); #else - /*Call legacy weak Input complete callback*/ - HAL_CRYP_InCpltCallback(hcryp); + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ - } - else if ((hcryp->Init.HeaderSize) >= 4U) - { - /* Write the input block in the IN FIFO */ - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount ); - hcryp->CrypHeaderCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount ); - hcryp->CrypHeaderCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount ); - hcryp->CrypHeaderCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount ); - hcryp->CrypHeaderCount++; - } - else - { - /* Nothing to do */ - } + } + else if ((hcryp->Init.HeaderSize) >= 4U) + { + /* Write the input block in the IN FIFO */ + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++; + } + else + { + /* Nothing to do */ + } #endif /* End AES or CRYP */ + } /* end of if (DoKeyIVConfig == 1U) */ /* Return function status */ return HAL_OK; @@ -3858,114 +4143,140 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp) { __IO uint32_t count = 0U; uint32_t wordsize; + uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ - /* Reset CrypHeaderCount */ - hcryp->CrypHeaderCount = 0U; + if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) + { + if (hcryp->KeyIVConfig == 1U) + { + /* If the Key and IV configuration has to be done only once + and if it has already been done, skip it */ + DoKeyIVConfig = 0U; + hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */ + } + else + { + /* If the Key and IV configuration has to be done only once + and if it has not been done already, do it and set KeyIVConfig + to keep track it won't have to be done again next time */ + hcryp->KeyIVConfig = 1U; + hcryp->SizesSum = hcryp->Size; /* Merely store payload length */ + } + } + else + { + hcryp->SizesSum = hcryp->Size; + } - /*************************** Init phase ************************************/ + if (DoKeyIVConfig == 1U) + { + /* Reset CrypHeaderCount */ + hcryp->CrypHeaderCount = 0U; + + /*************************** Init phase ************************************/ - CRYP_SET_PHASE(hcryp,CRYP_PHASE_INIT); + CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT); - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); + /* Set the key */ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); #if defined(CRYP) - /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/ - hcryp->Instance->IV0LR = *(uint32_t*)(hcryp->Init.pInitVect); - hcryp->Instance->IV0RR = *(uint32_t*)(hcryp->Init.pInitVect+1); - hcryp->Instance->IV1LR = *(uint32_t*)(hcryp->Init.pInitVect+2); - hcryp->Instance->IV1RR = *(uint32_t*)(hcryp->Init.pInitVect+3); + /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/ + hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect); + hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1); + hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2); + hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3); - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); - /*Wait for the CRYPEN bit to be cleared*/ - count = CRYP_TIMEOUT_GCMCCMINITPHASE; - do - { - count-- ; - if(count == 0U) + /*Wait for the CRYPEN bit to be cleared*/ + count = CRYP_TIMEOUT_GCMCCMINITPHASE; + do { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); + count-- ; + if (count == 0U) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - } - while((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN); + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN); #else /* AES */ - /*Workaround 1 : only AES - Datatype configuration must be 32 bits during Init phase. Only, after Init, and before re - enabling the IP, datatype different from 32 bits can be configured.*/ - /* Select DATATYPE 32 */ - MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, CRYP_DATATYPE_32B); + /*Workaround 1 : only AES + Datatype configuration must be 32 bits during Init phase. Only, after Init, and before re + enabling the IP, datatype different from 32 bits can be configured.*/ + /* Select DATATYPE 32 */ + MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, CRYP_DATATYPE_32B); - /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/ - hcryp->Instance->IVR3 = *(uint32_t*)(hcryp->Init.pInitVect); - hcryp->Instance->IVR2 = *(uint32_t*)(hcryp->Init.pInitVect+1); - hcryp->Instance->IVR1 = *(uint32_t*)(hcryp->Init.pInitVect+2); - hcryp->Instance->IVR0 = *(uint32_t*)(hcryp->Init.pInitVect+3); + /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/ + hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect); + hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1); + hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2); + hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3); - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); - /* just wait for hash computation */ - count = CRYP_TIMEOUT_GCMCCMINITPHASE; - do - { - count-- ; - if(count == 0U) + /* just wait for hash computation */ + count = CRYP_TIMEOUT_GCMCCMINITPHASE; + do { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); + count-- ; + if (count == 0U) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - } - while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); - /* Clear CCF flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); + /* Clear CCF flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); #endif /* End AES or CRYP */ - /************************ Header phase *************************************/ + /************************ Header phase *************************************/ - if(CRYP_GCMCCM_SetHeaderPhase_DMA(hcryp) != HAL_OK) - { - return HAL_ERROR; - } + if (CRYP_GCMCCM_SetHeaderPhase_DMA(hcryp) != HAL_OK) + { + return HAL_ERROR; + } - /************************ Payload phase ************************************/ + /************************ Payload phase ************************************/ - /* Set the phase */ - hcryp->Phase = CRYP_PHASE_PROCESS; + /* Set the phase */ + hcryp->Phase = CRYP_PHASE_PROCESS; #if defined(CRYP) - /* Disable the CRYP peripheral */ - __HAL_CRYP_DISABLE(hcryp); + /* Disable the CRYP peripheral */ + __HAL_CRYP_DISABLE(hcryp); #endif /* CRYP */ - /* Select payload phase once the header phase is performed */ - CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); + /* Select payload phase once the header phase is performed */ + CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); - if(hcryp->Size != 0U) + } /* if (DoKeyIVConfig == 1U) */ + + if (hcryp->Size != 0U) { /* CRYP1 IP V < 2.2.1 Size should be %4 otherwise Tag will be incorrectly generated for GCM Encryption: Workaround is implemented in polling mode, so if last block of @@ -3973,14 +4284,15 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp) /* Set the input and output addresses and start DMA transfer */ if ((hcryp->Size % 16U) == 0U) { - CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), (hcryp->Size/4U), (uint32_t)(hcryp->pCrypOutBuffPtr)); + CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), (uint32_t)(hcryp->pCrypOutBuffPtr)); } else /*to compute last word<128bits, otherwise it will not be encrypted/decrypted */ { - wordsize = (uint32_t)(hcryp->Size)+(16U-((uint32_t)(hcryp->Size)%16U)) ; + wordsize = (uint32_t)(hcryp->Size) + (16U - ((uint32_t)(hcryp->Size) % 16U)) ; /* Set the input and output addresses and start DMA transfer, pCrypOutBuffPtr size should be %4 */ - CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), ((uint16_t)wordsize/4U), (uint32_t)(hcryp->pCrypOutBuffPtr)); + CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), ((uint16_t)wordsize / 4U), + (uint32_t)(hcryp->pCrypOutBuffPtr)); } } else @@ -4008,185 +4320,241 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp) static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) { uint32_t tickstart; - uint32_t wordsize= (uint32_t)(hcryp->Size)/4U; + uint32_t wordsize = (uint32_t)(hcryp->Size) / 4U; uint16_t outcount; /* Temporary CrypOutCount Value */ + uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ #if defined(AES) uint32_t loopcounter; uint32_t npblb; uint32_t lastwordsize; #endif /* AES */ - /* Reset CrypHeaderCount */ - hcryp->CrypHeaderCount = 0U; + if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) + { + if (hcryp->KeyIVConfig == 1U) + { + /* If the Key and IV configuration has to be done only once + and if it has already been done, skip it */ + DoKeyIVConfig = 0U; + hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */ + } + else + { + /* If the Key and IV configuration has to be done only once + and if it has not been done already, do it and set KeyIVConfig + to keep track it won't have to be done again next time */ + hcryp->KeyIVConfig = 1U; + hcryp->SizesSum = hcryp->Size; /* Merely store payload length */ + } + } + else + { + hcryp->SizesSum = hcryp->Size; + } + + if (DoKeyIVConfig == 1U) + { + + /* Reset CrypHeaderCount */ + hcryp->CrypHeaderCount = 0U; #if defined(CRYP) - /********************** Init phase ******************************************/ + /********************** Init phase ******************************************/ - CRYP_SET_PHASE(hcryp,CRYP_PHASE_INIT); + CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT); - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); + /* Set the key */ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); - /* Set the initialization vector (IV) with CTR1 information */ - hcryp->Instance->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0; - hcryp->Instance->IV0RR = hcryp->Init.B0[1]; - hcryp->Instance->IV1LR = hcryp->Init.B0[2]; - hcryp->Instance->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1)| CRYP_CCM_CTR1_2; + /* Set the initialization vector (IV) with CTR1 information */ + hcryp->Instance->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0; + hcryp->Instance->IV0RR = hcryp->Init.B0[1]; + hcryp->Instance->IV1LR = hcryp->Init.B0[2]; + hcryp->Instance->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1) | CRYP_CCM_CTR1_2; - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); - /*Write B0 packet into CRYP_DIN Register*/ - if(hcryp->Init.DataType == CRYP_DATATYPE_8B) - { - hcryp->Instance->DIN = __REV(*(uint32_t*)(hcryp->Init.B0)); - hcryp->Instance->DIN = __REV( *(uint32_t*)(hcryp->Init.B0+1)); - hcryp->Instance->DIN = __REV(*(uint32_t*)(hcryp->Init.B0+2)); - hcryp->Instance->DIN = __REV(*(uint32_t*)(hcryp->Init.B0+3)); - } - else if(hcryp->Init.DataType == CRYP_DATATYPE_16B) - { - hcryp->Instance->DIN = __ROR(*(uint32_t*)(hcryp->Init.B0), 16); - hcryp->Instance->DIN = __ROR( *(uint32_t*)(hcryp->Init.B0+1), 16); - hcryp->Instance->DIN = __ROR(*(uint32_t*)(hcryp->Init.B0+2), 16); - hcryp->Instance->DIN = __ROR(*(uint32_t*)(hcryp->Init.B0+3), 16); - } - else if(hcryp->Init.DataType == CRYP_DATATYPE_1B) - { - hcryp->Instance->DIN = __RBIT(*(uint32_t*)(hcryp->Init.B0)); - hcryp->Instance->DIN = __RBIT( *(uint32_t*)(hcryp->Init.B0+1)); - hcryp->Instance->DIN = __RBIT(*(uint32_t*)(hcryp->Init.B0+2)); - hcryp->Instance->DIN = __RBIT(*(uint32_t*)(hcryp->Init.B0+3)); - } - else - { - hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0); - hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0+1); - hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0+2); - hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0+3); - } - /* Get tick */ - tickstart = HAL_GetTick(); + /*Write B0 packet into CRYP_DIN Register*/ + if (hcryp->Init.DataType == CRYP_DATATYPE_8B) + { + hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0)); + hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 1)); + hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 2)); + hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 3)); + } + else if (hcryp->Init.DataType == CRYP_DATATYPE_16B) + { + hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0), 16); + hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 1), 16); + hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 2), 16); + hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 3), 16); + } + else if (hcryp->Init.DataType == CRYP_DATATYPE_1B) + { + hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0)); + hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 1)); + hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 2)); + hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 3)); + } + else + { + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 1); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 2); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 3); + } + /* Get tick */ + tickstart = HAL_GetTick(); - /*Wait for the CRYPEN bit to be cleared*/ - while((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + /*Wait for the CRYPEN bit to be cleared*/ + while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN) { - if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U)) + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } } } - } #else /* AES */ - /*AES2v1.1.1 : CCM authentication : no init phase, only header and final phase */ - /* Select header phase */ - CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); + /*AES2v1.1.1 : CCM authentication : no init phase, only header and final phase */ + /* Select header phase */ + CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); - /* configured encryption mode */ - MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT); + /* configured encryption mode */ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT); - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); + /* Set the key */ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); - /* Set the initialization vector with zero values*/ - hcryp->Instance->IVR3 = 0U; - hcryp->Instance->IVR2 = 0U; - hcryp->Instance->IVR1 = 0U; - hcryp->Instance->IVR0 = 0U; + /* Set the initialization vector with zero values*/ + hcryp->Instance->IVR3 = 0U; + hcryp->Instance->IVR2 = 0U; + hcryp->Instance->IVR1 = 0U; + hcryp->Instance->IVR0 = 0U; - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); - /*Write the B0 packet into CRYP_DIN*/ - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0); - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0+1); - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0+2); - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0+3); + /*Write the B0 packet into CRYP_DIN*/ + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 1); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 2); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 3); - /* wait until the end of computation */ - if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) - { - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; + /* wait until the end of computation */ + if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + { + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; - /* Process unlocked & return error */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - /* Clear CCF flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); + /* Process unlocked & return error */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + /* Clear CCF flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - /* Set the phase */ - hcryp->Phase = CRYP_PHASE_PROCESS; + /* Set the phase */ + hcryp->Phase = CRYP_PHASE_PROCESS; - /* From that point the whole message must be processed, first the Header then the payload. - First the Header block(B1) : associated data length expressed in bytes concatenated with Associated Data (A)*/ + /* From that point the whole message must be processed, first the Header then the payload. + First the Header block(B1) : associated data length expressed in bytes concatenated with Associated Data (A)*/ - if (hcryp->Init.HeaderSize != 0U) - { - if ((hcryp->Init.HeaderSize %4U )== 0U) + if (hcryp->Init.HeaderSize != 0U) { - /* HeaderSize %4, no padding */ - for(loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter+=4U) + if ((hcryp->Init.HeaderSize % 4U) == 0U) { - /* Write the Input block in the Data Input register */ - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - - if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + /* HeaderSize %4, no padding */ + for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U) { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); + /* Write the Input block in the Data Input register */ + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + + if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + /* Clear CCF Flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); } - /* Clear CCF Flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); } - } - else - { - /*Write Header block in the IN FIFO without last block */ - for(loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize)-(hcryp->Init.HeaderSize %4U ))); loopcounter+=4U) + else { - /* Write the input block in the data input register */ - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; + /*Write Header block in the IN FIFO without last block */ + for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U))); loopcounter += 4U) + { + /* Write the input block in the data input register */ + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + + if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + /* Clear CCF Flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); + } + /* Last block optionally pad the data with zeros*/ + for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++) + { + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + } + while (loopcounter < 4U) + { + /* Pad the data with zeros to have a complete block */ + hcryp->Instance->DINR = 0x0U; + loopcounter++; + } - if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) { /* Disable the CRYP peripheral clock */ __HAL_CRYP_DISABLE(hcryp); @@ -4199,39 +4567,11 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t __HAL_UNLOCK(hcryp); return HAL_ERROR; } - /* Clear CCF Flag */ + /* Clear CCF flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); } - /* Last block optionally pad the data with zeros*/ - for(loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize %4U )); loopcounter++) - { - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - } - while(loopcounter <4U ) - { - /* Pad the data with zeros to have a complete block */ - hcryp->Instance->DINR = 0x0U; - loopcounter++; - } - - if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) - { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); - - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - /* Clear CCF flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); } - } + } /* if (DoKeyIVConfig == 1U) */ /* Then the payload: cleartext payload (not the ciphertext payload). Write input Data, no output Data to get */ if (hcryp->Size != 0U) @@ -4239,7 +4579,7 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t if ((hcryp->Size % 16U) != 0U) { /* recalculate wordsize */ - wordsize = ((wordsize/4U)*4U) ; + wordsize = ((wordsize / 4U) * 4U) ; } /* Get tick */ @@ -4247,18 +4587,18 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t /*Temporary CrypOutCount Value*/ outcount = hcryp->CrypOutCount; - while((hcryp->CrypInCount < wordsize) && (outcount < wordsize)) + while ((hcryp->CrypInCount < wordsize) && (outcount < wordsize)) { /* Write plain data and get cipher data */ - CRYP_AES_ProcessData(hcryp,Timeout); + CRYP_AES_ProcessData(hcryp, Timeout); - /*Temporary CrypOutCount Value*/ - outcount = hcryp->CrypOutCount; + /*Temporary CrypOutCount Value*/ + outcount = hcryp->CrypOutCount; /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { /* Disable the CRYP peripheral clock */ __HAL_CRYP_DISABLE(hcryp); @@ -4277,32 +4617,32 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t if ((hcryp->Size % 16U) != 0U) { /* Compute the number of padding bytes in last block of payload */ - npblb = ((((uint32_t)(hcryp->Size)/16U)+1U)*16U)- (uint32_t)(hcryp->Size); + npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size); /* Number of valid words (lastwordsize) in last block */ - if ((npblb%4U) ==0U) + if ((npblb % 4U) == 0U) { - lastwordsize = (16U-npblb)/4U; + lastwordsize = (16U - npblb) / 4U; } else { - lastwordsize = ((16U-npblb)/4U) +1U; + lastwordsize = ((16U - npblb) / 4U) + 1U; } /* Last block optionally pad the data with zeros*/ - for(loopcounter=0U; loopcounter < lastwordsize; loopcounter ++) + for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter ++) { /* Write the last input block in the IN FIFO */ - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; } - while(loopcounter < 4U) + while (loopcounter < 4U) { /* Pad the data with zeros to have a complete block */ hcryp->Instance->DINR = 0U; loopcounter++; } /* Wait for CCF flag to be raised */ - if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) { /* Disable the CRYP peripheral clock */ __HAL_CRYP_DISABLE(hcryp); @@ -4324,33 +4664,35 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t #if defined(CRYP) - /************************* Header phase *************************************/ - /* Header block(B1) : associated data length expressed in bytes concatenated - with Associated Data (A)*/ + /************************* Header phase *************************************/ + /* Header block(B1) : associated data length expressed in bytes concatenated + with Associated Data (A)*/ - if(CRYP_GCMCCM_SetHeaderPhase(hcryp, Timeout) != HAL_OK) - { - return HAL_ERROR; - } + if (CRYP_GCMCCM_SetHeaderPhase(hcryp, Timeout) != HAL_OK) + { + return HAL_ERROR; + } - /********************** Payload phase ***************************************/ + /********************** Payload phase ***************************************/ - /* Set the phase */ - hcryp->Phase = CRYP_PHASE_PROCESS; + /* Set the phase */ + hcryp->Phase = CRYP_PHASE_PROCESS; - /* Disable the CRYP peripheral */ - __HAL_CRYP_DISABLE(hcryp); + /* Disable the CRYP peripheral */ + __HAL_CRYP_DISABLE(hcryp); - /* Select payload phase once the header phase is performed */ - CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); + /* Select payload phase once the header phase is performed */ + CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); + + } /* if (DoKeyIVConfig == 1U) */ if ((hcryp->Size % 16U) != 0U) { /* recalculate wordsize */ - wordsize = ((wordsize/4U)*4U) ; + wordsize = ((wordsize / 4U) * 4U) ; } /* Get tick */ tickstart = HAL_GetTick(); @@ -4358,15 +4700,15 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t outcount = hcryp->CrypOutCount; /* Write input data and get output data */ - while((hcryp->CrypInCount < wordsize) && (outcount < wordsize)) + while ((hcryp->CrypInCount < wordsize) && (outcount < wordsize)) { /* Write plain data and get cipher data */ - CRYP_AES_ProcessData(hcryp,Timeout); + CRYP_AES_ProcessData(hcryp, Timeout); /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { /* Disable the CRYP peripheral clock */ __HAL_CRYP_DISABLE(hcryp); @@ -4387,7 +4729,7 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t /* CRYP Workaround : CRYP1 generates correct TAG during CCM decryption only when ciphertext blocks size is multiple of 128 bits. If lthe size of the last block of payload is inferior to 128 bits, when CCM decryption is selected, then the TAG message will be wrong.*/ - CRYP_Workaround(hcryp,Timeout); + CRYP_Workaround(hcryp, Timeout); } #endif /* CRYP */ @@ -4404,83 +4746,111 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t */ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp) { + uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ #if defined(CRYP) __IO uint32_t count = 0U; #endif /* CRYP */ - /* Reset CrypHeaderCount */ - hcryp->CrypHeaderCount = 0U; + if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) + { + if (hcryp->KeyIVConfig == 1U) + { + /* If the Key and IV configuration has to be done only once + and if it has already been done, skip it */ + DoKeyIVConfig = 0U; + hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */ + } + else + { + /* If the Key and IV configuration has to be done only once + and if it has not been done already, do it and set KeyIVConfig + to keep track it won't have to be done again next time */ + hcryp->KeyIVConfig = 1U; + hcryp->SizesSum = hcryp->Size; /* Merely store payload length */ + } + } + else + { + hcryp->SizesSum = hcryp->Size; + } + + /* Configure Key, IV and process message (header and payload) */ + if (DoKeyIVConfig == 1U) + { + /* Reset CrypHeaderCount */ + hcryp->CrypHeaderCount = 0U; #if defined(CRYP) - /************ Init phase ************/ + /************ Init phase ************/ - CRYP_SET_PHASE(hcryp,CRYP_PHASE_INIT); + CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT); - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); + /* Set the key */ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); - /* Set the initialization vector (IV) with CTR1 information */ - hcryp->Instance->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0; - hcryp->Instance->IV0RR = hcryp->Init.B0[1]; - hcryp->Instance->IV1LR = hcryp->Init.B0[2]; - hcryp->Instance->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1)| CRYP_CCM_CTR1_2; + /* Set the initialization vector (IV) with CTR1 information */ + hcryp->Instance->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0; + hcryp->Instance->IV0RR = hcryp->Init.B0[1]; + hcryp->Instance->IV1LR = hcryp->Init.B0[2]; + hcryp->Instance->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1) | CRYP_CCM_CTR1_2; - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); - /*Write the B0 packet into CRYP_DIN Register*/ - if(hcryp->Init.DataType == CRYP_DATATYPE_8B) - { - hcryp->Instance->DIN = __REV(*(uint32_t*)(hcryp->Init.B0)); - hcryp->Instance->DIN = __REV( *(uint32_t*)(hcryp->Init.B0+1)); - hcryp->Instance->DIN = __REV(*(uint32_t*)(hcryp->Init.B0+2)); - hcryp->Instance->DIN = __REV(*(uint32_t*)(hcryp->Init.B0+3)); - } - else if(hcryp->Init.DataType == CRYP_DATATYPE_16B) - { - hcryp->Instance->DIN = __ROR(*(uint32_t*)(hcryp->Init.B0), 16); - hcryp->Instance->DIN = __ROR( *(uint32_t*)(hcryp->Init.B0+1), 16); - hcryp->Instance->DIN = __ROR(*(uint32_t*)(hcryp->Init.B0+2), 16); - hcryp->Instance->DIN = __ROR(*(uint32_t*)(hcryp->Init.B0+3), 16); - } - else if(hcryp->Init.DataType == CRYP_DATATYPE_1B) - { - hcryp->Instance->DIN = __RBIT(*(uint32_t*)(hcryp->Init.B0)); - hcryp->Instance->DIN = __RBIT( *(uint32_t*)(hcryp->Init.B0+1)); - hcryp->Instance->DIN = __RBIT(*(uint32_t*)(hcryp->Init.B0+2)); - hcryp->Instance->DIN = __RBIT(*(uint32_t*)(hcryp->Init.B0+3)); - } - else - { - hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0); - hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0+1); - hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0+2); - hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0+3); - } - /*Wait for the CRYPEN bit to be cleared*/ - count = CRYP_TIMEOUT_GCMCCMINITPHASE; - do - { - count-- ; - if(count == 0U) + /*Write the B0 packet into CRYP_DIN Register*/ + if (hcryp->Init.DataType == CRYP_DATATYPE_8B) { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); + hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0)); + hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 1)); + hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 2)); + hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 3)); + } + else if (hcryp->Init.DataType == CRYP_DATATYPE_16B) + { + hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0), 16); + hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 1), 16); + hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 2), 16); + hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 3), 16); + } + else if (hcryp->Init.DataType == CRYP_DATATYPE_1B) + { + hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0)); + hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 1)); + hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 2)); + hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 3)); + } + else + { + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 1); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 2); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 3); + } + /*Wait for the CRYPEN bit to be cleared*/ + count = CRYP_TIMEOUT_GCMCCMINITPHASE; + do + { + count-- ; + if (count == 0U) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - } - while((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN); + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN); - /* Select header phase */ - CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); + /* Select header phase */ + CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); + + } /* end of if (DoKeyIVConfig == 1U) */ /* Enable interrupts */ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI); @@ -4490,33 +4860,34 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp) #else /* AES */ - /*AES2v1.1.1 : CCM authentication : no init phase, only header and final phase */ - /* Select header phase */ - CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); + /*AES2v1.1.1 : CCM authentication : no init phase, only header and final phase */ + /* Select header phase */ + CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); - /* configured mode and encryption mode */ - MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT); + /* configured mode and encryption mode */ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT); - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); + /* Set the key */ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); - /* Set the initialization vector with zero values*/ - hcryp->Instance->IVR3 = 0U; - hcryp->Instance->IVR2 = 0U; - hcryp->Instance->IVR1 = 0U; - hcryp->Instance->IVR0 = 0U; + /* Set the initialization vector with zero values*/ + hcryp->Instance->IVR3 = 0U; + hcryp->Instance->IVR2 = 0U; + hcryp->Instance->IVR1 = 0U; + hcryp->Instance->IVR0 = 0U; - /* Enable interrupts */ - __HAL_CRYP_ENABLE_IT(hcryp,CRYP_IT_CCFIE | CRYP_IT_ERRIE); - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); + /* Enable interrupts */ + __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE); + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); - /*Write the B0 packet into CRYP_DIN*/ - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0); - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0+1); - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0+2); - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0+3); + /*Write the B0 packet into CRYP_DIN*/ + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 1); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 2); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 3); + } /* end of if (DoKeyIVConfig == 1U) */ #endif /* End AES or CRYP */ /* Return function status */ @@ -4533,155 +4904,380 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp) { uint32_t wordsize; __IO uint32_t count = 0U; + uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ +#if defined(AES) + uint32_t loopcounter; + uint32_t npblb; + uint32_t lastwordsize; +#endif + + if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) + { + if (hcryp->KeyIVConfig == 1U) + { + /* If the Key and IV configuration has to be done only once + and if it has already been done, skip it */ + DoKeyIVConfig = 0U; + hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */ + } + else + { + /* If the Key and IV configuration has to be done only once + and if it has not been done already, do it and set KeyIVConfig + to keep track it won't have to be done again next time */ + hcryp->KeyIVConfig = 1U; + hcryp->SizesSum = hcryp->Size; /* Merely store payload length */ + } + } + else + { + hcryp->SizesSum = hcryp->Size; + } + + if (DoKeyIVConfig == 1U) + { - /* Reset CrypHeaderCount */ - hcryp->CrypHeaderCount = 0U; + /* Reset CrypHeaderCount */ + hcryp->CrypHeaderCount = 0U; #if defined(CRYP) - /************************** Init phase **************************************/ + /************************** Init phase **************************************/ - CRYP_SET_PHASE(hcryp,CRYP_PHASE_INIT); + CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT); - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); + /* Set the key */ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); - /* Set the initialization vector (IV) with CTR1 information */ - hcryp->Instance->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0; - hcryp->Instance->IV0RR = hcryp->Init.B0[1]; - hcryp->Instance->IV1LR = hcryp->Init.B0[2]; - hcryp->Instance->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1)| CRYP_CCM_CTR1_2; + /* Set the initialization vector (IV) with CTR1 information */ + hcryp->Instance->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0; + hcryp->Instance->IV0RR = hcryp->Init.B0[1]; + hcryp->Instance->IV1LR = hcryp->Init.B0[2]; + hcryp->Instance->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1) | CRYP_CCM_CTR1_2; - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); - /*Write the B0 packet into CRYP_DIN Register*/ - if(hcryp->Init.DataType == CRYP_DATATYPE_8B) - { - hcryp->Instance->DIN = __REV(*(uint32_t*)(hcryp->Init.B0)); - hcryp->Instance->DIN = __REV( *(uint32_t*)(hcryp->Init.B0+1)); - hcryp->Instance->DIN = __REV(*(uint32_t*)(hcryp->Init.B0+2)); - hcryp->Instance->DIN = __REV(*(uint32_t*)(hcryp->Init.B0+3)); - } - else if(hcryp->Init.DataType == CRYP_DATATYPE_16B) - { - hcryp->Instance->DIN = __ROR(*(uint32_t*)(hcryp->Init.B0), 16); - hcryp->Instance->DIN = __ROR( *(uint32_t*)(hcryp->Init.B0+1), 16); - hcryp->Instance->DIN = __ROR(*(uint32_t*)(hcryp->Init.B0+2), 16); - hcryp->Instance->DIN = __ROR(*(uint32_t*)(hcryp->Init.B0+3), 16); - } - else if(hcryp->Init.DataType == CRYP_DATATYPE_1B) - { - hcryp->Instance->DIN = __RBIT(*(uint32_t*)(hcryp->Init.B0)); - hcryp->Instance->DIN = __RBIT( *(uint32_t*)(hcryp->Init.B0+1)); - hcryp->Instance->DIN = __RBIT(*(uint32_t*)(hcryp->Init.B0+2)); - hcryp->Instance->DIN = __RBIT(*(uint32_t*)(hcryp->Init.B0+3)); - } - else - { - hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0); - hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0+1); - hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0+2); - hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.B0+3); - } + /*Write the B0 packet into CRYP_DIN Register*/ + if (hcryp->Init.DataType == CRYP_DATATYPE_8B) + { + hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0)); + hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 1)); + hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 2)); + hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 3)); + } + else if (hcryp->Init.DataType == CRYP_DATATYPE_16B) + { + hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0), 16); + hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 1), 16); + hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 2), 16); + hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 3), 16); + } + else if (hcryp->Init.DataType == CRYP_DATATYPE_1B) + { + hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0)); + hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 1)); + hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 2)); + hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 3)); + } + else + { + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 1); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 2); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 3); + } - /*Wait for the CRYPEN bit to be cleared*/ - count = CRYP_TIMEOUT_GCMCCMINITPHASE; - do - { - count-- ; - if(count == 0U) + /*Wait for the CRYPEN bit to be cleared*/ + count = CRYP_TIMEOUT_GCMCCMINITPHASE; + do { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); + count-- ; + if (count == 0U) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - } - while((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN); + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN); #else /* AES */ - /*AES2v1.1.1 : CCM authentication : no init phase, only header and final phase */ - /* Select header phase */ - CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); + /*AES2v1.1.1 : CCM authentication : no init phase, only header and final phase */ + /* Select header phase */ + CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); + + /* configured encryption mode */ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT); + + /* Set the key */ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + + /* Set the initialization vector with zero values*/ + hcryp->Instance->IVR3 = 0U; + hcryp->Instance->IVR2 = 0U; + hcryp->Instance->IVR1 = 0U; + hcryp->Instance->IVR0 = 0U; + + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); + + /*Write the B0 packet into CRYP_DIN*/ + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 1); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 2); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 3); + + count = CRYP_TIMEOUT_GCMCCMINITPHASE; + do + { + count-- ; + if (count == 0U) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + /* Clear CCF flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - /* configured CCM chaining mode and encryption mode */ - MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT); + /* Set the phase */ + hcryp->Phase = CRYP_PHASE_PROCESS; - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); + /* From that point the whole message must be processed, first the Header then the payload. + First the Header block(B1) : associated data length expressed in bytes concatenated with Associated Data (A)*/ - /* Set the initialization vector with zero values*/ - hcryp->Instance->IVR3 = 0U; - hcryp->Instance->IVR2 = 0U; - hcryp->Instance->IVR1 = 0U; - hcryp->Instance->IVR0 = 0U; + if (hcryp->Init.HeaderSize != 0U) + { + if ((hcryp->Init.HeaderSize % 4U) == 0U) + { + /* HeaderSize %4, no padding */ + for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U) + { + /* Write the Input block in the Data Input register */ + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + + /* wait until the end of computation */ + count = CRYP_TIMEOUT_GCMCCMINITPHASE; + do + { + count-- ; + if (count == 0U) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + /* Clear CCF flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); + } + } + else + { + /*Write Header block in the IN FIFO without last block */ + for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U))); loopcounter += 4U) + { + /* Write the input block in the data input register */ + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + + count = CRYP_TIMEOUT_GCMCCMINITPHASE; + do + { + count-- ; + if (count == 0U) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + /* Clear CCF flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); + } + /* Last block optionally pad the data with zeros*/ + for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++) + { + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + } + while (loopcounter < 4U) + { + /* Pad the data with zeros to have a complete block */ + hcryp->Instance->DINR = 0x0U; + loopcounter++; + } - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); + count = CRYP_TIMEOUT_GCMCCMINITPHASE; + do + { + count-- ; + if (count == 0U) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); - /*Write the B0 packet into CRYP_DIN*/ - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0); - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0+1); - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0+2); - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.B0+3); + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; - /* wait until the end of computation */ - count = CRYP_TIMEOUT_GCMCCMINITPHASE; - do + /* Process Unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + /* Clear CCF flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); + } + } + } /* if (DoKeyIVConfig == 1U) */ + /* Then the payload: cleartext payload (not the ciphertext payload). + Write input Data, no output Data to get */ + if (hcryp->Size != 0U) { - count-- ; - if(count == 0U) -{ - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); + if (hcryp->Size >= 16U) + { + if ((hcryp->Size % 16U) == 0U) + { + CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), (uint32_t)(hcryp->pCrypOutBuffPtr)); + } + else /*to compute last word<128bits, otherwise it will not be encrypted/decrypted */ + { + wordsize = (uint32_t)(hcryp->Size) + (16U - ((uint32_t)(hcryp->Size) % 16U)) ; - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; + /* Set the input and output addresses and start DMA transfer, pCrypOutBuffPtr size should be %4 */ + CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), ((uint16_t)wordsize / 4U), + (uint32_t)(hcryp->pCrypOutBuffPtr)); + } + } + if ((hcryp->Size < 16U) != 0U) + { + /* Compute the number of padding bytes in last block of payload */ + npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size); - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; -} - } - while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + /* Number of valid words (lastwordsize) in last block */ + if ((npblb % 4U) == 0U) + { + lastwordsize = (16U - npblb) / 4U; + } + else + { + lastwordsize = ((16U - npblb) / 4U) + 1U; + } + /* Last block optionally pad the data with zeros*/ + for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter ++) + { + /* Write the last input block in the IN FIFO */ + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + } + while (loopcounter < 4U) + { + /* Pad the data with zeros to have a complete block */ + hcryp->Instance->DINR = 0U; + loopcounter++; + } + count = CRYP_TIMEOUT_GCMCCMINITPHASE; + do + { + count-- ; + if (count == 0U) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); - /* Clear CCF flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; -#endif /* AES */ + /* Process Unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + /* Clear CCF flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - /********************* Header phase *****************************************/ + /* Process unlocked */ + __HAL_UNLOCK(hcryp); - if(CRYP_GCMCCM_SetHeaderPhase_DMA(hcryp) != HAL_OK) - { - return HAL_ERROR; + /* Change the CRYP state and phase */ + hcryp->State = HAL_CRYP_STATE_READY; + } } + else + { + /* Process unLocked */ + __HAL_UNLOCK(hcryp); - /******************** Payload phase *****************************************/ + /* Change the CRYP state and phase */ + hcryp->State = HAL_CRYP_STATE_READY; + } +#endif /* AES */ +#if defined(CRYP) + /********************* Header phase *****************************************/ - /* Set the phase */ - hcryp->Phase = CRYP_PHASE_PROCESS; + if (CRYP_GCMCCM_SetHeaderPhase_DMA(hcryp) != HAL_OK) + { + return HAL_ERROR; + } -#if defined(CRYP) + /******************** Payload phase *****************************************/ - /* Disable the CRYP peripheral */ - __HAL_CRYP_DISABLE(hcryp); + /* Set the phase */ + hcryp->Phase = CRYP_PHASE_PROCESS; - /* Select payload phase once the header phase is performed */ - CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); + /* Disable the CRYP peripheral */ + __HAL_CRYP_DISABLE(hcryp); -#endif /* CRYP */ + /* Select payload phase once the header phase is performed */ + CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); - if(hcryp->Size != 0U) + } /* if (DoKeyIVConfig == 1U) */ + if (hcryp->Size != 0U) { /* Size should be %4 otherwise Tag will be incorrectly generated for GCM Encryption & CCM Decryption Workaround is implemented in polling mode, so if last block of @@ -4689,14 +5285,15 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp) /* Set the input and output addresses and start DMA transfer */ if ((hcryp->Size % 16U) == 0U) { - CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), hcryp->Size/4U, (uint32_t)(hcryp->pCrypOutBuffPtr)); + CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), hcryp->Size / 4U, (uint32_t)(hcryp->pCrypOutBuffPtr)); } else { - wordsize = (uint32_t)(hcryp->Size)+16U-((uint32_t)(hcryp->Size) %16U) ; + wordsize = (uint32_t)(hcryp->Size) + 16U - ((uint32_t)(hcryp->Size) % 16U) ; /* Set the input and output addresses and start DMA transfer, pCrypOutBuffPtr size should be %4*/ - CRYP_SetDMAConfig(hcryp, (uint32_t)( hcryp->pCrypInBuffPtr), (uint16_t)wordsize/4U, (uint32_t)(hcryp->pCrypOutBuffPtr)); + CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (uint16_t)wordsize / 4U, + (uint32_t)(hcryp->pCrypOutBuffPtr)); } } else /*Size = 0*/ @@ -4707,7 +5304,7 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp) /* Change the CRYP state and phase */ hcryp->State = HAL_CRYP_STATE_READY; } - +#endif /* CRYP */ /* Return function status */ return HAL_OK; } @@ -4721,20 +5318,21 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp) static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp) { uint32_t loopcounter; - uint32_t temp; /* Temporary CrypOutBuff */ + uint32_t temp[4]; /* Temporary CrypOutBuff */ uint32_t lastwordsize; uint32_t npblb; - #if defined(AES) + uint32_t i; +#if defined(AES) uint16_t outcount; /* Temporary CrypOutCount Value */ #endif /* AES */ /***************************** Payload phase *******************************/ #if defined(CRYP) - if(hcryp->Size == 0U) + if (hcryp->Size == 0U) { /* Disable interrupts */ - __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI| CRYP_IT_OUTI); + __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI); /* Process unlocked */ __HAL_UNLOCK(hcryp); @@ -4743,18 +5341,18 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp) hcryp->State = HAL_CRYP_STATE_READY; } - else if (((hcryp->Size/4U) - (hcryp->CrypInCount)) >= 4U) + else if (((hcryp->Size / 4U) - (hcryp->CrypInCount)) >= 4U) { /* Write the input block in the IN FIFO */ - hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - if(((hcryp->Size/4U) == hcryp->CrypInCount) &&((hcryp->Size %16U )== 0U)) + if (((hcryp->Size / 4U) == hcryp->CrypInCount) && ((hcryp->Size % 16U) == 0U)) { /* Disable interrupts */ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI); @@ -4768,22 +5366,21 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp) HAL_CRYP_InCpltCallback(hcryp); #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } - if(hcryp->CrypOutCount < (hcryp->Size/4U)) + if (hcryp->CrypOutCount < (hcryp->Size / 4U)) { /* Read the output block from the Output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */ - temp = hcryp->Instance->DOUT; - *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp; - hcryp->CrypOutCount++; - temp = hcryp->Instance->DOUT; - *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp; - hcryp->CrypOutCount++; - temp = hcryp->Instance->DOUT; - *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp; - hcryp->CrypOutCount++; - temp = hcryp->Instance->DOUT; - *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp; - hcryp->CrypOutCount++; - if (((hcryp->Size/4U) == hcryp->CrypOutCount)&&((hcryp->Size %16U )== 0U)) + for (i = 0U; i < 4U; i++) + { + temp[i] = hcryp->Instance->DOUT; + } + i = 0U; + while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 4U)) + { + *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i]; + hcryp->CrypOutCount++; + i++; + } + if (((hcryp->Size / 4U) == hcryp->CrypOutCount) && ((hcryp->Size % 16U) == 0U)) { /* Disable interrupts */ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI); @@ -4808,32 +5405,32 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp) } } } - else if ((hcryp->Size %16U )!= 0U) + else if ((hcryp->Size % 16U) != 0U) { /* Size should be %4 in word and %16 in byte otherwise TAG will be incorrectly generated for GCM Encryption & CCM Decryption Workaround is implemented in polling mode, so if last block of payload <128bit don't use CRYP_AESGCM_Encrypt_IT otherwise TAG is incorrectly generated. */ - /* Compute the number of padding bytes in last block of payload */ - npblb = ((((uint32_t)(hcryp->Size)/16U)+1U)*16U)- (uint32_t)(hcryp->Size); + /* Compute the number of padding bytes in last block of payload */ + npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size); /* Number of valid words (lastwordsize) in last block */ - if ((npblb%4U) ==0U) + if ((npblb % 4U) == 0U) { - lastwordsize = (16U-npblb)/4U; + lastwordsize = (16U - npblb) / 4U; } else { - lastwordsize = ((16U-npblb)/4U) +1U; + lastwordsize = ((16U - npblb) / 4U) + 1U; } /* Last block optionally pad the data with zeros*/ - for(loopcounter = 0U; loopcounter < lastwordsize; loopcounter++) + for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++) { - hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; } - while(loopcounter < 4U ) + while (loopcounter < 4U) { /* Pad the data with zeros to have a complete block */ hcryp->Instance->DIN = 0x0U; @@ -4841,22 +5438,32 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp) } __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI); - if((hcryp->Instance->SR & CRYP_FLAG_OFNE ) != 0x0U) + if ((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U) { - for(loopcounter = 0U; loopcounter < 4U; loopcounter++) + for (i = 0U; i < 4U; i++) { - /* Read the output block from the output FIFO and put them in temporary buffer */ - temp= hcryp->Instance->DOUT; - - /*get CrypOutBuff from temporary buffer */ - *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount))=temp; + temp[i] = hcryp->Instance->DOUT; + } + if (((hcryp->Size) / 4U) == 0U) + { + for (i = 0U; i < ((uint32_t)(hcryp->Size) % 4U); i++) + { + *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i]; + hcryp->CrypOutCount++; + } + } + i = 0x0U; + while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 4U)) + { + *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i]; hcryp->CrypOutCount++; + i++; } } - if(hcryp->CrypOutCount >= (hcryp->Size/4U)) + if (hcryp->CrypOutCount >= (hcryp->Size / 4U)) { /* Disable interrupts */ - __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI|CRYP_IT_INI); + __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI | CRYP_IT_INI); /* Change the CRYP peripheral state */ hcryp->State = HAL_CRYP_STATE_READY; @@ -4881,25 +5488,24 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp) #else /* AES */ /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/ - temp = hcryp->Instance->DOUTR; - *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) =temp; - hcryp->CrypOutCount++; - temp = hcryp->Instance->DOUTR; - *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) =temp; - hcryp->CrypOutCount++; - temp = hcryp->Instance->DOUTR; - *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp; - hcryp->CrypOutCount++; - temp = hcryp->Instance->DOUTR; - *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp; - hcryp->CrypOutCount++; + for (i = 0U; i < 4U; i++) + { + temp[i] = hcryp->Instance->DOUTR; + } + i = 0U; + while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (i < 4U)) + { + *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i]; + hcryp->CrypOutCount++; + i++; + } /*Temporary CrypOutCount Value*/ outcount = hcryp->CrypOutCount; - if((hcryp->CrypOutCount >= (hcryp->Size/4U)) && ((outcount*4U) >= hcryp->Size) ) + if ((hcryp->CrypOutCount >= (hcryp->Size / 4U)) && ((outcount * 4U) >= hcryp->Size)) { /* Disable computation complete flag and errors interrupts */ - __HAL_CRYP_DISABLE_IT(hcryp,CRYP_IT_CCFIE|CRYP_IT_ERRIE); + __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE); /* Change the CRYP state */ hcryp->State = HAL_CRYP_STATE_READY; @@ -4907,28 +5513,28 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp) /* Process unlocked */ __HAL_UNLOCK(hcryp); - /* Call output transfer complete callback */ + /* Call output transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) - /*Call registered Output complete callback*/ - hcryp->OutCpltCallback(hcryp); + /*Call registered Output complete callback*/ + hcryp->OutCpltCallback(hcryp); #else - /*Call legacy weak Output complete callback*/ - HAL_CRYP_OutCpltCallback(hcryp); + /*Call legacy weak Output complete callback*/ + HAL_CRYP_OutCpltCallback(hcryp); #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } - else if (((hcryp->Size/4U) - (hcryp->CrypInCount)) >= 4U) + else if (((hcryp->Size / 4U) - (hcryp->CrypInCount)) >= 4U) { /* Write the input block in the IN FIFO */ - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - if((hcryp->CrypInCount == hcryp->Size) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)) + if ((hcryp->CrypInCount == hcryp->Size) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)) { /* Call Input transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) @@ -4947,25 +5553,25 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp) payload <128bit don't use CRYP_Encrypt_IT otherwise TAG is incorrectly generated for GCM Encryption & CCM Decryption. */ /* Compute the number of padding bytes in last block of payload */ - npblb = ((((uint32_t)(hcryp->Size)/16U)+1U)*16U) - (uint32_t)(hcryp->Size); + npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size); - /* Number of valid words (lastwordsize) in last block */ - if ((npblb%4U) ==0U) + /* Number of valid words (lastwordsize) in last block */ + if ((npblb % 4U) == 0U) { - lastwordsize = (16U-npblb)/4U; + lastwordsize = (16U - npblb) / 4U; } else { - lastwordsize = ((16U-npblb)/4U) +1U; + lastwordsize = ((16U - npblb) / 4U) + 1U; } /* Last block optionally pad the data with zeros*/ - for(loopcounter = 0U; loopcounter < lastwordsize; loopcounter++) + for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++) { - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; } - while(loopcounter < 4U ) + while (loopcounter < 4U) { /* pad the data with zeros to have a complete block */ hcryp->Instance->DINR = 0x0U; @@ -4990,7 +5596,7 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u /***************************** Header phase for GCM/GMAC or CCM *********************************/ - if((hcryp->Init.HeaderSize != 0U)) + if ((hcryp->Init.HeaderSize != 0U)) { #if defined(CRYP) @@ -5001,22 +5607,22 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u /* Enable the CRYP peripheral */ __HAL_CRYP_ENABLE(hcryp); - if ((hcryp->Init.HeaderSize %4U )== 0U) + if ((hcryp->Init.HeaderSize % 4U) == 0U) { /* HeaderSize %4, no padding */ - for(loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter+=4U) + for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U) { - hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; - hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; - hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; - hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; /* Wait for IFEM to be raised */ - if(CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK) + if (CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK) { /* Disable the CRYP peripheral clock */ __HAL_CRYP_DISABLE(hcryp); @@ -5034,19 +5640,19 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u else { /*Write header block in the IN FIFO without last block */ - for(loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize)-(hcryp->Init.HeaderSize %4U ))); loopcounter+= 4U) + for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U))); loopcounter += 4U) { - hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; - hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; - hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; - hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; /* Wait for IFEM to be raised */ - if(CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK) + if (CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK) { /* Disable the CRYP peripheral clock */ __HAL_CRYP_DISABLE(hcryp); @@ -5061,19 +5667,19 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u } } /* Last block optionally pad the data with zeros*/ - for(loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize %4U )); loopcounter++) + for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++) { - hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; } - while(loopcounter <4U ) + while (loopcounter < 4U) { /* pad the data with zeros to have a complete block */ hcryp->Instance->DIN = 0x0U; loopcounter++; } /* Wait for CCF IFEM to be raised */ - if(CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK) + if (CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK) { /* Disable the CRYP peripheral clock */ __HAL_CRYP_DISABLE(hcryp); @@ -5088,7 +5694,7 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u } } /* Wait until the complete message has been processed */ - if(CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK) + if (CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK) { /* Disable the CRYP peripheral clock */ __HAL_CRYP_DISABLE(hcryp); @@ -5104,7 +5710,7 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u #else /* AES */ - if(hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC) + if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC) { /* Workaround 1 :only AES before re-enabling the IP, datatype can be configured.*/ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType); @@ -5116,22 +5722,22 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u __HAL_CRYP_ENABLE(hcryp); } - if ((hcryp->Init.HeaderSize %4U )== 0U) + if ((hcryp->Init.HeaderSize % 4U) == 0U) { /* HeaderSize %4, no padding */ - for(loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter+= 4U) + for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U) { /* Write the input block in the data input register */ - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; - if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) { /* Disable the CRYP peripheral clock */ __HAL_CRYP_DISABLE(hcryp); @@ -5151,19 +5757,19 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u else { /*Write header block in the IN FIFO without last block */ - for(loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize)-(hcryp->Init.HeaderSize %4U ))); loopcounter+=4U) + for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U))); loopcounter += 4U) { /* Write the input block in the data input register */ - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; - if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) { /* Disable the CRYP peripheral clock */ __HAL_CRYP_DISABLE(hcryp); @@ -5180,19 +5786,19 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); } /* Last block optionally pad the data with zeros*/ - for(loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize %4U )); loopcounter++) + for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++) { - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; } - while(loopcounter < 4U ) + while (loopcounter < 4U) { /*Pad the data with zeros to have a complete block */ hcryp->Instance->DINR = 0x0U; loopcounter++; } - if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) { /* Disable the CRYP peripheral clock */ __HAL_CRYP_DISABLE(hcryp); @@ -5213,7 +5819,7 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u else { #if defined(AES) - if(hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC) + if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC) { /*Workaround 1: only AES, before re-enabling the IP, datatype can be configured.*/ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType); @@ -5242,7 +5848,7 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry uint32_t loopcounter; /***************************** Header phase for GCM/GMAC or CCM *********************************/ - if((hcryp->Init.HeaderSize != 0U)) + if ((hcryp->Init.HeaderSize != 0U)) { #if defined(CRYP) @@ -5253,18 +5859,18 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry /* Enable the CRYP peripheral */ __HAL_CRYP_ENABLE(hcryp); - if ((hcryp->Init.HeaderSize %4U )== 0U) + if ((hcryp->Init.HeaderSize % 4U) == 0U) { /* HeaderSize %4, no padding */ - for(loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter+=4U) + for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U) { - hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; - hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; - hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; - hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; /* Wait for IFEM to be raised */ @@ -5272,7 +5878,7 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry do { count-- ; - if(count == 0U) + if (count == 0U) { /* Disable the CRYP peripheral clock */ __HAL_CRYP_DISABLE(hcryp); @@ -5285,22 +5891,21 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } - while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM)); + } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM)); } } else { /*Write header block in the IN FIFO without last block */ - for(loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize)-(hcryp->Init.HeaderSize %4U ))); loopcounter+=4U) + for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U))); loopcounter += 4U) { - hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; - hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; - hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; - hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; /* Wait for IFEM to be raised */ @@ -5308,7 +5913,7 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry do { count-- ; - if(count == 0U) + if (count == 0U) { /* Disable the CRYP peripheral clock */ __HAL_CRYP_DISABLE(hcryp); @@ -5321,16 +5926,15 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } - while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM)); + } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM)); } /* Last block optionally pad the data with zeros*/ - for(loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize %4U )); loopcounter++) + for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++) { - hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; } - while(loopcounter < 4U ) + while (loopcounter < 4U) { /* Pad the data with zeros to have a complete block */ hcryp->Instance->DIN = 0x0U; @@ -5341,7 +5945,7 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry do { count-- ; - if(count == 0U) + if (count == 0U) { /* Disable the CRYP peripheral clock */ __HAL_CRYP_DISABLE(hcryp); @@ -5354,15 +5958,14 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } - while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM)); + } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM)); } /* Wait until the complete message has been processed */ count = CRYP_TIMEOUT_GCMCCMHEADERPHASE; do { count-- ; - if(count == 0U) + if (count == 0U) { /* Disable the CRYP peripheral clock */ __HAL_CRYP_DISABLE(hcryp); @@ -5375,12 +5978,11 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } - while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY)); + } while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY)); #else /* AES */ - if(hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC) + if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC) { /* Workaround 1: only AES, before re-enabling the IP, datatype can be configured.*/ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType); @@ -5391,19 +5993,19 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry /* Enable the CRYP peripheral */ __HAL_CRYP_ENABLE(hcryp); } - if ((hcryp->Init.HeaderSize %4U )== 0U) + if ((hcryp->Init.HeaderSize % 4U) == 0U) { /* HeaderSize %4, no padding */ - for(loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter+=4U) + for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U) { /* Write the input block in the data input register */ - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; /*Wait on CCF flag*/ @@ -5411,7 +6013,7 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry do { count-- ; - if(count == 0U) + if (count == 0U) { /* Disable the CRYP peripheral clock */ __HAL_CRYP_DISABLE(hcryp); @@ -5424,8 +6026,7 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } - while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); /* Clear CCF flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); @@ -5434,16 +6035,16 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry else { /*Write header block in the IN FIFO without last block */ - for(loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize)-(hcryp->Init.HeaderSize %4U ))); loopcounter+=4U) + for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U))); loopcounter += 4U) { /* Write the Input block in the Data Input register */ - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; /*Wait on CCF flag*/ @@ -5451,7 +6052,7 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry do { count-- ; - if(count == 0U) + if (count == 0U) { /* Disable the CRYP peripheral clock */ __HAL_CRYP_DISABLE(hcryp); @@ -5464,19 +6065,18 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } - while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); /* Clear CCF flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); } /* Last block optionally pad the data with zeros*/ - for(loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize %4U )); loopcounter++) + for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++) { - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; } - while(loopcounter <4U ) + while (loopcounter < 4U) { /* Pad the data with zeros to have a complete block */ hcryp->Instance->DINR = 0x0U; @@ -5488,7 +6088,7 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry do { count-- ; - if(count == 0U) + if (count == 0U) { /* Disable the CRYP peripheral clock */ __HAL_CRYP_DISABLE(hcryp); @@ -5501,8 +6101,7 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } - while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); /* Clear CCF flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); @@ -5512,7 +6111,7 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry else { #if defined(AES) - if(hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC) + if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC) { /*Workaround 1: only AES, before re-enabling the IP, datatype can be configured.*/ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType); @@ -5545,10 +6144,10 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp) /***************************** Header phase *********************************/ #if defined(CRYP) - if(hcryp->Init.HeaderSize == hcryp->CrypHeaderCount) + if (hcryp->Init.HeaderSize == hcryp->CrypHeaderCount) { /* Disable interrupts */ - __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI ); + __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI); /* Disable the CRYP peripheral */ __HAL_CRYP_DISABLE(hcryp); @@ -5560,32 +6159,33 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp) CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); /* Enable Interrupts */ - __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI ); + __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI); /* Enable the CRYP peripheral */ __HAL_CRYP_ENABLE(hcryp); } else if (((hcryp->Init.HeaderSize) - (hcryp->CrypHeaderCount)) >= 4U) - { /* HeaderSize %4, no padding */ - hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount ); + { + /* HeaderSize %4, no padding */ + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; - hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; - hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; - hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; } else { /* Last block optionally pad the data with zeros*/ - for(loopcounter = 0U; loopcounter < (hcryp->Init.HeaderSize %4U ); loopcounter++) + for (loopcounter = 0U; loopcounter < (hcryp->Init.HeaderSize % 4U); loopcounter++) { - hcryp->Instance->DIN = *(uint32_t*)(hcryp->Init.Header+ hcryp->CrypHeaderCount); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; } - while(loopcounter <4U ) + while (loopcounter < 4U) { /* Pad the data with zeros to have a complete block */ hcryp->Instance->DIN = 0x0U; @@ -5594,27 +6194,27 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp) } #else /* AES */ - if(hcryp->Init.HeaderSize == hcryp->CrypHeaderCount) + if (hcryp->Init.HeaderSize == hcryp->CrypHeaderCount) { /* Set the phase */ hcryp->Phase = CRYP_PHASE_PROCESS; /* Payload phase not supported in CCM AES2 */ - if(hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC) + if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC) { /* Select payload phase once the header phase is performed */ MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_PAYLOAD); } - if(hcryp->Init.Algorithm == CRYP_AES_CCM) + if (hcryp->Init.Algorithm == CRYP_AES_CCM) { /* Increment CrypHeaderCount to pass in CRYP_GCMCCM_SetPayloadPhase_IT */ hcryp->CrypHeaderCount++; } /* Write the payload Input block in the IN FIFO */ - if(hcryp->Size == 0U) + if (hcryp->Size == 0U) { /* Disable interrupts */ - __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE| CRYP_IT_ERRIE); + __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE); /* Change the CRYP state */ hcryp->State = HAL_CRYP_STATE_READY; @@ -5624,16 +6224,16 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp) } else if (hcryp->Size >= 16U) { - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - if((hcryp->CrypInCount == (hcryp->Size/4U)) &&((hcryp->Size %16U )== 0U)) + if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) { /* Call the input data transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) @@ -5652,25 +6252,25 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp) payload <128bit don't use CRYP_Encrypt_IT otherwise TAG is incorrectly generated for GCM Encryption. */ /* Compute the number of padding bytes in last block of payload */ - npblb = ((((uint32_t)(hcryp->Size)/16U)+1U)*16U) - (uint32_t)(hcryp->Size); + npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size); /* Number of valid words (lastwordsize) in last block */ - if ((npblb % 4U) ==0U) + if ((npblb % 4U) == 0U) { - lastwordsize = (16U-npblb)/4U; + lastwordsize = (16U - npblb) / 4U; } else { - lastwordsize = ((16U-npblb)/4U) +1U; + lastwordsize = ((16U - npblb) / 4U) + 1U; } /* Last block optionally pad the data with zeros*/ - for(loopcounter = 0U; loopcounter < lastwordsize; loopcounter++) + for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++) { - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; } - while(loopcounter <4U ) + while (loopcounter < 4U) { /* Pad the data with zeros to have a complete block */ hcryp->Instance->DINR = 0x0U; @@ -5681,24 +6281,24 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp) else if (((hcryp->Init.HeaderSize) - (hcryp->CrypHeaderCount)) >= 4U) { /* Write the input block in the IN FIFO */ - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++; } else /*HeaderSize < 4 or HeaderSize >4 & HeaderSize %4 != 0*/ { /* Last block optionally pad the data with zeros*/ - for(loopcounter = 0U; loopcounter < (hcryp->Init.HeaderSize %4U ); loopcounter++) + for (loopcounter = 0U; loopcounter < (hcryp->Init.HeaderSize % 4U); loopcounter++) { - hcryp->Instance->DINR = *(uint32_t*)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; } - while(loopcounter <4U ) + while (loopcounter < 4U) { /* pad the data with zeros to have a complete block */ hcryp->Instance->DINR = 0x0U; @@ -5716,27 +6316,29 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp) * @param Timeout: specify Timeout value * @retval None */ -static void CRYP_Workaround(CRYP_HandleTypeDef *hcryp, uint32_t Timeout ) +static void CRYP_Workaround(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) { uint32_t lastwordsize; uint32_t npblb; #if defined(CRYP) uint32_t iv1temp; uint32_t temp[4] = {0}; - uint32_t temp2[4]= {0}; + uint32_t temp2[4] = {0}; #endif /* CRYP */ - uint32_t intermediate_data[4]={0}; + uint32_t intermediate_data[4] = {0}; uint32_t index; /* Compute the number of padding bytes in last block of payload */ - npblb = ((((uint32_t)(hcryp->Size)/16U)+1U)*16U)- (uint32_t)(hcryp->Size); + npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size); /* Number of valid words (lastwordsize) in last block */ - if ((npblb%4U) ==0U) - { lastwordsize = (16U-npblb)/4U; + if ((npblb % 4U) == 0U) + { + lastwordsize = (16U - npblb) / 4U; } else - {lastwordsize = ((16U-npblb)/4U) +1U; + { + lastwordsize = ((16U - npblb) / 4U) + 1U; } #if defined(CRYP) @@ -5744,35 +6346,35 @@ static void CRYP_Workaround(CRYP_HandleTypeDef *hcryp, uint32_t Timeout ) /* Workaround 2, case GCM encryption */ if (hcryp->Init.Algorithm == CRYP_AES_GCM) { - if((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_ENCRYPT) - {/*Workaround in order to properly compute authentication tags while doing - a GCM encryption with the last block of payload size inferior to 128 bits*/ + if ((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_ENCRYPT) + { + /*Workaround in order to properly compute authentication tags while doing + a GCM encryption with the last block of payload size inferior to 128 bits*/ /* Disable CRYP to start the final phase */ __HAL_CRYP_DISABLE(hcryp); - /*Load CRYP_IV1R register content in a temporary variable. Decrement the value - by 1 and reinsert the result in CRYP_IV1R register*/ - hcryp->Instance->IV1RR = 0x5U; + /*Update CRYP_IV1R register and ALGOMODE*/ + hcryp->Instance->IV1RR = ((hcryp->Instance->CSGCMCCM7R) - 1U); MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_CTR); /* Enable CRYP to start the final phase */ __HAL_CRYP_ENABLE(hcryp); } /* Last block optionally pad the data with zeros*/ - for(index=0; index < lastwordsize; index ++) + for (index = 0; index < lastwordsize; index ++) { /* Write the last input block in the IN FIFO */ - hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; } - while(index < 4U) + while (index < 4U) { /* Pad the data with zeros to have a complete block */ hcryp->Instance->DIN = 0U; index++; } /* Wait for OFNE flag to be raised */ - if(CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK) + if (CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK) { /* Disable the CRYP peripheral clock */ __HAL_CRYP_DISABLE(hcryp); @@ -5791,20 +6393,20 @@ static void CRYP_Workaround(CRYP_HandleTypeDef *hcryp, uint32_t Timeout ) HAL_CRYP_ErrorCallback(hcryp); #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } - if((hcryp->Instance->SR & CRYP_FLAG_OFNE ) != 0x0U) + if ((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U) { - for(index=0U; index< 4U;index++) + for (index = 0U; index < 4U; index++) { /* Read the output block from the output FIFO */ intermediate_data[index] = hcryp->Instance->DOUT; /* Intermediate data buffer to be used in for the workaround*/ - *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount))=intermediate_data[index]; + *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = intermediate_data[index]; hcryp->CrypOutCount++; } } - if((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_ENCRYPT) + if ((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_ENCRYPT) { /*workaround in order to properly compute authentication tags while doing a GCM encryption with the last block of payload size inferior to 128 bits*/ @@ -5815,19 +6417,79 @@ static void CRYP_Workaround(CRYP_HandleTypeDef *hcryp, uint32_t Timeout ) /* configured final phase */ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH, CRYP_PHASE_FINAL); - for (index=0U; index < lastwordsize; index ++) + if ((hcryp->Instance->CR & CRYP_CR_DATATYPE) == CRYP_DATATYPE_32B) + { + if ((npblb % 4U) == 1U) + { + intermediate_data[lastwordsize - 1U] &= 0xFFFFFF00U; + } + if ((npblb % 4U) == 2U) + { + intermediate_data[lastwordsize - 1U] &= 0xFFFF0000U; + } + if ((npblb % 4U) == 3U) + { + intermediate_data[lastwordsize - 1U] &= 0xFF000000U; + } + } + else if ((hcryp->Instance->CR & CRYP_CR_DATATYPE) == CRYP_DATATYPE_8B) + { + if ((npblb % 4U) == 1U) + { + intermediate_data[lastwordsize - 1U] &= __REV(0xFFFFFF00U); + } + if ((npblb % 4U) == 2U) + { + intermediate_data[lastwordsize - 1U] &= __REV(0xFFFF0000U); + } + if ((npblb % 4U) == 3U) + { + intermediate_data[lastwordsize - 1U] &= __REV(0xFF000000U); + } + } + else if ((hcryp->Instance->CR & CRYP_CR_DATATYPE) == CRYP_DATATYPE_16B) + { + if ((npblb % 4U) == 1U) + { + intermediate_data[lastwordsize - 1U] &= __ROR((0xFFFFFF00U), 16); + } + if ((npblb % 4U) == 2U) + { + intermediate_data[lastwordsize - 1U] &= __ROR((0xFFFF0000U), 16); + } + if ((npblb % 4U) == 3U) + { + intermediate_data[lastwordsize - 1U] &= __ROR((0xFF000000U), 16); + } + } + else /*CRYP_DATATYPE_1B*/ + { + if ((npblb % 4U) == 1U) + { + intermediate_data[lastwordsize - 1U] &= __RBIT(0xFFFFFF00U); + } + if ((npblb % 4U) == 2U) + { + intermediate_data[lastwordsize - 1U] &= __RBIT(0xFFFF0000U); + } + if ((npblb % 4U) == 3U) + { + intermediate_data[lastwordsize - 1U] &= __RBIT(0xFF000000U); + } + } + for (index = 0U; index < lastwordsize; index ++) { /*Write the intermediate_data in the IN FIFO */ - hcryp->Instance->DIN=intermediate_data[index]; + hcryp->Instance->DIN = intermediate_data[index]; } - while(index < 4U) + while (index < 4U) { /* Pad the data with zeros to have a complete block */ hcryp->Instance->DIN = 0x0U; index++; } /* Wait for OFNE flag to be raised */ - if(CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK) + if (CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK) { /* Disable the CRYP peripheral clock */ __HAL_CRYP_DISABLE(hcryp); @@ -5839,40 +6501,42 @@ static void CRYP_Workaround(CRYP_HandleTypeDef *hcryp, uint32_t Timeout ) /* Process unlocked */ __HAL_UNLOCK(hcryp); #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) - /*Call registered error callback*/ - hcryp->ErrorCallback(hcryp); + /*Call registered error callback*/ + hcryp->ErrorCallback(hcryp); #else - /*Call legacy weak error callback*/ - HAL_CRYP_ErrorCallback(hcryp); + /*Call legacy weak error callback*/ + HAL_CRYP_ErrorCallback(hcryp); #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } - if((hcryp->Instance->SR & CRYP_FLAG_OFNE ) != 0x0U) + if ((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U) { - for( index=0U; index< 4U;index++) + for (index = 0U; index < 4U; index++) { - intermediate_data[index]=hcryp->Instance->DOUT; + intermediate_data[index] = hcryp->Instance->DOUT; } } } } /* End of GCM encryption */ - else{ /* Workaround 2, case CCM decryption, in order to properly compute - authentication tags while doing a CCM decryption with the last block - of payload size inferior to 128 bits*/ + else + { + /* Workaround 2, case CCM decryption, in order to properly compute + authentication tags while doing a CCM decryption with the last block + of payload size inferior to 128 bits*/ - if((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_DECRYPT) + if ((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_DECRYPT) { iv1temp = hcryp->Instance->CSGCMCCM7R; /* Disable CRYP to start the final phase */ __HAL_CRYP_DISABLE(hcryp); - temp[0]= hcryp->Instance->CSGCMCCM0R; - temp[1]= hcryp->Instance->CSGCMCCM1R; - temp[2]= hcryp->Instance->CSGCMCCM2R; - temp[3]= hcryp->Instance->CSGCMCCM3R; + temp[0] = hcryp->Instance->CSGCMCCM0R; + temp[1] = hcryp->Instance->CSGCMCCM1R; + temp[2] = hcryp->Instance->CSGCMCCM2R; + temp[3] = hcryp->Instance->CSGCMCCM3R; - hcryp->Instance->IV1RR= iv1temp; + hcryp->Instance->IV1RR = iv1temp; /* Configured CHMOD CTR */ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_CTR); @@ -5881,20 +6545,20 @@ static void CRYP_Workaround(CRYP_HandleTypeDef *hcryp, uint32_t Timeout ) __HAL_CRYP_ENABLE(hcryp); } /* Last block optionally pad the data with zeros*/ - for(index=0; index < lastwordsize; index ++) + for (index = 0; index < lastwordsize; index ++) { /* Write the last Input block in the IN FIFO */ - hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; } - while(index < 4U) + while (index < 4U) { /* Pad the data with zeros to have a complete block */ hcryp->Instance->DIN = 0U; index++; } /* Wait for OFNE flag to be raised */ - if(CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK) + if (CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK) { /* Disable the CRYP peripheral clock */ __HAL_CRYP_DISABLE(hcryp); @@ -5914,25 +6578,25 @@ static void CRYP_Workaround(CRYP_HandleTypeDef *hcryp, uint32_t Timeout ) #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } - if((hcryp->Instance->SR & CRYP_FLAG_OFNE ) != 0x0U) + if ((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U) { - for(index=0U; index< 4U;index++) + for (index = 0U; index < 4U; index++) { /* Read the Output block from the Output FIFO */ intermediate_data[index] = hcryp->Instance->DOUT; /*intermediate data buffer to be used in for the workaround*/ - *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount))=intermediate_data[index]; + *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = intermediate_data[index]; hcryp->CrypOutCount++; } } - if((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_DECRYPT) + if ((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_DECRYPT) { - temp2[0]= hcryp->Instance->CSGCMCCM0R; - temp2[1]= hcryp->Instance->CSGCMCCM1R; - temp2[2]= hcryp->Instance->CSGCMCCM2R; - temp2[3]= hcryp->Instance->CSGCMCCM3R; + temp2[0] = hcryp->Instance->CSGCMCCM0R; + temp2[1] = hcryp->Instance->CSGCMCCM1R; + temp2[2] = hcryp->Instance->CSGCMCCM2R; + temp2[3] = hcryp->Instance->CSGCMCCM3R; /* configured CHMOD CCM */ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_CCM); @@ -5941,35 +6605,35 @@ static void CRYP_Workaround(CRYP_HandleTypeDef *hcryp, uint32_t Timeout ) MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH, CRYP_PHASE_HEADER); /*set to zero the bits corresponding to the padded bits*/ - for(index = lastwordsize; index<4U; index ++) + for (index = lastwordsize; index < 4U; index ++) { - intermediate_data[index] =0U; + intermediate_data[index] = 0U; } - if ((npblb %4U)==1U) + if ((npblb % 4U) == 1U) { - intermediate_data[lastwordsize-1U] &= 0xFFFFFF00U; + intermediate_data[lastwordsize - 1U] &= 0xFFFFFF00U; } - if ((npblb %4U)==2U) + if ((npblb % 4U) == 2U) { - intermediate_data[lastwordsize-1U] &= 0xFFFF0000U; + intermediate_data[lastwordsize - 1U] &= 0xFFFF0000U; } - if ((npblb %4U)==3U) + if ((npblb % 4U) == 3U) { - intermediate_data[lastwordsize-1U] &= 0xFF000000U; + intermediate_data[lastwordsize - 1U] &= 0xFF000000U; } - for(index=0U; index < 4U ; index ++) + for (index = 0U; index < 4U ; index ++) { intermediate_data[index] ^= temp[index]; intermediate_data[index] ^= temp2[index]; } - for(index = 0U; index < 4U; index ++) + for (index = 0U; index < 4U; index ++) { /* Write the last Input block in the IN FIFO */ hcryp->Instance->DIN = intermediate_data[index] ; } /* Wait for BUSY flag to be raised */ - if(CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK) + if (CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK) { /* Disable the CRYP peripheral clock */ __HAL_CRYP_DISABLE(hcryp); @@ -5981,11 +6645,11 @@ static void CRYP_Workaround(CRYP_HandleTypeDef *hcryp, uint32_t Timeout ) /* Process Unlocked */ __HAL_UNLOCK(hcryp); #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) - /*Call registered error callback*/ - hcryp->ErrorCallback(hcryp); + /*Call registered error callback*/ + hcryp->ErrorCallback(hcryp); #else - /*Call legacy weak error callback*/ - HAL_CRYP_ErrorCallback(hcryp); + /*Call legacy weak error callback*/ + HAL_CRYP_ErrorCallback(hcryp); #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } } @@ -5999,52 +6663,52 @@ static void CRYP_Workaround(CRYP_HandleTypeDef *hcryp, uint32_t Timeout ) /*Workaround 2: case GCM encryption, during payload phase and before inserting the last block of paylaod, which size is inferior to 128 bits */ - if((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT) + if ((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT) { /* configured CHMOD CTR */ MODIFY_REG(hcryp->Instance->CR, AES_CR_CHMOD, CRYP_AES_CTR); } /* last block optionally pad the data with zeros*/ - for(index = 0U; index < lastwordsize; index ++) + for (index = 0U; index < lastwordsize; index ++) { /* Write the last Input block in the IN FIFO */ - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; } - while(index < 4U) + while (index < 4U) { /* pad the data with zeros to have a complete block */ hcryp->Instance->DINR = 0U; index++; } /* Wait for CCF flag to be raised */ - if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) { hcryp->State = HAL_CRYP_STATE_READY; __HAL_UNLOCK(hcryp); #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) - /*Call registered error callback*/ - hcryp->ErrorCallback(hcryp); + /*Call registered error callback*/ + hcryp->ErrorCallback(hcryp); #else - /*Call legacy weak error callback*/ - HAL_CRYP_ErrorCallback(hcryp); + /*Call legacy weak error callback*/ + HAL_CRYP_ErrorCallback(hcryp); #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } /* Clear CCF Flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - for(index = 0U; index< 4U;index++) + for (index = 0U; index < 4U; index++) { /* Read the Output block from the Output FIFO */ intermediate_data[index] = hcryp->Instance->DOUTR; /*intermediate data buffer to be used in the workaround*/ - *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount))= intermediate_data[index]; + *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = intermediate_data[index]; hcryp->CrypOutCount++; } - if((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT) + if ((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT) { /* configured CHMOD GCM */ MODIFY_REG(hcryp->Instance->CR, AES_CR_CHMOD, CRYP_AES_GCM_GMAC); @@ -6052,19 +6716,80 @@ static void CRYP_Workaround(CRYP_HandleTypeDef *hcryp, uint32_t Timeout ) /* Select final phase */ MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_FINAL); + if ((hcryp->Instance->CR & AES_CR_DATATYPE) == CRYP_DATATYPE_32B) + { + if ((npblb % 4U) == 1U) + { + intermediate_data[lastwordsize - 1U] &= 0xFFFFFF00U; + } + if ((npblb % 4U) == 2U) + { + intermediate_data[lastwordsize - 1U] &= 0xFFFF0000U; + } + if ((npblb % 4U) == 3U) + { + intermediate_data[lastwordsize - 1U] &= 0xFF000000U; + } + } + else if ((hcryp->Instance->CR & AES_CR_DATATYPE) == CRYP_DATATYPE_8B) + { + if ((npblb % 4U) == 1U) + { + intermediate_data[lastwordsize - 1U] &= __REV(0xFFFFFF00U); + } + if ((npblb % 4U) == 2U) + { + intermediate_data[lastwordsize - 1U] &= __REV(0xFFFF0000U); + } + if ((npblb % 4U) == 3U) + { + intermediate_data[lastwordsize - 1U] &= __REV(0xFF000000U); + } + } + else if ((hcryp->Instance->CR & AES_CR_DATATYPE) == CRYP_DATATYPE_16B) + { + if ((npblb % 4U) == 1U) + { + intermediate_data[lastwordsize - 1U] &= __ROR((0xFFFFFF00U), 16); + } + if ((npblb % 4U) == 2U) + { + intermediate_data[lastwordsize - 1U] &= __ROR((0xFFFF0000U), 16); + } + if ((npblb % 4U) == 3U) + { + intermediate_data[lastwordsize - 1U] &= __ROR((0xFF000000U), 16); + } + } + else /*CRYP_DATATYPE_1B*/ + { + if ((npblb % 4U) == 1U) + { + intermediate_data[lastwordsize - 1U] &= __RBIT(0xFFFFFF00U); + } + if ((npblb % 4U) == 2U) + { + intermediate_data[lastwordsize - 1U] &= __RBIT(0xFFFF0000U); + } + if ((npblb % 4U) == 3U) + { + intermediate_data[lastwordsize - 1U] &= __RBIT(0xFF000000U); + } + } + /*Write the intermediate_data in the IN FIFO */ - for(index = 0U; index < lastwordsize; index ++) + for (index = 0U; index < lastwordsize; index ++) { hcryp->Instance->DINR = intermediate_data[index]; } - while(index < 4U) + while (index < 4U) { /* pad the data with zeros to have a complete block */ hcryp->Instance->DINR = 0U; index++; } /* Wait for CCF flag to be raised */ - if(CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) { /* Disable the CRYP peripheral clock */ __HAL_CRYP_DISABLE(hcryp); @@ -6086,12 +6811,11 @@ static void CRYP_Workaround(CRYP_HandleTypeDef *hcryp, uint32_t Timeout ) /* Clear CCF Flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - for( index = 0U; index< 4U;index++) + for (index = 0U; index < 4U; index++) { - intermediate_data[index]=hcryp->Instance->DOUTR; + intermediate_data[index] = hcryp->Instance->DOUTR; } }/*End of Workaround 2*/ - #endif /* End AES or CRYP */ } @@ -6111,12 +6835,12 @@ static HAL_StatusTypeDef CRYP_WaitOnIFEMFlag(CRYP_HandleTypeDef *hcryp, uint32_t /* Get timeout */ tickstart = HAL_GetTick(); - while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM)) + while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM)) { /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { return HAL_ERROR; } @@ -6139,12 +6863,12 @@ static HAL_StatusTypeDef CRYP_WaitOnBUSYFlag(CRYP_HandleTypeDef *hcryp, uint32_t /* Get timeout */ tickstart = HAL_GetTick(); - while(HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY)) + while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY)) { /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { return HAL_ERROR; } @@ -6168,12 +6892,12 @@ static HAL_StatusTypeDef CRYP_WaitOnOFNEFlag(CRYP_HandleTypeDef *hcryp, uint32_t /* Get timeout */ tickstart = HAL_GetTick(); - while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE)) + while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE)) { /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { return HAL_ERROR; } @@ -6198,12 +6922,12 @@ static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t T /* Get timeout */ tickstart = HAL_GetTick(); - while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)) + while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)) { /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U) ) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { return HAL_ERROR; } diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cryp_ex.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cryp_ex.c index bf146dd126..1a7a6b9ede 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cryp_ex.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cryp_ex.c @@ -79,7 +79,7 @@ #define CRYPEx_PHASE_PROCESS 0x02U /*!< CRYP peripheral is in processing phase */ #define CRYPEx_PHASE_FINAL 0x03U /*!< CRYP peripheral is in final phase this is relevant only with CCM and GCM modes */ - /* CTR0 information to use in CCM algorithm */ +/* CTR0 information to use in CCM algorithm */ #define CRYP_CCM_CTR0_0 0x07FFFFFFU #define CRYP_CCM_CTR0_3 0xFFFFFF00U @@ -100,8 +100,8 @@ */ /** @defgroup CRYPEx_Exported_Functions_Group1 Extended AES processing functions - * @brief Extended processing functions. - * + * @brief Extended processing functions. + * @verbatim ============================================================================== ##### Extended AES processing functions ##### @@ -129,10 +129,10 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u { uint32_t tickstart; uint64_t headerlength = (uint64_t)(hcryp->Init.HeaderSize) * 32U; /* Header length in bits */ - uint64_t inputlength = (uint64_t)(hcryp->Size) * 8U; /* input length in bits */ + uint64_t inputlength = (uint64_t)hcryp->SizesSum * 8U; /* input length in bits */ uint32_t tagaddr = (uint32_t)AuthTag; - if(hcryp->State == HAL_CRYP_STATE_READY) + if (hcryp->State == HAL_CRYP_STATE_READY) { /* Process locked */ __HAL_LOCK(hcryp); @@ -141,7 +141,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u hcryp->State = HAL_CRYP_STATE_BUSY; /* Check if initialization phase has already been performed */ - if(hcryp->Phase == CRYPEx_PHASE_PROCESS) + if (hcryp->Phase == CRYPEx_PHASE_PROCESS) { /* Change the CRYP phase */ hcryp->Phase = CRYPEx_PHASE_FINAL; @@ -178,28 +178,28 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u /* Write the number of bits in header (64 bits) followed by the number of bits in the payload */ - if(hcryp->Init.DataType == CRYP_DATATYPE_1B) + if (hcryp->Init.DataType == CRYP_DATATYPE_1B) { hcryp->Instance->DIN = 0U; hcryp->Instance->DIN = __RBIT((uint32_t)(headerlength)); hcryp->Instance->DIN = 0U; hcryp->Instance->DIN = __RBIT((uint32_t)(inputlength)); } - else if(hcryp->Init.DataType == CRYP_DATATYPE_8B) + else if (hcryp->Init.DataType == CRYP_DATATYPE_8B) { hcryp->Instance->DIN = 0U; hcryp->Instance->DIN = __REV((uint32_t)(headerlength)); hcryp->Instance->DIN = 0U; hcryp->Instance->DIN = __REV((uint32_t)(inputlength)); } - else if(hcryp->Init.DataType == CRYP_DATATYPE_16B) + else if (hcryp->Init.DataType == CRYP_DATATYPE_16B) { hcryp->Instance->DIN = 0U; hcryp->Instance->DIN = __ROR((uint32_t)headerlength, 16U); hcryp->Instance->DIN = 0U; hcryp->Instance->DIN = __ROR((uint32_t)inputlength, 16U); } - else if(hcryp->Init.DataType == CRYP_DATATYPE_32B) + else if (hcryp->Init.DataType == CRYP_DATATYPE_32B) { hcryp->Instance->DIN = 0U; hcryp->Instance->DIN = (uint32_t)(headerlength); @@ -213,12 +213,12 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u /* Wait for OFNE flag to be raised */ tickstart = HAL_GetTick(); - while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE)) + while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE)) { /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { /* Disable the CRYP Peripheral Clock */ __HAL_CRYP_DISABLE(hcryp); @@ -235,13 +235,13 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u } /* Read the authentication TAG in the output FIFO */ - *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT; - tagaddr+=4U; - *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT; - tagaddr+=4U; - *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT; - tagaddr+=4U; - *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT; + *(uint32_t *)(tagaddr) = hcryp->Instance->DOUT; + tagaddr += 4U; + *(uint32_t *)(tagaddr) = hcryp->Instance->DOUT; + tagaddr += 4U; + *(uint32_t *)(tagaddr) = hcryp->Instance->DOUT; + tagaddr += 4U; + *(uint32_t *)(tagaddr) = hcryp->Instance->DOUT; #else /* AES*/ @@ -250,28 +250,28 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u /* Write the number of bits in header (64 bits) followed by the number of bits in the payload */ - if(hcryp->Init.DataType == CRYP_DATATYPE_1B) + if (hcryp->Init.DataType == CRYP_DATATYPE_1B) { hcryp->Instance->DINR = 0U; hcryp->Instance->DINR = __RBIT((uint32_t)(headerlength)); hcryp->Instance->DINR = 0U; hcryp->Instance->DINR = __RBIT((uint32_t)(inputlength)); } - else if(hcryp->Init.DataType == CRYP_DATATYPE_8B) + else if (hcryp->Init.DataType == CRYP_DATATYPE_8B) { hcryp->Instance->DINR = 0U; hcryp->Instance->DINR = __REV((uint32_t)(headerlength)); hcryp->Instance->DINR = 0U; hcryp->Instance->DINR = __REV((uint32_t)(inputlength)); } - else if(hcryp->Init.DataType == CRYP_DATATYPE_16B) + else if (hcryp->Init.DataType == CRYP_DATATYPE_16B) { hcryp->Instance->DINR = 0U; hcryp->Instance->DINR = __ROR((uint32_t)headerlength, 16U); hcryp->Instance->DINR = 0U; hcryp->Instance->DINR = __ROR((uint32_t)inputlength, 16U); } - else if(hcryp->Init.DataType == CRYP_DATATYPE_32B) + else if (hcryp->Init.DataType == CRYP_DATATYPE_32B) { hcryp->Instance->DINR = 0U; hcryp->Instance->DINR = (uint32_t)(headerlength); @@ -284,12 +284,12 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u } /* Wait for CCF flag to be raised */ tickstart = HAL_GetTick(); - while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)) + while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)) { /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { /* Disable the CRYP peripheral clock */ __HAL_CRYP_DISABLE(hcryp); @@ -306,13 +306,13 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u } /* Read the authentication TAG in the output FIFO */ - *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR; - tagaddr+=4U; - *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR; - tagaddr+=4U; - *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR; - tagaddr+=4U; - *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR; + *(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR; + tagaddr += 4U; + *(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR; + tagaddr += 4U; + *(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR; + tagaddr += 4U; + *(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR; /* Clear CCF flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); @@ -349,11 +349,11 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout) { uint32_t tagaddr = (uint32_t)AuthTag; - uint32_t ctr0 [4]={0}; + uint32_t ctr0 [4] = {0}; uint32_t ctr0addr = (uint32_t)ctr0; uint32_t tickstart; - if(hcryp->State == HAL_CRYP_STATE_READY) + if (hcryp->State == HAL_CRYP_STATE_READY) { /* Process locked */ __HAL_LOCK(hcryp); @@ -362,7 +362,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u hcryp->State = HAL_CRYP_STATE_BUSY; /* Check if initialization phase has already been performed */ - if(hcryp->Phase == CRYPEx_PHASE_PROCESS) + if (hcryp->Phase == CRYPEx_PHASE_PROCESS) { /* Change the CRYP phase */ hcryp->Phase = CRYPEx_PHASE_FINAL; @@ -389,66 +389,66 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u __HAL_CRYP_DISABLE(hcryp); /* Select final phase & ALGODIR bit must be set to �0�. */ - MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH|CRYP_CR_ALGODIR, CRYP_PHASE_FINAL|CRYP_OPERATINGMODE_ENCRYPT); + MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH | CRYP_CR_ALGODIR, CRYP_PHASE_FINAL | CRYP_OPERATINGMODE_ENCRYPT); /* Enable the CRYP peripheral */ __HAL_CRYP_ENABLE(hcryp); /* Write the counter block in the IN FIFO, CTR0 information from B0 data has to be swapped according to the DATATYPE*/ - ctr0[0]=(hcryp->Init.B0[0]) & CRYP_CCM_CTR0_0; - ctr0[1]=hcryp->Init.B0[1]; - ctr0[2]=hcryp->Init.B0[2]; - ctr0[3]=hcryp->Init.B0[3] & CRYP_CCM_CTR0_3; + ctr0[0] = (hcryp->Init.B0[0]) & CRYP_CCM_CTR0_0; + ctr0[1] = hcryp->Init.B0[1]; + ctr0[2] = hcryp->Init.B0[2]; + ctr0[3] = hcryp->Init.B0[3] & CRYP_CCM_CTR0_3; - if(hcryp->Init.DataType == CRYP_DATATYPE_8B) + if (hcryp->Init.DataType == CRYP_DATATYPE_8B) { - hcryp->Instance->DIN = __REV(*(uint32_t*)(ctr0addr)); - ctr0addr+=4U; - hcryp->Instance->DIN = __REV(*(uint32_t*)(ctr0addr)); - ctr0addr+=4U; - hcryp->Instance->DIN = __REV(*(uint32_t*)(ctr0addr)); - ctr0addr+=4U; - hcryp->Instance->DIN = __REV(*(uint32_t*)(ctr0addr)); + hcryp->Instance->DIN = __REV(*(uint32_t *)(ctr0addr)); + ctr0addr += 4U; + hcryp->Instance->DIN = __REV(*(uint32_t *)(ctr0addr)); + ctr0addr += 4U; + hcryp->Instance->DIN = __REV(*(uint32_t *)(ctr0addr)); + ctr0addr += 4U; + hcryp->Instance->DIN = __REV(*(uint32_t *)(ctr0addr)); } - else if(hcryp->Init.DataType == CRYP_DATATYPE_16B) + else if (hcryp->Init.DataType == CRYP_DATATYPE_16B) { - hcryp->Instance->DIN = __ROR(*(uint32_t*)(ctr0addr), 16U); - ctr0addr+=4U; - hcryp->Instance->DIN = __ROR(*(uint32_t*)(ctr0addr), 16U); - ctr0addr+=4U; - hcryp->Instance->DIN = __ROR(*(uint32_t*)(ctr0addr), 16U); - ctr0addr+=4U; - hcryp->Instance->DIN = __ROR(*(uint32_t*)(ctr0addr), 16U); + hcryp->Instance->DIN = __ROR(*(uint32_t *)(ctr0addr), 16U); + ctr0addr += 4U; + hcryp->Instance->DIN = __ROR(*(uint32_t *)(ctr0addr), 16U); + ctr0addr += 4U; + hcryp->Instance->DIN = __ROR(*(uint32_t *)(ctr0addr), 16U); + ctr0addr += 4U; + hcryp->Instance->DIN = __ROR(*(uint32_t *)(ctr0addr), 16U); } - else if(hcryp->Init.DataType == CRYP_DATATYPE_1B) + else if (hcryp->Init.DataType == CRYP_DATATYPE_1B) { - hcryp->Instance->DIN = __RBIT(*(uint32_t*)(ctr0addr)); - ctr0addr+=4U; - hcryp->Instance->DIN = __RBIT(*(uint32_t*)(ctr0addr)); - ctr0addr+=4U; - hcryp->Instance->DIN = __RBIT(*(uint32_t*)(ctr0addr)); - ctr0addr+=4U; - hcryp->Instance->DIN = __RBIT(*(uint32_t*)(ctr0addr)); + hcryp->Instance->DIN = __RBIT(*(uint32_t *)(ctr0addr)); + ctr0addr += 4U; + hcryp->Instance->DIN = __RBIT(*(uint32_t *)(ctr0addr)); + ctr0addr += 4U; + hcryp->Instance->DIN = __RBIT(*(uint32_t *)(ctr0addr)); + ctr0addr += 4U; + hcryp->Instance->DIN = __RBIT(*(uint32_t *)(ctr0addr)); } else { - hcryp->Instance->DIN = *(uint32_t*)(ctr0addr); - ctr0addr+=4U; - hcryp->Instance->DIN = *(uint32_t*)(ctr0addr); - ctr0addr+=4U; - hcryp->Instance->DIN = *(uint32_t*)(ctr0addr); - ctr0addr+=4U; - hcryp->Instance->DIN = *(uint32_t*)(ctr0addr); + hcryp->Instance->DIN = *(uint32_t *)(ctr0addr); + ctr0addr += 4U; + hcryp->Instance->DIN = *(uint32_t *)(ctr0addr); + ctr0addr += 4U; + hcryp->Instance->DIN = *(uint32_t *)(ctr0addr); + ctr0addr += 4U; + hcryp->Instance->DIN = *(uint32_t *)(ctr0addr); } /* Wait for OFNE flag to be raised */ tickstart = HAL_GetTick(); - while(HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE)) + while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE)) { /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { /* Disable the CRYP peripheral Clock */ __HAL_CRYP_DISABLE(hcryp); @@ -465,13 +465,13 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u } /* Read the Auth TAG in the IN FIFO */ - *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT; - tagaddr+=4U; - *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT; - tagaddr+=4U; - *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT; - tagaddr+=4U; - *(uint32_t*)(tagaddr) = hcryp->Instance->DOUT; + *(uint32_t *)(tagaddr) = hcryp->Instance->DOUT; + tagaddr += 4U; + *(uint32_t *)(tagaddr) = hcryp->Instance->DOUT; + tagaddr += 4U; + *(uint32_t *)(tagaddr) = hcryp->Instance->DOUT; + tagaddr += 4U; + *(uint32_t *)(tagaddr) = hcryp->Instance->DOUT; #else /* AES */ @@ -480,75 +480,75 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u /* Write the counter block in the IN FIFO, CTR0 information from B0 data has to be swapped according to the DATATYPE*/ - if(hcryp->Init.DataType == CRYP_DATATYPE_8B) + if (hcryp->Init.DataType == CRYP_DATATYPE_8B) { - ctr0[0]=(__REV(hcryp->Init.B0[0]) & CRYP_CCM_CTR0_0); - ctr0[1]=__REV(hcryp->Init.B0[1]); - ctr0[2]=__REV(hcryp->Init.B0[2]); - ctr0[3]=(__REV(hcryp->Init.B0[3])& CRYP_CCM_CTR0_3); - - hcryp->Instance->DINR = __REV(*(uint32_t*)(ctr0addr)); - ctr0addr+=4U; - hcryp->Instance->DINR = __REV(*(uint32_t*)(ctr0addr)); - ctr0addr+=4U; - hcryp->Instance->DINR = __REV(*(uint32_t*)(ctr0addr)); - ctr0addr+=4U; - hcryp->Instance->DINR = __REV(*(uint32_t*)(ctr0addr)); + ctr0[0] = (__REV(hcryp->Init.B0[0]) & CRYP_CCM_CTR0_0); + ctr0[1] = __REV(hcryp->Init.B0[1]); + ctr0[2] = __REV(hcryp->Init.B0[2]); + ctr0[3] = (__REV(hcryp->Init.B0[3])& CRYP_CCM_CTR0_3); + + hcryp->Instance->DINR = __REV(*(uint32_t *)(ctr0addr)); + ctr0addr += 4U; + hcryp->Instance->DINR = __REV(*(uint32_t *)(ctr0addr)); + ctr0addr += 4U; + hcryp->Instance->DINR = __REV(*(uint32_t *)(ctr0addr)); + ctr0addr += 4U; + hcryp->Instance->DINR = __REV(*(uint32_t *)(ctr0addr)); } - else if(hcryp->Init.DataType == CRYP_DATATYPE_16B) + else if (hcryp->Init.DataType == CRYP_DATATYPE_16B) { - ctr0[0]= ( __ROR((hcryp->Init.B0[0]), 16U)& CRYP_CCM_CTR0_0); - ctr0[1]= __ROR((hcryp->Init.B0[1]), 16U); - ctr0[2]= __ROR((hcryp->Init.B0[2]), 16U); - ctr0[3]= ( __ROR((hcryp->Init.B0[3]), 16U)& CRYP_CCM_CTR0_3); - - hcryp->Instance->DINR = __ROR(*(uint32_t*)(ctr0addr), 16U); - ctr0addr+=4U; - hcryp->Instance->DINR = __ROR(*(uint32_t*)(ctr0addr), 16U); - ctr0addr+=4U; - hcryp->Instance->DINR = __ROR(*(uint32_t*)(ctr0addr), 16U); - ctr0addr+=4U; - hcryp->Instance->DINR = __ROR(*(uint32_t*)(ctr0addr), 16U); + ctr0[0] = (__ROR((hcryp->Init.B0[0]), 16U)& CRYP_CCM_CTR0_0); + ctr0[1] = __ROR((hcryp->Init.B0[1]), 16U); + ctr0[2] = __ROR((hcryp->Init.B0[2]), 16U); + ctr0[3] = (__ROR((hcryp->Init.B0[3]), 16U)& CRYP_CCM_CTR0_3); + + hcryp->Instance->DINR = __ROR(*(uint32_t *)(ctr0addr), 16U); + ctr0addr += 4U; + hcryp->Instance->DINR = __ROR(*(uint32_t *)(ctr0addr), 16U); + ctr0addr += 4U; + hcryp->Instance->DINR = __ROR(*(uint32_t *)(ctr0addr), 16U); + ctr0addr += 4U; + hcryp->Instance->DINR = __ROR(*(uint32_t *)(ctr0addr), 16U); } - else if(hcryp->Init.DataType == CRYP_DATATYPE_1B) + else if (hcryp->Init.DataType == CRYP_DATATYPE_1B) { - ctr0[0]=(__RBIT(hcryp->Init.B0[0])& CRYP_CCM_CTR0_0); - ctr0[1]=__RBIT(hcryp->Init.B0[1]); - ctr0[2]=__RBIT(hcryp->Init.B0[2]); - ctr0[3]=(__RBIT(hcryp->Init.B0[3])& CRYP_CCM_CTR0_3); - - hcryp->Instance->DINR = __RBIT(*(uint32_t*)(ctr0addr)); - ctr0addr+=4U; - hcryp->Instance->DINR = __RBIT(*(uint32_t*)(ctr0addr)); - ctr0addr+=4U; - hcryp->Instance->DINR = __RBIT(*(uint32_t*)(ctr0addr)); - ctr0addr+=4U; - hcryp->Instance->DINR = __RBIT(*(uint32_t*)(ctr0addr)); + ctr0[0] = (__RBIT(hcryp->Init.B0[0])& CRYP_CCM_CTR0_0); + ctr0[1] = __RBIT(hcryp->Init.B0[1]); + ctr0[2] = __RBIT(hcryp->Init.B0[2]); + ctr0[3] = (__RBIT(hcryp->Init.B0[3])& CRYP_CCM_CTR0_3); + + hcryp->Instance->DINR = __RBIT(*(uint32_t *)(ctr0addr)); + ctr0addr += 4U; + hcryp->Instance->DINR = __RBIT(*(uint32_t *)(ctr0addr)); + ctr0addr += 4U; + hcryp->Instance->DINR = __RBIT(*(uint32_t *)(ctr0addr)); + ctr0addr += 4U; + hcryp->Instance->DINR = __RBIT(*(uint32_t *)(ctr0addr)); } else { - ctr0[0]=(hcryp->Init.B0[0]) & CRYP_CCM_CTR0_0; - ctr0[1]=hcryp->Init.B0[1]; - ctr0[2]=hcryp->Init.B0[2]; - ctr0[3]=hcryp->Init.B0[3] & CRYP_CCM_CTR0_3; - - hcryp->Instance->DINR = *(uint32_t*)(ctr0addr); - ctr0addr+=4U; - hcryp->Instance->DINR = *(uint32_t*)(ctr0addr); - ctr0addr+=4U; - hcryp->Instance->DINR = *(uint32_t*)(ctr0addr); - ctr0addr+=4U; - hcryp->Instance->DINR = *(uint32_t*)(ctr0addr); + ctr0[0] = (hcryp->Init.B0[0]) & CRYP_CCM_CTR0_0; + ctr0[1] = hcryp->Init.B0[1]; + ctr0[2] = hcryp->Init.B0[2]; + ctr0[3] = hcryp->Init.B0[3] & CRYP_CCM_CTR0_3; + + hcryp->Instance->DINR = *(uint32_t *)(ctr0addr); + ctr0addr += 4U; + hcryp->Instance->DINR = *(uint32_t *)(ctr0addr); + ctr0addr += 4U; + hcryp->Instance->DINR = *(uint32_t *)(ctr0addr); + ctr0addr += 4U; + hcryp->Instance->DINR = *(uint32_t *)(ctr0addr); } /* Wait for CCF flag to be raised */ tickstart = HAL_GetTick(); - while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)) + while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)) { /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { /* Disable the CRYP peripheral Clock */ __HAL_CRYP_DISABLE(hcryp); @@ -565,13 +565,13 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u } /* Read the authentication TAG in the output FIFO */ - *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR; - tagaddr+=4U; - *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR; - tagaddr+=4U; - *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR; - tagaddr+=4U; - *(uint32_t*)(tagaddr) = hcryp->Instance->DOUTR; + *(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR; + tagaddr += 4U; + *(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR; + tagaddr += 4U; + *(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR; + tagaddr += 4U; + *(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR; /* Clear CCF Flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); @@ -603,8 +603,8 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u #if defined (AES) /** @defgroup CRYPEx_Exported_Functions_Group2 Key Derivation functions - * @brief AutoKeyDerivation functions - * + * @brief AutoKeyDerivation functions + * @verbatim ============================================================================== ##### Key Derivation functions ##### @@ -624,7 +624,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u */ void HAL_CRYPEx_EnableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp) { - if(hcryp->State == HAL_CRYP_STATE_READY) + if (hcryp->State == HAL_CRYP_STATE_READY) { hcryp->AutoKeyDerivation = ENABLE; } @@ -641,7 +641,7 @@ void HAL_CRYPEx_EnableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp) */ void HAL_CRYPEx_DisableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp) { - if(hcryp->State == HAL_CRYP_STATE_READY) + if (hcryp->State == HAL_CRYP_STATE_READY) { hcryp->AutoKeyDerivation = DISABLE; } diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dcmi.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dcmi.c index b7dc1e3961..29c22f61a2 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dcmi.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dcmi.c @@ -177,9 +177,9 @@ static void DCMI_DMAError(DMA_HandleTypeDef *hdma); HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi) { /* Check the DCMI peripheral state */ - if(hdcmi == NULL) + if (hdcmi == NULL) { - return HAL_ERROR; + return HAL_ERROR; } /* Check function parameters */ @@ -192,21 +192,23 @@ HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi) assert_param(IS_DCMI_EXTENDED_DATA(hdcmi->Init.ExtendedDataMode)); assert_param(IS_DCMI_MODE_JPEG(hdcmi->Init.JPEGMode)); +#ifdef DCMI_CR_BSM assert_param(IS_DCMI_BYTE_SELECT_MODE(hdcmi->Init.ByteSelectMode)); assert_param(IS_DCMI_BYTE_SELECT_START(hdcmi->Init.ByteSelectStart)); assert_param(IS_DCMI_LINE_SELECT_MODE(hdcmi->Init.LineSelectMode)); assert_param(IS_DCMI_LINE_SELECT_START(hdcmi->Init.LineSelectStart)); +#endif - if(hdcmi->State == HAL_DCMI_STATE_RESET) + if (hdcmi->State == HAL_DCMI_STATE_RESET) { - /* Init the DCMI Callback settings */ + /* Init the DCMI Callback settings */ #if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1) hdcmi->FrameEventCallback = HAL_DCMI_FrameEventCallback; /* Legacy weak FrameEventCallback */ hdcmi->VsyncEventCallback = HAL_DCMI_VsyncEventCallback; /* Legacy weak VsyncEventCallback */ hdcmi->LineEventCallback = HAL_DCMI_LineEventCallback; /* Legacy weak LineEventCallback */ hdcmi->ErrorCallback = HAL_DCMI_ErrorCallback; /* Legacy weak ErrorCallback */ - if(hdcmi->MspInitCallback == NULL) + if (hdcmi->MspInitCallback == NULL) { /* Legacy weak MspInit Callback */ hdcmi->MspInitCallback = HAL_DCMI_MspInit; @@ -221,24 +223,43 @@ HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi) /* Change the DCMI state */ hdcmi->State = HAL_DCMI_STATE_BUSY; - /* Configures the HS, VS, DE and PC polarity */ - hdcmi->Instance->CR &= ~(DCMI_CR_PCKPOL | DCMI_CR_HSPOL | DCMI_CR_VSPOL | DCMI_CR_EDM_0 |\ - DCMI_CR_EDM_1 | DCMI_CR_FCRC_0 | DCMI_CR_FCRC_1 | DCMI_CR_JPEG |\ - DCMI_CR_ESS | DCMI_CR_BSM_0 | DCMI_CR_BSM_1 | DCMI_CR_OEBS |\ + +#ifdef DCMI_CR_BSM + if (hdcmi->Init.ExtendedDataMode != DCMI_EXTEND_DATA_8B) + { + /* Byte select mode must be programmed to the reset value if the extended mode + is not set to 8-bit data capture on every pixel clock */ + hdcmi->Init.ByteSelectMode = DCMI_BSM_ALL; + } +#endif + /* Configures the HS, VS, DE and PC polarity */ +#ifdef DCMI_CR_BSM + hdcmi->Instance->CR &= ~(DCMI_CR_PCKPOL | DCMI_CR_HSPOL | DCMI_CR_VSPOL | DCMI_CR_EDM_0 | \ + DCMI_CR_EDM_1 | DCMI_CR_FCRC_0 | DCMI_CR_FCRC_1 | DCMI_CR_JPEG | \ + DCMI_CR_ESS | DCMI_CR_BSM_0 | DCMI_CR_BSM_1 | DCMI_CR_OEBS | \ DCMI_CR_LSM | DCMI_CR_OELS); - hdcmi->Instance->CR |= (uint32_t)(hdcmi->Init.SynchroMode | hdcmi->Init.CaptureRate |\ - hdcmi->Init.VSPolarity | hdcmi->Init.HSPolarity |\ - hdcmi->Init.PCKPolarity | hdcmi->Init.ExtendedDataMode |\ - hdcmi->Init.JPEGMode | hdcmi->Init.ByteSelectMode |\ - hdcmi->Init.ByteSelectStart | hdcmi->Init.LineSelectMode |\ - hdcmi->Init.LineSelectStart); + hdcmi->Instance->CR |= (uint32_t)(hdcmi->Init.SynchroMode | hdcmi->Init.CaptureRate | \ + hdcmi->Init.VSPolarity | hdcmi->Init.HSPolarity | \ + hdcmi->Init.PCKPolarity | hdcmi->Init.ExtendedDataMode | \ + hdcmi->Init.JPEGMode | hdcmi->Init.ByteSelectMode | \ + hdcmi->Init.ByteSelectStart | hdcmi->Init.LineSelectMode | \ + hdcmi->Init.LineSelectStart); +#else + hdcmi->Instance->CR &= ~(DCMI_CR_PCKPOL | DCMI_CR_HSPOL | DCMI_CR_VSPOL | DCMI_CR_EDM_0 | \ + DCMI_CR_EDM_1 | DCMI_CR_FCRC_0 | DCMI_CR_FCRC_1 | DCMI_CR_JPEG); + + hdcmi->Instance->CR |= (uint32_t)(hdcmi->Init.SynchroMode | hdcmi->Init.CaptureRate | \ + hdcmi->Init.VSPolarity | hdcmi->Init.HSPolarity | \ + hdcmi->Init.PCKPolarity | hdcmi->Init.ExtendedDataMode | \ + hdcmi->Init.JPEGMode); +#endif - if(hdcmi->Init.SynchroMode == DCMI_SYNCHRO_EMBEDDED) + if (hdcmi->Init.SynchroMode == DCMI_SYNCHRO_EMBEDDED) { - hdcmi->Instance->ESCR = (((uint32_t)hdcmi->Init.SyncroCode.FrameStartCode) |\ - ((uint32_t)hdcmi->Init.SyncroCode.LineStartCode << DCMI_ESCR_LSC_Pos)|\ - ((uint32_t)hdcmi->Init.SyncroCode.LineEndCode << DCMI_ESCR_LEC_Pos) |\ + hdcmi->Instance->ESCR = (((uint32_t)hdcmi->Init.SyncroCode.FrameStartCode) | \ + ((uint32_t)hdcmi->Init.SyncroCode.LineStartCode << DCMI_ESCR_LSC_Pos) | \ + ((uint32_t)hdcmi->Init.SyncroCode.LineEndCode << DCMI_ESCR_LEC_Pos) | \ ((uint32_t)hdcmi->Init.SyncroCode.FrameEndCode << DCMI_ESCR_FEC_Pos)); } @@ -266,7 +287,7 @@ HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi) HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi) { #if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1) - if(hdcmi->MspDeInitCallback == NULL) + if (hdcmi->MspDeInitCallback == NULL) { hdcmi->MspDeInitCallback = HAL_DCMI_MspDeInit; } @@ -295,7 +316,7 @@ HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi) * the configuration information for DCMI. * @retval None */ -__weak void HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi) +__weak void HAL_DCMI_MspInit(DCMI_HandleTypeDef *hdcmi) { /* Prevent unused argument(s) compilation warning */ UNUSED(hdcmi); @@ -311,7 +332,7 @@ __weak void HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi) * the configuration information for DCMI. * @retval None */ -__weak void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi) +__weak void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef *hdcmi) { /* Prevent unused argument(s) compilation warning */ UNUSED(hdcmi); @@ -350,7 +371,7 @@ __weak void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi) * @param Length The length of capture to be transferred. * @retval HAL status */ -HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length) +HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef *hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length) { /* Initialize the second memory address */ uint32_t SecondMemAddress = 0; @@ -369,7 +390,7 @@ HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mo /* Configure the DCMI Mode */ hdcmi->Instance->CR &= ~(DCMI_CR_CM); - hdcmi->Instance->CR |= (uint32_t)(DCMI_Mode); + hdcmi->Instance->CR |= (uint32_t)(DCMI_Mode); /* Set the DMA memory0 conversion complete callback */ hdcmi->DMA_Handle->XferCpltCallback = DCMI_DMAXferCplt; @@ -383,11 +404,16 @@ HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mo /* Reset transfer counters value */ hdcmi->XferCount = 0; hdcmi->XferTransferNumber = 0; + hdcmi->XferSize = 0; + hdcmi->pBuffPtr = 0; - if(Length <= 0xFFFF) + if (Length <= 0xFFFFU) { /* Enable the DMA Stream */ - HAL_DMA_Start_IT(hdcmi->DMA_Handle, (uint32_t)&hdcmi->Instance->DR, (uint32_t)pData, Length); + if (HAL_DMA_Start_IT(hdcmi->DMA_Handle, (uint32_t)&hdcmi->Instance->DR, (uint32_t)pData, Length) != HAL_OK) + { + return HAL_ERROR; + } } else /* DCMI_DOUBLE_BUFFER Mode */ { @@ -400,21 +426,24 @@ HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mo hdcmi->pBuffPtr = pData; /* Get the number of buffer */ - while(hdcmi->XferSize > 0xFFFF) + while (hdcmi->XferSize > 0xFFFFU) { - hdcmi->XferSize = (hdcmi->XferSize/2); - hdcmi->XferCount = hdcmi->XferCount*2; + hdcmi->XferSize = (hdcmi->XferSize / 2U); + hdcmi->XferCount = hdcmi->XferCount * 2U; } /* Update DCMI counter and transfer number*/ - hdcmi->XferCount = (hdcmi->XferCount - 2); + hdcmi->XferCount = (hdcmi->XferCount - 2U); hdcmi->XferTransferNumber = hdcmi->XferCount; /* Update second memory address */ - SecondMemAddress = (uint32_t)(pData + (4*hdcmi->XferSize)); + SecondMemAddress = (uint32_t)(pData + (4 * hdcmi->XferSize)); /* Start DMA multi buffer transfer */ - HAL_DMAEx_MultiBufferStart_IT(hdcmi->DMA_Handle, (uint32_t)&hdcmi->Instance->DR, (uint32_t)pData, SecondMemAddress, hdcmi->XferSize); + if (HAL_DMAEx_MultiBufferStart_IT(hdcmi->DMA_Handle, (uint32_t)&hdcmi->Instance->DR, (uint32_t)pData, SecondMemAddress, hdcmi->XferSize) != HAL_OK) + { + return HAL_ERROR; + } } /* Enable Capture */ @@ -433,9 +462,9 @@ HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mo * the configuration information for DCMI. * @retval HAL status */ -HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi) +HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef *hdcmi) { - register uint32_t count = HAL_TIMEOUT_DCMI_STOP * (SystemCoreClock /8/1000); + register uint32_t count = HAL_TIMEOUT_DCMI_STOP * (SystemCoreClock / 8U / 1000U); HAL_StatusTypeDef status = HAL_OK; /* Process locked */ @@ -450,7 +479,7 @@ HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi) /* Check if the DCMI capture effectively disabled */ do { - if (count-- == 0) + if (count-- == 0U) { /* Update error code */ hdcmi->ErrorCode |= HAL_DCMI_ERROR_TIMEOUT; @@ -459,13 +488,13 @@ HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi) break; } } - while((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0); + while ((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0U); /* Disable the DCMI */ __HAL_DCMI_DISABLE(hdcmi); /* Disable the DMA */ - HAL_DMA_Abort(hdcmi->DMA_Handle); + (void)HAL_DMA_Abort(hdcmi->DMA_Handle); /* Update error code */ hdcmi->ErrorCode |= HAL_DCMI_ERROR_NONE; @@ -486,15 +515,15 @@ HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi) * the configuration information for DCMI. * @retval HAL status */ -HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef* hdcmi) +HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef *hdcmi) { - register uint32_t count = HAL_TIMEOUT_DCMI_STOP * (SystemCoreClock /8/1000); + register uint32_t count = HAL_TIMEOUT_DCMI_STOP * (SystemCoreClock / 8U / 1000U); HAL_StatusTypeDef status = HAL_OK; /* Process locked */ __HAL_LOCK(hdcmi); - if(hdcmi->State == HAL_DCMI_STATE_BUSY) + if (hdcmi->State == HAL_DCMI_STATE_BUSY) { /* Change DCMI state */ hdcmi->State = HAL_DCMI_STATE_SUSPENDED; @@ -505,7 +534,7 @@ HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef* hdcmi) /* Check if the DCMI capture effectively disabled */ do { - if (count-- == 0) + if (count-- == 0U) { /* Update error code */ hdcmi->ErrorCode |= HAL_DCMI_ERROR_TIMEOUT; @@ -517,7 +546,7 @@ HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef* hdcmi) break; } } - while((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0); + while ((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0U); } /* Process Unlocked */ __HAL_UNLOCK(hdcmi); @@ -532,12 +561,12 @@ HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef* hdcmi) * the configuration information for DCMI. * @retval HAL status */ -HAL_StatusTypeDef HAL_DCMI_Resume(DCMI_HandleTypeDef* hdcmi) +HAL_StatusTypeDef HAL_DCMI_Resume(DCMI_HandleTypeDef *hdcmi) { /* Process locked */ __HAL_LOCK(hdcmi); - if(hdcmi->State == HAL_DCMI_STATE_SUSPENDED) + if (hdcmi->State == HAL_DCMI_STATE_SUSPENDED) { /* Change DCMI state */ hdcmi->State = HAL_DCMI_STATE_BUSY; @@ -563,7 +592,7 @@ void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi) uint32_t isr_value = READ_REG(hdcmi->Instance->MISR); /* Synchronization error interrupt management *******************************/ - if((isr_value & DCMI_FLAG_ERRRI) == DCMI_FLAG_ERRRI) + if ((isr_value & DCMI_FLAG_ERRRI) == DCMI_FLAG_ERRRI) { /* Clear the Synchronization error flag */ __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_ERRRI); @@ -578,10 +607,10 @@ void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi) hdcmi->DMA_Handle->XferAbortCallback = DCMI_DMAError; /* Abort the DMA Transfer */ - HAL_DMA_Abort_IT(hdcmi->DMA_Handle); + (void)HAL_DMA_Abort_IT(hdcmi->DMA_Handle); } /* Overflow interrupt management ********************************************/ - if((isr_value & DCMI_FLAG_OVRRI) == DCMI_FLAG_OVRRI) + if ((isr_value & DCMI_FLAG_OVRRI) == DCMI_FLAG_OVRRI) { /* Clear the Overflow flag */ __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_OVRRI); @@ -596,10 +625,13 @@ void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi) hdcmi->DMA_Handle->XferAbortCallback = DCMI_DMAError; /* Abort the DMA Transfer */ - HAL_DMA_Abort_IT(hdcmi->DMA_Handle); + if (HAL_DMA_Abort_IT(hdcmi->DMA_Handle) != HAL_OK) + { + DCMI_DMAError(hdcmi->DMA_Handle); + } } /* Line Interrupt management ************************************************/ - if((isr_value & DCMI_FLAG_LINERI) == DCMI_FLAG_LINERI) + if ((isr_value & DCMI_FLAG_LINERI) == DCMI_FLAG_LINERI) { /* Clear the Line interrupt flag */ __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_LINERI); @@ -613,7 +645,7 @@ void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi) #endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */ } /* VSYNC interrupt management ***********************************************/ - if((isr_value & DCMI_FLAG_VSYNCRI) == DCMI_FLAG_VSYNCRI) + if ((isr_value & DCMI_FLAG_VSYNCRI) == DCMI_FLAG_VSYNCRI) { /* Clear the VSYNC flag */ __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_VSYNCRI); @@ -627,10 +659,10 @@ void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi) #endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */ } /* FRAME interrupt management ***********************************************/ - if((isr_value & DCMI_FLAG_FRAMERI) == DCMI_FLAG_FRAMERI) + if ((isr_value & DCMI_FLAG_FRAMERI) == DCMI_FLAG_FRAMERI) { /* When snapshot mode, disable Vsync, Error and Overrun interrupts */ - if((hdcmi->Instance->CR & DCMI_CR_CM) == DCMI_MODE_SNAPSHOT) + if ((hdcmi->Instance->CR & DCMI_CR_CM) == DCMI_MODE_SNAPSHOT) { /* Disable the Line, Vsync, Error and Overrun interrupts */ __HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_LINE | DCMI_IT_VSYNC | DCMI_IT_ERR | DCMI_IT_OVR); @@ -822,6 +854,37 @@ HAL_StatusTypeDef HAL_DCMI_EnableCrop(DCMI_HandleTypeDef *hdcmi) return HAL_OK; } +/** + * @brief Set embedded synchronization delimiters unmasks. + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains + * the configuration information for DCMI. + * @param SyncUnmask pointer to a DCMI_SyncUnmaskTypeDef structure that contains + * the embedded synchronization delimiters unmasks. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DCMI_ConfigSyncUnmask(DCMI_HandleTypeDef *hdcmi, DCMI_SyncUnmaskTypeDef *SyncUnmask) +{ + /* Process Locked */ + __HAL_LOCK(hdcmi); + + /* Lock the DCMI peripheral state */ + hdcmi->State = HAL_DCMI_STATE_BUSY; + + /* Write DCMI embedded synchronization unmask register */ + hdcmi->Instance->ESUR = (((uint32_t)SyncUnmask->FrameStartUnmask) | \ + ((uint32_t)SyncUnmask->LineStartUnmask << DCMI_ESUR_LSU_Pos) | \ + ((uint32_t)SyncUnmask->LineEndUnmask << DCMI_ESUR_LEU_Pos) | \ + ((uint32_t)SyncUnmask->FrameEndUnmask << DCMI_ESUR_FEU_Pos)); + + /* Change the DCMI state*/ + hdcmi->State = HAL_DCMI_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdcmi); + + return HAL_OK; +} + /** * @} */ @@ -877,7 +940,7 @@ HAL_StatusTypeDef HAL_DCMI_RegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_ { HAL_StatusTypeDef status = HAL_OK; - if(pCallback == NULL) + if (pCallback == NULL) { /* update the error code */ hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK; @@ -886,58 +949,58 @@ HAL_StatusTypeDef HAL_DCMI_RegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_ } else { - if(hdcmi->State == HAL_DCMI_STATE_READY) + if (hdcmi->State == HAL_DCMI_STATE_READY) { switch (CallbackID) { - case HAL_DCMI_FRAME_EVENT_CB_ID : - hdcmi->FrameEventCallback = pCallback; - break; - - case HAL_DCMI_VSYNC_EVENT_CB_ID : - hdcmi->VsyncEventCallback = pCallback; - break; - - case HAL_DCMI_LINE_EVENT_CB_ID : - hdcmi->LineEventCallback = pCallback; - break; - - case HAL_DCMI_ERROR_CB_ID : - hdcmi->ErrorCallback = pCallback; - break; - - case HAL_DCMI_MSPINIT_CB_ID : - hdcmi->MspInitCallback = pCallback; - break; - - case HAL_DCMI_MSPDEINIT_CB_ID : - hdcmi->MspDeInitCallback = pCallback; - break; - - default : - /* Return error status */ - status = HAL_ERROR; - break; + case HAL_DCMI_FRAME_EVENT_CB_ID : + hdcmi->FrameEventCallback = pCallback; + break; + + case HAL_DCMI_VSYNC_EVENT_CB_ID : + hdcmi->VsyncEventCallback = pCallback; + break; + + case HAL_DCMI_LINE_EVENT_CB_ID : + hdcmi->LineEventCallback = pCallback; + break; + + case HAL_DCMI_ERROR_CB_ID : + hdcmi->ErrorCallback = pCallback; + break; + + case HAL_DCMI_MSPINIT_CB_ID : + hdcmi->MspInitCallback = pCallback; + break; + + case HAL_DCMI_MSPDEINIT_CB_ID : + hdcmi->MspDeInitCallback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; } } - else if(hdcmi->State == HAL_DCMI_STATE_RESET) + else if (hdcmi->State == HAL_DCMI_STATE_RESET) { switch (CallbackID) { - case HAL_DCMI_MSPINIT_CB_ID : - hdcmi->MspInitCallback = pCallback; - break; - - case HAL_DCMI_MSPDEINIT_CB_ID : - hdcmi->MspDeInitCallback = pCallback; - break; - - default : - /* update the error code */ - hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; + case HAL_DCMI_MSPINIT_CB_ID : + hdcmi->MspInitCallback = pCallback; + break; + + case HAL_DCMI_MSPDEINIT_CB_ID : + hdcmi->MspDeInitCallback = pCallback; + break; + + default : + /* update the error code */ + hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; } } else @@ -962,60 +1025,60 @@ HAL_StatusTypeDef HAL_DCMI_UnRegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCM { HAL_StatusTypeDef status = HAL_OK; - if(hdcmi->State == HAL_DCMI_STATE_READY) + if (hdcmi->State == HAL_DCMI_STATE_READY) { switch (CallbackID) { - case HAL_DCMI_FRAME_EVENT_CB_ID : - hdcmi->FrameEventCallback = HAL_DCMI_FrameEventCallback; /* Legacy weak FrameEventCallback */ - break; + case HAL_DCMI_FRAME_EVENT_CB_ID : + hdcmi->FrameEventCallback = HAL_DCMI_FrameEventCallback; /* Legacy weak FrameEventCallback */ + break; - case HAL_DCMI_VSYNC_EVENT_CB_ID : - hdcmi->VsyncEventCallback = HAL_DCMI_VsyncEventCallback; /* Legacy weak VsyncEventCallback */ - break; + case HAL_DCMI_VSYNC_EVENT_CB_ID : + hdcmi->VsyncEventCallback = HAL_DCMI_VsyncEventCallback; /* Legacy weak VsyncEventCallback */ + break; - case HAL_DCMI_LINE_EVENT_CB_ID : - hdcmi->LineEventCallback = HAL_DCMI_LineEventCallback; /* Legacy weak LineEventCallback */ - break; + case HAL_DCMI_LINE_EVENT_CB_ID : + hdcmi->LineEventCallback = HAL_DCMI_LineEventCallback; /* Legacy weak LineEventCallback */ + break; - case HAL_DCMI_ERROR_CB_ID : - hdcmi->ErrorCallback = HAL_DCMI_ErrorCallback; /* Legacy weak ErrorCallback */ - break; + case HAL_DCMI_ERROR_CB_ID : + hdcmi->ErrorCallback = HAL_DCMI_ErrorCallback; /* Legacy weak ErrorCallback */ + break; - case HAL_DCMI_MSPINIT_CB_ID : - hdcmi->MspInitCallback = HAL_DCMI_MspInit; - break; + case HAL_DCMI_MSPINIT_CB_ID : + hdcmi->MspInitCallback = HAL_DCMI_MspInit; + break; - case HAL_DCMI_MSPDEINIT_CB_ID : - hdcmi->MspDeInitCallback = HAL_DCMI_MspDeInit; - break; + case HAL_DCMI_MSPDEINIT_CB_ID : + hdcmi->MspDeInitCallback = HAL_DCMI_MspDeInit; + break; - default : - /* update the error code */ - hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; + default : + /* update the error code */ + hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; } } - else if(hdcmi->State == HAL_DCMI_STATE_RESET) + else if (hdcmi->State == HAL_DCMI_STATE_RESET) { switch (CallbackID) { - case HAL_DCMI_MSPINIT_CB_ID : - hdcmi->MspInitCallback = HAL_DCMI_MspInit; - break; + case HAL_DCMI_MSPINIT_CB_ID : + hdcmi->MspInitCallback = HAL_DCMI_MspInit; + break; - case HAL_DCMI_MSPDEINIT_CB_ID : - hdcmi->MspDeInitCallback = HAL_DCMI_MspDeInit; - break; + case HAL_DCMI_MSPDEINIT_CB_ID : + hdcmi->MspDeInitCallback = HAL_DCMI_MspDeInit; + break; - default : - /* update the error code */ - hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; + default : + /* update the error code */ + hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; } } else @@ -1037,59 +1100,59 @@ HAL_StatusTypeDef HAL_DCMI_UnRegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCM /** @defgroup DCMI_Private_Functions DCMI Private Functions * @{ */ - /** - * @brief DMA conversion complete callback. - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ +/** +* @brief DMA conversion complete callback. +* @param hdma pointer to a DMA_HandleTypeDef structure that contains +* the configuration information for the specified DMA module. +* @retval None +*/ static void DCMI_DMAXferCplt(DMA_HandleTypeDef *hdma) { uint32_t tmp = 0; - DCMI_HandleTypeDef* hdcmi = ( DCMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + DCMI_HandleTypeDef *hdcmi = (DCMI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - if(hdcmi->XferCount != 0) + if (hdcmi->XferCount != 0) { /* Update memory 0 address location */ tmp = ((hdcmi->DMA_Handle->Instance->CR) & DMA_SxCR_CT); - if(((hdcmi->XferCount % 2) == 0) && (tmp != 0)) + if (((hdcmi->XferCount % 2) == 0) && (tmp != 0)) { tmp = hdcmi->DMA_Handle->Instance->M0AR; - HAL_DMAEx_ChangeMemory(hdcmi->DMA_Handle, (tmp + (8*hdcmi->XferSize)), MEMORY0); + HAL_DMAEx_ChangeMemory(hdcmi->DMA_Handle, (tmp + (8 * hdcmi->XferSize)), MEMORY0); hdcmi->XferCount--; } /* Update memory 1 address location */ - else if((hdcmi->DMA_Handle->Instance->CR & DMA_SxCR_CT) == 0) + else if ((hdcmi->DMA_Handle->Instance->CR & DMA_SxCR_CT) == 0) { tmp = hdcmi->DMA_Handle->Instance->M1AR; - HAL_DMAEx_ChangeMemory(hdcmi->DMA_Handle, (tmp + (8*hdcmi->XferSize)), MEMORY1); + HAL_DMAEx_ChangeMemory(hdcmi->DMA_Handle, (tmp + (8 * hdcmi->XferSize)), MEMORY1); hdcmi->XferCount--; } } /* Update memory 0 address location */ - else if((hdcmi->DMA_Handle->Instance->CR & DMA_SxCR_CT) != 0) + else if ((hdcmi->DMA_Handle->Instance->CR & DMA_SxCR_CT) != 0) { hdcmi->DMA_Handle->Instance->M0AR = hdcmi->pBuffPtr; } /* Update memory 1 address location */ - else if((hdcmi->DMA_Handle->Instance->CR & DMA_SxCR_CT) == 0) + else if ((hdcmi->DMA_Handle->Instance->CR & DMA_SxCR_CT) == 0) { tmp = hdcmi->pBuffPtr; - hdcmi->DMA_Handle->Instance->M1AR = (tmp + (4*hdcmi->XferSize)); + hdcmi->DMA_Handle->Instance->M1AR = (tmp + (4 * hdcmi->XferSize)); hdcmi->XferCount = hdcmi->XferTransferNumber; } /* Check if the frame is transferred */ - if(hdcmi->XferCount == hdcmi->XferTransferNumber) + if (hdcmi->XferCount == hdcmi->XferTransferNumber) { /* Enable the Frame interrupt */ __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_FRAME); /* When snapshot mode, set dcmi state to ready */ - if((hdcmi->Instance->CR & DCMI_CR_CM) == DCMI_MODE_SNAPSHOT) + if ((hdcmi->Instance->CR & DCMI_CR_CM) == DCMI_MODE_SNAPSHOT) { - hdcmi->State= HAL_DCMI_STATE_READY; + hdcmi->State = HAL_DCMI_STATE_READY; } } } @@ -1102,9 +1165,9 @@ static void DCMI_DMAXferCplt(DMA_HandleTypeDef *hdma) */ static void DCMI_DMAError(DMA_HandleTypeDef *hdma) { - DCMI_HandleTypeDef* hdcmi = ( DCMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + DCMI_HandleTypeDef *hdcmi = (DCMI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - if(hdcmi->DMA_Handle->ErrorCode != HAL_DMA_ERROR_FE) + if (hdcmi->DMA_Handle->ErrorCode != HAL_DMA_ERROR_FE) { /* Initialize the DCMI state*/ hdcmi->State = HAL_DCMI_STATE_READY; @@ -1115,10 +1178,10 @@ static void DCMI_DMAError(DMA_HandleTypeDef *hdma) /* DCMI error Callback */ #if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1) - /*Call registered DCMI error callback*/ - hdcmi->ErrorCallback(hdcmi); + /*Call registered DCMI error callback*/ + hdcmi->ErrorCallback(hdcmi); #else - HAL_DCMI_ErrorCallback(hdcmi); + HAL_DCMI_ErrorCallback(hdcmi); #endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */ } diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dcmi_ex.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dcmi_ex.c index b852675c44..9a059b102c 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dcmi_ex.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dcmi_ex.c @@ -4,8 +4,8 @@ * @author MCD Application Team * @brief Empty file; This file is no longer used to handle the Black&White * feature. Its content is now moved to common files - * (stm32f7xx_hal_dcmi.c/.h) as there's no device's dependency within F7 - * family. It's just kept for compatibility reasons. + * (stm32f7xx_hal_dcmi.c/.h) as there's no device's dependency within + * this family. It's just kept for compatibility reasons. * ****************************************************************************** * @attention diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dfsdm.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dfsdm.c index 2a8e053fa6..5802390534 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dfsdm.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dfsdm.c @@ -157,23 +157,26 @@ *** Callback registration *** ============================= - + [..] The compilation define USE_HAL_DFSDM_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use functions @ref HAL_DFSDM_Channel_RegisterCallback(), - @ref HAL_DFSDM_Filter_RegisterCallback() or - @ref HAL_DFSDM_Filter_RegisterAwdCallback() to register a user callback. + Use functions HAL_DFSDM_Channel_RegisterCallback(), + HAL_DFSDM_Filter_RegisterCallback() or + HAL_DFSDM_Filter_RegisterAwdCallback() to register a user callback. - Function @ref HAL_DFSDM_Channel_RegisterCallback() allows to register + [..] + Function HAL_DFSDM_Channel_RegisterCallback() allows to register following callbacks: (+) CkabCallback : DFSDM channel clock absence detection callback. (+) ScdCallback : DFSDM channel short circuit detection callback. (+) MspInitCallback : DFSDM channel MSP init callback. (+) MspDeInitCallback : DFSDM channel MSP de-init callback. + [..] This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. - Function @ref HAL_DFSDM_Filter_RegisterCallback() allows to register + [..] + Function HAL_DFSDM_Filter_RegisterCallback() allows to register following callbacks: (+) RegConvCpltCallback : DFSDM filter regular conversion complete callback. (+) RegConvHalfCpltCallback : DFSDM filter half regular conversion complete callback. @@ -182,26 +185,33 @@ (+) ErrorCallback : DFSDM filter error callback. (+) MspInitCallback : DFSDM filter MSP init callback. (+) MspDeInitCallback : DFSDM filter MSP de-init callback. + [..] This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. + [..] For specific DFSDM filter analog watchdog callback use dedicated register callback: - @ref HAL_DFSDM_Filter_RegisterAwdCallback(). + HAL_DFSDM_Filter_RegisterAwdCallback(). - Use functions @ref HAL_DFSDM_Channel_UnRegisterCallback() or - @ref HAL_DFSDM_Filter_UnRegisterCallback() to reset a callback to the default + [..] + Use functions HAL_DFSDM_Channel_UnRegisterCallback() or + HAL_DFSDM_Filter_UnRegisterCallback() to reset a callback to the default weak function. - @ref HAL_DFSDM_Channel_UnRegisterCallback() takes as parameters the HAL peripheral handle, + [..] + HAL_DFSDM_Channel_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. + [..] This function allows to reset following callbacks: (+) CkabCallback : DFSDM channel clock absence detection callback. (+) ScdCallback : DFSDM channel short circuit detection callback. (+) MspInitCallback : DFSDM channel MSP init callback. (+) MspDeInitCallback : DFSDM channel MSP de-init callback. - @ref HAL_DFSDM_Filter_UnRegisterCallback() takes as parameters the HAL peripheral handle, + [..] + HAL_DFSDM_Filter_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. + [..] This function allows to reset following callbacks: (+) RegConvCpltCallback : DFSDM filter regular conversion complete callback. (+) RegConvHalfCpltCallback : DFSDM filter half regular conversion complete callback. @@ -211,29 +221,34 @@ (+) MspInitCallback : DFSDM filter MSP init callback. (+) MspDeInitCallback : DFSDM filter MSP de-init callback. + [..] For specific DFSDM filter analog watchdog callback use dedicated unregister callback: - @ref HAL_DFSDM_Filter_UnRegisterAwdCallback(). + HAL_DFSDM_Filter_UnRegisterAwdCallback(). + [..] By default, after the call of init function and if the state is RESET all callbacks are reset to the corresponding legacy weak functions: - examples @ref HAL_DFSDM_ChannelScdCallback(), @ref HAL_DFSDM_FilterErrorCallback(). + examples HAL_DFSDM_ChannelScdCallback(), HAL_DFSDM_FilterErrorCallback(). Exception done for MspInit and MspDeInit callbacks that are respectively reset to the legacy weak functions in the init and de-init only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the init and de-init keep and use the user MspInit/MspDeInit callbacks (registered beforehand) + [..] Callbacks can be registered/unregistered in READY state only. Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the init/de-init. In that case first register the MspInit/MspDeInit user callbacks using - @ref HAL_DFSDM_Channel_RegisterCallback() or - @ref HAL_DFSDM_Filter_RegisterCallback() before calling init or de-init function. + HAL_DFSDM_Channel_RegisterCallback() or + HAL_DFSDM_Filter_RegisterCallback() before calling init or de-init function. + [..] When The compilation define USE_HAL_DFSDM_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available and weak callbacks are used. + @endverbatim ****************************************************************************** * @attention diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c index 869b8a90a7..d4fe0891a9 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c @@ -85,7 +85,6 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32f7xx_hal.h" -#include "stm32f7xx_hal_exti.h" /** @addtogroup STM32F7xx_HAL_Driver * @{ @@ -105,7 +104,7 @@ #ifdef HAL_EXTI_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ -/* Private defines ------------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ /** @defgroup EXTI_Private_Constants EXTI Private Constants * @{ */ @@ -144,6 +143,8 @@ HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) { uint32_t regval; + uint32_t linepos; + uint32_t maskline; /* Check null pointer */ if ((hexti == NULL) || (pExtiConfig == NULL)) @@ -154,37 +155,77 @@ HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT /* Check parameters */ assert_param(IS_EXTI_LINE(pExtiConfig->Line)); assert_param(IS_EXTI_MODE(pExtiConfig->Mode)); - assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger)); /* Assign line number to handle */ hexti->Line = pExtiConfig->Line; - /* Clear EXTI line configuration */ - EXTI->IMR &= ~pExtiConfig->Line; - EXTI->EMR &= ~pExtiConfig->Line; + /* Compute line mask */ + linepos = (pExtiConfig->Line & EXTI_PIN_MASK); + maskline = (1uL << linepos); + + /* Configure triggers for configurable lines */ + if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) + { + assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger)); + + /* Configure rising trigger */ + /* Mask or set line */ + if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00u) + { + EXTI->RTSR |= maskline; + } + else + { + EXTI->RTSR &= ~maskline; + } + + /* Configure falling trigger */ + /* Mask or set line */ + if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00u) + { + EXTI->FTSR |= maskline; + } + else + { + EXTI->FTSR &= ~maskline; + } - /* Select the Mode for the selected external interrupts */ - regval = (uint32_t)EXTI_BASE; - regval += pExtiConfig->Mode; - *(__IO uint32_t *) regval |= pExtiConfig->Line; - /* Clear Rising Falling edge configuration */ - EXTI->RTSR &= ~pExtiConfig->Line; - EXTI->FTSR &= ~pExtiConfig->Line; + /* Configure gpio port selection in case of gpio exti line */ + if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) + { + assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel)); + assert_param(IS_EXTI_GPIO_PIN(linepos)); - /* Select the trigger for the selected external interrupts */ - if (pExtiConfig->Trigger == EXTI_TRIGGER_RISING_FALLING) + regval = SYSCFG->EXTICR[linepos >> 2u]; + regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + SYSCFG->EXTICR[linepos >> 2u] = regval; + } + } + + /* Configure interrupt mode : read current mode */ + /* Mask or set line */ + if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00u) + { + EXTI->IMR |= maskline; + } + else + { + EXTI->IMR &= ~maskline; + } + + /* Configure event mode : read current mode */ + /* Mask or set line */ + if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00u) { - /* Rising Falling edge */ - EXTI->RTSR |= pExtiConfig->Line; - EXTI->FTSR |= pExtiConfig->Line; + EXTI->EMR |= maskline; } else { - regval = (uint32_t)EXTI_BASE; - regval += pExtiConfig->Trigger; - *(__IO uint32_t *) regval |= pExtiConfig->Line; + EXTI->EMR &= ~maskline; } + return HAL_OK; } @@ -196,6 +237,10 @@ HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT */ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) { + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + /* Check null pointer */ if ((hexti == NULL) || (pExtiConfig == NULL)) { @@ -208,41 +253,67 @@ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT /* Store handle line number to configuration structure */ pExtiConfig->Line = hexti->Line; - /* Get EXTI mode to configiguration structure */ - if ((EXTI->IMR & hexti->Line) == hexti->Line) + /* Compute line mask */ + linepos = (pExtiConfig->Line & EXTI_PIN_MASK); + maskline = (1uL << linepos); + + /* 1] Get core mode : interrupt */ + + /* Check if selected line is enable */ + if ((EXTI->IMR & maskline) != 0x00u) { pExtiConfig->Mode = EXTI_MODE_INTERRUPT; } - else if ((EXTI->EMR & hexti->Line) == hexti->Line) + else { - pExtiConfig->Mode = EXTI_MODE_EVENT; + pExtiConfig->Mode = EXTI_MODE_NONE; } - else + + /* Get event mode */ + /* Check if selected line is enable */ + if ((EXTI->EMR & maskline) != 0x00u) { - /* No MODE selected */ - pExtiConfig->Mode = 0x0Bu; + pExtiConfig->Mode |= EXTI_MODE_EVENT; } - /* Get EXTI Trigger to configiguration structure */ - if ((EXTI->RTSR & hexti->Line) == hexti->Line) + /* 2] Get trigger for configurable lines : rising */ + if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) { - if ((EXTI->FTSR & hexti->Line) == hexti->Line) + /* Check if configuration of selected line is enable */ + if ((EXTI->RTSR & maskline) != 0x00u) { - pExtiConfig->Trigger = EXTI_TRIGGER_RISING_FALLING; + pExtiConfig->Trigger = EXTI_TRIGGER_RISING; } else { - pExtiConfig->Trigger = EXTI_TRIGGER_RISING; + pExtiConfig->Trigger = EXTI_TRIGGER_NONE; + } + + /* Get falling configuration */ + /* Check if configuration of selected line is enable */ + if ((EXTI->FTSR & maskline) != 0x00u) + { + pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING; + } + + /* Get Gpio port selection for gpio lines */ + if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) + { + assert_param(IS_EXTI_GPIO_PIN(linepos)); + + regval = SYSCFG->EXTICR[linepos >> 2u]; + pExtiConfig->GPIOSel = ((regval << (SYSCFG_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> 24); + } + else + { + pExtiConfig->GPIOSel = 0x00u; } - } - else if ((EXTI->FTSR & hexti->Line) == hexti->Line) - { - pExtiConfig->Trigger = EXTI_TRIGGER_FALLING; } else { /* No Trigger selected */ - pExtiConfig->Trigger = 0x00u; + pExtiConfig->Trigger = EXTI_TRIGGER_NONE; + pExtiConfig->GPIOSel = 0x00u; } return HAL_OK; @@ -255,6 +326,10 @@ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT */ HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti) { + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + /* Check null pointer */ if (hexti == NULL) { @@ -264,15 +339,32 @@ HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti) /* Check the parameter */ assert_param(IS_EXTI_LINE(hexti->Line)); + /* compute line mask */ + linepos = (hexti->Line & EXTI_PIN_MASK); + maskline = (1uL << linepos); + /* 1] Clear interrupt mode */ - EXTI->IMR = (EXTI->IMR & ~hexti->Line); + EXTI->IMR = (EXTI->IMR & ~maskline); /* 2] Clear event mode */ - EXTI->EMR = (EXTI->EMR & ~hexti->Line); + EXTI->EMR = (EXTI->EMR & ~maskline); + + /* 3] Clear triggers in case of configurable lines */ + if ((hexti->Line & EXTI_CONFIG) != 0x00u) + { + EXTI->RTSR = (EXTI->RTSR & ~maskline); + EXTI->FTSR = (EXTI->FTSR & ~maskline); - /* 3] Clear triggers */ - EXTI->RTSR = (EXTI->RTSR & ~hexti->Line); - EXTI->FTSR = (EXTI->FTSR & ~hexti->Line); + /* Get Gpio port selection for gpio lines */ + if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO) + { + assert_param(IS_EXTI_GPIO_PIN(linepos)); + + regval = SYSCFG->EXTICR[linepos >> 2u]; + regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + SYSCFG->EXTICR[linepos >> 2u] = regval; + } + } return HAL_OK; } @@ -352,17 +444,18 @@ HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLin */ void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti) { - __IO uint32_t *regaddr; uint32_t regval; + uint32_t maskline; - /* Get pending bit */ - regaddr = (&EXTI->PR); - regval = (*regaddr & hexti->Line); + /* Compute line mask */ + maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); + /* Get pending bit */ + regval = (EXTI->PR & maskline); if (regval != 0x00u) { /* Clear pending bit */ - *regaddr = hexti->Line; + EXTI->PR = maskline; /* Call callback */ if (hexti->PendingCallback != NULL) @@ -383,19 +476,21 @@ void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti) */ uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) { - __IO uint32_t *regaddr; uint32_t regval; + uint32_t linepos; + uint32_t maskline; /* Check parameters */ assert_param(IS_EXTI_LINE(hexti->Line)); + assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); assert_param(IS_EXTI_PENDING_EDGE(Edge)); - /* Get pending bit */ - regaddr = &EXTI->PR; + /* Compute line mask */ + linepos = (hexti->Line & EXTI_PIN_MASK); + maskline = (1uL << linepos); /* return 1 if bit is set else 0 */ - regval = ((*regaddr & hexti->Line) >> POSITION_VAL(hexti->Line)); - + regval = ((EXTI->PR & maskline) >> linepos); return regval; } @@ -410,12 +505,18 @@ uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) */ void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) { + uint32_t maskline; + /* Check parameters */ assert_param(IS_EXTI_LINE(hexti->Line)); + assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); assert_param(IS_EXTI_PENDING_EDGE(Edge)); + /* Compute line mask */ + maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); + /* Clear Pending bit */ - EXTI->PR = hexti->Line; + EXTI->PR = maskline; } /** @@ -425,10 +526,17 @@ void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) */ void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti) { + uint32_t maskline; + /* Check parameters */ assert_param(IS_EXTI_LINE(hexti->Line)); + assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + + /* Compute line mask */ + maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); - EXTI->SWIER = hexti->Line; + /* Generate Software interrupt */ + EXTI->SWIER = maskline; } /** diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c index 8fc3583135..0e24ced236 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c @@ -190,25 +190,6 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) if(iocurrent == ioposition) { /*--------------------- GPIO Mode Configuration ------------------------*/ - /* In case of Alternate function mode selection */ - if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) - { - /* Check the Alternate function parameter */ - assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); - - /* Configure Alternate function mapped with the current IO */ - temp = GPIOx->AFR[position >> 3]; - temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ; - temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4)); - GPIOx->AFR[position >> 3] = temp; - } - - /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ - temp = GPIOx->MODER; - temp &= ~(GPIO_MODER_MODER0 << (position * 2)); - temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2)); - GPIOx->MODER = temp; - /* In case of Output or Alternate function mode selection */ if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) @@ -234,6 +215,25 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) temp |= ((GPIO_Init->Pull) << (position * 2)); GPIOx->PUPDR = temp; + /* In case of Alternate function mode selection */ + if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) + { + /* Check the Alternate function parameter */ + assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); + + /* Configure Alternate function mapped with the current IO */ + temp = GPIOx->AFR[position >> 3]; + temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ; + temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4)); + GPIOx->AFR[position >> 3] = temp; + } + + /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ + temp = GPIOx->MODER; + temp &= ~(GPIO_MODER_MODER0 << (position * 2)); + temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2)); + GPIOx->MODER = temp; + /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) @@ -316,10 +316,6 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) tmp &= (((uint32_t)0x0F) << (4 * (position & 0x03))); if(tmp == ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03)))) { - /* Configure the External Interrupt or event for the current IO */ - tmp = ((uint32_t)0x0F) << (4 * (position & 0x03)); - SYSCFG->EXTICR[position >> 2] &= ~tmp; - /* Clear EXTI line configuration */ EXTI->IMR &= ~((uint32_t)iocurrent); EXTI->EMR &= ~((uint32_t)iocurrent); @@ -327,6 +323,10 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) /* Clear Rising Falling edge configuration */ EXTI->RTSR &= ~((uint32_t)iocurrent); EXTI->FTSR &= ~((uint32_t)iocurrent); + + /* Configure the External Interrupt or event for the current IO */ + tmp = ((uint32_t)0x0F) << (4 * (position & 0x03)); + SYSCFG->EXTICR[position >> 2] &= ~tmp; } /*------------------------- GPIO Mode Configuration --------------------*/ /* Configure IO Direction in Input Floating Mode */ @@ -335,14 +335,14 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) /* Configure the default Alternate Function in current IO */ GPIOx->AFR[position >> 3] &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ; - /* Configure the default value for IO Speed */ - GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2)); + /* Deactivate the Pull-up and Pull-down resistor for the current IO */ + GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2)); /* Configure the default value IO Output Type */ GPIOx->OTYPER &= ~(GPIO_OTYPER_OT_0 << position) ; - /* Deactivate the Pull-up and Pull-down resistor for the current IO */ - GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2)); + /* Configure the default value for IO Speed */ + GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2)); } } } @@ -431,13 +431,13 @@ void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); - if ((GPIOx->ODR & GPIO_Pin) == GPIO_Pin) + if ((GPIOx->ODR & GPIO_Pin) != 0X00u) { GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER; } else { - GPIOx->BSRR = GPIO_Pin; + GPIOx->BSRR = (uint32_t)GPIO_Pin; } } @@ -467,10 +467,11 @@ HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) GPIOx->LCKR = GPIO_Pin; /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ GPIOx->LCKR = tmp; - /* Read LCKK bit*/ + /* Read LCKR register. This read is mandatory to complete key lock sequence */ tmp = GPIOx->LCKR; - if((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET) + /* Read again in order to confirm lock is active */ + if((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET) { return HAL_OK; } diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_hash.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_hash.c index bb33540945..52a5187dfa 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_hash.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_hash.c @@ -57,24 +57,29 @@ (#)When the processing function is called after HAL_HASH_Init(), the HASH peripheral is initialized and processes the buffer fed in input. When the input data have all been - fed to the IP, the digest computation can start. + fed to the Peripheral, the digest computation can start. - (#)Multi-buffer processing is possible in polling and DMA mode. + (#)Multi-buffer processing is possible in polling, interrupt and DMA modes. (##) In polling mode, only multi-buffer HASH processing is possible. API HAL_HASH_xxx_Accumulate() must be called for each input buffer, except for the last one. - User must resort to HAL_HASH_xxx_Start() to enter the last one and retrieve as + User must resort to HAL_HASH_xxx_Accumulate_End() to enter the last one and retrieve as + well the computed digest. + + (##) In interrupt mode, API HAL_HASH_xxx_Accumulate_IT() must be called for each input buffer, + except for the last one. + User must resort to HAL_HASH_xxx_Accumulate_End_IT() to enter the last one and retrieve as well the computed digest. (##) In DMA mode, multi-buffer HASH and HMAC processing are possible. (+++) HASH processing: once initialization is done, MDMAT bit must be set thru __HAL_HASH_SET_MDMAT() macro. - From that point, each buffer can be fed to the IP thru HAL_HASH_xxx_Start_DMA() API. + From that point, each buffer can be fed to the Peripheral thru HAL_HASH_xxx_Start_DMA() API. Before entering the last buffer, reset the MDMAT bit with __HAL_HASH_RESET_MDMAT() macro then wrap-up the HASH processing in feeding the last input buffer thru the same API HAL_HASH_xxx_Start_DMA(). The digest can then be retrieved with a call to API HAL_HASH_xxx_Finish(). (+++) HMAC processing (requires to resort to extended functions): after initialization, the key and the first input buffer are entered - in the IP with the API HAL_HMACEx_xxx_Step1_2_DMA(). This carries out HMAC step 1 and + in the Peripheral with the API HAL_HMACEx_xxx_Step1_2_DMA(). This carries out HMAC step 1 and starts step 2. The following buffers are next entered with the API HAL_HMACEx_xxx_Step2_DMA(). At this point, the HMAC processing is still carrying out step 2. @@ -90,16 +95,50 @@ (+++) HAL_HASH_DMAFeed_ProcessSuspend() when data are entered by DMA. (##) When HASH or HMAC processing is suspended, HAL_HASH_ContextSaving() allows - to save in memory the IP context. This context can be restored afterwards + to save in memory the Peripheral context. This context can be restored afterwards to resume the HASH processing thanks to HAL_HASH_ContextRestoring(). - (##) Once the HASH IP has been restored to the same configuration as that at suspension + (##) Once the HASH Peripheral has been restored to the same configuration as that at suspension time, processing can be restarted with the same API call (same API, same handle, same parameters) as done before the suspension. Relevant parameters to restart at the proper location are internally saved in the HASH handle. (#)Call HAL_HASH_DeInit() to deinitialize the HASH peripheral. + *** Remarks on message length *** + =================================== + [..] + (#) HAL in interruption mode (interruptions driven) + + (##)Due to HASH peripheral hardware design, the peripheral interruption is triggered every 64 bytes. + This is why, for driver implementation simplicity’s sake, user is requested to enter a message the + length of which is a multiple of 4 bytes. + + (##) When the message length (in bytes) is not a multiple of words, a specific field exists in HASH_STR + to specify which bits to discard at the end of the complete message to process only the message bits + and not extra bits. + + (##) If user needs to perform a hash computation of a large input buffer that is spread around various places + in memory and where each piece of this input buffer is not necessarily a multiple of 4 bytes in size, it + becomes necessary to use a temporary buffer to format the data accordingly before feeding them to the Peripheral. + It is advised to the user to + (+++) achieve the first formatting operation by software then enter the data + (+++) while the Peripheral is processing the first input set, carry out the second formatting operation by software, to be ready when DINIS occurs. + (+++) repeat step 2 until the whole message is processed. + + [..] + (#) HAL in DMA mode + + (##) Again, due to hardware design, the DMA transfer to feed the data can only be done on a word-basis. + The same field described above in HASH_STR is used to specify which bits to discard at the end of the DMA transfer + to process only the message bits and not extra bits. Due to hardware implementation, this is possible only at the + end of the complete message. When several DMA transfers are needed to enter the message, this is not applicable at + the end of the intermediary transfers. + + (##) Similarly to the interruption-driven mode, it is suggested to the user to format the consecutive chunks of data + by software while the DMA transfer and processing is on-going for the first parts of the message. Due to the 32-bit alignment + required for the DMA transfer, it is underlined that the software formatting operation is more complex than in the IT mode. + *** Callback registration *** =================================== [..] @@ -260,7 +299,7 @@ static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Tim [..] This section provides as well call back functions definitions for user code to manage: - (+) Input data transfer to IP completion + (+) Input data transfer to Peripheral completion (+) Calculated digest retrieval completion (+) Error management @@ -273,26 +312,26 @@ static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Tim /** * @brief Initialize the HASH according to the specified parameters in the HASH_HandleTypeDef and create the associated handle. - * @note Only MDMAT and DATATYPE bits of HASH IP are set by HAL_HASH_Init(), + * @note Only MDMAT and DATATYPE bits of HASH Peripheral are set by HAL_HASH_Init(), * other configuration bits are set by HASH or HMAC processing APIs. * @note MDMAT bit is systematically reset by HAL_HASH_Init(). To set it for * multi-buffer HASH processing, user needs to resort to * __HAL_HASH_SET_MDMAT() macro. For HMAC multi-buffer processing, the * relevant APIs manage themselves the MDMAT bit. - * @param hhash: HASH handle + * @param hhash HASH handle * @retval HAL status */ HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash) { - /* Check the parameters */ - assert_param(IS_HASH_DATATYPE(hhash->Init.DataType)); - /* Check the hash handle allocation */ if(hhash == NULL) { return HAL_ERROR; } + /* Check the parameters */ + assert_param(IS_HASH_DATATYPE(hhash->Init.DataType)); + #if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) if (hhash->State == HAL_HASH_STATE_RESET) { @@ -334,6 +373,8 @@ HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash) hhash->DigestCalculationDisable = RESET; /* Set phase to READY */ hhash->Phase = HAL_HASH_PHASE_READY; + /* Reset suspension request flag */ + hhash->SuspendRequest = HAL_HASH_SUSPEND_NONE; /* Set the data type bit */ MODIFY_REG(HASH->CR, HASH_CR_DATATYPE, hhash->Init.DataType); @@ -354,7 +395,7 @@ __HAL_HASH_RESET_MDMAT(); /** * @brief DeInitialize the HASH peripheral. - * @param hhash: HASH handle. + * @param hhash HASH handle. * @retval HAL status */ HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash) @@ -401,13 +442,16 @@ HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash) /* Initialise the error code */ hhash->ErrorCode = HAL_HASH_ERROR_NONE; + /* Reset multi buffers accumulation flag */ + hhash->Accumulation = 0U; + /* Return function status */ return HAL_OK; } /** * @brief Initialize the HASH MSP. - * @param hhash: HASH handle. + * @param hhash HASH handle. * @retval None */ __weak void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash) @@ -422,7 +466,7 @@ __weak void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash) /** * @brief DeInitialize the HASH MSP. - * @param hhash: HASH handle. + * @param hhash HASH handle. * @retval None */ __weak void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash) @@ -438,12 +482,12 @@ __weak void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash) /** * @brief Input data transfer complete call back. * @note HAL_HASH_InCpltCallback() is called when the complete input message - * has been fed to the IP. This API is invoked only when input data are + * has been fed to the Peripheral. This API is invoked only when input data are * entered under interruption or thru DMA. * @note In case of HASH or HMAC multi-buffer DMA feeding case (MDMAT bit set), * HAL_HASH_InCpltCallback() is called at the end of each buffer feeding - * to the IP. - * @param hhash: HASH handle. + * to the Peripheral. + * @param hhash HASH handle. * @retval None */ __weak void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash) @@ -460,7 +504,7 @@ __weak void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash) * @brief Digest computation complete call back. * @note HAL_HASH_DgstCpltCallback() is used under interruption, is not * relevant with DMA. - * @param hhash: HASH handle. + * @param hhash HASH handle. * @retval None */ __weak void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash) @@ -477,7 +521,7 @@ __weak void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash) * @brief Error callback. * @note Code user can resort to hhash->Status (HAL_ERROR, HAL_TIMEOUT,...) * to retrieve the error type. - * @param hhash: HASH handle. + * @param hhash HASH handle. * @retval None */ __weak void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash) @@ -684,17 +728,19 @@ HAL_StatusTypeDef status = HAL_OK; the hash value using one of the following algorithms: (+) MD5 (++) HAL_HASH_MD5_Start() - (++) HAL_HASH_MD5_Accumulate() + (++) HAL_HASH_MD5_Accmlt() + (++) HAL_HASH_MD5_Accmlt_End() (+) SHA1 (++) HAL_HASH_SHA1_Start() - (++) HAL_HASH_SHA1_Accumulate() + (++) HAL_HASH_SHA1_Accmlt() + (++) HAL_HASH_SHA1_Accmlt_End() [..] For a single buffer to be hashed, user can resort to HAL_HASH_xxx_Start(). [..] In case of multi-buffer HASH processing (a single digest is computed while - several buffers are fed to the IP), the user can resort to successive calls + several buffers are fed to the Peripheral), the user can resort to successive calls to HAL_HASH_xxx_Accumulate() and wrap-up the digest computation by a call - to HAL_HASH_xxx_Start(). + to HAL_HASH_xxx_Accumulate_End(). @endverbatim * @{ @@ -704,11 +750,11 @@ HAL_StatusTypeDef status = HAL_OK; * @brief Initialize the HASH peripheral in MD5 mode, next process pInBuffer then * read the computed digest. * @note Digest is available in pOutBuffer. - * @param hhash: HASH handle. - * @param pInBuffer: pointer to the input buffer (buffer to be hashed). - * @param Size: length of the input buffer in bytes. - * @param pOutBuffer: pointer to the computed digest. Digest size is 16 bytes. - * @param Timeout: Timeout value + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (buffer to be hashed). + * @param Size length of the input buffer in bytes. + * @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes. + * @param Timeout Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) @@ -719,37 +765,52 @@ HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuff /** * @brief If not already done, initialize the HASH peripheral in MD5 mode then * processes pInBuffer. - * @note Consecutive calls to HAL_HASH_MD5_Accumulate() can be used to feed - * several input buffers back-to-back to the IP that will yield a single + * @note Consecutive calls to HAL_HASH_MD5_Accmlt() can be used to feed + * several input buffers back-to-back to the Peripheral that will yield a single * HASH signature once all buffers have been entered. Wrap-up of input * buffers feeding and retrieval of digest is done by a call to - * HAL_HASH_MD5_Start(). + * HAL_HASH_MD5_Accmlt_End(). * @note Field hhash->Phase of HASH handle is tested to check whether or not - * the IP has already been initialized. - * @note Digest is not retrieved by this API, user must resort to HAL_HASH_MD5_Start() - * to read it, feeding at the same time the last input buffer to the IP. + * the Peripheral has already been initialized. + * @note Digest is not retrieved by this API, user must resort to HAL_HASH_MD5_Accmlt_End() + * to read it, feeding at the same time the last input buffer to the Peripheral. * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the - * HASH digest computation is corrupted. Only HAL_HASH_MD5_Start() is able + * HASH digest computation is corrupted. Only HAL_HASH_MD5_Accmlt_End() is able * to manage the ending buffer with a length in bytes not a multiple of 4. - * @param hhash: HASH handle. - * @param pInBuffer: pointer to the input buffer (buffer to be hashed). - * @param Size: length of the input buffer in bytes, must be a multiple of 4. + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (buffer to be hashed). + * @param Size length of the input buffer in bytes, must be a multiple of 4. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_MD5_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) { return HASH_Accumulate(hhash, pInBuffer, Size,HASH_ALGOSELECTION_MD5); } +/** + * @brief End computation of a single HASH signature after several calls to HAL_HASH_MD5_Accmlt() API. + * @note Digest is available in pOutBuffer. + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (buffer to be hashed). + * @param Size length of the input buffer in bytes. + * @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes. + * @param Timeout Timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) +{ + return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_MD5); +} + /** * @brief Initialize the HASH peripheral in SHA1 mode, next process pInBuffer then * read the computed digest. * @note Digest is available in pOutBuffer. - * @param hhash: HASH handle. - * @param pInBuffer: pointer to the input buffer (buffer to be hashed). - * @param Size: length of the input buffer in bytes. - * @param pOutBuffer: pointer to the computed digest. Digest size is 20 bytes. - * @param Timeout: Timeout value + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (buffer to be hashed). + * @param Size length of the input buffer in bytes. + * @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes. + * @param Timeout Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) @@ -760,28 +821,42 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuf /** * @brief If not already done, initialize the HASH peripheral in SHA1 mode then * processes pInBuffer. - * @note Consecutive calls to HAL_HASH_SHA1_Accumulate() can be used to feed - * several input buffers back-to-back to the IP that will yield a single + * @note Consecutive calls to HAL_HASH_SHA1_Accmlt() can be used to feed + * several input buffers back-to-back to the Peripheral that will yield a single * HASH signature once all buffers have been entered. Wrap-up of input * buffers feeding and retrieval of digest is done by a call to - * HAL_HASH_SHA1_Start(). + * HAL_HASH_SHA1_Accmlt_End(). * @note Field hhash->Phase of HASH handle is tested to check whether or not - * the IP has already been initialized. - * @note Digest is not retrieved by this API, user must resort to HAL_HASH_SHA1_Start() - * to read it, feeding at the same time the last input buffer to the IP. + * the Peripheral has already been initialized. + * @note Digest is not retrieved by this API, user must resort to HAL_HASH_SHA1_Accmlt_End() + * to read it, feeding at the same time the last input buffer to the Peripheral. * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the - * HASH digest computation is corrupted. Only HAL_HASH_SHA1_Start() is able + * HASH digest computation is corrupted. Only HAL_HASH_SHA1_Accmlt_End() is able * to manage the ending buffer with a length in bytes not a multiple of 4. - * @param hhash: HASH handle. - * @param pInBuffer: pointer to the input buffer (buffer to be hashed). - * @param Size: length of the input buffer in bytes, must be a multiple of 4. + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (buffer to be hashed). + * @param Size length of the input buffer in bytes, must be a multiple of 4. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) { return HASH_Accumulate(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA1); } +/** + * @brief End computation of a single HASH signature after several calls to HAL_HASH_SHA1_Accmlt() API. + * @note Digest is available in pOutBuffer. + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (buffer to be hashed). + * @param Size length of the input buffer in bytes. + * @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes. + * @param Timeout Timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) +{ + return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA1); +} /** * @} @@ -798,12 +873,16 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *p the hash value using one of the following algorithms: (+) MD5 (++) HAL_HASH_MD5_Start_IT() + (++) HAL_HASH_MD5_Accmlt_IT() + (++) HAL_HASH_MD5_Accmlt_End_IT() (+) SHA1 (++) HAL_HASH_SHA1_Start_IT() + (++) HAL_HASH_SHA1_Accmlt_IT() + (++) HAL_HASH_SHA1_Accmlt_End_IT() [..] API HAL_HASH_IRQHandler() manages each HASH interruption. - [..] Note that HAL_HASH_IRQHandler() manages as well HASH IP interruptions when in + [..] Note that HAL_HASH_IRQHandler() manages as well HASH Peripheral interruptions when in HMAC processing mode. @@ -815,10 +894,10 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *p * @brief Initialize the HASH peripheral in MD5 mode, next process pInBuffer then * read the computed digest in interruption mode. * @note Digest is available in pOutBuffer. - * @param hhash: HASH handle. - * @param pInBuffer: pointer to the input buffer (buffer to be hashed). - * @param Size: length of the input buffer in bytes. - * @param pOutBuffer: pointer to the computed digest. Digest size is 16 bytes. + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (buffer to be hashed). + * @param Size length of the input buffer in bytes. + * @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes. * @retval HAL status */ HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer) @@ -826,15 +905,51 @@ HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInB return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_MD5); } +/** + * @brief If not already done, initialize the HASH peripheral in MD5 mode then + * processes pInBuffer in interruption mode. + * @note Consecutive calls to HAL_HASH_MD5_Accmlt_IT() can be used to feed + * several input buffers back-to-back to the Peripheral that will yield a single + * HASH signature once all buffers have been entered. Wrap-up of input + * buffers feeding and retrieval of digest is done by a call to + * HAL_HASH_MD5_Accmlt_End_IT(). + * @note Field hhash->Phase of HASH handle is tested to check whether or not + * the Peripheral has already been initialized. + * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the + * HASH digest computation is corrupted. Only HAL_HASH_MD5_Accmlt_End_IT() is able + * to manage the ending buffer with a length in bytes not a multiple of 4. + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (buffer to be hashed). + * @param Size length of the input buffer in bytes, must be a multiple of 4. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +{ + return HASH_Accumulate_IT(hhash, pInBuffer, Size,HASH_ALGOSELECTION_MD5); +} + +/** + * @brief End computation of a single HASH signature after several calls to HAL_HASH_MD5_Accmlt_IT() API. + * @note Digest is available in pOutBuffer. + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (buffer to be hashed). + * @param Size length of the input buffer in bytes. + * @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer) +{ + return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_MD5); +} /** * @brief Initialize the HASH peripheral in SHA1 mode, next process pInBuffer then * read the computed digest in interruption mode. * @note Digest is available in pOutBuffer. - * @param hhash: HASH handle. - * @param pInBuffer: pointer to the input buffer (buffer to be hashed). - * @param Size: length of the input buffer in bytes. - * @param pOutBuffer: pointer to the computed digest. Digest size is 20 bytes. + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (buffer to be hashed). + * @param Size length of the input buffer in bytes. + * @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes. * @retval HAL status */ HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer) @@ -842,9 +957,47 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA1); } + +/** + * @brief If not already done, initialize the HASH peripheral in SHA1 mode then + * processes pInBuffer in interruption mode. + * @note Consecutive calls to HAL_HASH_SHA1_Accmlt_IT() can be used to feed + * several input buffers back-to-back to the Peripheral that will yield a single + * HASH signature once all buffers have been entered. Wrap-up of input + * buffers feeding and retrieval of digest is done by a call to + * HAL_HASH_SHA1_Accmlt_End_IT(). + * @note Field hhash->Phase of HASH handle is tested to check whether or not + * the Peripheral has already been initialized. + * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the + * HASH digest computation is corrupted. Only HAL_HASH_SHA1_Accmlt_End_IT() is able + * to manage the ending buffer with a length in bytes not a multiple of 4. + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (buffer to be hashed). + * @param Size length of the input buffer in bytes, must be a multiple of 4. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +{ + return HASH_Accumulate_IT(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA1); +} + +/** + * @brief End computation of a single HASH signature after several calls to HAL_HASH_SHA1_Accmlt_IT() API. + * @note Digest is available in pOutBuffer. + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (buffer to be hashed). + * @param Size length of the input buffer in bytes. + * @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer) +{ + return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA1); +} + /** * @brief Handle HASH interrupt request. - * @param hhash: HASH handle. + * @param hhash HASH handle. * @note HAL_HASH_IRQHandler() handles interrupts in HMAC processing as well. * @note In case of error reported during the HASH interruption processing, * HAL_HASH_ErrorCallback() API is called so that user code can @@ -887,7 +1040,7 @@ void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash) (++) HAL_HASH_SHA1_Start_DMA() (++) HAL_HASH_SHA1_Finish() - [..] When resorting to DMA mode to enter the data in the IP, user must resort + [..] When resorting to DMA mode to enter the data in the Peripheral, user must resort to HAL_HASH_xxx_Start_DMA() then read the resulting digest with HAL_HASH_xxx_Finish(). [..] In case of multi-buffer HASH processing, MDMAT bit must first be set before @@ -901,12 +1054,12 @@ void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash) /** * @brief Initialize the HASH peripheral in MD5 mode then initiate a DMA transfer - * to feed the input buffer to the IP. + * to feed the input buffer to the Peripheral. * @note Once the DMA transfer is finished, HAL_HASH_MD5_Finish() API must * be called to retrieve the computed digest. - * @param hhash: HASH handle. - * @param pInBuffer: pointer to the input buffer (buffer to be hashed). - * @param Size: length of the input buffer in bytes. + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (buffer to be hashed). + * @param Size length of the input buffer in bytes. * @retval HAL status */ HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) @@ -919,9 +1072,9 @@ HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pIn * @note The API waits for DCIS to be set then reads the computed digest. * @note HAL_HASH_MD5_Finish() can be used as well to retrieve the digest in * HMAC MD5 mode. - * @param hhash: HASH handle. - * @param pOutBuffer: pointer to the computed digest. Digest size is 16 bytes. - * @param Timeout: Timeout value. + * @param hhash HASH handle. + * @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes. + * @param Timeout Timeout value. * @retval HAL status */ HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout) @@ -931,12 +1084,12 @@ HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBu /** * @brief Initialize the HASH peripheral in SHA1 mode then initiate a DMA transfer - * to feed the input buffer to the IP. + * to feed the input buffer to the Peripheral. * @note Once the DMA transfer is finished, HAL_HASH_SHA1_Finish() API must * be called to retrieve the computed digest. - * @param hhash: HASH handle. - * @param pInBuffer: pointer to the input buffer (buffer to be hashed). - * @param Size: length of the input buffer in bytes. + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (buffer to be hashed). + * @param Size length of the input buffer in bytes. * @retval HAL status */ HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) @@ -950,9 +1103,9 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pI * @note The API waits for DCIS to be set then reads the computed digest. * @note HAL_HASH_SHA1_Finish() can be used as well to retrieve the digest in * HMAC SHA1 mode. - * @param hhash: HASH handle. - * @param pOutBuffer: pointer to the computed digest. Digest size is 20 bytes. - * @param Timeout: Timeout value. + * @param hhash HASH handle. + * @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes. + * @param Timeout Timeout value. * @retval HAL status */ HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout) @@ -989,11 +1142,11 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutB * @note Digest is available in pOutBuffer. * @note Same key is used for the inner and the outer hash functions; pointer to key and * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. - * @param hhash: HASH handle. - * @param pInBuffer: pointer to the input buffer (buffer to be hashed). - * @param Size: length of the input buffer in bytes. - * @param pOutBuffer: pointer to the computed digest. Digest size is 16 bytes. - * @param Timeout: Timeout value. + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (buffer to be hashed). + * @param Size length of the input buffer in bytes. + * @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes. + * @param Timeout Timeout value. * @retval HAL status */ HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) @@ -1007,11 +1160,11 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuff * @note Digest is available in pOutBuffer. * @note Same key is used for the inner and the outer hash functions; pointer to key and * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. - * @param hhash: HASH handle. - * @param pInBuffer: pointer to the input buffer (buffer to be hashed). - * @param Size: length of the input buffer in bytes. - * @param pOutBuffer: pointer to the computed digest. Digest size is 20 bytes. - * @param Timeout: Timeout value. + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (buffer to be hashed). + * @param Size length of the input buffer in bytes. + * @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes. + * @param Timeout Timeout value. * @retval HAL status */ HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) @@ -1049,10 +1202,10 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuf * @note Digest is available in pOutBuffer. * @note Same key is used for the inner and the outer hash functions; pointer to key and * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. - * @param hhash: HASH handle. - * @param pInBuffer: pointer to the input buffer (buffer to be hashed). - * @param Size: length of the input buffer in bytes. - * @param pOutBuffer: pointer to the computed digest. Digest size is 16 bytes. + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (buffer to be hashed). + * @param Size length of the input buffer in bytes. + * @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes. * @retval HAL status */ HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer) @@ -1066,10 +1219,10 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInB * @note Digest is available in pOutBuffer. * @note Same key is used for the inner and the outer hash functions; pointer to key and * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. - * @param hhash: HASH handle. - * @param pInBuffer: pointer to the input buffer (buffer to be hashed). - * @param Size: length of the input buffer in bytes. - * @param pOutBuffer: pointer to the computed digest. Digest size is 20 bytes. + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (buffer to be hashed). + * @param Size length of the input buffer in bytes. + * @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes. * @retval HAL status */ HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer) @@ -1097,7 +1250,7 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn (+) SHA1 (++) HAL_HMAC_SHA1_Start_DMA() - [..] When resorting to DMA mode to enter the data in the IP for HMAC processing, + [..] When resorting to DMA mode to enter the data in the Peripheral for HMAC processing, user must resort to HAL_HMAC_xxx_Start_DMA() then read the resulting digest with HAL_HASH_xxx_Finish(). @@ -1108,7 +1261,7 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn /** * @brief Initialize the HASH peripheral in HMAC MD5 mode then initiate the required - * DMA transfers to feed the key and the input buffer to the IP. + * DMA transfers to feed the key and the input buffer to the Peripheral. * @note Once the DMA transfers are finished (indicated by hhash->State set back * to HAL_HASH_STATE_READY), HAL_HASH_MD5_Finish() API must be called to retrieve * the computed digest. @@ -1120,9 +1273,9 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn * For the processing of the last buffer of the thread, MDMAT bit must * be reset and the buffer length (in bytes) doesn't have to be a * multiple of 4. - * @param hhash: HASH handle. - * @param pInBuffer: pointer to the input buffer (buffer to be hashed). - * @param Size: length of the input buffer in bytes. + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (buffer to be hashed). + * @param Size length of the input buffer in bytes. * @retval HAL status */ HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) @@ -1133,7 +1286,7 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pIn /** * @brief Initialize the HASH peripheral in HMAC SHA1 mode then initiate the required - * DMA transfers to feed the key and the input buffer to the IP. + * DMA transfers to feed the key and the input buffer to the Peripheral. * @note Once the DMA transfers are finished (indicated by hhash->State set back * to HAL_HASH_STATE_READY), HAL_HASH_SHA1_Finish() API must be called to retrieve * the computed digest. @@ -1145,9 +1298,9 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pIn * For the processing of the last buffer of the thread, MDMAT bit must * be reset and the buffer length (in bytes) doesn't have to be a * multiple of 4. - * @param hhash: HASH handle. - * @param pInBuffer: pointer to the input buffer (buffer to be hashed). - * @param Size: length of the input buffer in bytes. + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (buffer to be hashed). + * @param Size length of the input buffer in bytes. * @retval HAL status */ HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) @@ -1180,9 +1333,9 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pI [..] This subsection provides functions allowing to suspend the HASH processing - (+) when input are fed to the IP by software + (+) when input are fed to the Peripheral by software (++) HAL_HASH_SwFeed_ProcessSuspend() - (+) when input are fed to the IP by DMA + (+) when input are fed to the Peripheral by DMA (++) HAL_HASH_DMAFeed_ProcessSuspend() @@ -1194,7 +1347,7 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pI /** * @brief Return the HASH handle state. * @note The API yields the current state of the handle (BUSY, READY,...). - * @param hhash: HASH handle. + * @param hhash HASH handle. * @retval HAL HASH state */ HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash) @@ -1207,7 +1360,7 @@ HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash) * @brief Return the HASH HAL status. * @note The API yields the HAL status of the handle: it is the result of the * latest HASH processing and allows to report any issue (e.g. HAL_TIMEOUT). - * @param hhash: HASH handle. + * @param hhash HASH handle. * @retval HAL status */ HAL_StatusTypeDef HAL_HASH_GetStatus(HASH_HandleTypeDef *hhash) @@ -1217,8 +1370,8 @@ HAL_StatusTypeDef HAL_HASH_GetStatus(HASH_HandleTypeDef *hhash) /** * @brief Save the HASH context in case of processing suspension. - * @param hhash: HASH handle. - * @param pMemBuffer: pointer to the memory buffer where the HASH context + * @param hhash HASH handle. + * @param pMemBuffer pointer to the memory buffer where the HASH context * is saved. * @note The IMR, STR, CR then all the CSR registers are saved * in that order. Only the r/w bits are read to be restored later on. @@ -1258,8 +1411,8 @@ void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer) /** * @brief Restore the HASH context in case of processing resumption. - * @param hhash: HASH handle. - * @param pMemBuffer: pointer to the memory buffer where the HASH context + * @param hhash HASH handle. + * @param pMemBuffer pointer to the memory buffer where the HASH context * is stored. * @note The IMR, STR, CR then all the CSR registers are restored * in that order. Only the r/w bits are restored. @@ -1303,7 +1456,7 @@ void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer) /** * @brief Initiate HASH processing suspension when in polling or interruption mode. - * @param hhash: HASH handle. + * @param hhash HASH handle. * @note Set the handle field SuspendRequest to the appropriate value so that * the on-going HASH processing is suspended as soon as the required * conditions are met. Note that the actual suspension is carried out @@ -1319,9 +1472,9 @@ void HAL_HASH_SwFeed_ProcessSuspend(HASH_HandleTypeDef *hhash) /** * @brief Suspend the HASH processing when in DMA mode. - * @param hhash: HASH handle. + * @param hhash HASH handle. * @note When suspension attempt occurs at the very end of a DMA transfer and - * all the data have already been entered in the IP, hhash->State is + * all the data have already been entered in the Peripheral, hhash->State is * set to HAL_HASH_STATE_READY and the API returns HAL_ERROR. It is * recommended to wrap-up the processing in reading the digest as usual. * @retval HAL status @@ -1349,7 +1502,7 @@ HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash) return HAL_ERROR; } - /* Wait for DMAS to be reset */ + /* Wait for BUSY flag to be reset */ if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK) { return HAL_TIMEOUT; @@ -1360,26 +1513,26 @@ HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash) return HAL_ERROR; } - /* Wait for DMAS to be set */ + /* Wait for BUSY flag to be set */ if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, RESET, HASH_TIMEOUTVALUE) != HAL_OK) { return HAL_TIMEOUT; } - /* Disable DMA channel */ - if (HAL_DMA_Abort(hhash->hdmain) ==HAL_OK) - { - /* - Note that the Abort function will + /* Note that the Abort function will - Clear the transfer error flags - Unlock - Set the State - */ + */ + if (HAL_DMA_Abort(hhash->hdmain) !=HAL_OK) + { + return HAL_ERROR; } /* Clear DMAE bit */ CLEAR_BIT(HASH->CR,HASH_CR_DMAE); + /* Wait for BUSY flag to be reset */ if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK) { return HAL_TIMEOUT; @@ -1413,8 +1566,8 @@ HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash) /* Compute how many words were supposed to be transferred by DMA */ tmp_initial_DMATransferSize_inWords = (((hhash->HashInCount%4U)!=0U) ? ((hhash->HashInCount+3U)/4U): (hhash->HashInCount/4U)); - /* If discrepancy between the number of words reported by DMA IP and the numbers of words entered as reported - by HASH IP, correct it */ + /* If discrepancy between the number of words reported by DMA Peripheral and the numbers of words entered as reported + by HASH Peripheral, correct it */ /* tmp_words_already_pushed reflects the number of words that were already pushed before the start of DMA transfer (multi-buffer processing case) */ tmp_words_already_pushed = hhash->NbWordsAlreadyPushed; @@ -1423,7 +1576,7 @@ HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash) tmp_remaining_DMATransferSize_inWords--; /* one less word to be transferred again */ } - /* Accordingly, update the input pointer that points at the next word to be transferred to the IP by DMA */ + /* Accordingly, update the input pointer that points at the next word to be transferred to the Peripheral by DMA */ hhash->pHashInBuffPtr += 4U * (tmp_initial_DMATransferSize_inWords - tmp_remaining_DMATransferSize_inWords) ; /* And store in HashInCount the remaining size to transfer (in bytes) */ @@ -1441,7 +1594,7 @@ HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash) /** * @brief Return the HASH handle error code. - * @param hhash: pointer to a HASH_HandleTypeDef structure. + * @param hhash pointer to a HASH_HandleTypeDef structure. * @retval HASH Error Code */ uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash) @@ -1464,7 +1617,7 @@ uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash) /** * @brief DMA HASH Input Data transfer completion callback. - * @param hdma: DMA handle. + * @param hdma DMA handle. * @note In case of HMAC processing, HASH_DMAXferCplt() initiates * the next DMA transfer for the following HMAC step. * @retval None @@ -1537,7 +1690,7 @@ static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma) if (hhash->DigestCalculationDisable != RESET) { /* Digest calculation is disabled: Step 2 must start with MDMAT bit set, - no digest calculation will be triggered at the end of the input buffer feeding to the IP */ + no digest calculation will be triggered at the end of the input buffer feeding to the Peripheral */ __HAL_HASH_SET_MDMAT(); } } @@ -1545,7 +1698,7 @@ static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma) { if (hhash->DigestCalculationDisable != RESET) { - /* No automatic move to Step 3 as a new message buffer will be fed to the IP + /* No automatic move to Step 3 as a new message buffer will be fed to the Peripheral (case of multi-buffer HMAC processing): DCAL must not be set. Phase remains in Step 2, MDMAT remains set at this point. @@ -1588,12 +1741,12 @@ static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma) /* Return function status */ if (status != HAL_OK) { - /* Update DAC state machine to error */ + /* Update HASH state machine to error */ hhash->State = HAL_HASH_STATE_ERROR; } else { - /* Change DAC state */ + /* Change HASH state */ hhash->State = HAL_HASH_STATE_READY; } } @@ -1604,7 +1757,7 @@ static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA HASH communication error callback. - * @param hdma: DMA handle. + * @param hdma DMA handle. * @note HASH_DMAError() callback invokes HAL_HASH_ErrorCallback() that * can contain user code to manage the error. * @retval None @@ -1633,13 +1786,13 @@ static void HASH_DMAError(DMA_HandleTypeDef *hdma) } /** - * @brief Feed the input buffer to the HASH IP. - * @param hhash: HASH handle. - * @param pInBuffer: pointer to input buffer. - * @param Size: the size of input buffer in bytes. + * @brief Feed the input buffer to the HASH Peripheral. + * @param hhash HASH handle. + * @param pInBuffer pointer to input buffer. + * @param Size the size of input buffer in bytes. * @note HASH_WriteData() regularly reads hhash->SuspendRequest to check whether * or not the HASH processing must be suspended. If this is the case, the - * processing is suspended when possible and the IP feeding point reached at + * processing is suspended when possible and the Peripheral feeding point reached at * suspension time is stored in the handle for resumption later on. * @retval HAL status */ @@ -1665,7 +1818,7 @@ static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInB /* Reset SuspendRequest */ hhash->SuspendRequest = HAL_HASH_SUSPEND_NONE; - /* Depending whether the key or the input data were fed to the IP, the feeding point + /* Depending whether the key or the input data were fed to the Peripheral, the feeding point reached at suspension time is not saved in the same handle fields */ if ((hhash->Phase == HAL_HASH_PHASE_PROCESS) || (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2)) { @@ -1697,14 +1850,14 @@ static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInB } /* if ((hhash->SuspendRequest == HAL_HASH_SUSPEND) && ((buffercounter+4) < Size)) */ } /* for(buffercounter = 0; buffercounter < Size; buffercounter+=4) */ - /* At this point, all the data have been entered to the IP: exit */ + /* At this point, all the data have been entered to the Peripheral: exit */ return HAL_OK; } /** * @brief Retrieve the message digest. - * @param pMsgDigest: pointer to the computed digest. - * @param Size: message digest size in bytes. + * @param pMsgDigest pointer to the computed digest. + * @param Size message digest size in bytes. * @retval None */ static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size) @@ -1775,10 +1928,10 @@ static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size) /** * @brief Handle HASH processing Timeout. - * @param hhash: HASH handle. - * @param Flag: specifies the HASH flag to check. - * @param Status: the Flag status (SET or RESET). - * @param Timeout: Timeout duration. + * @param hhash HASH handle. + * @param Flag specifies the HASH flag to check. + * @param Status the Flag status (SET or RESET). + * @param Timeout Timeout duration. * @retval HAL status */ static HAL_StatusTypeDef HASH_WaitOnFlagUntilTimeout(HASH_HandleTypeDef *hhash, uint32_t Flag, FlagStatus Status, uint32_t Timeout) @@ -1836,10 +1989,10 @@ static HAL_StatusTypeDef HASH_WaitOnFlagUntilTimeout(HASH_HandleTypeDef *hhash, /** * @brief HASH processing in interruption mode. - * @param hhash: HASH handle. + * @param hhash HASH handle. * @note HASH_IT() regularly reads hhash->SuspendRequest to check whether * or not the HASH processing must be suspended. If this is the case, the - * processing is suspended when possible and the IP feeding point reached at + * processing is suspended when possible and the Peripheral feeding point reached at * suspension time is stored in the handle for resumption later on. * @retval HAL status */ @@ -1860,7 +2013,7 @@ static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash) else if (hhash->HashITCounter == 1U) { /* This is the first call to HASH_IT, the first input data are about to be - entered in the IP. A specific processing is carried out at this point to + entered in the Peripheral. A specific processing is carried out at this point to start-up the processing. */ hhash->HashITCounter = 2U; } @@ -1881,6 +2034,8 @@ static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash) __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI); /* Change the HASH state */ hhash->State = HAL_HASH_STATE_READY; + /* Reset HASH state machine */ + hhash->Phase = HAL_HASH_PHASE_READY; /* Call digest computation complete call back */ #if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) hhash->DgstCpltCallback(hhash); @@ -1891,7 +2046,7 @@ static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash) return HAL_OK; } - /* If IP ready to accept new data */ + /* If Peripheral ready to accept new data */ if (__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS)) { @@ -1911,7 +2066,7 @@ static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash) return HAL_OK; } - /* Enter input data in the IP thru HASH_Write_Block_Data() call and + /* Enter input data in the Peripheral thru HASH_Write_Block_Data() call and check whether the digest calculation has been triggered */ if (HASH_Write_Block_Data(hhash) == HASH_DIGEST_CALCULATION_STARTED) { @@ -1925,7 +2080,7 @@ static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash) if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1) { - /* Wait until IP is not busy anymore */ + /* Wait until Peripheral is not busy anymore */ if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK) { /* Disable Interrupts */ @@ -1942,7 +2097,7 @@ static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash) } else if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2) { - /* Wait until IP is not busy anymore */ + /* Wait until Peripheral is not busy anymore */ if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK) { /* Disable Interrupts */ @@ -1975,8 +2130,8 @@ static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash) /** - * @brief Write a block of data in HASH IP in interruption mode. - * @param hhash: HASH handle. + * @brief Write a block of data in HASH Peripheral in interruption mode. + * @param hhash HASH handle. * @note HASH_Write_Block_Data() is called under interruption by HASH_IT(). * @retval HAL status */ @@ -2005,7 +2160,7 @@ static uint32_t HASH_Write_Block_Data(HASH_HandleTypeDef *hhash) HASH->DIN = *(uint32_t*)inputaddr; if(hhash->HashInCount >= 68U) { - /* There are still data waiting to be entered in the IP. + /* There are still data waiting to be entered in the Peripheral. Decrement buffer counter and set pointer to the proper memory location for the next data entering round. */ hhash->HashInCount -= 68U; @@ -2044,13 +2199,33 @@ static uint32_t HASH_Write_Block_Data(HASH_HandleTypeDef *hhash) HASH->DIN = *(uint32_t*)inputaddr; inputaddr+=4U; } - /* Start the Digest calculation */ - __HAL_HASH_START_DIGEST(); - /* Return indication that digest calculation has started: - this return value triggers the call to Input data transfer - complete call back as well as the proper transition from - one step to another in HMAC mode. */ - ret = HASH_DIGEST_CALCULATION_STARTED; + + if (hhash->Accumulation == 1U) + { + /* Field accumulation is set, API only feeds data to the Peripheral and under interruption. + The digest computation will be started when the last buffer data are entered. */ + + /* Reset multi buffers accumulation flag */ + hhash->Accumulation = 0U; + /* Change the HASH state */ + hhash->State = HAL_HASH_STATE_READY; + /* Call Input data transfer complete call back */ +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) + hhash->InCpltCallback(hhash); +#else + HAL_HASH_InCpltCallback(hhash); +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ + } + else + { + /* Start the Digest calculation */ + __HAL_HASH_START_DIGEST(); + /* Return indication that digest calculation has started: + this return value triggers the call to Input data transfer + complete call back as well as the proper transition from + one step to another in HMAC mode. */ + ret = HASH_DIGEST_CALCULATION_STARTED; + } /* Reset buffer counter */ hhash->HashInCount = 0; } @@ -2061,8 +2236,8 @@ static uint32_t HASH_Write_Block_Data(HASH_HandleTypeDef *hhash) /** * @brief HMAC processing in polling mode. - * @param hhash: HASH handle. - * @param Timeout: Timeout value. + * @param hhash HASH handle. + * @param Timeout Timeout value. * @retval HAL status */ static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Timeout) @@ -2204,6 +2379,9 @@ static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Tim /* Read the message digest */ HASH_GetDigest(hhash->pHashOutBuffPtr, HASH_DIGEST_LENGTH()); + + /* Reset HASH state machine */ + hhash->Phase = HAL_HASH_PHASE_READY; } /* Change the HASH state */ @@ -2221,12 +2399,12 @@ static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Tim * @brief Initialize the HASH peripheral, next process pInBuffer then * read the computed digest. * @note Digest is available in pOutBuffer. - * @param hhash: HASH handle. - * @param pInBuffer: pointer to the input buffer (buffer to be hashed). - * @param Size: length of the input buffer in bytes. - * @param pOutBuffer: pointer to the computed digest. - * @param Timeout: Timeout value. - * @param Algorithm: HASH algorithm. + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (buffer to be hashed). + * @param Size length of the input buffer in bytes. + * @param pOutBuffer pointer to the computed digest. + * @param Timeout Timeout value. + * @param Algorithm HASH algorithm. * @retval HAL status */ HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm) @@ -2240,7 +2418,7 @@ HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED)) { /* Check input parameters */ - if ((pInBuffer == NULL) || (Size == 0U) || (pOutBuffer == NULL)) + if ((pInBuffer == NULL) || (pOutBuffer == NULL)) { hhash->State = HAL_HASH_STATE_READY; return HAL_ERROR; @@ -2271,7 +2449,7 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED } else if (hhash->Phase == HAL_HASH_PHASE_PROCESS) { - /* if the IP has already been initialized, two cases are possible */ + /* if the Peripheral has already been initialized, two cases are possible */ /* Process resumption time ... */ if (hhash->State == HAL_HASH_STATE_SUSPENDED) @@ -2333,6 +2511,9 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED /* Change the HASH state */ hhash->State = HAL_HASH_STATE_READY; + /* Reset HASH state machine */ + hhash->Phase = HAL_HASH_PHASE_READY; + } /* Process Unlocked */ @@ -2353,13 +2534,13 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED * @brief If not already done, initialize the HASH peripheral then * processes pInBuffer. * @note Field hhash->Phase of HASH handle is tested to check whether or not - * the IP has already been initialized. + * the Peripheral has already been initialized. * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the * HASH digest computation is corrupted. - * @param hhash: HASH handle. - * @param pInBuffer: pointer to the input buffer (buffer to be hashed). - * @param Size: length of the input buffer in bytes, must be a multiple of 4. - * @param Algorithm: HASH algorithm. + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (buffer to be hashed). + * @param Size length of the input buffer in bytes, must be a multiple of 4. + * @param Algorithm HASH algorithm. * @retval HAL status */ HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm) @@ -2369,7 +2550,10 @@ HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, HAL_HASH_StateTypeDef State_tmp = hhash->State; /* Make sure the input buffer size (in bytes) is a multiple of 4 */ - assert_param(IS_HASH_POLLING_MULTIBUFFER_SIZE(Size)); + if ((Size % 4U) != 0U) + { + return HAL_ERROR; + } /* Initiate HASH processing in case of start or resumption */ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED)) @@ -2449,20 +2633,148 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED } +/** + * @brief If not already done, initialize the HASH peripheral then + * processes pInBuffer in interruption mode. + * @note Field hhash->Phase of HASH handle is tested to check whether or not + * the Peripheral has already been initialized. + * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the + * HASH digest computation is corrupted. + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (buffer to be hashed). + * @param Size length of the input buffer in bytes, must be a multiple of 4. + * @param Algorithm HASH algorithm. + * @retval HAL status + */ +HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm) +{ + HAL_HASH_StateTypeDef State_tmp = hhash->State; + __IO uint32_t inputaddr = (uint32_t) pInBuffer; + uint32_t SizeVar = Size; + + /* Make sure the input buffer size (in bytes) is a multiple of 4 */ + if ((Size % 4U) != 0U) + { + return HAL_ERROR; + } + + /* Initiate HASH processing in case of start or resumption */ + if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED)) + { + /* Check input parameters */ + if ((pInBuffer == NULL) || (Size == 0U)) + { + hhash->State = HAL_HASH_STATE_READY; + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hhash); + + /* If resuming the HASH processing */ + if (hhash->State == HAL_HASH_STATE_SUSPENDED) + { + /* Change the HASH state */ + hhash->State = HAL_HASH_STATE_BUSY; + } + else + { + /* Change the HASH state */ + hhash->State = HAL_HASH_STATE_BUSY; + + /* Check if initialization phase has already be performed */ + if(hhash->Phase == HAL_HASH_PHASE_READY) + { + /* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */ + MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT); + hhash->HashITCounter = 1; + } + else + { + hhash->HashITCounter = 3; /* 'cruise-speed' reached during a previous buffer processing */ + } + + /* Set the phase */ + hhash->Phase = HAL_HASH_PHASE_PROCESS; + + /* If DINIS is equal to 0 (for example if an incomplete block has been previously + fed to the Peripheral), the DINIE interruption won't be triggered when DINIE is set. + Therefore, first words are manually entered until DINIS raises, or until there + is not more data to enter. */ + while((!(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))) && (SizeVar > 0U)) + { + + /* Write input data 4 bytes at a time */ + HASH->DIN = *(uint32_t*)inputaddr; + inputaddr+=4U; + SizeVar-=4U; + } + + /* If DINIS is still not set or if all the data have been fed, stop here */ + if ((!(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))) || (SizeVar == 0U)) + { + /* Change the HASH state */ + hhash->State = HAL_HASH_STATE_READY; + + /* Process Unlock */ + __HAL_UNLOCK(hhash); + + /* Return function status */ + return HAL_OK; + } + + /* otherwise, carry on in interrupt-mode */ + hhash->HashInCount = SizeVar; /* Counter used to keep track of number of data + to be fed to the Peripheral */ + hhash->pHashInBuffPtr = (uint8_t *)inputaddr; /* Points at data which will be fed to the Peripheral at + the next interruption */ + /* In case of suspension, hhash->HashInCount and hhash->pHashInBuffPtr contain + the information describing where the HASH process is stopped. + These variables are used later on to resume the HASH processing at the + correct location. */ + + } + + /* Set multi buffers accumulation flag */ + hhash->Accumulation = 1U; + + /* Process Unlock */ + __HAL_UNLOCK(hhash); + + /* Enable Data Input interrupt */ + __HAL_HASH_ENABLE_IT(HASH_IT_DINI); + + /* Return function status */ + return HAL_OK; + + } + else + { + return HAL_BUSY; + } + +} + + + /** * @brief Initialize the HASH peripheral, next process pInBuffer then * read the computed digest in interruption mode. * @note Digest is available in pOutBuffer. - * @param hhash: HASH handle. - * @param pInBuffer: pointer to the input buffer (buffer to be hashed). - * @param Size: length of the input buffer in bytes. - * @param pOutBuffer: pointer to the computed digest. - * @param Algorithm: HASH algorithm. + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (buffer to be hashed). + * @param Size length of the input buffer in bytes. + * @param pOutBuffer pointer to the computed digest. + * @param Algorithm HASH algorithm. * @retval HAL status */ HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm) { HAL_HASH_StateTypeDef State_tmp = hhash->State; + __IO uint32_t inputaddr = (uint32_t) pInBuffer; + uint32_t polling_step = 0U; + uint32_t initialization_skipped = 0U; + uint32_t SizeVar = Size; /* If State is ready or suspended, start or resume IT-based HASH processing */ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED)) @@ -2490,12 +2802,12 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT); /* Configure the number of valid bits in last word of the message */ - __HAL_HASH_SET_NBVALIDBITS(Size); + __HAL_HASH_SET_NBVALIDBITS(SizeVar); - hhash->HashInCount = Size; /* Counter used to keep track of number of data - to be fed to the IP */ - hhash->pHashInBuffPtr = pInBuffer; /* Points at data which will be fed to the IP at + hhash->HashInCount = SizeVar; /* Counter used to keep track of number of data + to be fed to the Peripheral */ + hhash->pHashInBuffPtr = pInBuffer; /* Points at data which will be fed to the Peripheral at the next interruption */ /* In case of suspension, hhash->HashInCount and hhash->pHashInBuffPtr contain the information describing where the HASH process is stopped. @@ -2504,10 +2816,82 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED hhash->pHashOutBuffPtr = pOutBuffer; /* Points at the computed digest */ } + else + { + initialization_skipped = 1; /* info user later on in case of multi-buffer */ + } /* Set the phase */ hhash->Phase = HAL_HASH_PHASE_PROCESS; + /* If DINIS is equal to 0 (for example if an incomplete block has been previously + fed to the Peripheral), the DINIE interruption won't be triggered when DINIE is set. + Therefore, first words are manually entered until DINIS raises. */ + while((!(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))) && (SizeVar > 3U)) + { + polling_step = 1U; /* note that some words are entered before enabling the interrupt */ + + /* Write input data 4 bytes at a time */ + HASH->DIN = *(uint32_t*)inputaddr; + inputaddr+=4U; + SizeVar-=4U; + } + + if (polling_step == 1U) + { + if (SizeVar == 0U) + { + /* If all the data have been entered at this point, it only remains to + read the digest */ + hhash->pHashOutBuffPtr = pOutBuffer; /* Points at the computed digest */ + + /* Start the Digest calculation */ + __HAL_HASH_START_DIGEST(); + /* Process Unlock */ + __HAL_UNLOCK(hhash); + + /* Enable Interrupts */ + __HAL_HASH_ENABLE_IT(HASH_IT_DCI); + + /* Return function status */ + return HAL_OK; + } + else if (__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS)) + { + /* It remains data to enter and the Peripheral is ready to trigger DINIE, + carry on as usual. + Update HashInCount and pHashInBuffPtr accordingly. */ + hhash->HashInCount = SizeVar; + hhash->pHashInBuffPtr = (uint8_t *)inputaddr; + __HAL_HASH_SET_NBVALIDBITS(SizeVar); /* Update the configuration of the number of valid bits in last word of the message */ + hhash->pHashOutBuffPtr = pOutBuffer; /* Points at the computed digest */ + if (initialization_skipped == 1U) + { + hhash->HashITCounter = 3; /* 'cruise-speed' reached during a previous buffer processing */ + } + } + else + { + /* DINIS is not set but it remains a few data to enter (not enough for a full word). + Manually enter the last bytes before enabling DCIE. */ + __HAL_HASH_SET_NBVALIDBITS(SizeVar); + HASH->DIN = *(uint32_t*)inputaddr; + + /* Start the Digest calculation */ + hhash->pHashOutBuffPtr = pOutBuffer; /* Points at the computed digest */ + __HAL_HASH_START_DIGEST(); + /* Process Unlock */ + __HAL_UNLOCK(hhash); + + /* Enable Interrupts */ + __HAL_HASH_ENABLE_IT(HASH_IT_DCI); + + /* Return function status */ + return HAL_OK; + } + } /* if (polling_step == 1) */ + + /* Process Unlock */ __HAL_UNLOCK(hhash); @@ -2527,17 +2911,17 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED /** * @brief Initialize the HASH peripheral then initiate a DMA transfer - * to feed the input buffer to the IP. + * to feed the input buffer to the Peripheral. * @note If MDMAT bit is set before calling this function (multi-buffer * HASH processing case), the input buffer size (in bytes) must be * a multiple of 4 otherwise, the HASH digest computation is corrupted. * For the processing of the last buffer of the thread, MDMAT bit must * be reset and the buffer length (in bytes) doesn't have to be a * multiple of 4. - * @param hhash: HASH handle. - * @param pInBuffer: pointer to the input buffer (buffer to be hashed). - * @param Size: length of the input buffer in bytes. - * @param Algorithm: HASH algorithm. + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (buffer to be hashed). + * @param Size length of the input buffer in bytes. + * @param Algorithm HASH algorithm. * @retval HAL status */ HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm) @@ -2637,11 +3021,6 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED /* Update HASH state machine to error */ hhash->State = HAL_HASH_STATE_ERROR; } - else - { - /* Change HASH state */ - hhash->State = HAL_HASH_STATE_READY; - } return status; } @@ -2654,9 +3033,9 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED /** * @brief Return the computed digest. * @note The API waits for DCIS to be set then reads the computed digest. - * @param hhash: HASH handle. - * @param pOutBuffer: pointer to the computed digest. - * @param Timeout: Timeout value. + * @param hhash HASH handle. + * @param pOutBuffer pointer to the computed digest. + * @param Timeout Timeout value. * @retval HAL status */ HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout) @@ -2688,6 +3067,9 @@ HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, ui /* Change the HASH state to ready */ hhash->State = HAL_HASH_STATE_READY; + /* Reset HASH state machine */ + hhash->Phase = HAL_HASH_PHASE_READY; + /* Process UnLock */ __HAL_UNLOCK(hhash); @@ -2709,12 +3091,12 @@ HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, ui * @note Digest is available in pOutBuffer. * @note Same key is used for the inner and the outer hash functions; pointer to key and * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. - * @param hhash: HASH handle. - * @param pInBuffer: pointer to the input buffer (buffer to be hashed). - * @param Size: length of the input buffer in bytes. - * @param pOutBuffer: pointer to the computed digest. - * @param Timeout: Timeout value. - * @param Algorithm: HASH algorithm. + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (buffer to be hashed). + * @param Size length of the input buffer in bytes. + * @param pOutBuffer pointer to the computed digest. + * @param Timeout Timeout value. + * @param Algorithm HASH algorithm. * @retval HAL status */ HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm) @@ -2751,7 +3133,7 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED } /* Set the phase to Step 1 */ hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_1; - /* Resort to hhash internal fields to feed the IP. + /* Resort to hhash internal fields to feed the Peripheral. Parameters will be updated in case of suspension to contain the proper information at resumption time. */ hhash->pHashOutBuffPtr = pOutBuffer; /* Output digest address */ @@ -2780,11 +3162,11 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED * @note Digest is available in pOutBuffer. * @note Same key is used for the inner and the outer hash functions; pointer to key and * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. - * @param hhash: HASH handle. - * @param pInBuffer: pointer to the input buffer (buffer to be hashed). - * @param Size: length of the input buffer in bytes. - * @param pOutBuffer: pointer to the computed digest. - * @param Algorithm: HASH algorithm. + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (buffer to be hashed). + * @param Size length of the input buffer in bytes. + * @param pOutBuffer pointer to the computed digest. + * @param Algorithm HASH algorithm. * @retval HAL status */ HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm) @@ -2824,7 +3206,7 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED } /* Resort to hhash internal fields hhash->pHashInBuffPtr and hhash->HashInCount - to feed the IP whatever the HMAC step. + to feed the Peripheral whatever the HMAC step. Lines below are set to start HMAC Step 1 processing where key is entered first. */ hhash->HashInCount = hhash->Init.KeySize; /* Key size */ hhash->pHashInBuffPtr = hhash->Init.pKey ; /* Key address */ @@ -2881,17 +3263,17 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED /** * @brief Initialize the HASH peripheral in HMAC mode then initiate the required - * DMA transfers to feed the key and the input buffer to the IP. + * DMA transfers to feed the key and the input buffer to the Peripheral. * @note Same key is used for the inner and the outer hash functions; pointer to key and * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. * @note In case of multi-buffer HMAC processing, the input buffer size (in bytes) must * be a multiple of 4 otherwise, the HASH digest computation is corrupted. * Only the length of the last buffer of the thread doesn't have to be a * multiple of 4. - * @param hhash: HASH handle. - * @param pInBuffer: pointer to the input buffer (buffer to be hashed). - * @param Size: length of the input buffer in bytes. - * @param Algorithm: HASH algorithm. + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (buffer to be hashed). + * @param Size length of the input buffer in bytes. + * @param Algorithm HASH algorithm. * @retval HAL status */ HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm) @@ -3027,11 +3409,7 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED /* Update HASH state machine to error */ hhash->State = HAL_HASH_STATE_ERROR; } - else - { - /* Change HASH state */ - hhash->State = HAL_HASH_STATE_READY; - } + /* Return function status */ return status; } diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_hash_ex.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_hash_ex.c index e666d0a1ce..b36342dfbe 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_hash_ex.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_hash_ex.c @@ -33,16 +33,21 @@ e.g. HAL_HASHEx_xxx_Start_DMA(). Note that in DMA mode, a call to HAL_HASHEx_xxx_Finish() is then required to retrieve the digest. - (#)Multi-buffer processing is possible in polling and DMA mode. + (#)Multi-buffer processing is possible in polling, interrupt and DMA modes. (##) In polling mode, only multi-buffer HASH processing is possible. API HAL_HASHEx_xxx_Accumulate() must be called for each input buffer, except for the last one. - User must resort to HAL_HASHEx_xxx_Start() to enter the last one and retrieve as + User must resort to HAL_HASHEx_xxx_Accumulate_End() to enter the last one and retrieve as + well the computed digest. + + (##) In interrupt mode, API HAL_HASHEx_xxx_Accumulate_IT() must be called for each input buffer, + except for the last one. + User must resort to HAL_HASHEx_xxx_Accumulate_End_IT() to enter the last one and retrieve as well the computed digest. (##) In DMA mode, multi-buffer HASH and HMAC processing are possible. (+++) HASH processing: once initialization is done, MDMAT bit must be set thru __HAL_HASH_SET_MDMAT() macro. - From that point, each buffer can be fed to the IP thru HAL_HASHEx_xxx_Start_DMA() API. + From that point, each buffer can be fed to the Peripheral thru HAL_HASHEx_xxx_Start_DMA() API. Before entering the last buffer, reset the MDMAT bit with __HAL_HASH_RESET_MDMAT() macro then wrap-up the HASH processing in feeding the last input buffer thru the same API HAL_HASHEx_xxx_Start_DMA(). The digest can then be retrieved with a call to @@ -50,7 +55,7 @@ (+++) HMAC processing (MD-5, SHA-1, SHA-224 and SHA-256 must all resort to extended functions): after initialization, the key and the first input buffer are entered - in the IP with the API HAL_HMACEx_xxx_Step1_2_DMA(). This carries out HMAC step 1 and + in the Peripheral with the API HAL_HMACEx_xxx_Step1_2_DMA(). This carries out HMAC step 1 and starts step 2. The following buffers are next entered with the API HAL_HMACEx_xxx_Step2_DMA(). At this point, the HMAC processing is still carrying out step 2. @@ -112,17 +117,19 @@ the hash value using one of the following algorithms: (+) SHA224 (++) HAL_HASHEx_SHA224_Start() - (++) HAL_HASHEx_SHA224_Accumulate() + (++) HAL_HASHEx_SHA224_Accmlt() + (++) HAL_HASHEx_SHA224_Accmlt_End() (+) SHA256 (++) HAL_HASHEx_SHA256_Start() - (++) HAL_HASHEx_SHA256_Accumulate() + (++) HAL_HASHEx_SHA256_Accmlt() + (++) HAL_HASHEx_SHA256_Accmlt_End() [..] For a single buffer to be hashed, user can resort to HAL_HASH_xxx_Start(). [..] In case of multi-buffer HASH processing (a single digest is computed while - several buffers are fed to the IP), the user can resort to successive calls + several buffers are fed to the Peripheral), the user can resort to successive calls to HAL_HASHEx_xxx_Accumulate() and wrap-up the digest computation by a call - to HAL_HASHEx_xxx_Start(). + to HAL_HASHEx_xxx_Accumulate_End(). @endverbatim * @{ @@ -133,11 +140,11 @@ * @brief Initialize the HASH peripheral in SHA224 mode, next process pInBuffer then * read the computed digest. * @note Digest is available in pOutBuffer. - * @param hhash: HASH handle. - * @param pInBuffer: pointer to the input buffer (buffer to be hashed). - * @param Size: length of the input buffer in bytes. - * @param pOutBuffer: pointer to the computed digest. Digest size is 28 bytes. - * @param Timeout: Timeout value + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (buffer to be hashed). + * @param Size length of the input buffer in bytes. + * @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes. + * @param Timeout Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) @@ -148,37 +155,52 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pI /** * @brief If not already done, initialize the HASH peripheral in SHA224 mode then * processes pInBuffer. - * @note Consecutive calls to HAL_HASHEx_SHA224_Accumulate() can be used to feed - * several input buffers back-to-back to the IP that will yield a single + * @note Consecutive calls to HAL_HASHEx_SHA224_Accmlt() can be used to feed + * several input buffers back-to-back to the Peripheral that will yield a single * HASH signature once all buffers have been entered. Wrap-up of input * buffers feeding and retrieval of digest is done by a call to - * HAL_HASHEx_SHA224_Start(). + * HAL_HASHEx_SHA224_Accmlt_End(). * @note Field hhash->Phase of HASH handle is tested to check whether or not - * the IP has already been initialized. - * @note Digest is not retrieved by this API, user must resort to HAL_HASHEx_SHA224_Start() - * to read it, feeding at the same time the last input buffer to the IP. + * the Peripheral has already been initialized. + * @note Digest is not retrieved by this API, user must resort to HAL_HASHEx_SHA224_Accmlt_End() + * to read it, feeding at the same time the last input buffer to the Peripheral. * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the - * HASH digest computation is corrupted. Only HAL_HASHEx_SHA224_Start() is able + * HASH digest computation is corrupted. Only HAL_HASHEx_SHA224_Accmlt_End() is able * to manage the ending buffer with a length in bytes not a multiple of 4. - * @param hhash: HASH handle. - * @param pInBuffer: pointer to the input buffer (buffer to be hashed). - * @param Size: length of the input buffer in bytes, must be a multiple of 4. + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (buffer to be hashed). + * @param Size length of the input buffer in bytes, must be a multiple of 4. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) { return HASH_Accumulate(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA224); } +/** + * @brief End computation of a single HASH signature after several calls to HAL_HASHEx_SHA224_Accmlt() API. + * @note Digest is available in pOutBuffer. + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (buffer to be hashed). + * @param Size length of the input buffer in bytes. + * @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes. + * @param Timeout Timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) +{ + return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA224); +} + /** * @brief Initialize the HASH peripheral in SHA256 mode, next process pInBuffer then * read the computed digest. * @note Digest is available in pOutBuffer. - * @param hhash: HASH handle. - * @param pInBuffer: pointer to the input buffer (buffer to be hashed). - * @param Size: length of the input buffer in bytes. - * @param pOutBuffer: pointer to the computed digest. Digest size is 32 bytes. - * @param Timeout: Timeout value + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (buffer to be hashed). + * @param Size length of the input buffer in bytes. + * @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes. + * @param Timeout Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) @@ -189,28 +211,42 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI /** * @brief If not already done, initialize the HASH peripheral in SHA256 mode then * processes pInBuffer. - * @note Consecutive calls to HAL_HASHEx_SHA256_Accumulate() can be used to feed - * several input buffers back-to-back to the IP that will yield a single + * @note Consecutive calls to HAL_HASHEx_SHA256_Accmlt() can be used to feed + * several input buffers back-to-back to the Peripheral that will yield a single * HASH signature once all buffers have been entered. Wrap-up of input * buffers feeding and retrieval of digest is done by a call to - * HAL_HASHEx_SHA256_Start(). + * HAL_HASHEx_SHA256_Accmlt_End(). * @note Field hhash->Phase of HASH handle is tested to check whether or not - * the IP has already been initialized. - * @note Digest is not retrieved by this API, user must resort to HAL_HASHEx_SHA256_Start() - * to read it, feeding at the same time the last input buffer to the IP. + * the Peripheral has already been initialized. + * @note Digest is not retrieved by this API, user must resort to HAL_HASHEx_SHA256_Accmlt_End() + * to read it, feeding at the same time the last input buffer to the Peripheral. * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the - * HASH digest computation is corrupted. Only HAL_HASHEx_SHA256_Start() is able + * HASH digest computation is corrupted. Only HAL_HASHEx_SHA256_Accmlt_End() is able * to manage the ending buffer with a length in bytes not a multiple of 4. - * @param hhash: HASH handle. - * @param pInBuffer: pointer to the input buffer (buffer to be hashed). - * @param Size: length of the input buffer in bytes, must be a multiple of 4. + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (buffer to be hashed). + * @param Size length of the input buffer in bytes, must be a multiple of 4. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) { return HASH_Accumulate(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA256); } +/** + * @brief End computation of a single HASH signature after several calls to HAL_HASHEx_SHA256_Accmlt() API. + * @note Digest is available in pOutBuffer. + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (buffer to be hashed). + * @param Size length of the input buffer in bytes. + * @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes. + * @param Timeout Timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) +{ + return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA256); +} /** * @} @@ -227,8 +263,12 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate(HASH_HandleTypeDef *hhash, uint8_ the hash value using one of the following algorithms: (+) SHA224 (++) HAL_HASHEx_SHA224_Start_IT() + (++) HAL_HASHEx_SHA224_Accmlt_IT() + (++) HAL_HASHEx_SHA224_Accmlt_End_IT() (+) SHA256 (++) HAL_HASHEx_SHA256_Start_IT() + (++) HAL_HASHEx_SHA256_Accmlt_IT() + (++) HAL_HASHEx_SHA256_Accmlt_End_IT() @endverbatim * @{ @@ -239,10 +279,10 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate(HASH_HandleTypeDef *hhash, uint8_ * @brief Initialize the HASH peripheral in SHA224 mode, next process pInBuffer then * read the computed digest in interruption mode. * @note Digest is available in pOutBuffer. - * @param hhash: HASH handle. - * @param pInBuffer: pointer to the input buffer (buffer to be hashed). - * @param Size: length of the input buffer in bytes. - * @param pOutBuffer: pointer to the computed digest. Digest size is 28 bytes. + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (buffer to be hashed). + * @param Size length of the input buffer in bytes. + * @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes. * @retval HAL status */ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer) @@ -250,14 +290,51 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA224); } +/** + * @brief If not already done, initialize the HASH peripheral in SHA224 mode then + * processes pInBuffer in interruption mode. + * @note Consecutive calls to HAL_HASHEx_SHA224_Accmlt_IT() can be used to feed + * several input buffers back-to-back to the Peripheral that will yield a single + * HASH signature once all buffers have been entered. Wrap-up of input + * buffers feeding and retrieval of digest is done by a call to + * HAL_HASHEx_SHA224_Accmlt_End_IT(). + * @note Field hhash->Phase of HASH handle is tested to check whether or not + * the Peripheral has already been initialized. + * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the + * HASH digest computation is corrupted. Only HAL_HASHEx_SHA224_Accmlt_End_IT() is able + * to manage the ending buffer with a length in bytes not a multiple of 4. + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (buffer to be hashed). + * @param Size length of the input buffer in bytes, must be a multiple of 4. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +{ + return HASH_Accumulate_IT(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA224); +} + +/** + * @brief End computation of a single HASH signature after several calls to HAL_HASHEx_SHA224_Accmlt_IT() API. + * @note Digest is available in pOutBuffer. + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (buffer to be hashed). + * @param Size length of the input buffer in bytes. + * @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer) +{ + return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA224); +} + /** * @brief Initialize the HASH peripheral in SHA256 mode, next process pInBuffer then * read the computed digest in interruption mode. * @note Digest is available in pOutBuffer. - * @param hhash: HASH handle. - * @param pInBuffer: pointer to the input buffer (buffer to be hashed). - * @param Size: length of the input buffer in bytes. - * @param pOutBuffer: pointer to the computed digest. Digest size is 32 bytes. + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (buffer to be hashed). + * @param Size length of the input buffer in bytes. + * @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes. * @retval HAL status */ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer) @@ -265,6 +342,43 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA256); } +/** + * @brief If not already done, initialize the HASH peripheral in SHA256 mode then + * processes pInBuffer in interruption mode. + * @note Consecutive calls to HAL_HASHEx_SHA256_Accmlt_IT() can be used to feed + * several input buffers back-to-back to the Peripheral that will yield a single + * HASH signature once all buffers have been entered. Wrap-up of input + * buffers feeding and retrieval of digest is done by a call to + * HAL_HASHEx_SHA256_Accmlt_End_IT(). + * @note Field hhash->Phase of HASH handle is tested to check whether or not + * the Peripheral has already been initialized. + * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the + * HASH digest computation is corrupted. Only HAL_HASHEx_SHA256_Accmlt_End_IT() is able + * to manage the ending buffer with a length in bytes not a multiple of 4. + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (buffer to be hashed). + * @param Size length of the input buffer in bytes, must be a multiple of 4. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +{ + return HASH_Accumulate_IT(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA256); +} + +/** + * @brief End computation of a single HASH signature after several calls to HAL_HASHEx_SHA256_Accmlt_IT() API. + * @note Digest is available in pOutBuffer. + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (buffer to be hashed). + * @param Size length of the input buffer in bytes. + * @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer) +{ + return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA256); +} + /** * @} */ @@ -285,7 +399,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t (++) HAL_HASHEx_SHA256_Start_DMA() (++) HAL_HASHEx_SHA256_Finish() - [..] When resorting to DMA mode to enter the data in the IP, user must resort + [..] When resorting to DMA mode to enter the data in the Peripheral, user must resort to HAL_HASHEx_xxx_Start_DMA() then read the resulting digest with HAL_HASHEx_xxx_Finish(). @@ -303,12 +417,12 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t /** * @brief Initialize the HASH peripheral in SHA224 mode then initiate a DMA transfer - * to feed the input buffer to the IP. + * to feed the input buffer to the Peripheral. * @note Once the DMA transfer is finished, HAL_HASHEx_SHA224_Finish() API must * be called to retrieve the computed digest. - * @param hhash: HASH handle. - * @param pInBuffer: pointer to the input buffer (buffer to be hashed). - * @param Size: length of the input buffer in bytes. + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (buffer to be hashed). + * @param Size length of the input buffer in bytes. * @retval HAL status */ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) @@ -321,9 +435,9 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t * @note The API waits for DCIS to be set then reads the computed digest. * @note HAL_HASHEx_SHA224_Finish() can be used as well to retrieve the digest in * HMAC SHA224 mode. - * @param hhash: HASH handle. - * @param pOutBuffer: pointer to the computed digest. Digest size is 28 bytes. - * @param Timeout: Timeout value. + * @param hhash HASH handle. + * @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes. + * @param Timeout Timeout value. * @retval HAL status */ HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout) @@ -333,12 +447,12 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* p /** * @brief Initialize the HASH peripheral in SHA256 mode then initiate a DMA transfer - * to feed the input buffer to the IP. + * to feed the input buffer to the Peripheral. * @note Once the DMA transfer is finished, HAL_HASHEx_SHA256_Finish() API must * be called to retrieve the computed digest. - * @param hhash: HASH handle. - * @param pInBuffer: pointer to the input buffer (buffer to be hashed). - * @param Size: length of the input buffer in bytes. + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (buffer to be hashed). + * @param Size length of the input buffer in bytes. * @retval HAL status */ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) @@ -351,9 +465,9 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t * @note The API waits for DCIS to be set then reads the computed digest. * @note HAL_HASHEx_SHA256_Finish() can be used as well to retrieve the digest in * HMAC SHA256 mode. - * @param hhash: HASH handle. - * @param pOutBuffer: pointer to the computed digest. Digest size is 32 bytes. - * @param Timeout: Timeout value. + * @param hhash HASH handle. + * @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes. + * @param Timeout Timeout value. * @retval HAL status */ HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout) @@ -391,11 +505,11 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* p * @note Digest is available in pOutBuffer. * @note Same key is used for the inner and the outer hash functions; pointer to key and * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. - * @param hhash: HASH handle. - * @param pInBuffer: pointer to the input buffer (buffer to be hashed). - * @param Size: length of the input buffer in bytes. - * @param pOutBuffer: pointer to the computed digest. Digest size is 28 bytes. - * @param Timeout: Timeout value. + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (buffer to be hashed). + * @param Size length of the input buffer in bytes. + * @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes. + * @param Timeout Timeout value. * @retval HAL status */ HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) @@ -409,11 +523,11 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pI * @note Digest is available in pOutBuffer. * @note Same key is used for the inner and the outer hash functions; pointer to key and * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. - * @param hhash: HASH handle. - * @param pInBuffer: pointer to the input buffer (buffer to be hashed). - * @param Size: length of the input buffer in bytes. - * @param pOutBuffer: pointer to the computed digest. Digest size is 32 bytes. - * @param Timeout: Timeout value. + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (buffer to be hashed). + * @param Size length of the input buffer in bytes. + * @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes. + * @param Timeout Timeout value. * @retval HAL status */ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) @@ -452,10 +566,10 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI * @note Digest is available in pOutBuffer. * @note Same key is used for the inner and the outer hash functions; pointer to key and * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. - * @param hhash: HASH handle. - * @param pInBuffer: pointer to the input buffer (buffer to be hashed). - * @param Size: length of the input buffer in bytes. - * @param pOutBuffer: pointer to the computed digest. Digest size is 28 bytes. + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (buffer to be hashed). + * @param Size length of the input buffer in bytes. + * @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes. * @retval HAL status */ HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer) @@ -469,10 +583,10 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t * @note Digest is available in pOutBuffer. * @note Same key is used for the inner and the outer hash functions; pointer to key and * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. - * @param hhash: HASH handle. - * @param pInBuffer: pointer to the input buffer (buffer to be hashed). - * @param Size: length of the input buffer in bytes. - * @param pOutBuffer: pointer to the computed digest. Digest size is 32 bytes. + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (buffer to be hashed). + * @param Size length of the input buffer in bytes. + * @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes. * @retval HAL status */ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer) @@ -502,7 +616,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t (+) SHA256 (++) HAL_HMACEx_SHA256_Start_DMA() - [..] When resorting to DMA mode to enter the data in the IP for HMAC processing, + [..] When resorting to DMA mode to enter the data in the Peripheral for HMAC processing, user must resort to HAL_HMACEx_xxx_Start_DMA() then read the resulting digest with HAL_HASHEx_xxx_Finish(). @@ -515,7 +629,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t /** * @brief Initialize the HASH peripheral in HMAC SHA224 mode then initiate the required - * DMA transfers to feed the key and the input buffer to the IP. + * DMA transfers to feed the key and the input buffer to the Peripheral. * @note Once the DMA transfers are finished (indicated by hhash->State set back * to HAL_HASH_STATE_READY), HAL_HASHEx_SHA224_Finish() API must be called to retrieve * the computed digest. @@ -527,9 +641,9 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t * For the processing of the last buffer of the thread, MDMAT bit must * be reset and the buffer length (in bytes) doesn't have to be a * multiple of 4. - * @param hhash: HASH handle. - * @param pInBuffer: pointer to the input buffer (buffer to be hashed). - * @param Size: length of the input buffer in bytes. + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (buffer to be hashed). + * @param Size length of the input buffer in bytes. * @retval HAL status */ HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) @@ -539,7 +653,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t /** * @brief Initialize the HASH peripheral in HMAC SHA224 mode then initiate the required - * DMA transfers to feed the key and the input buffer to the IP. + * DMA transfers to feed the key and the input buffer to the Peripheral. * @note Once the DMA transfers are finished (indicated by hhash->State set back * to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve * the computed digest. @@ -551,9 +665,9 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t * For the processing of the last buffer of the thread, MDMAT bit must * be reset and the buffer length (in bytes) doesn't have to be a * multiple of 4. - * @param hhash: HASH handle. - * @param pInBuffer: pointer to the input buffer (buffer to be hashed). - * @param Size: length of the input buffer in bytes. + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (buffer to be hashed). + * @param Size length of the input buffer in bytes. * @retval HAL status */ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) @@ -597,13 +711,13 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t calling HAL_HMACEx_xxx_Step1_2_DMA(). This carries out HMAC step 1 and intiates step 2 with the first input buffer. - [..] The following buffers are next fed to the IP with a call to the API + [..] The following buffers are next fed to the Peripheral with a call to the API HAL_HMACEx_xxx_Step2_DMA(). There may be several consecutive calls to this API. [..] Multi-buffer DMA-based HMAC computation is wrapped up by a call to HAL_HMACEx_xxx_Step2_3_DMA(). This finishes step 2 in feeding the last input - buffer to the IP then carries out step 3. + buffer to the Peripheral then carries out step 3. [..] Digest is retrieved by a call to HAL_HASH_xxx_Finish() for MD-5 or SHA-1, to HAL_HASHEx_xxx_Finish() for SHA-224 or SHA-256. @@ -618,18 +732,18 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t /** * @brief MD5 HMAC step 1 completion and step 2 start in multi-buffer DMA mode. - * @note Step 1 consists in writing the inner hash function key in the IP, + * @note Step 1 consists in writing the inner hash function key in the Peripheral, * step 2 consists in writing the message text. * @note The API carries out the HMAC step 1 then starts step 2 with - * the first buffer entered to the IP. DCAL bit is not automatically set after + * the first buffer entered to the Peripheral. DCAL bit is not automatically set after * the message buffer feeding, allowing other messages DMA transfers to occur. * @note Same key is used for the inner and the outer hash functions; pointer to key and * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the * HASH digest computation is corrupted. - * @param hhash: HASH handle. - * @param pInBuffer: pointer to the input buffer (message buffer). - * @param Size: length of the input buffer in bytes. + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (message buffer). + * @param Size length of the input buffer in bytes. * @retval HAL status */ HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) @@ -640,7 +754,7 @@ HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t /** * @brief MD5 HMAC step 2 in multi-buffer DMA mode. - * @note Step 2 consists in writing the message text in the IP. + * @note Step 2 consists in writing the message text in the Peripheral. * @note The API carries on the HMAC step 2, applied to the buffer entered as input * parameter. DCAL bit is not automatically set after the message buffer feeding, * allowing other messages DMA transfers to occur. @@ -648,9 +762,9 @@ HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the * HASH digest computation is corrupted. - * @param hhash: HASH handle. - * @param pInBuffer: pointer to the input buffer (message buffer). - * @param Size: length of the input buffer in bytes. + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (message buffer). + * @param Size length of the input buffer in bytes. * @retval HAL status */ HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) @@ -664,7 +778,7 @@ HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *p /** * @brief MD5 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode. - * @note Step 2 consists in writing the message text in the IP, + * @note Step 2 consists in writing the message text in the Peripheral, * step 3 consists in writing the outer hash function key. * @note The API wraps up the HMAC step 2 in processing the buffer entered as input * parameter (the input buffer must be the last one of the multi-buffer thread) @@ -674,9 +788,9 @@ HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *p * @note Once the DMA transfers are finished (indicated by hhash->State set back * to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve * the computed digest. - * @param hhash: HASH handle. - * @param pInBuffer: pointer to the input buffer (message buffer). - * @param Size: length of the input buffer in bytes. + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (message buffer). + * @param Size length of the input buffer in bytes. * @retval HAL status */ HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) @@ -688,18 +802,18 @@ HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t /** * @brief SHA1 HMAC step 1 completion and step 2 start in multi-buffer DMA mode. - * @note Step 1 consists in writing the inner hash function key in the IP, + * @note Step 1 consists in writing the inner hash function key in the Peripheral, * step 2 consists in writing the message text. * @note The API carries out the HMAC step 1 then starts step 2 with - * the first buffer entered to the IP. DCAL bit is not automatically set after + * the first buffer entered to the Peripheral. DCAL bit is not automatically set after * the message buffer feeding, allowing other messages DMA transfers to occur. * @note Same key is used for the inner and the outer hash functions; pointer to key and * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the * HASH digest computation is corrupted. - * @param hhash: HASH handle. - * @param pInBuffer: pointer to the input buffer (message buffer). - * @param Size: length of the input buffer in bytes. + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (message buffer). + * @param Size length of the input buffer in bytes. * @retval HAL status */ HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) @@ -710,7 +824,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t /** * @brief SHA1 HMAC step 2 in multi-buffer DMA mode. - * @note Step 2 consists in writing the message text in the IP. + * @note Step 2 consists in writing the message text in the Peripheral. * @note The API carries on the HMAC step 2, applied to the buffer entered as input * parameter. DCAL bit is not automatically set after the message buffer feeding, * allowing other messages DMA transfers to occur. @@ -718,9 +832,9 @@ HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the * HASH digest computation is corrupted. - * @param hhash: HASH handle. - * @param pInBuffer: pointer to the input buffer (message buffer). - * @param Size: length of the input buffer in bytes. + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (message buffer). + * @param Size length of the input buffer in bytes. * @retval HAL status */ HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) @@ -734,7 +848,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t * /** * @brief SHA1 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode. - * @note Step 2 consists in writing the message text in the IP, + * @note Step 2 consists in writing the message text in the Peripheral, * step 3 consists in writing the outer hash function key. * @note The API wraps up the HMAC step 2 in processing the buffer entered as input * parameter (the input buffer must be the last one of the multi-buffer thread) @@ -744,9 +858,9 @@ HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t * * @note Once the DMA transfers are finished (indicated by hhash->State set back * to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve * the computed digest. - * @param hhash: HASH handle. - * @param pInBuffer: pointer to the input buffer (message buffer). - * @param Size: length of the input buffer in bytes. + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (message buffer). + * @param Size length of the input buffer in bytes. * @retval HAL status */ HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) @@ -757,18 +871,18 @@ HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t /** * @brief SHA224 HMAC step 1 completion and step 2 start in multi-buffer DMA mode. - * @note Step 1 consists in writing the inner hash function key in the IP, + * @note Step 1 consists in writing the inner hash function key in the Peripheral, * step 2 consists in writing the message text. * @note The API carries out the HMAC step 1 then starts step 2 with - * the first buffer entered to the IP. DCAL bit is not automatically set after + * the first buffer entered to the Peripheral. DCAL bit is not automatically set after * the message buffer feeding, allowing other messages DMA transfers to occur. * @note Same key is used for the inner and the outer hash functions; pointer to key and * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the * HASH digest computation is corrupted. - * @param hhash: HASH handle. - * @param pInBuffer: pointer to the input buffer (message buffer). - * @param Size: length of the input buffer in bytes. + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (message buffer). + * @param Size length of the input buffer in bytes. * @retval HAL status */ HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) @@ -779,7 +893,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8 /** * @brief SHA224 HMAC step 2 in multi-buffer DMA mode. - * @note Step 2 consists in writing the message text in the IP. + * @note Step 2 consists in writing the message text in the Peripheral. * @note The API carries on the HMAC step 2, applied to the buffer entered as input * parameter. DCAL bit is not automatically set after the message buffer feeding, * allowing other messages DMA transfers to occur. @@ -787,9 +901,9 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8 * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the * HASH digest computation is corrupted. - * @param hhash: HASH handle. - * @param pInBuffer: pointer to the input buffer (message buffer). - * @param Size: length of the input buffer in bytes. + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (message buffer). + * @param Size length of the input buffer in bytes. * @retval HAL status */ HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) @@ -803,7 +917,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t /** * @brief SHA224 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode. - * @note Step 2 consists in writing the message text in the IP, + * @note Step 2 consists in writing the message text in the Peripheral, * step 3 consists in writing the outer hash function key. * @note The API wraps up the HMAC step 2 in processing the buffer entered as input * parameter (the input buffer must be the last one of the multi-buffer thread) @@ -813,9 +927,9 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t * @note Once the DMA transfers are finished (indicated by hhash->State set back * to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve * the computed digest. - * @param hhash: HASH handle. - * @param pInBuffer: pointer to the input buffer (message buffer). - * @param Size: length of the input buffer in bytes. + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (message buffer). + * @param Size length of the input buffer in bytes. * @retval HAL status */ HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) @@ -826,18 +940,18 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8 /** * @brief SHA256 HMAC step 1 completion and step 2 start in multi-buffer DMA mode. - * @note Step 1 consists in writing the inner hash function key in the IP, + * @note Step 1 consists in writing the inner hash function key in the Peripheral, * step 2 consists in writing the message text. * @note The API carries out the HMAC step 1 then starts step 2 with - * the first buffer entered to the IP. DCAL bit is not automatically set after + * the first buffer entered to the Peripheral. DCAL bit is not automatically set after * the message buffer feeding, allowing other messages DMA transfers to occur. * @note Same key is used for the inner and the outer hash functions; pointer to key and * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the * HASH digest computation is corrupted. - * @param hhash: HASH handle. - * @param pInBuffer: pointer to the input buffer (message buffer). - * @param Size: length of the input buffer in bytes. + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (message buffer). + * @param Size length of the input buffer in bytes. * @retval HAL status */ HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) @@ -848,7 +962,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8 /** * @brief SHA256 HMAC step 2 in multi-buffer DMA mode. - * @note Step 2 consists in writing the message text in the IP. + * @note Step 2 consists in writing the message text in the Peripheral. * @note The API carries on the HMAC step 2, applied to the buffer entered as input * parameter. DCAL bit is not automatically set after the message buffer feeding, * allowing other messages DMA transfers to occur. @@ -856,9 +970,9 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8 * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the * HASH digest computation is corrupted. - * @param hhash: HASH handle. - * @param pInBuffer: pointer to the input buffer (message buffer). - * @param Size: length of the input buffer in bytes. + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (message buffer). + * @param Size length of the input buffer in bytes. * @retval HAL status */ HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) @@ -872,7 +986,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t /** * @brief SHA256 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode. - * @note Step 2 consists in writing the message text in the IP, + * @note Step 2 consists in writing the message text in the Peripheral, * step 3 consists in writing the outer hash function key. * @note The API wraps up the HMAC step 2 in processing the buffer entered as input * parameter (the input buffer must be the last one of the multi-buffer thread) @@ -882,9 +996,9 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t * @note Once the DMA transfers are finished (indicated by hhash->State set back * to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve * the computed digest. - * @param hhash: HASH handle. - * @param pInBuffer: pointer to the input buffer (message buffer). - * @param Size: length of the input buffer in bytes. + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (message buffer). + * @param Size length of the input buffer in bytes. * @retval HAL status */ HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_hcd.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_hcd.c index 92a6277ed1..735d7d188b 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_hcd.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_hcd.c @@ -42,11 +42,7 @@ ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2017 STMicroelectronics

    - * - * @attention - * - *

    © Copyright (c) YYYY STMicroelectronics. + *

    © Copyright (c) 2017 STMicroelectronics. * All rights reserved.

    * * This software component is licensed by ST under BSD 3-Clause license, @@ -114,6 +110,8 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd); */ HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd) { + USB_OTG_GlobalTypeDef *USBx; + /* Check the HCD handle allocation */ if (hhcd == NULL) { @@ -123,6 +121,8 @@ HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd) /* Check the parameters */ assert_param(IS_HCD_ALL_INSTANCE(hhcd->Instance)); + USBx = hhcd->Instance; + if (hhcd->State == HAL_HCD_STATE_RESET) { /* Allocate lock resource and initialize it */ @@ -151,6 +151,12 @@ HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd) hhcd->State = HAL_HCD_STATE_BUSY; + /* Disable DMA mode for FS instance */ + if ((USBx->CID & (0x1U << 8)) == 0U) + { + hhcd->Init.dma_enable = 0U; + } + /* Disable the Interrupts */ __HAL_HCD_DISABLE(hhcd); @@ -367,14 +373,13 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, uint16_t length, uint8_t do_ping) { - UNUSED(do_ping); - hhcd->hc[ch_num].ep_is_in = direction; hhcd->hc[ch_num].ep_type = ep_type; if (token == 0U) { hhcd->hc[ch_num].data_pid = HC_PID_SETUP; + hhcd->hc[ch_num].do_ping = do_ping; } else { @@ -528,20 +533,19 @@ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd) /* Handle Host Disconnect Interrupts */ if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT)) { + __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT); - /* Cleanup HPRT */ - USBx_HPRT0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | \ - USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG); - - /* Handle Host Port Disconnect Interrupt */ + if ((USBx_HPRT0 & USB_OTG_HPRT_PCSTS) == 0U) + { + /* Handle Host Port Disconnect Interrupt */ #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) - hhcd->DisconnectCallback(hhcd); + hhcd->DisconnectCallback(hhcd); #else - HAL_HCD_Disconnect_Callback(hhcd); + HAL_HCD_Disconnect_Callback(hhcd); #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ - (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ); - __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT); + (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ); + } } /* Handle Host Port Interrupts */ @@ -1003,6 +1007,7 @@ HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd) __HAL_HCD_ENABLE(hhcd); (void)USB_DriveVbus(hhcd->Instance, 1U); __HAL_UNLOCK(hhcd); + return HAL_OK; } @@ -1017,6 +1022,7 @@ HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd) __HAL_LOCK(hhcd); (void)USB_StopHost(hhcd->Instance); __HAL_UNLOCK(hhcd); + return HAL_OK; } @@ -1164,6 +1170,13 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_AHBERR); __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); } + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_BBERR) == USB_OTG_HCINT_BBERR) + { + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_BBERR); + hhcd->hc[ch_num].state = HC_BBLERR; + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + } else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_ACK) == USB_OTG_HCINT_ACK) { __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_ACK); @@ -1219,6 +1232,17 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) USBx_HC(ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM; hhcd->hc[ch_num].urb_state = URB_DONE; +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); +#else + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + } + else if (hhcd->hc[ch_num].ep_type == EP_TYPE_ISOC) + { + hhcd->hc[ch_num].urb_state = URB_DONE; + hhcd->hc[ch_num].toggle_in ^= 1U; + #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); #else @@ -1273,6 +1297,11 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) tmpreg |= USB_OTG_HCCHAR_CHENA; USBx_HC(ch_num)->HCCHAR = tmpreg; } + else if (hhcd->hc[ch_num].state == HC_BBLERR) + { + hhcd->hc[ch_num].ErrCnt++; + hhcd->hc[ch_num].urb_state = URB_ERROR; + } else { /* ... */ @@ -1300,6 +1329,7 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) (hhcd->hc[ch_num].ep_type == EP_TYPE_BULK)) { hhcd->hc[ch_num].ErrCnt = 0U; + if (hhcd->Init.dma_enable == 0U) { hhcd->hc[ch_num].state = HC_NAK; @@ -1548,8 +1578,6 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd) { if ((hprt0 & USB_OTG_HPRT_PCSTS) == USB_OTG_HPRT_PCSTS) { - USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_DISCINT); - #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) hhcd->ConnectCallback(hhcd); #else @@ -1586,10 +1614,8 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd) } #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) hhcd->PortEnabledCallback(hhcd); - hhcd->ConnectCallback(hhcd); #else HAL_HCD_PortEnabled_Callback(hhcd); - HAL_HCD_Connect_Callback(hhcd); #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ } @@ -1600,12 +1626,6 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd) #else HAL_HCD_PortDisabled_Callback(hhcd); #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ - - /* Cleanup HPRT */ - USBx_HPRT0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | \ - USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG); - - USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_DISCINT); } } diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c index d74bb1dd4a..4b3cee4d7e 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c @@ -223,12 +223,12 @@ *** Callback registration *** ============================================= - + [..] The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. Use Functions @ref HAL_I2C_RegisterCallback() or @ref HAL_I2C_RegisterAddrCallback() to register an interrupt callback. - + [..] Function @ref HAL_I2C_RegisterCallback() allows to register following callbacks: (+) MasterTxCpltCallback : callback for Master transmission end of transfer. (+) MasterRxCpltCallback : callback for Master reception end of transfer. @@ -243,9 +243,9 @@ (+) MspDeInitCallback : callback for Msp DeInit. This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. - + [..] For specific callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_RegisterAddrCallback(). - + [..] Use function @ref HAL_I2C_UnRegisterCallback to reset a callback to the default weak function. @ref HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle, @@ -262,9 +262,9 @@ (+) AbortCpltCallback : callback for abort completion process. (+) MspInitCallback : callback for Msp Init. (+) MspDeInitCallback : callback for Msp DeInit. - + [..] For callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_UnRegisterAddrCallback(). - + [..] By default, after the @ref HAL_I2C_Init() and when the state is @ref HAL_I2C_STATE_RESET all callbacks are set to the corresponding weak functions: examples @ref HAL_I2C_MasterTxCpltCallback(), @ref HAL_I2C_MasterRxCpltCallback(). @@ -273,7 +273,7 @@ these callbacks are null (not registered beforehand). If MspInit or MspDeInit are not null, the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. - + [..] Callbacks can be registered/unregistered in @ref HAL_I2C_STATE_READY state only. Exception done MspInit/MspDeInit functions that can be registered/unregistered in @ref HAL_I2C_STATE_READY or @ref HAL_I2C_STATE_RESET state, @@ -281,7 +281,7 @@ Then, the user first registers the MspInit/MspDeInit user callbacks using @ref HAL_I2C_RegisterCallback() before calling @ref HAL_I2C_DeInit() or @ref HAL_I2C_Init() function. - + [..] When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available and all callbacks are set to the corresponding weak functions. @@ -4737,6 +4737,13 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint /* Process locked */ __HAL_LOCK(hi2c); + /* Check if STOPF is set */ + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Slave complete process */ + I2C_ITSlaveCplt(hi2c, tmpITFlags); + } + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) { /* Check that I2C transfer finished */ @@ -4788,9 +4795,6 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint { if (hi2c->XferCount > 0U) { - /* Remove RXNE flag on temporary variable as read done */ - tmpITFlags &= ~I2C_FLAG_RXNE; - /* Read data from RXDR */ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; @@ -4844,13 +4848,6 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint /* Nothing to do */ } - /* Check if STOPF is set */ - if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) - { - /* Call I2C Slave complete process */ - I2C_ITSlaveCplt(hi2c, tmpITFlags); - } - /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -5008,6 +5005,13 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin /* Process locked */ __HAL_LOCK(hi2c); + /* Check if STOPF is set */ + if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Slave complete process */ + I2C_ITSlaveCplt(hi2c, ITFlags); + } + if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) { /* Check that I2C transfer finished */ @@ -5092,11 +5096,6 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin { I2C_ITAddrCplt(hi2c, ITFlags); } - else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) - { - /* Call I2C Slave complete process */ - I2C_ITSlaveCplt(hi2c, ITFlags); - } else { /* Nothing to do */ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_irda.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_irda.c index e79476fbc7..03675cbd76 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_irda.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_irda.c @@ -206,7 +206,7 @@ #define IRDA_TEACK_REACK_TIMEOUT 1000U /*!< IRDA TX or RX enable acknowledge time-out value */ #define IRDA_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE \ - | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE)) /*!< UART or USART CR1 fields of parameters set by IRDA_SetConfig API */ + | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE)) /*!< UART or USART CR1 fields of parameters set by IRDA_SetConfig API */ #define USART_BRR_MIN 0x10U /*!< USART BRR minimum authorized value */ @@ -239,7 +239,8 @@ void IRDA_InitCallbacksToDefault(IRDA_HandleTypeDef *hirda); #endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda); static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda); -static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout); +static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout); static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda); static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda); static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma); @@ -475,7 +476,8 @@ __weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda) * @param pCallback pointer to the Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID, pIRDA_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID, + pIRDA_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -714,6 +716,7 @@ HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRD While receiving data, transmission should be avoided as the data to be transmitted could be corrupted. + [..] (#) There are two modes of transfer: (++) Blocking mode: the communication is performed in polling mode. The HAL status of all data processing is returned by the same function @@ -751,28 +754,28 @@ HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRD (++) HAL_IRDA_ErrorCallback() (#) Non-Blocking mode transfers could be aborted using Abort API's : - (+) HAL_IRDA_Abort() - (+) HAL_IRDA_AbortTransmit() - (+) HAL_IRDA_AbortReceive() - (+) HAL_IRDA_Abort_IT() - (+) HAL_IRDA_AbortTransmit_IT() - (+) HAL_IRDA_AbortReceive_IT() + (++) HAL_IRDA_Abort() + (++) HAL_IRDA_AbortTransmit() + (++) HAL_IRDA_AbortReceive() + (++) HAL_IRDA_Abort_IT() + (++) HAL_IRDA_AbortTransmit_IT() + (++) HAL_IRDA_AbortReceive_IT() (#) For Abort services based on interrupts (HAL_IRDA_Abortxxx_IT), a set of Abort Complete Callbacks are provided: - (+) HAL_IRDA_AbortCpltCallback() - (+) HAL_IRDA_AbortTransmitCpltCallback() - (+) HAL_IRDA_AbortReceiveCpltCallback() + (++) HAL_IRDA_AbortCpltCallback() + (++) HAL_IRDA_AbortTransmitCpltCallback() + (++) HAL_IRDA_AbortReceiveCpltCallback() (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. Errors are handled as follows : - (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is - to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception . - Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type, - and HAL_IRDA_ErrorCallback() user callback is executed. Transfer is kept ongoing on IRDA side. - If user wants to abort it, Abort services should be called by user. - (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted. - This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. - Error code is set to allow user to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed. + (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is + to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception . + Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type, + and HAL_IRDA_ErrorCallback() user callback is executed. Transfer is kept ongoing on IRDA side. + If user wants to abort it, Abort services should be called by user. + (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted. + This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. + Error code is set to allow user to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed. @endverbatim * @{ @@ -780,10 +783,13 @@ HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRD /** * @brief Send an amount of data in blocking mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must reflect the number + * of u16 available through pData. * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. - * @param pData Pointer to data buffer. - * @param Size Amount of data to be sent. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent. * @param Timeout Specify timeout value. * @retval HAL status */ @@ -866,10 +872,13 @@ HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, u /** * @brief Receive an amount of data in blocking mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must reflect the number + * of u16 available through pData. * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. - * @param pData Pointer to data buffer. - * @param Size Amount of data to be received. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. * @param Timeout Specify timeout value. * @retval HAL status */ @@ -954,10 +963,13 @@ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, ui /** * @brief Send an amount of data in interrupt mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must reflect the number + * of u16 available through pData. * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. - * @param pData Pointer to data buffer. - * @param Size Amount of data to be sent. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent. * @retval HAL status */ HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) @@ -996,10 +1008,13 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData /** * @brief Receive an amount of data in interrupt mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must reflect the number + * of u16 available through pData. * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. - * @param pData Pointer to data buffer. - * @param Size Amount of data to be received. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. * @retval HAL status */ HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) @@ -1045,10 +1060,13 @@ HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, /** * @brief Send an amount of data in DMA mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must reflect the number + * of u16 available through pData. * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. - * @param pData pointer to data buffer. - * @param Size amount of data to be sent. + * @param pData pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent. * @retval HAL status */ HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) @@ -1120,12 +1138,15 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pDat /** * @brief Receive an amount of data in DMA mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must reflect the number + * of u16 available through pData. * @note When the IRDA parity is enabled (PCE = 1), the received data contains * the parity bit (MSB position). * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. - * @param pData Pointer to data buffer. - * @param Size Amount of data to be received. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. * @retval HAL status */ HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) @@ -1353,7 +1374,7 @@ HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda) * - Set handle State to READY * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda) { /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ @@ -1439,7 +1460,7 @@ HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda) * - Set handle State to READY * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda) { /* Disable TXEIE and TCIE interrupts */ @@ -1491,7 +1512,7 @@ HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda) * - Set handle State to READY * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda) { /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ @@ -1549,7 +1570,7 @@ HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda) * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be * considered as completed only when user abort complete callback is executed (not when exiting function). * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda) { uint32_t abortcplt = 1U; @@ -1681,7 +1702,7 @@ HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda) * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be * considered as completed only when user abort complete callback is executed (not when exiting function). * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda) { /* Disable TXEIE and TCIE interrupts */ @@ -1759,7 +1780,7 @@ HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda) * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be * considered as completed only when user abort complete callback is executed (not when exiting function). * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda) { /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ @@ -2150,7 +2171,8 @@ __weak void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda) HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda) { /* Return IRDA handle state */ - uint32_t temp1, temp2; + uint32_t temp1; + uint32_t temp2; temp1 = (uint32_t)hirda->gState; temp2 = (uint32_t)hirda->RxState; @@ -2212,6 +2234,7 @@ static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda) uint32_t tmpreg; IRDA_ClockSourceTypeDef clocksource; HAL_StatusTypeDef ret = HAL_OK; + uint32_t pclk; /* Check the communication parameters */ assert_param(IS_IRDA_BAUDRATE(hirda->Init.BaudRate)); @@ -2235,7 +2258,7 @@ static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda) /*-------------------------- USART GTPR Configuration ----------------------*/ - MODIFY_REG(hirda->Instance->GTPR, (uint16_t)USART_GTPR_PSC, hirda->Init.Prescaler); + MODIFY_REG(hirda->Instance->GTPR, (uint16_t)USART_GTPR_PSC, (uint16_t)hirda->Init.Prescaler); /*-------------------------- USART BRR Configuration -----------------------*/ IRDA_GETCLOCKSOURCE(hirda, clocksource); @@ -2243,16 +2266,19 @@ static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda) switch (clocksource) { case IRDA_CLOCKSOURCE_PCLK1: - tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), hirda->Init.BaudRate)); + pclk = HAL_RCC_GetPCLK1Freq(); + tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate)); break; case IRDA_CLOCKSOURCE_PCLK2: - tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), hirda->Init.BaudRate)); + pclk = HAL_RCC_GetPCLK2Freq(); + tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate)); break; case IRDA_CLOCKSOURCE_HSI: tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(HSI_VALUE, hirda->Init.BaudRate)); break; case IRDA_CLOCKSOURCE_SYSCLK: - tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), hirda->Init.BaudRate)); + pclk = HAL_RCC_GetSysClockFreq(); + tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate)); break; case IRDA_CLOCKSOURCE_LSE: tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16((uint32_t)LSE_VALUE, hirda->Init.BaudRate)); @@ -2322,7 +2348,8 @@ static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda) * @param Timeout Timeout duration * @retval HAL status */ -static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) +static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout) { /* Wait until flag is set */ while ((__HAL_IRDA_GET_FLAG(hirda, Flag) ? SET : RESET) == Status) diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_lptim.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_lptim.c index 1decaa97d4..09fed9a68f 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_lptim.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_lptim.c @@ -20,62 +20,62 @@ (#)Initialize the LPTIM low level resources by implementing the HAL_LPTIM_MspInit(): - (##) Enable the LPTIM interface clock using __LPTIMx_CLK_ENABLE(). - (##) In case of using interrupts (e.g. HAL_LPTIM_PWM_Start_IT()): + (++) Enable the LPTIM interface clock using __HAL_RCC_LPTIMx_CLK_ENABLE(). + (++) In case of using interrupts (e.g. HAL_LPTIM_PWM_Start_IT()): (+++) Configure the LPTIM interrupt priority using HAL_NVIC_SetPriority(). (+++) Enable the LPTIM IRQ handler using HAL_NVIC_EnableIRQ(). (+++) In LPTIM IRQ handler, call HAL_LPTIM_IRQHandler(). (#)Initialize the LPTIM HAL using HAL_LPTIM_Init(). This function configures mainly: - (##) The instance: LPTIM1. - (##) Clock: the counter clock. - (+++) Source: it can be either the ULPTIM input (IN1) or one of + (++) The instance: LPTIM1. + (++) Clock: the counter clock. + (+++) Source : it can be either the ULPTIM input (IN1) or one of the internal clock; (APB, LSE, LSI or MSI). - (+++) Prescaler: select the clock divider. - (##) UltraLowPowerClock : To be used only if the ULPTIM is selected + (+++) Prescaler: select the clock divider. + (++) UltraLowPowerClock : To be used only if the ULPTIM is selected as counter clock source. - (+++) Polarity: polarity of the active edge for the counter unit + (+++) Polarity: polarity of the active edge for the counter unit if the ULPTIM input is selected. - (+++) SampleTime: clock sampling time to configure the clock glitch + (+++) SampleTime: clock sampling time to configure the clock glitch filter. - (##) Trigger: How the counter start. - (+++) Source: trigger can be software or one of the hardware triggers. - (+++) ActiveEdge: only for hardware trigger. - (+++) SampleTime: trigger sampling time to configure the trigger + (++) Trigger: How the counter start. + (+++) Source: trigger can be software or one of the hardware triggers. + (+++) ActiveEdge : only for hardware trigger. + (+++) SampleTime : trigger sampling time to configure the trigger glitch filter. - (##) OutputPolarity: 2 opposite polarities are possibles. - (##) UpdateMode: specifies whether the update of the autoreload and + (++) OutputPolarity : 2 opposite polarities are possible. + (++) UpdateMode: specifies whether the update of the autoreload and the compare values is done immediately or after the end of current period. (#)Six modes are available: - (##) PWM Mode: To generate a PWM signal with specified period and pulse, + (++) PWM Mode: To generate a PWM signal with specified period and pulse, call HAL_LPTIM_PWM_Start() or HAL_LPTIM_PWM_Start_IT() for interruption mode. - (##) One Pulse Mode: To generate pulse with specified width in response + (++) One Pulse Mode: To generate pulse with specified width in response to a stimulus, call HAL_LPTIM_OnePulse_Start() or HAL_LPTIM_OnePulse_Start_IT() for interruption mode. - (##) Set once Mode: In this mode, the output changes the level (from + (++) Set once Mode: In this mode, the output changes the level (from low level to high level if the output polarity is configured high, else the opposite) when a compare match occurs. To start this mode, call HAL_LPTIM_SetOnce_Start() or HAL_LPTIM_SetOnce_Start_IT() for interruption mode. - (##) Encoder Mode: To use the encoder interface call + (++) Encoder Mode: To use the encoder interface call HAL_LPTIM_Encoder_Start() or HAL_LPTIM_Encoder_Start_IT() for - interruption mode. + interruption mode. Only available for LPTIM1 instance. - (##) Time out Mode: an active edge on one selected trigger input rests + (++) Time out Mode: an active edge on one selected trigger input rests the counter. The first trigger event will start the timer, any successive trigger event will reset the counter and the timer will restart. To start this mode call HAL_LPTIM_TimeOut_Start_IT() or HAL_LPTIM_TimeOut_Start_IT() for interruption mode. - (##) Counter Mode: counter can be used to count external events on + (++) Counter Mode: counter can be used to count external events on the LPTIM Input1 or it can be used to count internal clock cycles. To start this mode, call HAL_LPTIM_Counter_Start() or HAL_LPTIM_Counter_Start_IT() for interruption mode. @@ -85,51 +85,55 @@ HAL_LPTIM_Xxx_Stop() or HAL_LPTIM_Xxx_Stop_IT() if the process is already started in interruption mode. - (#) Call HAL_LPTIM_DeInit() to deinitialize the LPTIM peripheral. + (#) De-initialize the LPTIM peripheral using HAL_LPTIM_DeInit(). - *** Callback registration *** + *** Callback registration *** ============================================= - - The compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS when set to 1 + [..] + The compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - + [..] Use Function @ref HAL_LPTIM_RegisterCallback() to register a callback. @ref HAL_LPTIM_RegisterCallback() takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. - - Use function @ref HAL_LPTIM_UnRegisterCallback() to reset a callback to the default - weak function. + [..] + Use function @ref HAL_LPTIM_UnRegisterCallback() to reset a callback to the + default weak function. @ref HAL_LPTIM_UnRegisterCallback takes as parameters the HAL peripheral handle, and the Callback ID. - + [..] These functions allow to register/unregister following callbacks: - (+) MspInitCallback : LPTIM Msp Init Callback. - (+) MspDeInitCallback : LPTIM Msp DeInit Callback. - (+) CompareMatchCallback : LPTIM Compare Match Init Callback. - (+) AutoReloadMatchCallback : LPTIM Auto Reload Match Callback. - (+) TriggerCallback : LPTIM Trigger Callback. - (+) CompareWriteCallback : LPTIM Compare Write Callback. - (+) AutoReloadWriteCallback : LPTIM Auto Reload Write Callback. - (+) DirectionUpCallback : LPTIM Direction Up Callback. - (+) DirectionDownCallback : LPTIM Direction Down Callback. - - By default, after the @ref HAL_LPTIM_Init and when the state is HAL_LPTIM_STATE_RESET + + (+) MspInitCallback : LPTIM Base Msp Init Callback. + (+) MspDeInitCallback : LPTIM Base Msp DeInit Callback. + (+) CompareMatchCallback : Compare match Callback. + (+) AutoReloadMatchCallback : Auto-reload match Callback. + (+) TriggerCallback : External trigger event detection Callback. + (+) CompareWriteCallback : Compare register write complete Callback. + (+) AutoReloadWriteCallback : Auto-reload register write complete Callback. + (+) DirectionUpCallback : Up-counting direction change Callback. + (+) DirectionDownCallback : Down-counting direction change Callback. + + [..] + By default, after the Init and when the state is HAL_LPTIM_STATE_RESET all interrupt callbacks are set to the corresponding weak functions: - examples @ref HAL_LPTIM_CompareMatchCallback(), @ref HAL_LPTIM_AutoReloadMatchCallback(). + examples @ref HAL_LPTIM_TriggerCallback(), @ref HAL_LPTIM_CompareMatchCallback(). + [..] Exception done for MspInit and MspDeInit functions that are reset to the legacy weak - functionalities in the @ref HAL_LPTIM_Init/@ref HAL_LPTIM_DeInit only when these - callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, - the @ref HAL_LPTIM_Init/@ref HAL_LPTIM_DeInit keep and use the user MspInit/MspDeInit - callbacks (registered beforehand) + functionalities in the Init/DeInit only when these callbacks are null + (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init/DeInit + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) + [..] Callbacks can be registered/unregistered in HAL_LPTIM_STATE_READY state only. Exception done MspInit/MspDeInit that can be registered/unregistered - in HAL_LPTIM_STATE_READY or HAL_LPTIM_STATE_RESET state, thus registered (user) - MspInit/DeInit callbacks can be used during the @ref HAL_LPTIM_Init/@ref HAL_LPTIM_DeInit. - In that case first register the MspInit/MspDeInit user callbacks using - @ref HAL_LPTIM_RegisterCallback() before calling DeInit or Init function. + in HAL_LPTIM_STATE_READY or HAL_LPTIM_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using @ref HAL_LPTIM_RegisterCallback() before calling DeInit or Init function. + [..] When The compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available and all callbacks are set to the corresponding weak functions. @@ -162,75 +166,34 @@ */ #ifdef HAL_LPTIM_MODULE_ENABLED -/* Private types -------------------------------------------------------------*/ -/** @defgroup LPTIM_Private_Types LPTIM Private Types - * @{ - */ -/** - * @} - */ +#if defined (LPTIM1) -/* Private defines -----------------------------------------------------------*/ -/** @defgroup LPTIM_Private_Defines LPTIM Private Defines +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup LPTIM_Private_Constants * @{ */ - +#define TIMEOUT 1000UL /* Timeout is 1s */ /** * @} */ +/* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ -/** @addtogroup LPTIM_Private_Variables LPTIM Private Variables - * @{ - */ - -/** - * @} - */ - -/* Private constants ---------------------------------------------------------*/ -/** @addtogroup LPTIM_Private_Constants LPTIM Private Constants - * @{ - */ - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @addtogroup LPTIM_Private_Macros LPTIM Private Macros - * @{ - */ - -/** - * @} - */ - /* Private function prototypes -----------------------------------------------*/ -/** @addtogroup LPTIM_Private_Functions_Prototypes LPTIM Private Functions Prototypes - * @{ - */ - -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ -/** @addtogroup LPTIM_Private_Functions LPTIM Private Functions - * @{ - */ +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) +static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ +static HAL_StatusTypeDef LPTIM_WaitForFlag(LPTIM_HandleTypeDef *hlptim, uint32_t flag); -/** - * @} - */ +/* Exported functions --------------------------------------------------------*/ -/* Exported functions ---------------------------------------------------------*/ /** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions * @{ */ -/** @defgroup LPTIM_Group1 Initialization/de-initialization functions +/** @defgroup LPTIM_Exported_Functions_Group1 Initialization/de-initialization functions * @brief Initialization and Configuration functions. * @verbatim @@ -239,27 +202,27 @@ ============================================================================== [..] This section provides functions allowing to: (+) Initialize the LPTIM according to the specified parameters in the - LPTIM_InitTypeDef and creates the associated handle. + LPTIM_InitTypeDef and initialize the associated handle. (+) DeInitialize the LPTIM peripheral. (+) Initialize the LPTIM MSP. - (+) DeInitialize LPTIM MSP. + (+) DeInitialize the LPTIM MSP. @endverbatim * @{ */ /** - * @brief Initializes the LPTIM according to the specified parameters in the - * LPTIM_InitTypeDef and creates the associated handle. + * @brief Initialize the LPTIM according to the specified parameters in the + * LPTIM_InitTypeDef and initialize the associated handle. * @param hlptim LPTIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim) { - uint32_t tmpcfgr = 0; + uint32_t tmpcfgr; /* Check the LPTIM handle allocation */ - if(hlptim == NULL) + if (hlptim == NULL) { return HAL_ERROR; } @@ -269,65 +232,68 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim) assert_param(IS_LPTIM_CLOCK_SOURCE(hlptim->Init.Clock.Source)); assert_param(IS_LPTIM_CLOCK_PRESCALER(hlptim->Init.Clock.Prescaler)); - if ((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM) + if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) { assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity)); - assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime)); } assert_param(IS_LPTIM_TRG_SOURCE(hlptim->Init.Trigger.Source)); - if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) + if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE) { - assert_param(IS_LPTIM_TRIG_SAMPLE_TIME(hlptim->Init.Trigger.SampleTime)); assert_param(IS_LPTIM_EXT_TRG_POLARITY(hlptim->Init.Trigger.ActiveEdge)); } + if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC) + { + assert_param(IS_LPTIM_TRIG_SAMPLE_TIME(hlptim->Init.Trigger.SampleTime)); + assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime)); + } assert_param(IS_LPTIM_OUTPUT_POLARITY(hlptim->Init.OutputPolarity)); assert_param(IS_LPTIM_UPDATE_MODE(hlptim->Init.UpdateMode)); assert_param(IS_LPTIM_COUNTER_SOURCE(hlptim->Init.CounterSource)); - if(hlptim->State == HAL_LPTIM_STATE_RESET) + if (hlptim->State == HAL_LPTIM_STATE_RESET) { /* Allocate lock resource and initialize it */ hlptim->Lock = HAL_UNLOCKED; #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) - /* Reset the LPTIM callback to the legacy weak callbacks */ - hlptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback; - hlptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback; - hlptim->TriggerCallback = HAL_LPTIM_TriggerCallback; - hlptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback; - hlptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback; - hlptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback; - hlptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback; - - if(hlptim->MspInitCallback == NULL) + /* Reset interrupt callbacks to legacy weak callbacks */ + LPTIM_ResetCallback(hlptim); + + if (hlptim->MspInitCallback == NULL) { hlptim->MspInitCallback = HAL_LPTIM_MspInit; } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ hlptim->MspInitCallback(hlptim); #else - /* Init the low level hardware */ + /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_LPTIM_MspInit(hlptim); #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ } + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_BUSY; /* Get the LPTIMx CFGR value */ tmpcfgr = hlptim->Instance->CFGR; - if ((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM) + if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) + { + tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL)); + } + if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE) { - tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL | LPTIM_CFGR_CKFLT)); + tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRIGSEL)); } - if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) + if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC) { - tmpcfgr &= (uint32_t)(~ (LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGSEL)); + tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRGFLT | LPTIM_CFGR_CKFLT)); } - /* Clear CKSEL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */ - tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKSEL | LPTIM_CFGR_TRIGEN | LPTIM_CFGR_PRELOAD | - LPTIM_CFGR_WAVPOL | LPTIM_CFGR_PRESC | LPTIM_CFGR_COUNTMODE )); + /* Clear CKSEL, CKPOL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */ + tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKSEL | LPTIM_CFGR_CKPOL | LPTIM_CFGR_TRIGEN | LPTIM_CFGR_PRELOAD | + LPTIM_CFGR_WAVPOL | LPTIM_CFGR_PRESC | LPTIM_CFGR_COUNTMODE)); /* Set initialization parameters */ tmpcfgr |= (hlptim->Init.Clock.Source | @@ -336,18 +302,28 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim) hlptim->Init.UpdateMode | hlptim->Init.CounterSource); - if ((hlptim->Init.Clock.Source) == LPTIM_CLOCKSOURCE_ULPTIM) + /* Glitch filters for internal triggers and external inputs are configured + * only if an internal clock source is provided to the LPTIM + */ + if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC) { - tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity | + tmpcfgr |= (hlptim->Init.Trigger.SampleTime | hlptim->Init.UltraLowPowerClock.SampleTime); } - if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) + /* Configure the active edge or edges used by the counter only if LPTIM is + * clocked by an external clock source + */ + if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) + { + tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity); + } + + if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE) { /* Enable External trigger and set the trigger source */ - tmpcfgr |= (hlptim->Init.Trigger.Source | - hlptim->Init.Trigger.ActiveEdge | - hlptim->Init.Trigger.SampleTime); + tmpcfgr |= (hlptim->Init.Trigger.Source | + hlptim->Init.Trigger.ActiveEdge); } /* Write to LPTIMx CFGR */ @@ -361,14 +337,14 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim) } /** - * @brief DeInitializes the LPTIM peripheral. + * @brief DeInitialize the LPTIM peripheral. * @param hlptim LPTIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim) { /* Check the LPTIM handle allocation */ - if(hlptim == NULL) + if (hlptim == NULL) { return HAL_ERROR; } @@ -379,12 +355,18 @@ HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim) /* Disable the LPTIM Peripheral Clock */ __HAL_LPTIM_DISABLE(hlptim); + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) - if(hlptim->MspDeInitCallback == NULL) + if (hlptim->MspDeInitCallback == NULL) { hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit; } - /* DeInit the low level hardware */ + + /* DeInit the low level hardware: CLOCK, NVIC.*/ hlptim->MspDeInitCallback(hlptim); #else /* DeInit the low level hardware: CLOCK, NVIC.*/ @@ -402,7 +384,7 @@ HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim) } /** - * @brief Initializes the LPTIM MSP. + * @brief Initialize the LPTIM MSP. * @param hlptim LPTIM handle * @retval None */ @@ -411,13 +393,13 @@ __weak void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim) /* Prevent unused argument(s) compilation warning */ UNUSED(hlptim); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_LPTIM_MspInit could be implemented in the user file */ } /** - * @brief DeInitializes LPTIM MSP. + * @brief DeInitialize LPTIM MSP. * @param hlptim LPTIM handle * @retval None */ @@ -426,7 +408,7 @@ __weak void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim) /* Prevent unused argument(s) compilation warning */ UNUSED(hlptim); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_LPTIM_MspDeInit could be implemented in the user file */ } @@ -435,7 +417,7 @@ __weak void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim) * @} */ -/** @defgroup LPTIM_Group2 LPTIM Start-Stop operation functions +/** @defgroup LPTIM_Exported_Functions_Group2 LPTIM Start-Stop operation functions * @brief Start-Stop operation functions. * @verbatim @@ -462,11 +444,11 @@ __weak void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim) */ /** - * @brief Starts the LPTIM PWM generation. - * @param hlptim LPTIM handle - * @param Period Specifies the Autoreload value. + * @brief Start the LPTIM PWM generation. + * @param hlptim LPTIM handle + * @param Period Specifies the Autoreload value. * This parameter must be a value between 0x0000 and 0xFFFF. - * @param Pulse Specifies the compare value. + * @param Pulse Specifies the compare value. * This parameter must be a value between 0x0000 and 0xFFFF. * @retval HAL status */ @@ -478,7 +460,7 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Peri assert_param(IS_LPTIM_PULSE(Pulse)); /* Set the LPTIM state */ - hlptim->State= HAL_LPTIM_STATE_BUSY; + hlptim->State = HAL_LPTIM_STATE_BUSY; /* Reset WAVE bit to set PWM mode */ hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE; @@ -486,25 +468,43 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Peri /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); + /* Load the period value in the autoreload register */ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); + /* Wait for the completion of the write operation to the LPTIM_ARR register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK); + /* Load the pulse value in the compare register */ __HAL_LPTIM_COMPARE_SET(hlptim, Pulse); + /* Wait for the completion of the write operation to the LPTIM_CMP register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); /* Change the TIM state*/ - hlptim->State= HAL_LPTIM_STATE_READY; + hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ return HAL_OK; } /** - * @brief Stops the LPTIM PWM generation. - * @param hlptim LPTIM handle + * @brief Stop the LPTIM PWM generation. + * @param hlptim LPTIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim) @@ -513,24 +513,29 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim) assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); /* Set the LPTIM state */ - hlptim->State= HAL_LPTIM_STATE_BUSY; + hlptim->State = HAL_LPTIM_STATE_BUSY; /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Change the TIM state*/ - hlptim->State= HAL_LPTIM_STATE_READY; + hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ return HAL_OK; } /** - * @brief Starts the LPTIM PWM generation in interrupt mode. - * @param hlptim LPTIM handle - * @param Period Specifies the Autoreload value. + * @brief Start the LPTIM PWM generation in interrupt mode. + * @param hlptim LPTIM handle + * @param Period Specifies the Autoreload value. * This parameter must be a value between 0x0000 and 0xFFFF - * @param Pulse Specifies the compare value. + * @param Pulse Specifies the compare value. * This parameter must be a value between 0x0000 and 0xFFFF * @retval HAL status */ @@ -542,11 +547,46 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t P assert_param(IS_LPTIM_PULSE(Pulse)); /* Set the LPTIM state */ - hlptim->State= HAL_LPTIM_STATE_BUSY; + hlptim->State = HAL_LPTIM_STATE_BUSY; /* Reset WAVE bit to set PWM mode */ hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE; + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); + + /* Load the period value in the autoreload register */ + __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); + + /* Wait for the completion of the write operation to the LPTIM_ARR register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK); + + /* Load the pulse value in the compare register */ + __HAL_LPTIM_COMPARE_SET(hlptim, Pulse); + + /* Wait for the completion of the write operation to the LPTIM_CMP register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Enable Autoreload write complete interrupt */ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK); @@ -560,7 +600,7 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t P __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM); /* If external trigger source is used, then enable external trigger interrupt */ - if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) + if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) { /* Enable external trigger interrupt */ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG); @@ -569,25 +609,19 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t P /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); - /* Load the period value in the autoreload register */ - __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); - - /* Load the pulse value in the compare register */ - __HAL_LPTIM_COMPARE_SET(hlptim, Pulse); - /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); /* Change the TIM state*/ - hlptim->State= HAL_LPTIM_STATE_READY; + hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ return HAL_OK; } /** - * @brief Stops the LPTIM PWM generation in interrupt mode. - * @param hlptim LPTIM handle + * @brief Stop the LPTIM PWM generation in interrupt mode. + * @param hlptim LPTIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim) @@ -596,12 +630,17 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim) assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); /* Set the LPTIM state */ - hlptim->State= HAL_LPTIM_STATE_BUSY; + hlptim->State = HAL_LPTIM_STATE_BUSY; /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); - /* Disable Autoreload write complete interrupt */ + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Disable Autoreload write complete interrupt */ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK); /* Disable Compare write complete interrupt */ @@ -614,25 +653,25 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim) __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM); /* If external trigger source is used, then disable external trigger interrupt */ - if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) + if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) { /* Disable external trigger interrupt */ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG); } /* Change the TIM state*/ - hlptim->State= HAL_LPTIM_STATE_READY; + hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ return HAL_OK; } /** - * @brief Starts the LPTIM One pulse generation. - * @param hlptim LPTIM handle - * @param Period Specifies the Autoreload value. + * @brief Start the LPTIM One pulse generation. + * @param hlptim LPTIM handle + * @param Period Specifies the Autoreload value. * This parameter must be a value between 0x0000 and 0xFFFF. - * @param Pulse Specifies the compare value. + * @param Pulse Specifies the compare value. * This parameter must be a value between 0x0000 and 0xFFFF. * @retval HAL status */ @@ -644,7 +683,7 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t assert_param(IS_LPTIM_PULSE(Pulse)); /* Set the LPTIM state */ - hlptim->State= HAL_LPTIM_STATE_BUSY; + hlptim->State = HAL_LPTIM_STATE_BUSY; /* Reset WAVE bit to set one pulse mode */ hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE; @@ -652,25 +691,43 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); + /* Load the period value in the autoreload register */ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); + /* Wait for the completion of the write operation to the LPTIM_ARR register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK); + /* Load the pulse value in the compare register */ __HAL_LPTIM_COMPARE_SET(hlptim, Pulse); - /* Start timer in continuous mode */ + /* Wait for the completion of the write operation to the LPTIM_CMP register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Start timer in single (one shot) mode */ __HAL_LPTIM_START_SINGLE(hlptim); /* Change the TIM state*/ - hlptim->State= HAL_LPTIM_STATE_READY; + hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ return HAL_OK; } /** - * @brief Stops the LPTIM One pulse generation. - * @param hlptim LPTIM handle + * @brief Stop the LPTIM One pulse generation. + * @param hlptim LPTIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim) @@ -679,24 +736,29 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim) assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); /* Set the LPTIM state */ - hlptim->State= HAL_LPTIM_STATE_BUSY; + hlptim->State = HAL_LPTIM_STATE_BUSY; /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Change the TIM state*/ - hlptim->State= HAL_LPTIM_STATE_READY; + hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ return HAL_OK; } /** - * @brief Starts the LPTIM One pulse generation in interrupt mode. - * @param hlptim LPTIM handle - * @param Period Specifies the Autoreload value. + * @brief Start the LPTIM One pulse generation in interrupt mode. + * @param hlptim LPTIM handle + * @param Period Specifies the Autoreload value. * This parameter must be a value between 0x0000 and 0xFFFF. - * @param Pulse Specifies the compare value. + * @param Pulse Specifies the compare value. * This parameter must be a value between 0x0000 and 0xFFFF. * @retval HAL status */ @@ -708,11 +770,46 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint3 assert_param(IS_LPTIM_PULSE(Pulse)); /* Set the LPTIM state */ - hlptim->State= HAL_LPTIM_STATE_BUSY; + hlptim->State = HAL_LPTIM_STATE_BUSY; /* Reset WAVE bit to set one pulse mode */ hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE; + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); + + /* Load the period value in the autoreload register */ + __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); + + /* Wait for the completion of the write operation to the LPTIM_ARR register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK); + + /* Load the pulse value in the compare register */ + __HAL_LPTIM_COMPARE_SET(hlptim, Pulse); + + /* Wait for the completion of the write operation to the LPTIM_CMP register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Enable Autoreload write complete interrupt */ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK); @@ -726,7 +823,7 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint3 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM); /* If external trigger source is used, then enable external trigger interrupt */ - if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) + if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) { /* Enable external trigger interrupt */ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG); @@ -735,25 +832,19 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint3 /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); - /* Load the period value in the autoreload register */ - __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); - - /* Load the pulse value in the compare register */ - __HAL_LPTIM_COMPARE_SET(hlptim, Pulse); - - /* Start timer in continuous mode */ + /* Start timer in single (one shot) mode */ __HAL_LPTIM_START_SINGLE(hlptim); /* Change the TIM state*/ - hlptim->State= HAL_LPTIM_STATE_READY; + hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ return HAL_OK; } /** - * @brief Stops the LPTIM One pulse generation in interrupt mode. - * @param hlptim LPTIM handle + * @brief Stop the LPTIM One pulse generation in interrupt mode. + * @param hlptim LPTIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim) @@ -762,11 +853,16 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim) assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); /* Set the LPTIM state */ - hlptim->State= HAL_LPTIM_STATE_BUSY; + hlptim->State = HAL_LPTIM_STATE_BUSY; /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Disable Autoreload write complete interrupt */ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK); @@ -780,25 +876,25 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim) __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM); /* If external trigger source is used, then disable external trigger interrupt */ - if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) + if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) { /* Disable external trigger interrupt */ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG); } /* Change the TIM state*/ - hlptim->State= HAL_LPTIM_STATE_READY; + hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ return HAL_OK; } /** - * @brief Starts the LPTIM in Set once mode. - * @param hlptim LPTIM handle - * @param Period Specifies the Autoreload value. + * @brief Start the LPTIM in Set once mode. + * @param hlptim LPTIM handle + * @param Period Specifies the Autoreload value. * This parameter must be a value between 0x0000 and 0xFFFF. - * @param Pulse Specifies the compare value. + * @param Pulse Specifies the compare value. * This parameter must be a value between 0x0000 and 0xFFFF. * @retval HAL status */ @@ -810,7 +906,7 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t assert_param(IS_LPTIM_PULSE(Pulse)); /* Set the LPTIM state */ - hlptim->State= HAL_LPTIM_STATE_BUSY; + hlptim->State = HAL_LPTIM_STATE_BUSY; /* Set WAVE bit to enable the set once mode */ hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE; @@ -818,25 +914,43 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); + /* Load the period value in the autoreload register */ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); + /* Wait for the completion of the write operation to the LPTIM_ARR register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK); + /* Load the pulse value in the compare register */ __HAL_LPTIM_COMPARE_SET(hlptim, Pulse); - /* Start timer in continuous mode */ + /* Wait for the completion of the write operation to the LPTIM_CMP register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Start timer in single (one shot) mode */ __HAL_LPTIM_START_SINGLE(hlptim); /* Change the TIM state*/ - hlptim->State= HAL_LPTIM_STATE_READY; + hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ return HAL_OK; } /** - * @brief Stops the LPTIM Set once mode. - * @param hlptim LPTIM handle + * @brief Stop the LPTIM Set once mode. + * @param hlptim LPTIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim) @@ -845,24 +959,29 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim) assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); /* Set the LPTIM state */ - hlptim->State= HAL_LPTIM_STATE_BUSY; + hlptim->State = HAL_LPTIM_STATE_BUSY; /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Change the TIM state*/ - hlptim->State= HAL_LPTIM_STATE_READY; + hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ return HAL_OK; } /** - * @brief Starts the LPTIM Set once mode in interrupt mode. - * @param hlptim LPTIM handle - * @param Period Specifies the Autoreload value. + * @brief Start the LPTIM Set once mode in interrupt mode. + * @param hlptim LPTIM handle + * @param Period Specifies the Autoreload value. * This parameter must be a value between 0x0000 and 0xFFFF. - * @param Pulse Specifies the compare value. + * @param Pulse Specifies the compare value. * This parameter must be a value between 0x0000 and 0xFFFF. * @retval HAL status */ @@ -874,11 +993,46 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 assert_param(IS_LPTIM_PULSE(Pulse)); /* Set the LPTIM state */ - hlptim->State= HAL_LPTIM_STATE_BUSY; + hlptim->State = HAL_LPTIM_STATE_BUSY; /* Set WAVE bit to enable the set once mode */ hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE; + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); + + /* Load the period value in the autoreload register */ + __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); + + /* Wait for the completion of the write operation to the LPTIM_ARR register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK); + + /* Load the pulse value in the compare register */ + __HAL_LPTIM_COMPARE_SET(hlptim, Pulse); + + /* Wait for the completion of the write operation to the LPTIM_CMP register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Enable Autoreload write complete interrupt */ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK); @@ -892,7 +1046,7 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM); /* If external trigger source is used, then enable external trigger interrupt */ - if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) + if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) { /* Enable external trigger interrupt */ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG); @@ -901,25 +1055,19 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); - /* Load the period value in the autoreload register */ - __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); - - /* Load the pulse value in the compare register */ - __HAL_LPTIM_COMPARE_SET(hlptim, Pulse); - - /* Start timer in continuous mode */ + /* Start timer in single (one shot) mode */ __HAL_LPTIM_START_SINGLE(hlptim); /* Change the TIM state*/ - hlptim->State= HAL_LPTIM_STATE_READY; + hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ return HAL_OK; } /** - * @brief Stops the LPTIM Set once mode in interrupt mode. - * @param hlptim LPTIM handle + * @brief Stop the LPTIM Set once mode in interrupt mode. + * @param hlptim LPTIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim) @@ -928,11 +1076,16 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim) assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); /* Set the LPTIM state */ - hlptim->State= HAL_LPTIM_STATE_BUSY; + hlptim->State = HAL_LPTIM_STATE_BUSY; /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Disable Autoreload write complete interrupt */ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK); @@ -946,29 +1099,29 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim) __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM); /* If external trigger source is used, then disable external trigger interrupt */ - if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) + if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) { /* Disable external trigger interrupt */ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG); } /* Change the TIM state*/ - hlptim->State= HAL_LPTIM_STATE_READY; + hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ return HAL_OK; } /** - * @brief Starts the Encoder interface. - * @param hlptim LPTIM handle - * @param Period Specifies the Autoreload value. + * @brief Start the Encoder interface. + * @param hlptim LPTIM handle + * @param Period Specifies the Autoreload value. * This parameter must be a value between 0x0000 and 0xFFFF. * @retval HAL status */ HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period) { - uint32_t tmpcfgr = 0; + uint32_t tmpcfgr; /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); @@ -978,7 +1131,7 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity)); /* Set the LPTIM state */ - hlptim->State= HAL_LPTIM_STATE_BUSY; + hlptim->State = HAL_LPTIM_STATE_BUSY; /* Get the LPTIMx CFGR value */ tmpcfgr = hlptim->Instance->CFGR; @@ -998,22 +1151,31 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); + /* Load the period value in the autoreload register */ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); + /* Wait for the completion of the write operation to the LPTIM_ARR register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); /* Change the TIM state*/ - hlptim->State= HAL_LPTIM_STATE_READY; + hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ return HAL_OK; } /** - * @brief Stops the Encoder interface. - * @param hlptim LPTIM handle + * @brief Stop the Encoder interface. + * @param hlptim LPTIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim) @@ -1022,31 +1184,36 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim) assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); /* Set the LPTIM state */ - hlptim->State= HAL_LPTIM_STATE_BUSY; + hlptim->State = HAL_LPTIM_STATE_BUSY; /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Reset ENC bit to disable the encoder interface */ hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC; /* Change the TIM state*/ - hlptim->State= HAL_LPTIM_STATE_READY; + hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ return HAL_OK; } /** - * @brief Starts the Encoder interface in interrupt mode. - * @param hlptim LPTIM handle - * @param Period Specifies the Autoreload value. + * @brief Start the Encoder interface in interrupt mode. + * @param hlptim LPTIM handle + * @param Period Specifies the Autoreload value. * This parameter must be a value between 0x0000 and 0xFFFF. * @retval HAL status */ HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period) { - uint32_t tmpcfgr = 0; + uint32_t tmpcfgr; /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); @@ -1056,7 +1223,7 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity)); /* Set the LPTIM state */ - hlptim->State= HAL_LPTIM_STATE_BUSY; + hlptim->State = HAL_LPTIM_STATE_BUSY; /* Configure edge sensitivity for encoder mode */ /* Get the LPTIMx CFGR value */ @@ -1074,7 +1241,30 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 /* Set ENC bit to enable the encoder interface */ hlptim->Instance->CFGR |= LPTIM_CFGR_ENC; - /* Enable "switch to down direction" interrupt */ + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); + + /* Load the period value in the autoreload register */ + __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); + + /* Wait for the completion of the write operation to the LPTIM_ARR register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Enable "switch to down direction" interrupt */ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_DOWN); /* Enable "switch to up direction" interrupt */ @@ -1083,22 +1273,19 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); - /* Load the period value in the autoreload register */ - __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); - /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); /* Change the TIM state*/ - hlptim->State= HAL_LPTIM_STATE_READY; + hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ return HAL_OK; } /** - * @brief Stops the Encoder interface in interrupt mode. - * @param hlptim LPTIM handle + * @brief Stop the Encoder interface in interrupt mode. + * @param hlptim LPTIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim) @@ -1107,11 +1294,16 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim) assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); /* Set the LPTIM state */ - hlptim->State= HAL_LPTIM_STATE_BUSY; + hlptim->State = HAL_LPTIM_STATE_BUSY; /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Reset ENC bit to disable the encoder interface */ hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC; @@ -1122,20 +1314,20 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim) __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_UP); /* Change the TIM state*/ - hlptim->State= HAL_LPTIM_STATE_READY; + hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ return HAL_OK; } /** - * @brief Starts the Timeout function. The first trigger event will start the - * timer, any successive trigger event will reset the counter and - * the timer restarts. - * @param hlptim LPTIM handle - * @param Period Specifies the Autoreload value. + * @brief Start the Timeout function. + * @note The first trigger event will start the timer, any successive + * trigger event will reset the counter and the timer restarts. + * @param hlptim LPTIM handle + * @param Period Specifies the Autoreload value. * This parameter must be a value between 0x0000 and 0xFFFF. - * @param Timeout Specifies the TimeOut value to rest the counter. + * @param Timeout Specifies the TimeOut value to reset the counter. * This parameter must be a value between 0x0000 and 0xFFFF. * @retval HAL status */ @@ -1147,7 +1339,7 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t assert_param(IS_LPTIM_PULSE(Timeout)); /* Set the LPTIM state */ - hlptim->State= HAL_LPTIM_STATE_BUSY; + hlptim->State = HAL_LPTIM_STATE_BUSY; /* Set TIMOUT bit to enable the timeout function */ hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT; @@ -1155,25 +1347,43 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); + /* Load the period value in the autoreload register */ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); + /* Wait for the completion of the write operation to the LPTIM_ARR register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK); + /* Load the Timeout value in the compare register */ __HAL_LPTIM_COMPARE_SET(hlptim, Timeout); + /* Wait for the completion of the write operation to the LPTIM_CMP register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); /* Change the TIM state*/ - hlptim->State= HAL_LPTIM_STATE_READY; + hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ return HAL_OK; } /** - * @brief Stops the Timeout function. - * @param hlptim LPTIM handle + * @brief Stop the Timeout function. + * @param hlptim LPTIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim) @@ -1182,29 +1392,34 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim) assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); /* Set the LPTIM state */ - hlptim->State= HAL_LPTIM_STATE_BUSY; + hlptim->State = HAL_LPTIM_STATE_BUSY; /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Reset TIMOUT bit to enable the timeout function */ hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT; /* Change the TIM state*/ - hlptim->State= HAL_LPTIM_STATE_READY; + hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ return HAL_OK; } /** - * @brief Starts the Timeout function in interrupt mode. The first trigger - * event will start the timer, any successive trigger event will reset - * the counter and the timer restarts. - * @param hlptim LPTIM handle - * @param Period Specifies the Autoreload value. + * @brief Start the Timeout function in interrupt mode. + * @note The first trigger event will start the timer, any successive + * trigger event will reset the counter and the timer restarts. + * @param hlptim LPTIM handle + * @param Period Specifies the Autoreload value. * This parameter must be a value between 0x0000 and 0xFFFF. - * @param Timeout Specifies the TimeOut value to rest the counter. + * @param Timeout Specifies the TimeOut value to reset the counter. * This parameter must be a value between 0x0000 and 0xFFFF. * @retval HAL status */ @@ -1216,42 +1431,70 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 assert_param(IS_LPTIM_PULSE(Timeout)); /* Set the LPTIM state */ - hlptim->State= HAL_LPTIM_STATE_BUSY; + hlptim->State = HAL_LPTIM_STATE_BUSY; /* Enable EXTI Line interrupt on the LPTIM Wake-up Timer */ __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT(); - /* Enable rising edge trigger on the LPTIM Wake-up Timer Exti line */ __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE(); /* Set TIMOUT bit to enable the timeout function */ hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT; - /* Enable Compare match interrupt */ - __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM); - /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); + /* Load the period value in the autoreload register */ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); + /* Wait for the completion of the write operation to the LPTIM_ARR register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK); + /* Load the Timeout value in the compare register */ __HAL_LPTIM_COMPARE_SET(hlptim, Timeout); + /* Wait for the completion of the write operation to the LPTIM_CMP register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Enable Compare match interrupt */ + __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM); + + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); /* Change the TIM state*/ - hlptim->State= HAL_LPTIM_STATE_READY; + hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ return HAL_OK; } /** - * @brief Stops the Timeout function in interrupt mode. - * @param hlptim LPTIM handle + * @brief Stop the Timeout function in interrupt mode. + * @param hlptim LPTIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim) @@ -1260,8 +1503,7 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim) assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); /* Set the LPTIM state */ - hlptim->State= HAL_LPTIM_STATE_BUSY; - + hlptim->State = HAL_LPTIM_STATE_BUSY; /* Disable rising edge trigger on the LPTIM Wake-up Timer Exti line */ __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE(); @@ -1271,6 +1513,11 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim) /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Reset TIMOUT bit to enable the timeout function */ hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT; @@ -1278,16 +1525,16 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim) __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM); /* Change the TIM state*/ - hlptim->State= HAL_LPTIM_STATE_READY; + hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ return HAL_OK; } /** - * @brief Starts the Counter mode. - * @param hlptim LPTIM handle - * @param Period Specifies the Autoreload value. + * @brief Start the Counter mode. + * @param hlptim LPTIM handle + * @param Period Specifies the Autoreload value. * This parameter must be a value between 0x0000 and 0xFFFF. * @retval HAL status */ @@ -1298,10 +1545,10 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t assert_param(IS_LPTIM_PERIOD(Period)); /* Set the LPTIM state */ - hlptim->State= HAL_LPTIM_STATE_BUSY; + hlptim->State = HAL_LPTIM_STATE_BUSY; /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */ - if((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) + if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) { /* Check if clock is prescaled */ assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler)); @@ -1312,22 +1559,31 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); + /* Load the period value in the autoreload register */ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); + /* Wait for the completion of the write operation to the LPTIM_ARR register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); /* Change the TIM state*/ - hlptim->State= HAL_LPTIM_STATE_READY; + hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ return HAL_OK; } /** - * @brief Stops the Counter mode. - * @param hlptim LPTIM handle + * @brief Stop the Counter mode. + * @param hlptim LPTIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim) @@ -1336,22 +1592,27 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim) assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); /* Set the LPTIM state */ - hlptim->State= HAL_LPTIM_STATE_BUSY; + hlptim->State = HAL_LPTIM_STATE_BUSY; /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Change the TIM state*/ - hlptim->State= HAL_LPTIM_STATE_READY; + hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ return HAL_OK; } /** - * @brief Starts the Counter mode in interrupt mode. - * @param hlptim LPTIM handle - * @param Period Specifies the Autoreload value. + * @brief Start the Counter mode in interrupt mode. + * @param hlptim LPTIM handle + * @param Period Specifies the Autoreload value. * This parameter must be a value between 0x0000 and 0xFFFF. * @retval HAL status */ @@ -1362,16 +1623,15 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 assert_param(IS_LPTIM_PERIOD(Period)); /* Set the LPTIM state */ - hlptim->State= HAL_LPTIM_STATE_BUSY; + hlptim->State = HAL_LPTIM_STATE_BUSY; /* Enable EXTI Line interrupt on the LPTIM Wake-up Timer */ __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT(); - /* Enable rising edge trigger on the LPTIM Wake-up Timer Exti line */ __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE(); /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */ - if((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) + if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) { /* Check if clock is prescaled */ assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler)); @@ -1379,6 +1639,29 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 hlptim->Instance->CFGR &= ~LPTIM_CFGR_PRESC; } + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); + + /* Load the period value in the autoreload register */ + __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); + + /* Wait for the completion of the write operation to the LPTIM_ARR register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Enable Autoreload write complete interrupt */ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK); @@ -1388,22 +1671,19 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); - /* Load the period value in the autoreload register */ - __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); - /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); /* Change the TIM state*/ - hlptim->State= HAL_LPTIM_STATE_READY; + hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ return HAL_OK; } /** - * @brief Stops the Counter mode in interrupt mode. - * @param hlptim LPTIM handle + * @brief Stop the Counter mode in interrupt mode. + * @param hlptim LPTIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim) @@ -1412,8 +1692,7 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim) assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); /* Set the LPTIM state */ - hlptim->State= HAL_LPTIM_STATE_BUSY; - + hlptim->State = HAL_LPTIM_STATE_BUSY; /* Disable rising edge trigger on the LPTIM Wake-up Timer Exti line */ __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE(); @@ -1423,14 +1702,18 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim) /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Disable Autoreload write complete interrupt */ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK); /* Disable Autoreload match interrupt */ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM); - /* Change the TIM state*/ - hlptim->State= HAL_LPTIM_STATE_READY; + hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ return HAL_OK; @@ -1440,7 +1723,7 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim) * @} */ -/** @defgroup LPTIM_Group3 LPTIM Read operation functions +/** @defgroup LPTIM_Exported_Functions_Group3 LPTIM Read operation functions * @brief Read operation functions. * @verbatim @@ -1456,39 +1739,39 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim) */ /** - * @brief This function returns the current counter value. + * @brief Return the current counter value. * @param hlptim LPTIM handle * @retval Counter value. */ uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); return (hlptim->Instance->CNT); } /** - * @brief This function return the current Autoreload (Period) value. + * @brief Return the current Autoreload (Period) value. * @param hlptim LPTIM handle * @retval Autoreload value. */ uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); return (hlptim->Instance->ARR); } /** - * @brief This function return the current Compare (Pulse) value. + * @brief Return the current Compare (Pulse) value. * @param hlptim LPTIM handle * @retval Compare value. */ uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); return (hlptim->Instance->CMP); @@ -1498,35 +1781,43 @@ uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim) * @} */ - - -/** @defgroup LPTIM_Group4 LPTIM IRQ handler +/** @defgroup LPTIM_Exported_Functions_Group4 LPTIM IRQ handler and callbacks * @brief LPTIM IRQ handler. * @verbatim ============================================================================== - ##### LPTIM IRQ handler ##### + ##### LPTIM IRQ handler and callbacks ##### ============================================================================== -[..] This section provides LPTIM IRQ handler function. +[..] This section provides LPTIM IRQ handler and callback functions called within + the IRQ handler: + (+) LPTIM interrupt request handler + (+) Compare match Callback + (+) Auto-reload match Callback + (+) External trigger event detection Callback + (+) Compare register write complete Callback + (+) Auto-reload register write complete Callback + (+) Up-counting direction change Callback + (+) Down-counting direction change Callback @endverbatim * @{ */ /** - * @brief This function handles LPTIM interrupt request. + * @brief Handle LPTIM interrupt request. * @param hlptim LPTIM handle * @retval None */ void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim) { /* Compare match interrupt */ - if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMPM) != RESET) - { - if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_CMPM) !=RESET) - { + if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMPM) != RESET) + { + if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_CMPM) != RESET) + { /* Clear Compare match flag */ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPM); + /* Compare match Callback */ #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) hlptim->CompareMatchCallback(hlptim); @@ -1537,12 +1828,13 @@ void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim) } /* Autoreload match interrupt */ - if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARRM) != RESET) - { - if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARRM) !=RESET) - { + if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARRM) != RESET) + { + if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARRM) != RESET) + { /* Clear Autoreload match flag */ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARRM); + /* Autoreload match Callback */ #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) hlptim->AutoReloadMatchCallback(hlptim); @@ -1553,12 +1845,13 @@ void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim) } /* Trigger detected interrupt */ - if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_EXTTRIG) != RESET) - { - if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_EXTTRIG) !=RESET) - { + if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_EXTTRIG) != RESET) + { + if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_EXTTRIG) != RESET) + { /* Clear Trigger detected flag */ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_EXTTRIG); + /* Trigger detected callback */ #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) hlptim->TriggerCallback(hlptim); @@ -1569,12 +1862,13 @@ void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim) } /* Compare write interrupt */ - if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMPOK) != RESET) - { - if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_FLAG_CMPM) !=RESET) - { + if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMPOK) != RESET) + { + if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_CMPOK) != RESET) + { /* Clear Compare write flag */ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK); + /* Compare write Callback */ #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) hlptim->CompareWriteCallback(hlptim); @@ -1585,12 +1879,13 @@ void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim) } /* Autoreload write interrupt */ - if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARROK) != RESET) - { - if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARROK) !=RESET) - { + if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARROK) != RESET) + { + if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARROK) != RESET) + { /* Clear Autoreload write flag */ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); + /* Autoreload write Callback */ #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) hlptim->AutoReloadWriteCallback(hlptim); @@ -1601,12 +1896,13 @@ void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim) } /* Direction counter changed from Down to Up interrupt */ - if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_UP) != RESET) - { - if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_UP) !=RESET) - { + if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_UP) != RESET) + { + if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_UP) != RESET) + { /* Clear Direction counter changed from Down to Up flag */ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_UP); + /* Direction counter changed from Down to Up Callback */ #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) hlptim->DirectionUpCallback(hlptim); @@ -1617,12 +1913,13 @@ void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim) } /* Direction counter changed from Up to Down interrupt */ - if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_DOWN) != RESET) - { - if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_DOWN) !=RESET) - { + if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_DOWN) != RESET) + { + if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_DOWN) != RESET) + { /* Clear Direction counter changed from Up to Down flag */ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DOWN); + /* Direction counter changed from Up to Down Callback */ #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) hlptim->DirectionDownCallback(hlptim); @@ -1631,13 +1928,12 @@ void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim) #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ } } - __HAL_LPTIM_WAKEUPTIMER_EXTI_CLEAR_FLAG(); } /** - * @brief Compare match callback in non blocking mode - * @param hlptim LPTIM handle + * @brief Compare match callback in non-blocking mode. + * @param hlptim LPTIM handle * @retval None */ __weak void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim) @@ -1645,14 +1941,14 @@ __weak void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim) /* Prevent unused argument(s) compilation warning */ UNUSED(hlptim); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_LPTIM_CompareMatchCallback could be implemented in the user file */ } /** - * @brief Autoreload match callback in non blocking mode - * @param hlptim LPTIM handle + * @brief Autoreload match callback in non-blocking mode. + * @param hlptim LPTIM handle * @retval None */ __weak void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim) @@ -1660,14 +1956,14 @@ __weak void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim) /* Prevent unused argument(s) compilation warning */ UNUSED(hlptim); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_LPTIM_AutoReloadMatchCallback could be implemented in the user file */ } /** - * @brief Trigger detected callback in non blocking mode - * @param hlptim LPTIM handle + * @brief Trigger detected callback in non-blocking mode. + * @param hlptim LPTIM handle * @retval None */ __weak void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim) @@ -1675,14 +1971,14 @@ __weak void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim) /* Prevent unused argument(s) compilation warning */ UNUSED(hlptim); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_LPTIM_TriggerCallback could be implemented in the user file */ } /** - * @brief Compare write callback in non blocking mode - * @param hlptim LPTIM handle + * @brief Compare write callback in non-blocking mode. + * @param hlptim LPTIM handle * @retval None */ __weak void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim) @@ -1690,14 +1986,14 @@ __weak void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim) /* Prevent unused argument(s) compilation warning */ UNUSED(hlptim); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_LPTIM_CompareWriteCallback could be implemented in the user file */ } /** - * @brief Autoreload write callback in non blocking mode - * @param hlptim LPTIM handle + * @brief Autoreload write callback in non-blocking mode. + * @param hlptim LPTIM handle * @retval None */ __weak void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim) @@ -1705,14 +2001,14 @@ __weak void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim) /* Prevent unused argument(s) compilation warning */ UNUSED(hlptim); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_LPTIM_AutoReloadWriteCallback could be implemented in the user file */ } /** - * @brief Direction counter changed from Down to Up callback in non blocking mode - * @param hlptim LPTIM handle + * @brief Direction counter changed from Down to Up callback in non-blocking mode. + * @param hlptim LPTIM handle * @retval None */ __weak void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim) @@ -1720,14 +2016,14 @@ __weak void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim) /* Prevent unused argument(s) compilation warning */ UNUSED(hlptim); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_LPTIM_DirectionUpCallback could be implemented in the user file */ } /** - * @brief Direction counter changed from Up to Down callback in non blocking mode - * @param hlptim LPTIM handle + * @brief Direction counter changed from Up to Down callback in non-blocking mode. + * @param hlptim LPTIM handle * @retval None */ __weak void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim) @@ -1735,102 +2031,105 @@ __weak void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim) /* Prevent unused argument(s) compilation warning */ UNUSED(hlptim); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_LPTIM_DirectionDownCallback could be implemented in the user file */ } #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) /** - * @brief Register user LPTIM callback to be used instead of the weak predefined callback - * @param hlptim lptim handle - * @param CallbackID ID of the callback to be registered - * This parameter can be one of the following values: - * @arg @ref HAL_LPTIM_MSPINIT_CB_ID MspInit Callback ID - * @arg @ref HAL_LPTIM_MSPDEINIT_CB_ID MspDeInit Callback ID - * @arg @ref HAL_LPTIM_COMPARE_MATCH_CB_ID Compare Match Callback ID - * @arg @ref HAL_LPTIM_AUTO_RELOAD_MATCH_CB_ID Auto Reload Match Callback ID - * @arg @ref HAL_LPTIM_TRIGGER_CB_ID Trigger Callback ID - * @arg @ref HAL_LPTIM_COMPARE_WRITE_CB_ID Compare Write Callback ID - * @arg @ref HAL_LPTIM_AUTO_RELOAD_WRITE_CB_ID Auto Reload Write Callback ID - * @arg @ref HAL_LPTIM_DIRECTION_UP_CB_ID Direction UP Callback ID - * @arg @ref HAL_LPTIM_DIRECTION_DOWN_CB_ID Direction Down Callback ID + * @brief Register a User LPTIM callback to be used instead of the weak predefined callback + * @param hlptim LPTIM handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_LPTIM_MSPINIT_CB_ID LPTIM Base Msp Init Callback ID + * @arg @ref HAL_LPTIM_MSPDEINIT_CB_ID LPTIM Base Msp DeInit Callback ID + * @arg @ref HAL_LPTIM_COMPARE_MATCH_CB_ID Compare match Callback ID + * @arg @ref HAL_LPTIM_AUTORELOAD_MATCH_CB_ID Auto-reload match Callback ID + * @arg @ref HAL_LPTIM_TRIGGER_CB_ID External trigger event detection Callback ID + * @arg @ref HAL_LPTIM_COMPARE_WRITE_CB_ID Compare register write complete Callback ID + * @arg @ref HAL_LPTIM_AUTORELOAD_WRITE_CB_ID Auto-reload register write complete Callback ID + * @arg @ref HAL_LPTIM_DIRECTION_UP_CB_ID Up-counting direction change Callback ID + * @arg @ref HAL_LPTIM_DIRECTION_DOWN_CB_ID Down-counting direction change Callback ID * @param pCallback pointer to the callback function * @retval status */ -HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *hlptim, HAL_LPTIM_CallbackIDTypeDef CallbackID, pLPTIM_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *hlptim, + HAL_LPTIM_CallbackIDTypeDef CallbackID, + pLPTIM_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; - if(pCallback == NULL) + if (pCallback == NULL) { return HAL_ERROR; } + /* Process locked */ __HAL_LOCK(hlptim); - if(hlptim->State == HAL_LPTIM_STATE_READY) + if (hlptim->State == HAL_LPTIM_STATE_READY) { switch (CallbackID) { - case HAL_LPTIM_MSPINIT_CB_ID : - hlptim->MspInitCallback = pCallback; - break; - - case HAL_LPTIM_MSPDEINIT_CB_ID : - hlptim->MspDeInitCallback = pCallback; - break; - - case HAL_LPTIM_COMPARE_MATCH_CB_ID : - hlptim->CompareMatchCallback = pCallback; - break; - - case HAL_LPTIM_AUTO_RELOAD_MATCH_CB_ID : - hlptim->AutoReloadMatchCallback = pCallback; - break; - - case HAL_LPTIM_TRIGGER_CB_ID : - hlptim->TriggerCallback = pCallback; - break; - - case HAL_LPTIM_COMPARE_WRITE_CB_ID : - hlptim->CompareWriteCallback = pCallback; - break; - - case HAL_LPTIM_AUTO_RELOAD_WRITE_CB_ID : - hlptim->AutoReloadWriteCallback = pCallback; - break; - - case HAL_LPTIM_DIRECTION_UP_CB_ID : - hlptim->DirectionUpCallback = pCallback; - break; - - case HAL_LPTIM_DIRECTION_DOWN_CB_ID : - hlptim->DirectionDownCallback = pCallback; - break; - - default : - /* Return error status */ - status = HAL_ERROR; - break; + case HAL_LPTIM_MSPINIT_CB_ID : + hlptim->MspInitCallback = pCallback; + break; + + case HAL_LPTIM_MSPDEINIT_CB_ID : + hlptim->MspDeInitCallback = pCallback; + break; + + case HAL_LPTIM_COMPARE_MATCH_CB_ID : + hlptim->CompareMatchCallback = pCallback; + break; + + case HAL_LPTIM_AUTORELOAD_MATCH_CB_ID : + hlptim->AutoReloadMatchCallback = pCallback; + break; + + case HAL_LPTIM_TRIGGER_CB_ID : + hlptim->TriggerCallback = pCallback; + break; + + case HAL_LPTIM_COMPARE_WRITE_CB_ID : + hlptim->CompareWriteCallback = pCallback; + break; + + case HAL_LPTIM_AUTORELOAD_WRITE_CB_ID : + hlptim->AutoReloadWriteCallback = pCallback; + break; + + case HAL_LPTIM_DIRECTION_UP_CB_ID : + hlptim->DirectionUpCallback = pCallback; + break; + + case HAL_LPTIM_DIRECTION_DOWN_CB_ID : + hlptim->DirectionDownCallback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; } } - else if(hlptim->State == HAL_LPTIM_STATE_RESET) + else if (hlptim->State == HAL_LPTIM_STATE_RESET) { switch (CallbackID) { - case HAL_LPTIM_MSPINIT_CB_ID : - hlptim->MspInitCallback = pCallback; - break; - - case HAL_LPTIM_MSPDEINIT_CB_ID : - hlptim->MspDeInitCallback = pCallback; - break; - - default : - /* Return error status */ - status = HAL_ERROR; - break; + case HAL_LPTIM_MSPINIT_CB_ID : + hlptim->MspInitCallback = pCallback; + break; + + case HAL_LPTIM_MSPDEINIT_CB_ID : + hlptim->MspDeInitCallback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; } } else @@ -1846,91 +2145,92 @@ HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *hlptim, HAL_LP } /** - * @brief UnRegister user LPTIM callback - * LPTIM callback is redirected to the weak predefined callback - * @param hlptim lptim handle - * @param CallbackID ID of the callback to be unregistered -+ * This parameter can be one of the following values: -+ * @arg @ref HAL_LPTIM_MSPINIT_CB_ID MspInit Callback ID -+ * @arg @ref HAL_LPTIM_MSPDEINIT_CB_ID MspDeInit Callback ID -+ * @arg @ref HAL_LPTIM_COMPARE_MATCH_CB_ID Compare Match Callback ID -+ * @arg @ref HAL_LPTIM_AUTO_RELOAD_MATCH_CB_ID Auto Reload Match Callback ID -+ * @arg @ref HAL_LPTIM_TRIGGER_CB_ID Trigger Callback ID -+ * @arg @ref HAL_LPTIM_COMPARE_WRITE_CB_ID Compare Write Callback ID -+ * @arg @ref HAL_LPTIM_AUTO_RELOAD_WRITE_CB_ID Auto Reload Write Callback ID -+ * @arg @ref HAL_LPTIM_DIRECTION_UP_CB_ID Direction UP Callback ID -+ * @arg @ref HAL_LPTIM_DIRECTION_DOWN_CB_ID Direction Down Callback ID + * @brief Unregister a LPTIM callback + * LLPTIM callback is redirected to the weak predefined callback + * @param hlptim LPTIM handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_LPTIM_MSPINIT_CB_ID LPTIM Base Msp Init Callback ID + * @arg @ref HAL_LPTIM_MSPDEINIT_CB_ID LPTIM Base Msp DeInit Callback ID + * @arg @ref HAL_LPTIM_COMPARE_MATCH_CB_ID Compare match Callback ID + * @arg @ref HAL_LPTIM_AUTORELOAD_MATCH_CB_ID Auto-reload match Callback ID + * @arg @ref HAL_LPTIM_TRIGGER_CB_ID External trigger event detection Callback ID + * @arg @ref HAL_LPTIM_COMPARE_WRITE_CB_ID Compare register write complete Callback ID + * @arg @ref HAL_LPTIM_AUTORELOAD_WRITE_CB_ID Auto-reload register write complete Callback ID + * @arg @ref HAL_LPTIM_DIRECTION_UP_CB_ID Up-counting direction change Callback ID + * @arg @ref HAL_LPTIM_DIRECTION_DOWN_CB_ID Down-counting direction change Callback ID * @retval status */ -HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlptim, HAL_LPTIM_CallbackIDTypeDef CallbackID) +HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlptim, + HAL_LPTIM_CallbackIDTypeDef CallbackID) { HAL_StatusTypeDef status = HAL_OK; /* Process locked */ __HAL_LOCK(hlptim); - if(hlptim->State == HAL_LPTIM_STATE_READY) + if (hlptim->State == HAL_LPTIM_STATE_READY) { switch (CallbackID) { - case HAL_LPTIM_MSPINIT_CB_ID : - hlptim->MspInitCallback = HAL_LPTIM_MspInit; /* Legacy weak MspInit Callback */ - break; - - case HAL_LPTIM_MSPDEINIT_CB_ID : - hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit; /* Legacy weak MspDeInit Callback */ - break; - - case HAL_LPTIM_COMPARE_MATCH_CB_ID : - hlptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback; /* Legacy weak Compare Match Callback */ - break; - - case HAL_LPTIM_AUTO_RELOAD_MATCH_CB_ID : - hlptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback; /* Legacy weak Auto Reload Match Callback */ - break; - - case HAL_LPTIM_TRIGGER_CB_ID : - hlptim->TriggerCallback = HAL_LPTIM_TriggerCallback; /* Legacy weak Trigger Callback */ - break; - - case HAL_LPTIM_COMPARE_WRITE_CB_ID : - hlptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback; /* Legacy weak Compare Write Callback */ - break; - - case HAL_LPTIM_AUTO_RELOAD_WRITE_CB_ID : - hlptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback; /* Legacy weak Auto Reload Write Callback */ - break; - - case HAL_LPTIM_DIRECTION_UP_CB_ID : - hlptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback; /* Legacy weak Direction Up Callback */ - break; - - case HAL_LPTIM_DIRECTION_DOWN_CB_ID : - hlptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback; /* Legacy weak Direction Down Callback */ - break; - - default : - /* Return error status */ - status = HAL_ERROR; - break; + case HAL_LPTIM_MSPINIT_CB_ID : + hlptim->MspInitCallback = HAL_LPTIM_MspInit; /* Legacy weak MspInit Callback */ + break; + + case HAL_LPTIM_MSPDEINIT_CB_ID : + hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit; /* Legacy weak Msp DeInit Callback */ + break; + + case HAL_LPTIM_COMPARE_MATCH_CB_ID : + hlptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback; /* Legacy weak Compare match Callback */ + break; + + case HAL_LPTIM_AUTORELOAD_MATCH_CB_ID : + hlptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback; /* Legacy weak Auto-reload match Callback */ + break; + + case HAL_LPTIM_TRIGGER_CB_ID : + hlptim->TriggerCallback = HAL_LPTIM_TriggerCallback; /* Legacy weak External trigger event detection Callback */ + break; + + case HAL_LPTIM_COMPARE_WRITE_CB_ID : + hlptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback; /* Legacy weak Compare register write complete Callback */ + break; + + case HAL_LPTIM_AUTORELOAD_WRITE_CB_ID : + hlptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback; /* Legacy weak Auto-reload register write complete Callback */ + break; + + case HAL_LPTIM_DIRECTION_UP_CB_ID : + hlptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback; /* Legacy weak Up-counting direction change Callback */ + break; + + case HAL_LPTIM_DIRECTION_DOWN_CB_ID : + hlptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback; /* Legacy weak Down-counting direction change Callback */ + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; } } - else if(hlptim->State == HAL_LPTIM_STATE_RESET) + else if (hlptim->State == HAL_LPTIM_STATE_RESET) { switch (CallbackID) { - case HAL_LPTIM_MSPINIT_CB_ID : - hlptim->MspInitCallback = HAL_LPTIM_MspInit; /* Legacy weak MspInit Callback */ - break; - - case HAL_LPTIM_MSPDEINIT_CB_ID : - hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit; /* Legacy weak MspDeInit Callback */ - break; - - default : - /* Return error status */ - status = HAL_ERROR; - break; + case HAL_LPTIM_MSPINIT_CB_ID : + hlptim->MspInitCallback = HAL_LPTIM_MspInit; /* Legacy weak MspInit Callback */ + break; + + case HAL_LPTIM_MSPDEINIT_CB_ID : + hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit; /* Legacy weak Msp DeInit Callback */ + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; } } else @@ -1965,12 +2265,13 @@ HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlptim, HAL_ */ /** - * @brief Returns the LPTIM state. + * @brief Return the LPTIM handle state. * @param hlptim LPTIM handle * @retval HAL state */ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim) { + /* Return LPTIM handle state */ return hlptim->State; } @@ -1983,6 +2284,167 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim) * @} */ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup LPTIM_Private_Functions LPTIM Private Functions + * @{ + */ +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) +/** + * @brief Reset interrupt callbacks to the legacy weak callbacks. + * @param lptim pointer to a LPTIM_HandleTypeDef structure that contains + * the configuration information for LPTIM module. + * @retval None + */ +static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim) +{ + /* Reset the LPTIM callback to the legacy weak callbacks */ + lptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback; /* Compare match Callback */ + lptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback; /* Auto-reload match Callback */ + lptim->TriggerCallback = HAL_LPTIM_TriggerCallback; /* External trigger event detection Callback */ + lptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback; /* Compare register write complete Callback */ + lptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback; /* Auto-reload register write complete Callback */ + lptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback; /* Up-counting direction change Callback */ + lptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback; /* Down-counting direction change Callback */ +} +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + +/** + * @brief LPTimer Wait for flag set + * @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains + * the configuration information for LPTIM module. + * @param flag The lptim flag + * @retval HAL status + */ +static HAL_StatusTypeDef LPTIM_WaitForFlag(LPTIM_HandleTypeDef *hlptim, uint32_t flag) +{ + HAL_StatusTypeDef result = HAL_OK; + uint32_t count = TIMEOUT * (SystemCoreClock / 20UL / 1000UL); + do + { + count--; + if (count == 0UL) + { + result = HAL_TIMEOUT; + } + } + while ((!(__HAL_LPTIM_GET_FLAG((hlptim), (flag)))) && (count != 0UL)); + + return result; +} + +/** + * @brief Disable LPTIM HW instance. + * @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains + * the configuration information for LPTIM module. + * @note The following sequence is required to solve LPTIM disable HW limitation. + * Please check Errata Sheet ES0335 for more details under "MCU may remain + * stuck in LPTIM interrupt when entering Stop mode" section. + * @retval None + */ +void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim) +{ + uint32_t tmpclksource = 0; + uint32_t tmpIER; + uint32_t tmpCFGR; + uint32_t tmpCMP; + uint32_t tmpARR; + + __disable_irq(); + + /*********** Save LPTIM Config ***********/ + /* Save LPTIM source clock */ + switch ((uint32_t)hlptim->Instance) + { + case LPTIM1_BASE: + tmpclksource = __HAL_RCC_GET_LPTIM1_SOURCE(); + break; + default: + break; + } + + /* Save LPTIM configuration registers */ + tmpIER = hlptim->Instance->IER; + tmpCFGR = hlptim->Instance->CFGR; + tmpCMP = hlptim->Instance->CMP; + tmpARR = hlptim->Instance->ARR; + + /*********** Reset LPTIM ***********/ + switch ((uint32_t)hlptim->Instance) + { + case LPTIM1_BASE: + __HAL_RCC_LPTIM1_FORCE_RESET(); + __HAL_RCC_LPTIM1_RELEASE_RESET(); + break; + default: + break; + } + + /*********** Restore LPTIM Config ***********/ + if ((tmpCMP != 0UL) || (tmpARR != 0UL)) + { + /* Force LPTIM source kernel clock from APB */ + switch ((uint32_t)hlptim->Instance) + { + case LPTIM1_BASE: + __HAL_RCC_LPTIM1_CONFIG(RCC_LPTIM1CLKSOURCE_PCLK1); + break; + default: + break; + } + + if (tmpCMP != 0UL) + { + /* Restore CMP register (LPTIM should be enabled first) */ + hlptim->Instance->CR |= LPTIM_CR_ENABLE; + hlptim->Instance->CMP = tmpCMP; + + /* Wait for the completion of the write operation to the LPTIM_CMP register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT) + { + hlptim->State = HAL_LPTIM_STATE_TIMEOUT; + } + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK); + } + + if (tmpARR != 0UL) + { + /* Restore ARR register (LPTIM should be enabled first) */ + hlptim->Instance->CR |= LPTIM_CR_ENABLE; + hlptim->Instance->ARR = tmpARR; + + /* Wait for the completion of the write operation to the LPTIM_ARR register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT) + { + hlptim->State = HAL_LPTIM_STATE_TIMEOUT; + } + + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); + } + + /* Restore LPTIM source kernel clock */ + switch ((uint32_t)hlptim->Instance) + { + case LPTIM1_BASE: + __HAL_RCC_LPTIM1_CONFIG(tmpclksource); + break; + default: + break; + } + } + + /* Restore configuration registers (LPTIM should be disabled first) */ + hlptim->Instance->CR &= ~(LPTIM_CR_ENABLE); + hlptim->Instance->IER = tmpIER; + hlptim->Instance->CFGR = tmpCFGR; + + __enable_irq(); +} +/** + * @} + */ +#endif /* LPTIM1 */ + #endif /* HAL_LPTIM_MODULE_ENABLED */ /** * @} diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_mmc.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_mmc.c index c8e497a1fa..d64fe074ee 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_mmc.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_mmc.c @@ -38,8 +38,8 @@ (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE(); (+++) Configure the DMA using the function HAL_DMA_Init() with predeclared and filled. (##) NVIC configuration if you need to use interrupt process when using DMA transfer. - (+++) Configure the SDMMC and DMA interrupt priorities using functions - HAL_NVIC_SetPriority(); DMA priority is superior to SDMMC's priority + (+++) Configure the SDMMC and DMA interrupt priorities using function HAL_NVIC_SetPriority(); + DMA priority is superior to SDMMC's priority (+++) Enable the NVIC DMA and SDMMC IRQs using function HAL_NVIC_EnableIRQ() (+++) SDMMC interrupts are managed using the macros __HAL_MMC_ENABLE_IT() and __HAL_MMC_DISABLE_IT() inside the communication process. @@ -47,8 +47,7 @@ and __HAL_MMC_CLEAR_IT() (##) NVIC configuration if you need to use interrupt process (HAL_MMC_ReadBlocks_IT() and HAL_MMC_WriteBlocks_IT() APIs). - (+++) Configure the SDMMC interrupt priorities using function - HAL_NVIC_SetPriority(); + (+++) Configure the SDMMC interrupt priorities using function HAL_NVIC_SetPriority(); (+++) Enable the NVIC SDMMC IRQs using function HAL_NVIC_EnableIRQ() (+++) SDMMC interrupts are managed using the macros __HAL_MMC_ENABLE_IT() and __HAL_MMC_DISABLE_IT() inside the communication process. @@ -61,7 +60,7 @@ ================================================ [..] To initialize the MMC Card, use the HAL_MMC_Init() function. It Initializes - SDMMC IP (STM32 side) and the MMC Card, and put it into StandBy State (Ready for data transfer). + SDMMC Peripheral (STM32 side) and the MMC Card, and put it into StandBy State (Ready for data transfer). This function provide the following operations: (#) Initialize the SDMMC peripheral interface with defaullt configuration. @@ -102,14 +101,16 @@ ============================== [..] (+) You can read from MMC card in polling mode by using function HAL_MMC_ReadBlocks(). - This function allows the read of 512 bytes blocks. + This function support only 512-bytes block length (the block size should be + chosen as 512 bytes). You can choose either one block read operation or multiple block read operation by adjusting the "NumberOfBlocks" parameter. After this, you have to ensure that the transfer is done correctly. The check is done through HAL_MMC_GetCardState() function for MMC card state. (+) You can read from MMC card in DMA mode by using function HAL_MMC_ReadBlocks_DMA(). - This function allows the read of 512 bytes blocks. + This function support only 512-bytes block length (the block size should be + chosen as 512 bytes). You can choose either one block read operation or multiple block read operation by adjusting the "NumberOfBlocks" parameter. After this, you have to ensure that the transfer is done correctly. The check is done @@ -128,14 +129,16 @@ =============================== [..] (+) You can write to MMC card in polling mode by using function HAL_MMC_WriteBlocks(). - This function allows the read of 512 bytes blocks. + This function support only 512-bytes block length (the block size should be + chosen as 512 bytes). You can choose either one block read operation or multiple block read operation by adjusting the "NumberOfBlocks" parameter. After this, you have to ensure that the transfer is done correctly. The check is done through HAL_MMC_GetCardState() function for MMC card state. (+) You can write to MMC card in DMA mode by using function HAL_MMC_WriteBlocks_DMA(). - This function allows the read of 512 bytes blocks. + This function support only 512-bytes block length (the block size should be + chosen as 512 byte). You can choose either one block read operation or multiple block read operation by adjusting the "NumberOfBlocks" parameter. After this, you have to ensure that the transfer is done correctly. The check is done @@ -226,12 +229,13 @@ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL__RegisterCallback before calling @ref HAL_MMC_DeInit + using @ref HAL_MMC_RegisterCallback before calling @ref HAL_MMC_DeInit or @ref HAL_MMC_Init function. When The compilation define USE_HAL_MMC_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available and weak (surcharged) callbacks are used. + @endverbatim ****************************************************************************** * @attention @@ -242,7 +246,7 @@ * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -261,6 +265,8 @@ #ifdef HAL_MMC_MODULE_ENABLED +#if defined(SDMMC1) + /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** @addtogroup MMC_Private_Defines @@ -281,18 +287,17 @@ static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc); static uint32_t MMC_PowerON(MMC_HandleTypeDef *hmmc); static uint32_t MMC_SendStatus(MMC_HandleTypeDef *hmmc, uint32_t *pCardStatus); -static HAL_StatusTypeDef MMC_PowerOFF(MMC_HandleTypeDef *hmmc); -static HAL_StatusTypeDef MMC_Write_IT(MMC_HandleTypeDef *hmmc); -static HAL_StatusTypeDef MMC_Read_IT(MMC_HandleTypeDef *hmmc); -static void MMC_DMATransmitCplt(DMA_HandleTypeDef *hdma); -static void MMC_DMAReceiveCplt(DMA_HandleTypeDef *hdma); -static void MMC_DMAError(DMA_HandleTypeDef *hdma); -static void MMC_DMATxAbort(DMA_HandleTypeDef *hdma); -static void MMC_DMARxAbort(DMA_HandleTypeDef *hdma); +static void MMC_PowerOFF(MMC_HandleTypeDef *hmmc); +static void MMC_Write_IT(MMC_HandleTypeDef *hmmc); +static void MMC_Read_IT(MMC_HandleTypeDef *hmmc); +static void MMC_DMATransmitCplt(DMA_HandleTypeDef *hdma); +static void MMC_DMAReceiveCplt(DMA_HandleTypeDef *hdma); +static void MMC_DMAError(DMA_HandleTypeDef *hdma); +static void MMC_DMATxAbort(DMA_HandleTypeDef *hdma); +static void MMC_DMARxAbort(DMA_HandleTypeDef *hdma); /** * @} */ - /* Exported functions --------------------------------------------------------*/ /** @addtogroup MMC_Exported_Functions * @{ @@ -316,7 +321,7 @@ static void MMC_DMARxAbort(DMA_HandleTypeDef *hdma); /** * @brief Initializes the MMC according to the specified parameters in the MMC_HandleTypeDef and create the associated handle. - * @param hmmc Pointer to the MMC handle + * @param hmmc: Pointer to the MMC handle * @retval HAL status */ HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc) @@ -340,7 +345,7 @@ HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc) { /* Allocate lock resource and initialize it */ hmmc->Lock = HAL_UNLOCKED; -#if (USE_HAL_MMC_REGISTER_CALLBACKS == 1) +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) /* Reset Callback pointers in HAL_MMC_STATE_RESET only */ hmmc->TxCpltCallback = HAL_MMC_TxCpltCallback; hmmc->RxCpltCallback = HAL_MMC_RxCpltCallback; @@ -363,7 +368,10 @@ HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc) hmmc->State = HAL_MMC_STATE_BUSY; /* Initialize the Card parameters */ - HAL_MMC_InitCard(hmmc); + if(HAL_MMC_InitCard(hmmc) == HAL_ERROR) + { + return HAL_ERROR; + } /* Initialize the error code */ hmmc->ErrorCode = HAL_DMA_ERROR_NONE; @@ -379,15 +387,16 @@ HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc) /** * @brief Initializes the MMC Card. - * @param hmmc Pointer to MMC handle + * @param hmmc: Pointer to MMC handle * @note This function initializes the MMC card. It could be used when a card re-initialization is needed. * @retval HAL status */ HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc) { - uint32_t errorstate = HAL_MMC_ERROR_NONE; + uint32_t errorstate; MMC_InitTypeDef Init; + HAL_StatusTypeDef status; /* Default SDMMC peripheral configuration for MMC card initialization */ Init.ClockEdge = SDMMC_CLOCK_EDGE_RISING; @@ -398,20 +407,25 @@ HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc) Init.ClockDiv = SDMMC_INIT_CLK_DIV; /* Initialize SDMMC peripheral interface with default configuration */ - SDMMC_Init(hmmc->Instance, Init); + status = SDMMC_Init(hmmc->Instance, Init); + if(status == HAL_ERROR) + { + return HAL_ERROR; + } /* Disable SDMMC Clock */ __HAL_MMC_DISABLE(hmmc); /* Set Power State to ON */ - SDMMC_PowerState_ON(hmmc->Instance); + status = SDMMC_PowerState_ON(hmmc->Instance); + if(status == HAL_ERROR) + { + return HAL_ERROR; + } /* Enable MMC Clock */ __HAL_MMC_ENABLE(hmmc); - /* Required power up waiting time before starting the SD initialization sequence */ - HAL_Delay(2); - /* Identify card operating voltage */ errorstate = MMC_PowerON(hmmc); if(errorstate != HAL_MMC_ERROR_NONE) @@ -435,7 +449,7 @@ HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc) /** * @brief De-Initializes the MMC card. - * @param hmmc Pointer to MMC handle + * @param hmmc: Pointer to MMC handle * @retval HAL status */ HAL_StatusTypeDef HAL_MMC_DeInit(MMC_HandleTypeDef *hmmc) @@ -454,7 +468,7 @@ HAL_StatusTypeDef HAL_MMC_DeInit(MMC_HandleTypeDef *hmmc) /* Set MMC power state to off */ MMC_PowerOFF(hmmc); -#if (USE_HAL_MMC_REGISTER_CALLBACKS == 1) +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) if(hmmc->MspDeInitCallback == NULL) { hmmc->MspDeInitCallback = HAL_MMC_MspDeInit; @@ -476,7 +490,7 @@ HAL_StatusTypeDef HAL_MMC_DeInit(MMC_HandleTypeDef *hmmc) /** * @brief Initializes the MMC MSP. - * @param hmmc Pointer to MMC handle + * @param hmmc: Pointer to MMC handle * @retval None */ __weak void HAL_MMC_MspInit(MMC_HandleTypeDef *hmmc) @@ -491,7 +505,7 @@ __weak void HAL_MMC_MspInit(MMC_HandleTypeDef *hmmc) /** * @brief De-Initialize MMC MSP. - * @param hmmc Pointer to MMC handle + * @param hmmc: Pointer to MMC handle * @retval None */ __weak void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc) @@ -528,19 +542,21 @@ __weak void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc) * is managed by polling mode. * @note This API should be followed by a check on the card state through * HAL_MMC_GetCardState(). - * @param hmmc Pointer to MMC handle - * @param pData pointer to the buffer that will contain the received data - * @param BlockAdd Block Address from where data is to be read - * @param NumberOfBlocks Number of MMC blocks to read - * @param Timeout Specify timeout value + * @param hmmc: Pointer to MMC handle + * @param pData: pointer to the buffer that will contain the received data + * @param BlockAdd: Block Address from where data is to be read + * @param NumberOfBlocks: Number of MMC blocks to read + * @param Timeout: Specify timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout) { SDMMC_DataInitTypeDef config; - uint32_t errorstate = HAL_MMC_ERROR_NONE; + uint32_t errorstate; uint32_t tickstart = HAL_GetTick(); - uint32_t count = 0, *tempbuff = (uint32_t *)pData; + uint32_t count, data, dataremaining; + uint32_t add = BlockAdd; + uint8_t *tempbuff = pData; if(NULL == pData) { @@ -550,7 +566,7 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, ui if(hmmc->State == HAL_MMC_STATE_READY) { - hmmc->ErrorCode = HAL_DMA_ERROR_NONE; + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) { @@ -561,16 +577,15 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, ui hmmc->State = HAL_MMC_STATE_BUSY; /* Initialize data control register */ - hmmc->Instance->DCTRL = 0; + hmmc->Instance->DCTRL = 0U; - /* Check the Card capacity in term of Logical number of blocks */ - if ((hmmc->MmcCard.LogBlockNbr) < CAPACITY) + if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD) { - BlockAdd *= 512; + add *= 512U; } /* Set Block Size for Card */ - errorstate = SDMMC_CmdBlockLength(hmmc->Instance, BLOCKSIZE); + errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE); if(errorstate != HAL_MMC_ERROR_NONE) { /* Clear all the static flags */ @@ -582,27 +597,27 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, ui /* Configure the MMC DPSM (Data Path State Machine) */ config.DataTimeOut = SDMMC_DATATIMEOUT; - config.DataLength = NumberOfBlocks * BLOCKSIZE; + config.DataLength = NumberOfBlocks * MMC_BLOCKSIZE; config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; config.DPSM = SDMMC_DPSM_ENABLE; - SDMMC_ConfigData(hmmc->Instance, &config); + (void)SDMMC_ConfigData(hmmc->Instance, &config); /* Read block(s) in polling mode */ - if(NumberOfBlocks > 1) + if(NumberOfBlocks > 1U) { hmmc->Context = MMC_CONTEXT_READ_MULTIPLE_BLOCK; /* Read Multi Block command */ - errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, BlockAdd); + errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, add); } else { hmmc->Context = MMC_CONTEXT_READ_SINGLE_BLOCK; /* Read Single Block command */ - errorstate = SDMMC_CmdReadSingleBlock(hmmc->Instance, BlockAdd); + errorstate = SDMMC_CmdReadSingleBlock(hmmc->Instance, add); } if(errorstate != HAL_MMC_ERROR_NONE) { @@ -614,19 +629,31 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, ui } /* Poll on SDMMC flags */ + dataremaining = config.DataLength; while(!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) { - if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF)) + if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) && (dataremaining > 0U)) { /* Read data from SDMMC Rx FIFO */ for(count = 0U; count < 8U; count++) { - *(tempbuff + count) = SDMMC_ReadFIFO(hmmc->Instance); + data = SDMMC_ReadFIFO(hmmc->Instance); + *tempbuff = (uint8_t)(data & 0xFFU); + tempbuff++; + dataremaining--; + *tempbuff = (uint8_t)((data >> 8U) & 0xFFU); + tempbuff++; + dataremaining--; + *tempbuff = (uint8_t)((data >> 16U) & 0xFFU); + tempbuff++; + dataremaining--; + *tempbuff = (uint8_t)((data >> 24U) & 0xFFU); + tempbuff++; + dataremaining--; } - tempbuff += 8U; } - if((Timeout == 0U)||((HAL_GetTick()-tickstart) >= Timeout)) + if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U)) { /* Clear all the static flags */ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); @@ -676,14 +703,29 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, ui hmmc->State = HAL_MMC_STATE_READY; return HAL_ERROR; } + else + { + /* Nothing to do */ + } /* Empty FIFO if there is still any data */ - while ((__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXDAVL))) + while ((__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXDAVL)) && (dataremaining > 0U)) { - *tempbuff = SDMMC_ReadFIFO(hmmc->Instance); + data = SDMMC_ReadFIFO(hmmc->Instance); + *tempbuff = (uint8_t)(data & 0xFFU); + tempbuff++; + dataremaining--; + *tempbuff = (uint8_t)((data >> 8U) & 0xFFU); + tempbuff++; + dataremaining--; + *tempbuff = (uint8_t)((data >> 16U) & 0xFFU); + tempbuff++; + dataremaining--; + *tempbuff = (uint8_t)((data >> 24U) & 0xFFU); tempbuff++; + dataremaining--; - if((Timeout == 0U)||((HAL_GetTick()-tickstart) >= Timeout)) + if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U)) { /* Clear all the static flags */ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); @@ -694,7 +736,7 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, ui } /* Clear all the static flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); hmmc->State = HAL_MMC_STATE_READY; @@ -712,20 +754,21 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, ui * transfer is managed by polling mode. * @note This API should be followed by a check on the card state through * HAL_MMC_GetCardState(). - * @param hmmc Pointer to MMC handle - * @param pData pointer to the buffer that will contain the data to transmit - * @param BlockAdd Block Address where data will be written - * @param NumberOfBlocks Number of MMC blocks to write - * @param Timeout Specify timeout value + * @param hmmc: Pointer to MMC handle + * @param pData: pointer to the buffer that will contain the data to transmit + * @param BlockAdd: Block Address where data will be written + * @param NumberOfBlocks: Number of MMC blocks to write + * @param Timeout: Specify timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout) { SDMMC_DataInitTypeDef config; - uint32_t errorstate = HAL_MMC_ERROR_NONE; + uint32_t errorstate; uint32_t tickstart = HAL_GetTick(); - uint32_t count = 0; - uint32_t *tempbuff = (uint32_t *)pData; + uint32_t count, data, dataremaining; + uint32_t add = BlockAdd; + uint8_t *tempbuff = pData; if(NULL == pData) { @@ -735,7 +778,7 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, u if(hmmc->State == HAL_MMC_STATE_READY) { - hmmc->ErrorCode = HAL_DMA_ERROR_NONE; + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) { @@ -746,16 +789,15 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, u hmmc->State = HAL_MMC_STATE_BUSY; /* Initialize data control register */ - hmmc->Instance->DCTRL = 0; + hmmc->Instance->DCTRL = 0U; - /* Check the Card capacity in term of Logical number of blocks */ - if ((hmmc->MmcCard.LogBlockNbr) < CAPACITY) + if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD) { - BlockAdd *= 512; + add *= 512U; } /* Set Block Size for Card */ - errorstate = SDMMC_CmdBlockLength(hmmc->Instance, BLOCKSIZE); + errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE); if(errorstate != HAL_MMC_ERROR_NONE) { /* Clear all the static flags */ @@ -771,14 +813,14 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, u hmmc->Context = MMC_CONTEXT_WRITE_MULTIPLE_BLOCK; /* Write Multi Block command */ - errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, BlockAdd); + errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, add); } else { hmmc->Context = MMC_CONTEXT_WRITE_SINGLE_BLOCK; /* Write Single Block command */ - errorstate = SDMMC_CmdWriteSingleBlock(hmmc->Instance, BlockAdd); + errorstate = SDMMC_CmdWriteSingleBlock(hmmc->Instance, add); } if(errorstate != HAL_MMC_ERROR_NONE) { @@ -791,27 +833,39 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, u /* Configure the MMC DPSM (Data Path State Machine) */ config.DataTimeOut = SDMMC_DATATIMEOUT; - config.DataLength = NumberOfBlocks * BLOCKSIZE; + config.DataLength = NumberOfBlocks * MMC_BLOCKSIZE; config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; config.DPSM = SDMMC_DPSM_ENABLE; - SDMMC_ConfigData(hmmc->Instance, &config); + (void)SDMMC_ConfigData(hmmc->Instance, &config); /* Write block(s) in polling mode */ + dataremaining = config.DataLength; while(!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) { - if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE)) + if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) && (dataremaining > 0U)) { /* Write data to SDMMC Tx FIFO */ for(count = 0U; count < 8U; count++) { - SDMMC_WriteFIFO(hmmc->Instance, (tempbuff + count)); + data = (uint32_t)(*tempbuff); + tempbuff++; + dataremaining--; + data |= ((uint32_t)(*tempbuff) << 8U); + tempbuff++; + dataremaining--; + data |= ((uint32_t)(*tempbuff) << 16U); + tempbuff++; + dataremaining--; + data |= ((uint32_t)(*tempbuff) << 24U); + tempbuff++; + dataremaining--; + (void)SDMMC_WriteFIFO(hmmc->Instance, &data); } - tempbuff += 8U; } - if((Timeout == 0U)||((HAL_GetTick()-tickstart) >= Timeout)) + if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U)) { /* Clear all the static flags */ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); @@ -861,9 +915,13 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, u hmmc->State = HAL_MMC_STATE_READY; return HAL_ERROR; } + else + { + /* Nothing to do */ + } /* Clear all the static flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); hmmc->State = HAL_MMC_STATE_READY; @@ -883,16 +941,17 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, u * HAL_MMC_GetCardState(). * @note You could also check the IT transfer process through the MMC Rx * interrupt event. - * @param hmmc Pointer to MMC handle - * @param pData Pointer to the buffer that will contain the received data - * @param BlockAdd Block Address from where data is to be read - * @param NumberOfBlocks Number of blocks to read. + * @param hmmc: Pointer to MMC handle + * @param pData: Pointer to the buffer that will contain the received data + * @param BlockAdd: Block Address from where data is to be read + * @param NumberOfBlocks: Number of blocks to read. * @retval HAL status */ HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) { SDMMC_DataInitTypeDef config; - uint32_t errorstate = HAL_MMC_ERROR_NONE; + uint32_t errorstate; + uint32_t add = BlockAdd; if(NULL == pData) { @@ -902,7 +961,7 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, if(hmmc->State == HAL_MMC_STATE_READY) { - hmmc->ErrorCode = HAL_DMA_ERROR_NONE; + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) { @@ -915,28 +974,18 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, /* Initialize data control register */ hmmc->Instance->DCTRL = 0U; - hmmc->pRxBuffPtr = (uint32_t *)pData; - hmmc->RxXferSize = BLOCKSIZE * NumberOfBlocks; + hmmc->pRxBuffPtr = pData; + hmmc->RxXferSize = MMC_BLOCKSIZE * NumberOfBlocks; __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND | SDMMC_FLAG_RXFIFOHF)); - /* Check the Card capacity in term of Logical number of blocks */ - if ((hmmc->MmcCard.LogBlockNbr) < CAPACITY) + if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD) { - BlockAdd *= 512; + add *= 512U; } - /* Configure the MMC DPSM (Data Path State Machine) */ - config.DataTimeOut = SDMMC_DATATIMEOUT; - config.DataLength = BLOCKSIZE * NumberOfBlocks; - config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; - config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; - config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; - config.DPSM = SDMMC_DPSM_ENABLE; - SDMMC_ConfigData(hmmc->Instance, &config); - /* Set Block Size for Card */ - errorstate = SDMMC_CmdBlockLength(hmmc->Instance, BLOCKSIZE); + errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE); if(errorstate != HAL_MMC_ERROR_NONE) { /* Clear all the static flags */ @@ -946,21 +995,31 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, return HAL_ERROR; } + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_ENABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); + /* Read Blocks in IT mode */ if(NumberOfBlocks > 1U) { hmmc->Context = (MMC_CONTEXT_READ_MULTIPLE_BLOCK | MMC_CONTEXT_IT); /* Read Multi Block command */ - errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, BlockAdd); + errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, add); } else { hmmc->Context = (MMC_CONTEXT_READ_SINGLE_BLOCK | MMC_CONTEXT_IT); /* Read Single Block command */ - errorstate = SDMMC_CmdReadSingleBlock(hmmc->Instance, BlockAdd); + errorstate = SDMMC_CmdReadSingleBlock(hmmc->Instance, add); } + if(errorstate != HAL_MMC_ERROR_NONE) { /* Clear all the static flags */ @@ -985,16 +1044,17 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, * HAL_MMC_GetCardState(). * @note You could also check the IT transfer process through the MMC Tx * interrupt event. - * @param hmmc Pointer to MMC handle - * @param pData Pointer to the buffer that will contain the data to transmit - * @param BlockAdd Block Address where data will be written - * @param NumberOfBlocks Number of blocks to write + * @param hmmc: Pointer to MMC handle + * @param pData: Pointer to the buffer that will contain the data to transmit + * @param BlockAdd: Block Address where data will be written + * @param NumberOfBlocks: Number of blocks to write * @retval HAL status */ HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) { SDMMC_DataInitTypeDef config; - uint32_t errorstate = HAL_MMC_ERROR_NONE; + uint32_t errorstate; + uint32_t add = BlockAdd; if(NULL == pData) { @@ -1004,7 +1064,7 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData if(hmmc->State == HAL_MMC_STATE_READY) { - hmmc->ErrorCode = HAL_DMA_ERROR_NONE; + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) { @@ -1017,20 +1077,19 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData /* Initialize data control register */ hmmc->Instance->DCTRL = 0U; - hmmc->pTxBuffPtr = (uint32_t *)pData; - hmmc->TxXferSize = BLOCKSIZE * NumberOfBlocks; + hmmc->pTxBuffPtr = pData; + hmmc->TxXferSize = MMC_BLOCKSIZE * NumberOfBlocks; /* Enable transfer interrupts */ __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | SDMMC_FLAG_TXFIFOHE)); - /* Check the Card capacity in term of Logical number of blocks */ - if ((hmmc->MmcCard.LogBlockNbr) < CAPACITY) + if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD) { - BlockAdd *= 512; + add *= 512U; } /* Set Block Size for Card */ - errorstate = SDMMC_CmdBlockLength(hmmc->Instance, BLOCKSIZE); + errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE); if(errorstate != HAL_MMC_ERROR_NONE) { /* Clear all the static flags */ @@ -1046,14 +1105,14 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData hmmc->Context = (MMC_CONTEXT_WRITE_MULTIPLE_BLOCK| MMC_CONTEXT_IT); /* Write Multi Block command */ - errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, BlockAdd); + errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, add); } else { hmmc->Context = (MMC_CONTEXT_WRITE_SINGLE_BLOCK | MMC_CONTEXT_IT); /* Write Single Block command */ - errorstate = SDMMC_CmdWriteSingleBlock(hmmc->Instance, BlockAdd); + errorstate = SDMMC_CmdWriteSingleBlock(hmmc->Instance, add); } if(errorstate != HAL_MMC_ERROR_NONE) { @@ -1066,12 +1125,12 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData /* Configure the MMC DPSM (Data Path State Machine) */ config.DataTimeOut = SDMMC_DATATIMEOUT; - config.DataLength = BLOCKSIZE * NumberOfBlocks; + config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks; config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; config.DPSM = SDMMC_DPSM_ENABLE; - SDMMC_ConfigData(hmmc->Instance, &config); + (void)SDMMC_ConfigData(hmmc->Instance, &config); return HAL_OK; } @@ -1088,16 +1147,17 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData * HAL_MMC_GetCardState(). * @note You could also check the DMA transfer process through the MMC Rx * interrupt event. - * @param hmmc Pointer MMC handle - * @param pData Pointer to the buffer that will contain the received data - * @param BlockAdd Block Address from where data is to be read - * @param NumberOfBlocks Number of blocks to read. + * @param hmmc: Pointer MMC handle + * @param pData: Pointer to the buffer that will contain the received data + * @param BlockAdd: Block Address from where data is to be read + * @param NumberOfBlocks: Number of blocks to read. * @retval HAL status */ HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) { SDMMC_DataInitTypeDef config; - uint32_t errorstate = HAL_MMC_ERROR_NONE; + uint32_t errorstate; + uint32_t add = BlockAdd; if(NULL == pData) { @@ -1131,63 +1191,72 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData /* Set the DMA Abort callback */ hmmc->hdmarx->XferAbortCallback = NULL; - /* Enable the DMA Channel */ - HAL_DMA_Start_IT(hmmc->hdmarx, (uint32_t)&hmmc->Instance->FIFO, (uint32_t)pData, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4); - - /* Enable MMC DMA transfer */ - __HAL_MMC_DMA_ENABLE(hmmc); - - /* Check the Card capacity in term of Logical number of blocks */ - if ((hmmc->MmcCard.LogBlockNbr) < CAPACITY) + if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD) { - BlockAdd *= 512; + add *= 512U; } - /* Configure the MMC DPSM (Data Path State Machine) */ - config.DataTimeOut = SDMMC_DATATIMEOUT; - config.DataLength = BLOCKSIZE * NumberOfBlocks; - config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; - config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; - config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; - config.DPSM = SDMMC_DPSM_ENABLE; - SDMMC_ConfigData(hmmc->Instance, &config); - /* Set Block Size for Card */ - errorstate = SDMMC_CmdBlockLength(hmmc->Instance, BLOCKSIZE); + errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE); if(errorstate != HAL_MMC_ERROR_NONE) { /* Clear all the static flags */ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); - hmmc->ErrorCode |= errorstate; + hmmc->ErrorCode = errorstate; hmmc->State = HAL_MMC_STATE_READY; return HAL_ERROR; } - /* Read Blocks in DMA mode */ - if(NumberOfBlocks > 1U) - { - hmmc->Context = (MMC_CONTEXT_READ_MULTIPLE_BLOCK | MMC_CONTEXT_DMA); - - /* Read Multi Block command */ - errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, BlockAdd); - } - else - { - hmmc->Context = (MMC_CONTEXT_READ_SINGLE_BLOCK | MMC_CONTEXT_DMA); - - /* Read Single Block command */ - errorstate = SDMMC_CmdReadSingleBlock(hmmc->Instance, BlockAdd); - } - if(errorstate != HAL_MMC_ERROR_NONE) + /* Enable the DMA Channel */ + if(HAL_DMA_Start_IT(hmmc->hdmarx, (uint32_t)&hmmc->Instance->FIFO, (uint32_t)pData, (uint32_t)(MMC_BLOCKSIZE * NumberOfBlocks)/4) != HAL_OK) { - /* Clear all the static flags */ + __HAL_MMC_DISABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND)); __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); - hmmc->ErrorCode |= errorstate; + hmmc->ErrorCode = HAL_MMC_ERROR_DMA; hmmc->State = HAL_MMC_STATE_READY; return HAL_ERROR; } + else + { + /* Enable MMC DMA transfer */ + __HAL_MMC_DMA_ENABLE(hmmc); - return HAL_OK; + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_ENABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); + + /* Read Blocks in DMA mode */ + if(NumberOfBlocks > 1U) + { + hmmc->Context = (MMC_CONTEXT_READ_MULTIPLE_BLOCK | MMC_CONTEXT_DMA); + + /* Read Multi Block command */ + errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, add); + } + else + { + hmmc->Context = (MMC_CONTEXT_READ_SINGLE_BLOCK | MMC_CONTEXT_DMA); + + /* Read Single Block command */ + errorstate = SDMMC_CmdReadSingleBlock(hmmc->Instance, add); + } + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + __HAL_MMC_DISABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND)); + hmmc->ErrorCode = errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + return HAL_OK; + } } else { @@ -1202,16 +1271,17 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData * HAL_MMC_GetCardState(). * @note You could also check the DMA transfer process through the MMC Tx * interrupt event. - * @param hmmc Pointer to MMC handle - * @param pData Pointer to the buffer that will contain the data to transmit - * @param BlockAdd Block Address where data will be written - * @param NumberOfBlocks Number of blocks to write + * @param hmmc: Pointer to MMC handle + * @param pData: Pointer to the buffer that will contain the data to transmit + * @param BlockAdd: Block Address where data will be written + * @param NumberOfBlocks: Number of blocks to write * @retval HAL status */ HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) { SDMMC_DataInitTypeDef config; - uint32_t errorstate = HAL_MMC_ERROR_NONE; + uint32_t errorstate; + uint32_t add = BlockAdd; if(NULL == pData) { @@ -1221,7 +1291,7 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pDat if(hmmc->State == HAL_MMC_STATE_READY) { - hmmc->ErrorCode = HAL_DMA_ERROR_NONE; + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) { @@ -1235,7 +1305,7 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pDat hmmc->Instance->DCTRL = 0U; /* Enable MMC Error interrupts */ - __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR)); + __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR)); /* Set the DMA transfer complete callback */ hmmc->hdmatx->XferCpltCallback = MMC_DMATransmitCplt; @@ -1246,14 +1316,13 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pDat /* Set the DMA Abort callback */ hmmc->hdmatx->XferAbortCallback = NULL; - /* Check the Card capacity in term of Logical number of blocks */ - if ((hmmc->MmcCard.LogBlockNbr) < CAPACITY) + if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD) { - BlockAdd *= 512; + add *= 512U; } /* Set Block Size for Card */ - errorstate = SDMMC_CmdBlockLength(hmmc->Instance, BLOCKSIZE); + errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE); if(errorstate != HAL_MMC_ERROR_NONE) { /* Clear all the static flags */ @@ -1269,19 +1338,20 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pDat hmmc->Context = (MMC_CONTEXT_WRITE_MULTIPLE_BLOCK | MMC_CONTEXT_DMA); /* Write Multi Block command */ - errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, BlockAdd); + errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, add); } else { hmmc->Context = (MMC_CONTEXT_WRITE_SINGLE_BLOCK | MMC_CONTEXT_DMA); /* Write Single Block command */ - errorstate = SDMMC_CmdWriteSingleBlock(hmmc->Instance, BlockAdd); + errorstate = SDMMC_CmdWriteSingleBlock(hmmc->Instance, add); } if(errorstate != HAL_MMC_ERROR_NONE) { /* Clear all the static flags */ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + __HAL_MMC_DISABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND)); hmmc->ErrorCode |= errorstate; hmmc->State = HAL_MMC_STATE_READY; return HAL_ERROR; @@ -1291,18 +1361,27 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pDat __HAL_MMC_DMA_ENABLE(hmmc); /* Enable the DMA Channel */ - HAL_DMA_Start_IT(hmmc->hdmatx, (uint32_t)pData, (uint32_t)&hmmc->Instance->FIFO, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4); - - /* Configure the MMC DPSM (Data Path State Machine) */ - config.DataTimeOut = SDMMC_DATATIMEOUT; - config.DataLength = BLOCKSIZE * NumberOfBlocks; - config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; - config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; - config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; - config.DPSM = SDMMC_DPSM_ENABLE; - SDMMC_ConfigData(hmmc->Instance, &config); + if(HAL_DMA_Start_IT(hmmc->hdmatx, (uint32_t)pData, (uint32_t)&hmmc->Instance->FIFO, (uint32_t)(MMC_BLOCKSIZE * NumberOfBlocks)/4) != HAL_OK) + { + __HAL_MMC_DISABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND)); + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DMA; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else + { + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_ENABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); - return HAL_OK; + return HAL_OK; + } } else { @@ -1314,26 +1393,28 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pDat * @brief Erases the specified memory area of the given MMC card. * @note This API should be followed by a check on the card state through * HAL_MMC_GetCardState(). - * @param hmmc Pointer to MMC handle - * @param BlockStartAdd Start Block address - * @param BlockEndAdd End Block address + * @param hmmc: Pointer to MMC handle + * @param BlockStartAdd: Start Block address + * @param BlockEndAdd: End Block address * @retval HAL status */ HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, uint32_t BlockEndAdd) { - uint32_t errorstate = HAL_MMC_ERROR_NONE; + uint32_t errorstate; + uint32_t start_add = BlockStartAdd; + uint32_t end_add = BlockEndAdd; if(hmmc->State == HAL_MMC_STATE_READY) { - hmmc->ErrorCode = HAL_DMA_ERROR_NONE; + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; - if(BlockEndAdd < BlockStartAdd) + if(end_add < start_add) { hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; return HAL_ERROR; } - if(BlockEndAdd > (hmmc->MmcCard.LogBlockNbr)) + if(end_add > (hmmc->MmcCard.LogBlockNbr)) { hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; return HAL_ERROR; @@ -1360,15 +1441,14 @@ HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, return HAL_ERROR; } - /* Check the Card capacity in term of Logical number of blocks */ - if ((hmmc->MmcCard.LogBlockNbr) < CAPACITY) + if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD) { - BlockStartAdd *= 512U; - BlockEndAdd *= 512U; + start_add *= 512U; + end_add *= 512U; } /* Send CMD35 MMC_ERASE_GRP_START with argument as addr */ - errorstate = SDMMC_CmdEraseStartAdd(hmmc->Instance, BlockStartAdd); + errorstate = SDMMC_CmdEraseStartAdd(hmmc->Instance, start_add); if(errorstate != HAL_MMC_ERROR_NONE) { /* Clear all the static flags */ @@ -1379,7 +1459,7 @@ HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, } /* Send CMD36 MMC_ERASE_GRP_END with argument as addr */ - errorstate = SDMMC_CmdEraseEndAdd(hmmc->Instance, BlockEndAdd); + errorstate = SDMMC_CmdEraseEndAdd(hmmc->Instance, end_add); if(errorstate != HAL_MMC_ERROR_NONE) { /* Clear all the static flags */ @@ -1412,132 +1492,149 @@ HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, /** * @brief This function handles MMC card interrupt request. - * @param hmmc Pointer to MMC handle + * @param hmmc: Pointer to MMC handle * @retval None */ void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc) { - uint32_t errorstate = HAL_MMC_ERROR_NONE; + uint32_t errorstate; + uint32_t context = hmmc->Context; /* Check for SDMMC interrupt flags */ - if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_DATAEND) != RESET) + if((__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) != RESET) && ((context & MMC_CONTEXT_IT) != 0U)) + { + MMC_Read_IT(hmmc); + } + + else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DATAEND) != RESET) { __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_DATAEND); - __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\ - SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR); + __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT |\ + SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR | SDMMC_IT_TXFIFOHE |\ + SDMMC_IT_RXFIFOHF); + + hmmc->Instance->DCTRL &= ~(SDMMC_DCTRL_DTEN); - if((hmmc->Context & MMC_CONTEXT_IT) != RESET) + if((context & MMC_CONTEXT_DMA) != 0U) { - if(((hmmc->Context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != RESET) || ((hmmc->Context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != RESET)) + if((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U) { errorstate = SDMMC_CmdStopTransfer(hmmc->Instance); if(errorstate != HAL_MMC_ERROR_NONE) { hmmc->ErrorCode |= errorstate; -#if (USE_HAL_MMC_REGISTER_CALLBACKS == 1) +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) hmmc->ErrorCallback(hmmc); #else HAL_MMC_ErrorCallback(hmmc); #endif } } + if(((context & MMC_CONTEXT_READ_SINGLE_BLOCK) == 0U) && ((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) == 0U)) + { + /* Disable the DMA transfer for transmit request by setting the DMAEN bit + in the MMC DCTRL register */ + hmmc->Instance->DCTRL &= (uint32_t)~((uint32_t)SDMMC_DCTRL_DMAEN); - /* Clear all the static flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->State = HAL_MMC_STATE_READY; - hmmc->State = HAL_MMC_STATE_READY; - if(((hmmc->Context & MMC_CONTEXT_READ_SINGLE_BLOCK) != RESET) || ((hmmc->Context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != RESET)) - { -#if (USE_HAL_MMC_REGISTER_CALLBACKS == 1) - hmmc->RxCpltCallback(hmmc); -#else - HAL_MMC_RxCpltCallback(hmmc); -#endif - } - else - { -#if (USE_HAL_MMC_REGISTER_CALLBACKS == 1) +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) hmmc->TxCpltCallback(hmmc); #else HAL_MMC_TxCpltCallback(hmmc); #endif } } - else if((hmmc->Context & MMC_CONTEXT_DMA) != RESET) + else if((context & MMC_CONTEXT_IT) != 0U) { - if((hmmc->Context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != RESET) + /* Stop Transfer for Write Multi blocks or Read Multi blocks */ + if(((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)) { errorstate = SDMMC_CmdStopTransfer(hmmc->Instance); if(errorstate != HAL_MMC_ERROR_NONE) { hmmc->ErrorCode |= errorstate; -#if (USE_HAL_MMC_REGISTER_CALLBACKS == 1) +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) hmmc->ErrorCallback(hmmc); #else HAL_MMC_ErrorCallback(hmmc); #endif } } - if(((hmmc->Context & MMC_CONTEXT_READ_SINGLE_BLOCK) == RESET) && ((hmmc->Context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) == RESET)) - { - /* Disable the DMA transfer for transmit request by setting the DMAEN bit - in the MMC DCTRL register */ - hmmc->Instance->DCTRL &= (uint32_t)~((uint32_t)SDMMC_DCTRL_DMAEN); - hmmc->State = HAL_MMC_STATE_READY; + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); -#if (USE_HAL_MMC_REGISTER_CALLBACKS == 1) + hmmc->State = HAL_MMC_STATE_READY; + if(((context & MMC_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U)) + { +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) + hmmc->RxCpltCallback(hmmc); +#else + HAL_MMC_RxCpltCallback(hmmc); +#endif + } + else + { +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) hmmc->TxCpltCallback(hmmc); #else HAL_MMC_TxCpltCallback(hmmc); #endif } } + else + { + /* Nothing to do */ + } } - else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_TXFIFOHE) != RESET) + else if((__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) != RESET) && ((context & MMC_CONTEXT_IT) != 0U)) { - __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE); - MMC_Write_IT(hmmc); } - else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_RXFIFOHF) != RESET) - { - __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF); - - MMC_Read_IT(hmmc); - } - - else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_TXUNDERR) != RESET) + else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_RXOVERR | SDMMC_FLAG_TXUNDERR) != RESET) { /* Set Error code */ - if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_DCRCFAIL) != RESET) + if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL) != RESET) { hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL; } - if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_DTIMEOUT) != RESET) + if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT) != RESET) { hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT; } - if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_RXOVERR) != RESET) + if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR) != RESET) { hmmc->ErrorCode |= HAL_MMC_ERROR_RX_OVERRUN; } - if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_TXUNDERR) != RESET) + if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXUNDERR) != RESET) { hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN; } /* Clear All flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); /* Disable all interrupts */ __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\ SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR); - if((hmmc->Context & MMC_CONTEXT_DMA) != RESET) + hmmc->ErrorCode |= SDMMC_CmdStopTransfer(hmmc->Instance); + + if((context & MMC_CONTEXT_IT) != 0U) + { + /* Set the MMC state to ready to be able to start again the process */ + hmmc->State = HAL_MMC_STATE_READY; +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) + hmmc->ErrorCallback(hmmc); +#else + HAL_MMC_ErrorCallback(hmmc); +#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */ + } + else if((context & MMC_CONTEXT_DMA) != 0U) { /* Abort the MMC DMA Streams */ if(hmmc->hdmatx != NULL) @@ -1564,29 +1661,28 @@ void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc) { hmmc->ErrorCode = HAL_MMC_ERROR_NONE; hmmc->State = HAL_MMC_STATE_READY; -#if (USE_HAL_MMC_REGISTER_CALLBACKS == 1) +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) hmmc->AbortCpltCallback(hmmc); #else HAL_MMC_AbortCallback(hmmc); #endif } } - else if((hmmc->Context & MMC_CONTEXT_IT) != RESET) + else { - /* Set the MMC state to ready to be able to start again the process */ - hmmc->State = HAL_MMC_STATE_READY; -#if (USE_HAL_MMC_REGISTER_CALLBACKS == 1) - hmmc->ErrorCallback(hmmc); -#else - HAL_MMC_ErrorCallback(hmmc); -#endif + /* Nothing to do */ } } + + else + { + /* Nothing to do */ + } } /** * @brief return the MMC state - * @param hmmc Pointer to mmc handle + * @param hmmc: Pointer to mmc handle * @retval HAL state */ HAL_MMC_StateTypeDef HAL_MMC_GetState(MMC_HandleTypeDef *hmmc) @@ -1596,7 +1692,7 @@ HAL_MMC_StateTypeDef HAL_MMC_GetState(MMC_HandleTypeDef *hmmc) /** * @brief Return the MMC error code -* @param hmmc Pointer to a MMC_HandleTypeDef structure that contains +* @param hmmc : Pointer to a MMC_HandleTypeDef structure that contains * the configuration information. * @retval MMC Error Code */ @@ -1607,10 +1703,10 @@ uint32_t HAL_MMC_GetError(MMC_HandleTypeDef *hmmc) /** * @brief Tx Transfer completed callbacks - * @param hmmc Pointer to MMC handle + * @param hmmc: Pointer to MMC handle * @retval None */ - __weak void HAL_MMC_TxCpltCallback(MMC_HandleTypeDef *hmmc) +__weak void HAL_MMC_TxCpltCallback(MMC_HandleTypeDef *hmmc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hmmc); @@ -1622,7 +1718,7 @@ uint32_t HAL_MMC_GetError(MMC_HandleTypeDef *hmmc) /** * @brief Rx Transfer completed callbacks - * @param hmmc Pointer MMC handle + * @param hmmc: Pointer MMC handle * @retval None */ __weak void HAL_MMC_RxCpltCallback(MMC_HandleTypeDef *hmmc) @@ -1637,7 +1733,7 @@ __weak void HAL_MMC_RxCpltCallback(MMC_HandleTypeDef *hmmc) /** * @brief MMC error callbacks - * @param hmmc Pointer MMC handle + * @param hmmc: Pointer MMC handle * @retval None */ __weak void HAL_MMC_ErrorCallback(MMC_HandleTypeDef *hmmc) @@ -1652,7 +1748,7 @@ __weak void HAL_MMC_ErrorCallback(MMC_HandleTypeDef *hmmc) /** * @brief MMC Abort callbacks - * @param hmmc Pointer MMC handle + * @param hmmc: Pointer MMC handle * @retval None */ __weak void HAL_MMC_AbortCallback(MMC_HandleTypeDef *hmmc) @@ -1661,16 +1757,16 @@ __weak void HAL_MMC_AbortCallback(MMC_HandleTypeDef *hmmc) UNUSED(hmmc); /* NOTE : This function should not be modified, when the callback is needed, - the HAL_MMC_ErrorCallback can be implemented in the user file + the HAL_MMC_AbortCallback can be implemented in the user file */ } -#if (USE_HAL_MMC_REGISTER_CALLBACKS == 1) +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) /** * @brief Register a User MMC Callback * To be used instead of the weak (surcharged) predefined callback * @param hmmc : MMC handle - * @param CallbackID : ID of the callback to be registered + * @param CallbackId : ID of the callback to be registered * This parameter can be one of the following values: * @arg @ref HAL_MMC_TX_CPLT_CB_ID MMC Tx Complete Callback ID * @arg @ref HAL_MMC_RX_CPLT_CB_ID MMC Rx Complete Callback ID @@ -1760,7 +1856,7 @@ HAL_StatusTypeDef HAL_MMC_RegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_Call * @brief Unregister a User MMC Callback * MMC Callback is redirected to the weak (surcharged) predefined callback * @param hmmc : MMC handle - * @param CallbackID : ID of the callback to be unregistered + * @param CallbackId : ID of the callback to be unregistered * This parameter can be one of the following values: * @arg @ref HAL_MMC_TX_CPLT_CB_ID MMC Tx Complete Callback ID * @arg @ref HAL_MMC_RX_CPLT_CB_ID MMC Rx Complete Callback ID @@ -1839,7 +1935,6 @@ HAL_StatusTypeDef HAL_MMC_UnRegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_Ca } #endif - /** * @} */ @@ -1862,80 +1957,32 @@ HAL_StatusTypeDef HAL_MMC_UnRegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_Ca /** * @brief Returns information the information of the card which are stored on * the CID register. - * @param hmmc Pointer to MMC handle - * @param pCID Pointer to a HAL_MMC_CIDTypedef structure that + * @param hmmc: Pointer to MMC handle + * @param pCID: Pointer to a HAL_MMC_CIDTypedef structure that * contains all CID register parameters * @retval HAL status */ HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID) { - uint32_t tmp = 0; - - /* Byte 0 */ - tmp = (uint8_t)((hmmc->CID[0] & 0xFF000000U) >> 24); - pCID->ManufacturerID = tmp; - - /* Byte 1 */ - tmp = (uint8_t)((hmmc->CID[0] & 0x00FF0000) >> 16); - pCID->OEM_AppliID = tmp << 8; - - /* Byte 2 */ - tmp = (uint8_t)((hmmc->CID[0] & 0x000000FF00) >> 8); - pCID->OEM_AppliID |= tmp; - - /* Byte 3 */ - tmp = (uint8_t)(hmmc->CID[0] & 0x000000FF); - pCID->ProdName1 = tmp << 24; - - /* Byte 4 */ - tmp = (uint8_t)((hmmc->CID[1] & 0xFF000000U) >> 24); - pCID->ProdName1 |= tmp << 16; - - /* Byte 5 */ - tmp = (uint8_t)((hmmc->CID[1] & 0x00FF0000) >> 16); - pCID->ProdName1 |= tmp << 8; + pCID->ManufacturerID = (uint8_t)((hmmc->CID[0] & 0xFF000000U) >> 24U); - /* Byte 6 */ - tmp = (uint8_t)((hmmc->CID[1] & 0x0000FF00) >> 8); - pCID->ProdName1 |= tmp; + pCID->OEM_AppliID = (uint16_t)((hmmc->CID[0] & 0x00FFFF00U) >> 8U); - /* Byte 7 */ - tmp = (uint8_t)(hmmc->CID[1] & 0x000000FF); - pCID->ProdName2 = tmp; + pCID->ProdName1 = (((hmmc->CID[0] & 0x000000FFU) << 24U) | ((hmmc->CID[1] & 0xFFFFFF00U) >> 8U)); - /* Byte 8 */ - tmp = (uint8_t)((hmmc->CID[2] & 0xFF000000U) >> 24); - pCID->ProdRev = tmp; + pCID->ProdName2 = (uint8_t)(hmmc->CID[1] & 0x000000FFU); - /* Byte 9 */ - tmp = (uint8_t)((hmmc->CID[2] & 0x00FF0000) >> 16); - pCID->ProdSN = tmp << 24; + pCID->ProdRev = (uint8_t)((hmmc->CID[2] & 0xFF000000U) >> 24U); - /* Byte 10 */ - tmp = (uint8_t)((hmmc->CID[2] & 0x0000FF00) >> 8); - pCID->ProdSN |= tmp << 16; + pCID->ProdSN = (((hmmc->CID[2] & 0x00FFFFFFU) << 8U) | ((hmmc->CID[3] & 0xFF000000U) >> 24U)); - /* Byte 11 */ - tmp = (uint8_t)(hmmc->CID[2] & 0x000000FF); - pCID->ProdSN |= tmp << 8; + pCID->Reserved1 = (uint8_t)((hmmc->CID[3] & 0x00F00000U) >> 20U); - /* Byte 12 */ - tmp = (uint8_t)((hmmc->CID[3] & 0xFF000000U) >> 24); - pCID->ProdSN |= tmp; + pCID->ManufactDate = (uint16_t)((hmmc->CID[3] & 0x000FFF00U) >> 8U); - /* Byte 13 */ - tmp = (uint8_t)((hmmc->CID[3] & 0x00FF0000) >> 16); - pCID->Reserved1 |= (tmp & 0xF0) >> 4; - pCID->ManufactDate = (tmp & 0x0F) << 8; + pCID->CID_CRC = (uint8_t)((hmmc->CID[3] & 0x000000FEU) >> 1U); - /* Byte 14 */ - tmp = (uint8_t)((hmmc->CID[3] & 0x0000FF00) >> 8); - pCID->ManufactDate |= tmp; - - /* Byte 15 */ - tmp = (uint8_t)(hmmc->CID[3] & 0x000000FF); - pCID->CID_CRC = (tmp & 0xFE) >> 1; - pCID->Reserved2 = 1; + pCID->Reserved2 = 1U; return HAL_OK; } @@ -1943,113 +1990,92 @@ HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTyp /** * @brief Returns information the information of the card which are stored on * the CSD register. - * @param hmmc Pointer to MMC handle - * @param pCSD Pointer to a HAL_MMC_CardInfoTypeDef structure that + * @param hmmc: Pointer to MMC handle + * @param pCSD: Pointer to a HAL_MMC_CardCSDTypeDef structure that * contains all CSD register parameters * @retval HAL status */ HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD) { - uint32_t tmp = 0; - - /* Byte 0 */ - tmp = (hmmc->CSD[0] & 0xFF000000U) >> 24; - pCSD->CSDStruct = (uint8_t)((tmp & 0xC0) >> 6); - pCSD->SysSpecVersion = (uint8_t)((tmp & 0x3C) >> 2); - pCSD->Reserved1 = tmp & 0x03; - - /* Byte 1 */ - tmp = (hmmc->CSD[0] & 0x00FF0000) >> 16; - pCSD->TAAC = (uint8_t)tmp; - - /* Byte 2 */ - tmp = (hmmc->CSD[0] & 0x0000FF00) >> 8; - pCSD->NSAC = (uint8_t)tmp; - - /* Byte 3 */ - tmp = hmmc->CSD[0] & 0x000000FF; - pCSD->MaxBusClkFrec = (uint8_t)tmp; - - /* Byte 4 */ - tmp = (hmmc->CSD[1] & 0xFF000000U) >> 24; - pCSD->CardComdClasses = (uint16_t)(tmp << 4); - - /* Byte 5 */ - tmp = (hmmc->CSD[1] & 0x00FF0000U) >> 16; - pCSD->CardComdClasses |= (uint16_t)((tmp & 0xF0) >> 4); - pCSD->RdBlockLen = (uint8_t)(tmp & 0x0F); - - /* Byte 6 */ - tmp = (hmmc->CSD[1] & 0x0000FF00U) >> 8; - pCSD->PartBlockRead = (uint8_t)((tmp & 0x80) >> 7); - pCSD->WrBlockMisalign = (uint8_t)((tmp & 0x40) >> 6); - pCSD->RdBlockMisalign = (uint8_t)((tmp & 0x20) >> 5); - pCSD->DSRImpl = (uint8_t)((tmp & 0x10) >> 4); - pCSD->Reserved2 = 0; /*!< Reserved */ - - pCSD->DeviceSize = (tmp & 0x03) << 10; - - /* Byte 7 */ - tmp = (uint8_t)(hmmc->CSD[1] & 0x000000FFU); - pCSD->DeviceSize |= (tmp) << 2; - - /* Byte 8 */ - tmp = (uint8_t)((hmmc->CSD[2] & 0xFF000000U) >> 24); - pCSD->DeviceSize |= (tmp & 0xC0) >> 6; - - pCSD->MaxRdCurrentVDDMin = (tmp & 0x38) >> 3; - pCSD->MaxRdCurrentVDDMax = (tmp & 0x07); - - /* Byte 9 */ - tmp = (uint8_t)((hmmc->CSD[2] & 0x00FF0000U) >> 16); - pCSD->MaxWrCurrentVDDMin = (tmp & 0xE0) >> 5; - pCSD->MaxWrCurrentVDDMax = (tmp & 0x1C) >> 2; - pCSD->DeviceSizeMul = (tmp & 0x03) << 1; - /* Byte 10 */ - tmp = (uint8_t)((hmmc->CSD[2] & 0x0000FF00U) >> 8); - pCSD->DeviceSizeMul |= (tmp & 0x80) >> 7; - - hmmc->MmcCard.BlockNbr = (pCSD->DeviceSize + 1) ; - hmmc->MmcCard.BlockNbr *= (1 << (pCSD->DeviceSizeMul + 2)); - hmmc->MmcCard.BlockSize = 1 << (pCSD->RdBlockLen); - - hmmc->MmcCard.LogBlockNbr = (hmmc->MmcCard.BlockNbr) * ((hmmc->MmcCard.BlockSize) / 512); - hmmc->MmcCard.LogBlockSize = 512; - - pCSD->EraseGrSize = (tmp & 0x40) >> 6; - pCSD->EraseGrMul = (tmp & 0x3F) << 1; - - /* Byte 11 */ - tmp = (uint8_t)(hmmc->CSD[2] & 0x000000FF); - pCSD->EraseGrMul |= (tmp & 0x80) >> 7; - pCSD->WrProtectGrSize = (tmp & 0x7F); - - /* Byte 12 */ - tmp = (uint8_t)((hmmc->CSD[3] & 0xFF000000U) >> 24); - pCSD->WrProtectGrEnable = (tmp & 0x80) >> 7; - pCSD->ManDeflECC = (tmp & 0x60) >> 5; - pCSD->WrSpeedFact = (tmp & 0x1C) >> 2; - pCSD->MaxWrBlockLen = (tmp & 0x03) << 2; - - /* Byte 13 */ - tmp = (uint8_t)((hmmc->CSD[3] & 0x00FF0000) >> 16); - pCSD->MaxWrBlockLen |= (tmp & 0xC0) >> 6; - pCSD->WriteBlockPaPartial = (tmp & 0x20) >> 5; - pCSD->Reserved3 = 0; - pCSD->ContentProtectAppli = (tmp & 0x01); - - /* Byte 14 */ - tmp = (uint8_t)((hmmc->CSD[3] & 0x0000FF00) >> 8); - pCSD->FileFormatGrouop = (tmp & 0x80) >> 7; - pCSD->CopyFlag = (tmp & 0x40) >> 6; - pCSD->PermWrProtect = (tmp & 0x20) >> 5; - pCSD->TempWrProtect = (tmp & 0x10) >> 4; - pCSD->FileFormat = (tmp & 0x0C) >> 2; - pCSD->ECC = (tmp & 0x03); - - /* Byte 15 */ - tmp = (uint8_t)(hmmc->CSD[3] & 0x000000FF); - pCSD->CSD_CRC = (tmp & 0xFE) >> 1; + pCSD->CSDStruct = (uint8_t)((hmmc->CSD[0] & 0xC0000000U) >> 30U); + + pCSD->SysSpecVersion = (uint8_t)((hmmc->CSD[0] & 0x3C000000U) >> 26U); + + pCSD->Reserved1 = (uint8_t)((hmmc->CSD[0] & 0x03000000U) >> 24U); + + pCSD->TAAC = (uint8_t)((hmmc->CSD[0] & 0x00FF0000U) >> 16U); + + pCSD->NSAC = (uint8_t)((hmmc->CSD[0] & 0x0000FF00U) >> 8U); + + pCSD->MaxBusClkFrec = (uint8_t)(hmmc->CSD[0] & 0x000000FFU); + + pCSD->CardComdClasses = (uint16_t)((hmmc->CSD[1] & 0xFFF00000U) >> 20U); + + pCSD->RdBlockLen = (uint8_t)((hmmc->CSD[1] & 0x000F0000U) >> 16U); + + pCSD->PartBlockRead = (uint8_t)((hmmc->CSD[1] & 0x00008000U) >> 15U); + + pCSD->WrBlockMisalign = (uint8_t)((hmmc->CSD[1] & 0x00004000U) >> 14U); + + pCSD->RdBlockMisalign = (uint8_t)((hmmc->CSD[1] & 0x00002000U) >> 13U); + + pCSD->DSRImpl = (uint8_t)((hmmc->CSD[1] & 0x00001000U) >> 12U); + + pCSD->Reserved2 = 0U; /*!< Reserved */ + + pCSD->DeviceSize = (((hmmc->CSD[1] & 0x000003FFU) << 2U) | ((hmmc->CSD[2] & 0xC0000000U) >> 30U)); + + pCSD->MaxRdCurrentVDDMin = (uint8_t)((hmmc->CSD[2] & 0x38000000U) >> 27U); + + pCSD->MaxRdCurrentVDDMax = (uint8_t)((hmmc->CSD[2] & 0x07000000U) >> 24U); + + pCSD->MaxWrCurrentVDDMin = (uint8_t)((hmmc->CSD[2] & 0x00E00000U) >> 21U); + + pCSD->MaxWrCurrentVDDMax = (uint8_t)((hmmc->CSD[2] & 0x001C0000U) >> 18U); + + pCSD->DeviceSizeMul = (uint8_t)((hmmc->CSD[2] & 0x00038000U) >> 15U); + + hmmc->MmcCard.BlockNbr = (pCSD->DeviceSize + 1U) ; + hmmc->MmcCard.BlockNbr *= (1UL << ((pCSD->DeviceSizeMul & 0x07U) + 2U)); + hmmc->MmcCard.BlockSize = (1UL << (pCSD->RdBlockLen & 0x0FU)); + + hmmc->MmcCard.LogBlockNbr = (hmmc->MmcCard.BlockNbr) * ((hmmc->MmcCard.BlockSize) / 512U); + hmmc->MmcCard.LogBlockSize = 512U; + + pCSD->EraseGrSize = (uint8_t)((hmmc->CSD[2] & 0x00004000U) >> 14U); + + pCSD->EraseGrMul = (uint8_t)((hmmc->CSD[2] & 0x00003F80U) >> 7U); + + pCSD->WrProtectGrSize = (uint8_t)(hmmc->CSD[2] & 0x0000007FU); + + pCSD->WrProtectGrEnable = (uint8_t)((hmmc->CSD[3] & 0x80000000U) >> 31U); + + pCSD->ManDeflECC = (uint8_t)((hmmc->CSD[3] & 0x60000000U) >> 29U); + + pCSD->WrSpeedFact = (uint8_t)((hmmc->CSD[3] & 0x1C000000U) >> 26U); + + pCSD->MaxWrBlockLen= (uint8_t)((hmmc->CSD[3] & 0x03C00000U) >> 22U); + + pCSD->WriteBlockPaPartial = (uint8_t)((hmmc->CSD[3] & 0x00200000U) >> 21U); + + pCSD->Reserved3 = 0; + + pCSD->ContentProtectAppli = (uint8_t)((hmmc->CSD[3] & 0x00010000U) >> 16U); + + pCSD->FileFormatGroup = (uint8_t)((hmmc->CSD[3] & 0x00008000U) >> 15U); + + pCSD->CopyFlag = (uint8_t)((hmmc->CSD[3] & 0x00004000U) >> 14U); + + pCSD->PermWrProtect = (uint8_t)((hmmc->CSD[3] & 0x00002000U) >> 13U); + + pCSD->TempWrProtect = (uint8_t)((hmmc->CSD[3] & 0x00001000U) >> 12U); + + pCSD->FileFormat = (uint8_t)((hmmc->CSD[3] & 0x00000C00U) >> 10U); + + pCSD->ECC= (uint8_t)((hmmc->CSD[3] & 0x00000300U) >> 8U); + + pCSD->CSD_CRC = (uint8_t)((hmmc->CSD[3] & 0x000000FEU) >> 1U); + pCSD->Reserved4 = 1; return HAL_OK; @@ -2057,8 +2083,8 @@ HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTyp /** * @brief Gets the MMC card info. - * @param hmmc Pointer to MMC handle - * @param pCardInfo Pointer to the HAL_MMC_CardInfoTypeDef structure that + * @param hmmc: Pointer to MMC handle + * @param pCardInfo: Pointer to the HAL_MMC_CardInfoTypeDef structure that * will contain the MMC card status information * @retval HAL status */ @@ -2078,8 +2104,8 @@ HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoT /** * @brief Enables wide bus operation for the requested card if supported by * card. - * @param hmmc Pointer to MMC handle - * @param WideMode Specifies the MMC card wide bus mode + * @param hmmc: Pointer to MMC handle + * @param WideMode: Specifies the MMC card wide bus mode * This parameter can be one of the following values: * @arg SDMMC_BUS_WIDE_8B: 8-bit data transfer * @arg SDMMC_BUS_WIDE_4B: 4-bit data transfer @@ -2088,12 +2114,12 @@ HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoT */ HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32_t WideMode) { - __IO uint32_t count = 0; + __IO uint32_t count = 0U; SDMMC_InitTypeDef Init; - uint32_t errorstate = HAL_MMC_ERROR_NONE; - uint32_t response = 0, busy = 0; + uint32_t errorstate; + uint32_t response = 0U, busy = 0U; - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_SDMMC_BUS_WIDE(WideMode)); /* Chnage Satte */ @@ -2107,11 +2133,11 @@ HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32 Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE; Init.ClockDiv = SDMMC_INIT_CLK_DIV; /* Initialize SDMMC*/ - SDMMC_Init(hmmc->Instance, Init); + (void)SDMMC_Init(hmmc->Instance, Init); if(WideMode == SDMMC_BUS_WIDE_8B) { - errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70200); + errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70200U); if(errorstate != HAL_MMC_ERROR_NONE) { hmmc->ErrorCode |= errorstate; @@ -2119,7 +2145,7 @@ HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32 } else if(WideMode == SDMMC_BUS_WIDE_4B) { - errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70100); + errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70100U); if(errorstate != HAL_MMC_ERROR_NONE) { hmmc->ErrorCode |= errorstate; @@ -2127,7 +2153,7 @@ HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32 } else if(WideMode == SDMMC_BUS_WIDE_1B) { - errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70000); + errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70000U); if(errorstate != HAL_MMC_ERROR_NONE) { hmmc->ErrorCode |= errorstate; @@ -2140,17 +2166,18 @@ HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32 } /* Check for switch error and violation of the trial number of sending CMD 13 */ - while(busy == 0) + while(busy == 0U) { - if(count++ == SDMMC_MAX_TRIAL) + if(count == SDMMC_MAX_TRIAL) { hmmc->State = HAL_MMC_STATE_READY; hmmc->ErrorCode |= HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE; return HAL_ERROR; } + count++; /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ - errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16)); + errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); if(errorstate != HAL_MMC_ERROR_NONE) { hmmc->ErrorCode |= errorstate; @@ -2160,22 +2187,23 @@ HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32 response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1); /* Get operating voltage*/ - busy = (((response >> 7) == 1) ? 0 : 1); + busy = (((response >> 7U) == 1U) ? 0U : 1U); } /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ count = SDMMC_DATATIMEOUT; - while((response & 0x00000100) == 0) + while((response & 0x00000100U) == 0U) { - if(count-- == 0) + if(count == 0U) { hmmc->State = HAL_MMC_STATE_READY; hmmc->ErrorCode |= HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE; return HAL_ERROR; } + count--; /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ - errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16)); + errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); if(errorstate != HAL_MMC_ERROR_NONE) { hmmc->ErrorCode |= errorstate; @@ -2201,7 +2229,7 @@ HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32 Init.BusWide = WideMode; Init.HardwareFlowControl = hmmc->Init.HardwareFlowControl; Init.ClockDiv = hmmc->Init.ClockDiv; - SDMMC_Init(hmmc->Instance, Init); + (void)SDMMC_Init(hmmc->Instance, Init); } /* Change State */ @@ -2210,32 +2238,31 @@ HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32 return HAL_OK; } - /** * @brief Gets the current mmc card data state. - * @param hmmc pointer to MMC handle + * @param hmmc: pointer to MMC handle * @retval Card state */ HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc) { - HAL_MMC_CardStateTypeDef cardstate = HAL_MMC_CARD_TRANSFER; - uint32_t errorstate = HAL_MMC_ERROR_NONE; - uint32_t resp1 = 0; + uint32_t cardstate; + uint32_t errorstate; + uint32_t resp1 = 0U; errorstate = MMC_SendStatus(hmmc, &resp1); - if(errorstate != HAL_OK) + if(errorstate != HAL_MMC_ERROR_NONE) { hmmc->ErrorCode |= errorstate; } - cardstate = (HAL_MMC_CardStateTypeDef)((resp1 >> 9) & 0x0F); + cardstate = ((resp1 >> 9U) & 0x0FU); - return cardstate; + return (HAL_MMC_CardStateTypeDef)cardstate; } /** * @brief Abort the current transfer and disable the MMC. - * @param hmmc pointer to a MMC_HandleTypeDef structure that contains + * @param hmmc: pointer to a MMC_HandleTypeDef structure that contains * the configuration information for MMC module. * @retval HAL status */ @@ -2245,10 +2272,10 @@ HAL_StatusTypeDef HAL_MMC_Abort(MMC_HandleTypeDef *hmmc) /* DIsable All interrupts */ __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\ - SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR); + SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR); /* Clear All flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); if((hmmc->hdmatx != NULL) || (hmmc->hdmarx != NULL)) { @@ -2258,16 +2285,26 @@ HAL_StatusTypeDef HAL_MMC_Abort(MMC_HandleTypeDef *hmmc) /* Abort the MMC DMA Tx Stream */ if(hmmc->hdmatx != NULL) { - HAL_DMA_Abort(hmmc->hdmatx); + if(HAL_DMA_Abort(hmmc->hdmatx) != HAL_OK) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_DMA; + } } /* Abort the MMC DMA Rx Stream */ if(hmmc->hdmarx != NULL) { - HAL_DMA_Abort(hmmc->hdmarx); + if(HAL_DMA_Abort(hmmc->hdmarx) != HAL_OK) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_DMA; + } } } hmmc->State = HAL_MMC_STATE_READY; + + /* Initialize the MMC operation */ + hmmc->Context = MMC_CONTEXT_NONE; + CardState = HAL_MMC_GetCardState(hmmc); if((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING)) { @@ -2282,7 +2319,7 @@ HAL_StatusTypeDef HAL_MMC_Abort(MMC_HandleTypeDef *hmmc) /** * @brief Abort the current transfer and disable the MMC (IT mode). - * @param hmmc pointer to a MMC_HandleTypeDef structure that contains + * @param hmmc: pointer to a MMC_HandleTypeDef structure that contains * the configuration information for MMC module. * @retval HAL status */ @@ -2295,7 +2332,7 @@ HAL_StatusTypeDef HAL_MMC_Abort_IT(MMC_HandleTypeDef *hmmc) SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR); /* Clear All flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); if((hmmc->hdmatx != NULL) || (hmmc->hdmarx != NULL)) { @@ -2327,6 +2364,7 @@ HAL_StatusTypeDef HAL_MMC_Abort_IT(MMC_HandleTypeDef *hmmc) { CardState = HAL_MMC_GetCardState(hmmc); hmmc->State = HAL_MMC_STATE_READY; + if((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING)) { hmmc->ErrorCode = SDMMC_CmdStopTransfer(hmmc->Instance); @@ -2337,7 +2375,11 @@ HAL_StatusTypeDef HAL_MMC_Abort_IT(MMC_HandleTypeDef *hmmc) } else { +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) + hmmc->AbortCpltCallback(hmmc); +#else HAL_MMC_AbortCallback(hmmc); +#endif } } @@ -2359,7 +2401,7 @@ HAL_StatusTypeDef HAL_MMC_Abort_IT(MMC_HandleTypeDef *hmmc) /** * @brief DMA MMC transmit process complete callback - * @param hdma DMA handle + * @param hdma: DMA handle * @retval None */ static void MMC_DMATransmitCplt(DMA_HandleTypeDef *hdma) @@ -2372,13 +2414,13 @@ static void MMC_DMATransmitCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA MMC receive process complete callback - * @param hdma DMA handle + * @param hdma: DMA handle * @retval None */ static void MMC_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { MMC_HandleTypeDef* hmmc = (MMC_HandleTypeDef* )(hdma->Parent); - uint32_t errorstate = HAL_MMC_ERROR_NONE; + uint32_t errorstate; /* Send stop command in multiblock write */ if(hmmc->Context == (MMC_CONTEXT_READ_MULTIPLE_BLOCK | MMC_CONTEXT_DMA)) @@ -2387,7 +2429,7 @@ static void MMC_DMAReceiveCplt(DMA_HandleTypeDef *hdma) if(errorstate != HAL_MMC_ERROR_NONE) { hmmc->ErrorCode |= errorstate; -#if (USE_HAL_MMC_REGISTER_CALLBACKS == 1) +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) hmmc->ErrorCallback(hmmc); #else HAL_MMC_ErrorCallback(hmmc); @@ -2400,11 +2442,11 @@ static void MMC_DMAReceiveCplt(DMA_HandleTypeDef *hdma) hmmc->Instance->DCTRL &= (uint32_t)~((uint32_t)SDMMC_DCTRL_DMAEN); /* Clear all the static flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); hmmc->State = HAL_MMC_STATE_READY; -#if (USE_HAL_MMC_REGISTER_CALLBACKS == 1) +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) hmmc->RxCpltCallback(hmmc); #else HAL_MMC_RxCpltCallback(hmmc); @@ -2413,18 +2455,21 @@ static void MMC_DMAReceiveCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA MMC communication error callback - * @param hdma DMA handle + * @param hdma: DMA handle * @retval None */ static void MMC_DMAError(DMA_HandleTypeDef *hdma) { MMC_HandleTypeDef* hmmc = (MMC_HandleTypeDef* )(hdma->Parent); HAL_MMC_CardStateTypeDef CardState; + uint32_t RxErrorCode, TxErrorCode; /* if DMA error is FIFO error ignore it */ if(HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE) { - if((hmmc->hdmarx->ErrorCode == HAL_DMA_ERROR_TE) || (hmmc->hdmatx->ErrorCode == HAL_DMA_ERROR_TE)) + RxErrorCode = hmmc->hdmarx->ErrorCode; + TxErrorCode = hmmc->hdmatx->ErrorCode; + if((RxErrorCode == HAL_DMA_ERROR_TE) || (TxErrorCode == HAL_DMA_ERROR_TE)) { /* Clear All flags */ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); @@ -2443,18 +2488,17 @@ static void MMC_DMAError(DMA_HandleTypeDef *hdma) hmmc->State= HAL_MMC_STATE_READY; } -#if (USE_HAL_MMC_REGISTER_CALLBACKS == 1) +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) hmmc->ErrorCallback(hmmc); #else HAL_MMC_ErrorCallback(hmmc); #endif } - } /** * @brief DMA MMC Tx Abort callback - * @param hdma DMA handle + * @param hdma: DMA handle * @retval None */ static void MMC_DMATxAbort(DMA_HandleTypeDef *hdma) @@ -2479,11 +2523,15 @@ static void MMC_DMATxAbort(DMA_HandleTypeDef *hdma) if(hmmc->ErrorCode != HAL_MMC_ERROR_NONE) { +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) + hmmc->AbortCpltCallback(hmmc); +#else HAL_MMC_AbortCallback(hmmc); +#endif } else { -#if (USE_HAL_MMC_REGISTER_CALLBACKS == 1) +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) hmmc->ErrorCallback(hmmc); #else HAL_MMC_ErrorCallback(hmmc); @@ -2495,7 +2543,7 @@ static void MMC_DMATxAbort(DMA_HandleTypeDef *hdma) /** * @brief DMA MMC Rx Abort callback - * @param hdma DMA handle + * @param hdma: DMA handle * @retval None */ static void MMC_DMARxAbort(DMA_HandleTypeDef *hdma) @@ -2520,11 +2568,15 @@ static void MMC_DMARxAbort(DMA_HandleTypeDef *hdma) if(hmmc->ErrorCode != HAL_MMC_ERROR_NONE) { +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) + hmmc->AbortCpltCallback(hmmc); +#else HAL_MMC_AbortCallback(hmmc); +#endif } else { -#if (USE_HAL_MMC_REGISTER_CALLBACKS == 1) +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) hmmc->ErrorCallback(hmmc); #else HAL_MMC_ErrorCallback(hmmc); @@ -2534,20 +2586,19 @@ static void MMC_DMARxAbort(DMA_HandleTypeDef *hdma) } } - /** * @brief Initializes the mmc card. - * @param hmmc Pointer to MMC handle + * @param hmmc: Pointer to MMC handle * @retval MMC Card error state */ static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc) { HAL_MMC_CardCSDTypeDef CSD; - uint32_t errorstate = HAL_MMC_ERROR_NONE; - uint16_t mmc_rca = 1; + uint32_t errorstate; + uint16_t mmc_rca = 1U; /* Check the power State */ - if(SDMMC_GetPowerState(hmmc->Instance) == 0) + if(SDMMC_GetPowerState(hmmc->Instance) == 0U) { /* Power off */ return HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE; @@ -2562,10 +2613,10 @@ static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc) else { /* Get Card identification number data */ - hmmc->CID[0] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1); - hmmc->CID[1] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP2); - hmmc->CID[2] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP3); - hmmc->CID[3] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP4); + hmmc->CID[0U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1); + hmmc->CID[1U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP2); + hmmc->CID[2U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP3); + hmmc->CID[3U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP4); } /* Send CMD3 SET_REL_ADDR with argument 0 */ @@ -2595,20 +2646,23 @@ static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc) } /* Get the Card Class */ - hmmc->MmcCard.Class = (SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP2) >> 20); + hmmc->MmcCard.Class = (SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP2) >> 20U); /* Get CSD parameters */ - HAL_MMC_GetCardCSD(hmmc, &CSD); + if (HAL_MMC_GetCardCSD(hmmc, &CSD) != HAL_OK) + { + return hmmc->ErrorCode; + } /* Select the Card */ - errorstate = SDMMC_CmdSelDesel(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16)); + errorstate = SDMMC_CmdSelDesel(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); if(errorstate != HAL_MMC_ERROR_NONE) { return errorstate; } /* Configure SDMMC peripheral interface */ - SDMMC_Init(hmmc->Instance, hmmc->Init); + (void)SDMMC_Init(hmmc->Instance, hmmc->Init); /* All cards are initialized */ return HAL_MMC_ERROR_NONE; @@ -2618,14 +2672,14 @@ static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc) * @brief Enquires cards about their operating voltage and configures clock * controls and stores MMC information that will be needed in future * in the MMC handle. - * @param hmmc Pointer to MMC handle + * @param hmmc: Pointer to MMC handle * @retval error state */ static uint32_t MMC_PowerON(MMC_HandleTypeDef *hmmc) { - __IO uint32_t count = 0; - uint32_t response = 0, validvoltage = 0; - uint32_t errorstate = HAL_MMC_ERROR_NONE; + __IO uint32_t count = 0U; + uint32_t response = 0U, validvoltage = 0U; + uint32_t errorstate; /* CMD0: GO_IDLE_STATE */ errorstate = SDMMC_CmdGoIdleState(hmmc->Instance); @@ -2634,7 +2688,7 @@ static uint32_t MMC_PowerON(MMC_HandleTypeDef *hmmc) return errorstate; } - while(validvoltage == 0) + while(validvoltage == 0U) { if(count++ == SDMMC_MAX_VOLT_TRIAL) { @@ -2652,19 +2706,17 @@ static uint32_t MMC_PowerON(MMC_HandleTypeDef *hmmc) response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1); /* Get operating voltage*/ - validvoltage = (((response >> 31) == 1) ? 1 : 0); + validvoltage = (((response >> 31U) == 1U) ? 1U : 0U); } /* When power routine is finished and command returns valid voltage */ - if ((response & MMC_HIGH_VOLTAGE_RANGE) == MMC_HIGH_VOLTAGE_RANGE) + if (((response & (0xFF000000U)) >> 24U) == 0xC0U) { - /* When voltage range of the card is within 2.7V and 3.6V */ - hmmc->MmcCard.CardType = MMC_HIGH_VOLTAGE_CARD; + hmmc->MmcCard.CardType = MMC_HIGH_CAPACITY_CARD; } else { - /* When voltage range of the card is within 1.65V and 1.95V or 2.7V and 3.6V */ - hmmc->MmcCard.CardType = MMC_DUAL_VOLTAGE_CARD; + hmmc->MmcCard.CardType = MMC_LOW_CAPACITY_CARD; } return HAL_MMC_ERROR_NONE; @@ -2672,27 +2724,25 @@ static uint32_t MMC_PowerON(MMC_HandleTypeDef *hmmc) /** * @brief Turns the SDMMC output signals off. - * @param hmmc Pointer to MMC handle - * @retval HAL status + * @param hmmc: Pointer to MMC handle + * @retval None */ -static HAL_StatusTypeDef MMC_PowerOFF(MMC_HandleTypeDef *hmmc) +static void MMC_PowerOFF(MMC_HandleTypeDef *hmmc) { /* Set Power State to OFF */ - SDMMC_PowerState_OFF(hmmc->Instance); - - return HAL_OK; + (void)SDMMC_PowerState_OFF(hmmc->Instance); } /** * @brief Returns the current card's status. - * @param hmmc Pointer to MMC handle - * @param pCardStatus pointer to the buffer that will contain the MMC card + * @param hmmc: Pointer to MMC handle + * @param pCardStatus: pointer to the buffer that will contain the MMC card * status (Card Status register) * @retval error state */ static uint32_t MMC_SendStatus(MMC_HandleTypeDef *hmmc, uint32_t *pCardStatus) { - uint32_t errorstate = HAL_MMC_ERROR_NONE; + uint32_t errorstate; if(pCardStatus == NULL) { @@ -2700,8 +2750,8 @@ static uint32_t MMC_SendStatus(MMC_HandleTypeDef *hmmc, uint32_t *pCardStatus) } /* Send Status command */ - errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(hmmc->MmcCard.RelCardAdd << 16)); - if(errorstate != HAL_OK) + errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(hmmc->MmcCard.RelCardAdd << 16U)); + if(errorstate != HAL_MMC_ERROR_NONE) { return errorstate; } @@ -2714,56 +2764,88 @@ static uint32_t MMC_SendStatus(MMC_HandleTypeDef *hmmc, uint32_t *pCardStatus) /** * @brief Wrap up reading in non-blocking mode. - * @param hmmc pointer to a MMC_HandleTypeDef structure that contains + * @param hmmc: pointer to a MMC_HandleTypeDef structure that contains * the configuration information. - * @retval HAL status + * @retval None */ -static HAL_StatusTypeDef MMC_Read_IT(MMC_HandleTypeDef *hmmc) +static void MMC_Read_IT(MMC_HandleTypeDef *hmmc) { - uint32_t count = 0; - uint32_t* tmp; + uint32_t count, data, dataremaining; + uint8_t* tmp; - tmp = (uint32_t*)hmmc->pRxBuffPtr; + tmp = hmmc->pRxBuffPtr; + dataremaining = hmmc->RxXferSize; - /* Read data from SDMMC Rx FIFO */ - for(count = 0; count < 8; count++) + if (dataremaining > 0U) { - *(tmp + count) = SDMMC_ReadFIFO(hmmc->Instance); - } - - hmmc->pRxBuffPtr += 8; + /* Read data from SDMMC Rx FIFO */ + for(count = 0U; count < 8U; count++) + { + data = SDMMC_ReadFIFO(hmmc->Instance); + *tmp = (uint8_t)(data & 0xFFU); + tmp++; + dataremaining--; + *tmp = (uint8_t)((data >> 8U) & 0xFFU); + tmp++; + dataremaining--; + *tmp = (uint8_t)((data >> 16U) & 0xFFU); + tmp++; + dataremaining--; + *tmp = (uint8_t)((data >> 24U) & 0xFFU); + tmp++; + dataremaining--; + } - return HAL_OK; + hmmc->pRxBuffPtr = tmp; + hmmc->RxXferSize = dataremaining; + } } /** * @brief Wrap up writing in non-blocking mode. - * @param hmmc pointer to a MMC_HandleTypeDef structure that contains + * @param hmmc: pointer to a MMC_HandleTypeDef structure that contains * the configuration information. - * @retval HAL status + * @retval None */ -static HAL_StatusTypeDef MMC_Write_IT(MMC_HandleTypeDef *hmmc) +static void MMC_Write_IT(MMC_HandleTypeDef *hmmc) { - uint32_t count = 0; - uint32_t* tmp; + uint32_t count, data, dataremaining; + uint8_t* tmp; - tmp = (uint32_t*)hmmc->pTxBuffPtr; + tmp = hmmc->pTxBuffPtr; + dataremaining = hmmc->TxXferSize; - /* Write data to SDMMC Tx FIFO */ - for(count = 0; count < 8; count++) + if (dataremaining > 0U) { - SDMMC_WriteFIFO(hmmc->Instance, (tmp + count)); - } - - hmmc->pTxBuffPtr += 8; + /* Write data to SDMMC Tx FIFO */ + for(count = 0U; count < 8U; count++) + { + data = (uint32_t)(*tmp); + tmp++; + dataremaining--; + data |= ((uint32_t)(*tmp) << 8U); + tmp++; + dataremaining--; + data |= ((uint32_t)(*tmp) << 16U); + tmp++; + dataremaining--; + data |= ((uint32_t)(*tmp) << 24U); + tmp++; + dataremaining--; + (void)SDMMC_WriteFIFO(hmmc->Instance, &data); + } - return HAL_OK; + hmmc->pTxBuffPtr = tmp; + hmmc->TxXferSize = dataremaining; + } } /** * @} */ +#endif /* SDMMC1 */ + #endif /* HAL_MMC_MODULE_ENABLED */ /** diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pcd.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pcd.c index c089e7e52d..7b236c5fe8 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pcd.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pcd.c @@ -122,6 +122,7 @@ static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint */ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) { + USB_OTG_GlobalTypeDef *USBx; uint8_t i; /* Check the PCD handle allocation */ @@ -133,6 +134,8 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) /* Check the parameters */ assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance)); + USBx = hpcd->Instance; + if (hpcd->State == HAL_PCD_STATE_RESET) { /* Allocate lock resource and initialize it */ @@ -166,6 +169,12 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) hpcd->State = HAL_PCD_STATE_BUSY; + /* Disable DMA mode for FS instance */ + if ((USBx->CID & (0x1U << 8)) == 0U) + { + hpcd->Init.dma_enable = 0U; + } + /* Disable the Interrupts */ __HAL_PCD_DISABLE(hpcd); @@ -943,7 +952,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) { USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t i, ep_intr, epint, epnum = 0U; + uint32_t i, ep_intr, epint, epnum; uint32_t fifoemptymsk, temp; USB_OTG_EPTypeDef *ep; @@ -962,6 +971,38 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS); } + /* Handle RxQLevel Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL)) + { + USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); + + temp = USBx->GRXSTSP; + + ep = &hpcd->OUT_ep[temp & USB_OTG_GRXSTSP_EPNUM]; + + if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT) + { + if ((temp & USB_OTG_GRXSTSP_BCNT) != 0U) + { + (void)USB_ReadPacket(USBx, ep->xfer_buff, + (uint16_t)((temp & USB_OTG_GRXSTSP_BCNT) >> 4)); + + ep->xfer_buff += (temp & USB_OTG_GRXSTSP_BCNT) >> 4; + ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4; + } + } + else if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_SETUP_UPDT) + { + (void)USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U); + ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4; + } + else + { + /* ... */ + } + USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); + } + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT)) { epnum = 0U; @@ -983,9 +1024,9 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) if ((epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP); /* Class B setup phase done for previous decoded setup */ (void)PCD_EP_OutSetupPacket_int(hpcd, epnum); - CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP); } if ((epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS) @@ -996,10 +1037,6 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /* Clear Status Phase Received interrupt */ if ((epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) { - if (hpcd->Init.dma_enable == 1U) - { - (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); - } CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR); } @@ -1037,16 +1074,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) if (hpcd->Init.dma_enable == 1U) { hpcd->IN_ep[epnum].xfer_buff += hpcd->IN_ep[epnum].maxpacket; - } - -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->DataInStageCallback(hpcd, (uint8_t)epnum); -#else - HAL_PCD_DataInStageCallback(hpcd, (uint8_t)epnum); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - if (hpcd->Init.dma_enable == 1U) - { /* this is ZLP, so prepare EP0 for next setup */ if ((epnum == 0U) && (hpcd->IN_ep[epnum].xfer_len == 0U)) { @@ -1054,6 +1082,12 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); } } + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DataInStageCallback(hpcd, (uint8_t)epnum); +#else + HAL_PCD_DataInStageCallback(hpcd, (uint8_t)epnum); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } if ((epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC) { @@ -1159,8 +1193,10 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) { USBx_INEP(i)->DIEPINT = 0xFB7FU; USBx_INEP(i)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; + USBx_INEP(i)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK; USBx_OUTEP(i)->DOEPINT = 0xFB7FU; USBx_OUTEP(i)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; + USBx_OUTEP(i)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK; } USBx_DEVICE->DAINTMSK |= 0x10001U; @@ -1201,15 +1237,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE)) { (void)USB_ActivateSetup(hpcd->Instance); - - if (USB_GetDevSpeed(hpcd->Instance) == USB_OTG_SPEED_HIGH) - { - hpcd->Init.speed = USB_OTG_SPEED_HIGH; - } - else - { - hpcd->Init.speed = USB_OTG_SPEED_FULL; - } + hpcd->Init.speed = USB_GetDevSpeed(hpcd->Instance); /* Set USB Turnaround time */ (void)USB_SetTurnaroundTime(hpcd->Instance, @@ -1225,38 +1253,6 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE); } - /* Handle RxQLevel Interrupt */ - if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL)) - { - USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); - - temp = USBx->GRXSTSP; - - ep = &hpcd->OUT_ep[temp & USB_OTG_GRXSTSP_EPNUM]; - - if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT) - { - if ((temp & USB_OTG_GRXSTSP_BCNT) != 0U) - { - (void)USB_ReadPacket(USBx, ep->xfer_buff, - (uint16_t)((temp & USB_OTG_GRXSTSP_BCNT) >> 4)); - - ep->xfer_buff += (temp & USB_OTG_GRXSTSP_BCNT) >> 4; - ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4; - } - } - else if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_SETUP_UPDT) - { - (void)USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U); - ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4; - } - else - { - /* ... */ - } - USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); - } - /* Handle SOF Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF)) { @@ -1272,6 +1268,10 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /* Handle Incomplete ISO IN Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR)) { + /* Keep application checking the corresponding Iso IN endpoint + causing the incomplete Interrupt */ + epnum = 0U; + #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->ISOINIncompleteCallback(hpcd, (uint8_t)epnum); #else @@ -1284,6 +1284,10 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /* Handle Incomplete ISO OUT Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT)) { + /* Keep application checking the corresponding Iso OUT endpoint + causing the incomplete Interrupt */ + epnum = 0U; + #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum); #else @@ -1963,16 +1967,6 @@ static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint { CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); } - - /* Inform the upper layer that a setup packet is available */ -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->SetupStageCallback(hpcd); -#else - HAL_PCD_SetupStageCallback(hpcd); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - - (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); - CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP); } else if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) /* Class E */ { @@ -1995,17 +1989,16 @@ static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint hpcd->OUT_ep[epnum].xfer_buff += hpcd->OUT_ep[epnum].maxpacket; -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); -#else - HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - if ((epnum == 0U) && (hpcd->OUT_ep[epnum].xfer_len == 0U)) { /* this is ZLP, so prepare EP0 for next setup */ (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); } +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); +#else + HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } } else @@ -2038,6 +2031,12 @@ static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint } else { + if ((epnum == 0U) && (hpcd->OUT_ep[epnum].xfer_len == 0U)) + { + /* this is ZLP, so prepare EP0 for next setup */ + (void)USB_EP0_OutStart(hpcd->Instance, 0U, (uint8_t *)hpcd->Setup); + } + #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); #else @@ -2063,22 +2062,10 @@ static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U); uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT; - if (hpcd->Init.dma_enable == 1U) + if ((gSNPSiD > USB_OTG_CORE_ID_300A) && + ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)) { - /* StupPktRcvd = 1 pending setup packet int */ - if ((gSNPSiD > USB_OTG_CORE_ID_300A) && - ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)) - { - CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); - } - } - else - { - if ((gSNPSiD == USB_OTG_CORE_ID_310A) && - ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)) - { - CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); - } + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); } /* Inform the upper layer that a setup packet is available */ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_qspi.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_qspi.c index 5947f4c4d5..7a064e1643 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_qspi.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_qspi.c @@ -24,7 +24,7 @@ [..] (#) As prerequisite, fill in the HAL_QSPI_MspInit() : (++) Enable QuadSPI clock interface with __HAL_RCC_QSPI_CLK_ENABLE(). - (++) Reset QuadSPI IP with __HAL_RCC_QSPI_FORCE_RESET() and __HAL_RCC_QSPI_RELEASE_RESET(). + (++) Reset QuadSPI Peripheral with __HAL_RCC_QSPI_FORCE_RESET() and __HAL_RCC_QSPI_RELEASE_RESET(). (++) Enable the clocks for the QuadSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE(). (++) Configure these QuadSPI pins in alternate mode using HAL_GPIO_Init(). (++) If interrupt mode is used, enable and configure QuadSPI global @@ -108,7 +108,7 @@ the address range. HAL_QSPI_TimeOutCallback() will be called when the timeout expires. *** Errors management and abort functionality *** - ================================================== + ================================================= [..] (#) HAL_QSPI_GetError() function gives the error raised during the last operation. (#) HAL_QSPI_Abort() and HAL_QSPI_AbortIT() functions aborts any on-going operation and @@ -116,7 +116,7 @@ (++) In polling mode, the output of the function is done when the transfer complete bit is set and the busy bit cleared. (++) In interrupt mode, HAL_QSPI_AbortCpltCallback() will be called when - the transfer complete bi is set. + the transfer complete bit is set. *** Control functions *** ========================= @@ -125,6 +125,7 @@ (#) HAL_QSPI_SetTimeout() function configures the timeout value used in the driver. (#) HAL_QSPI_SetFifoThreshold() function configures the threshold on the Fifo of the QSPI IP. (#) HAL_QSPI_GetFifoThreshold() function gives the current of the Fifo's threshold + (#) HAL_QSPI_SetFlashID() function configures the index of the flash memory to be accessed. *** Callback registration *** ============================================= @@ -201,7 +202,7 @@ * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -209,22 +210,25 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32f7xx_hal.h" +#if defined(QUADSPI) + /** @addtogroup STM32F7xx_HAL_Driver * @{ */ /** @defgroup QSPI QSPI - * @brief HAL QSPI module driver + * @brief QSPI HAL module driver * @{ */ #ifdef HAL_QSPI_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ + /* Private define ------------------------------------------------------------*/ -/** @addtogroup QSPI_Private_Constants +/** @defgroup QSPI_Private_Constants QSPI Private Constants * @{ */ -#define QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE ((uint32_t)0x00000000U) /*!Init.FlashID)); } - /* Process locked */ - __HAL_LOCK(hqspi); - if(hqspi->State == HAL_QSPI_STATE_RESET) { /* Allocate lock resource and initialize it */ @@ -349,24 +345,27 @@ HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi) #endif /* Configure the default timeout for the QSPI memory access */ - HAL_QSPI_SetTimeout(hqspi, HAL_QPSI_TIMEOUT_DEFAULT_VALUE); + HAL_QSPI_SetTimeout(hqspi, HAL_QSPI_TIMEOUT_DEFAULT_VALUE); } /* Configure QSPI FIFO Threshold */ - MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES, ((hqspi->Init.FifoThreshold - 1) << 8)); + MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES, + ((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos)); /* Wait till BUSY flag reset */ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout); if(status == HAL_OK) { - /* Configure QSPI Clock Prescaler and Sample Shift */ - MODIFY_REG(hqspi->Instance->CR,(QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT | QUADSPI_CR_FSEL | QUADSPI_CR_DFM), ((hqspi->Init.ClockPrescaler << 24)| hqspi->Init.SampleShifting | hqspi->Init.FlashID| hqspi->Init.DualFlash )); + MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT | QUADSPI_CR_FSEL | QUADSPI_CR_DFM), + ((hqspi->Init.ClockPrescaler << QUADSPI_CR_PRESCALER_Pos) | + hqspi->Init.SampleShifting | hqspi->Init.FlashID | hqspi->Init.DualFlash)); /* Configure QSPI Flash Size, CS High Time and Clock Mode */ MODIFY_REG(hqspi->Instance->DCR, (QUADSPI_DCR_FSIZE | QUADSPI_DCR_CSHT | QUADSPI_DCR_CKMODE), - ((hqspi->Init.FlashSize << 16) | hqspi->Init.ChipSelectHighTime | hqspi->Init.ClockMode)); + ((hqspi->Init.FlashSize << QUADSPI_DCR_FSIZE_Pos) | + hqspi->Init.ChipSelectHighTime | hqspi->Init.ClockMode)); /* Enable the QSPI peripheral */ __HAL_QSPI_ENABLE(hqspi); @@ -386,8 +385,8 @@ HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi) } /** - * @brief DeInitializes the QSPI peripheral - * @param hqspi qspi handle + * @brief De-Initialize the QSPI peripheral. + * @param hqspi : QSPI handle * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi) @@ -398,9 +397,6 @@ HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi) return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hqspi); - /* Disable the QSPI Peripheral Clock */ __HAL_QSPI_DISABLE(hqspi); @@ -430,11 +426,11 @@ HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi) } /** - * @brief QSPI MSP Init - * @param hqspi QSPI handle + * @brief Initialize the QSPI MSP. + * @param hqspi : QSPI handle * @retval None */ - __weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi) +__weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi) { /* Prevent unused argument(s) compilation warning */ UNUSED(hqspi); @@ -445,11 +441,11 @@ HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi) } /** - * @brief QSPI MSP DeInit - * @param hqspi QSPI handle + * @brief DeInitialize the QSPI MSP. + * @param hqspi : QSPI handle * @retval None */ - __weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi) +__weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi) { /* Prevent unused argument(s) compilation warning */ UNUSED(hqspi); @@ -463,14 +459,14 @@ HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi) * @} */ -/** @defgroup QSPI_Exported_Functions_Group2 IO operation functions +/** @defgroup QSPI_Exported_Functions_Group2 Input and Output operation functions * @brief QSPI Transmit/Receive functions * @verbatim =============================================================================== ##### IO operation functions ##### =============================================================================== - [..] + [..] This subsection provides a set of functions allowing to : (+) Handle the interrupts. (+) Handle the command sequence. @@ -484,9 +480,9 @@ HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi) */ /** - * @brief This function handles QSPI interrupt request. - * @param hqspi QSPI handle - * @retval None. + * @brief Handle QSPI interrupt request. + * @param hqspi : QSPI handle + * @retval None */ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) { @@ -495,19 +491,20 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) uint32_t itsource = READ_REG(hqspi->Instance->CR); /* QSPI Fifo Threshold interrupt occurred ----------------------------------*/ - if(((flag & QSPI_FLAG_FT)!= RESET) && ((itsource & QSPI_IT_FT)!= RESET)) + if(((flag & QSPI_FLAG_FT) != 0U) && ((itsource & QSPI_IT_FT) != 0U)) { data_reg = &hqspi->Instance->DR; if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX) { /* Transmission process */ - while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != 0) + while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != RESET) { - if (hqspi->TxXferCount > 0) + if (hqspi->TxXferCount > 0U) { - /* Fill the FIFO until it is full */ - *(__IO uint8_t *)data_reg = *hqspi->pTxBuffPtr++; + /* Fill the FIFO until the threshold is reached */ + *((__IO uint8_t *)data_reg) = *hqspi->pTxBuffPtr; + hqspi->pTxBuffPtr++; hqspi->TxXferCount--; } else @@ -522,12 +519,13 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX) { /* Receiving Process */ - while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != 0) + while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != RESET) { - if (hqspi->RxXferCount > 0) + if (hqspi->RxXferCount > 0U) { - /* Read the FIFO until it is empty */ - *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg; + /* Read the FIFO until the threshold is reached */ + *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg); + hqspi->pRxBuffPtr++; hqspi->RxXferCount--; } else @@ -539,6 +537,10 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) } } } + else + { + /* Nothing to do */ + } /* FIFO Threshold callback */ #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) @@ -549,7 +551,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) } /* QSPI Transfer Complete interrupt occurred -------------------------------*/ - else if(((flag & QSPI_FLAG_TC)!= RESET) && ((itsource & QSPI_IT_TC)!= RESET)) + else if(((flag & QSPI_FLAG_TC) != 0U) && ((itsource & QSPI_IT_TC) != 0U)) { /* Clear interrupt */ WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TC); @@ -560,7 +562,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) /* Transfer complete callback */ if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX) { - if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET) + if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U) { /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */ CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); @@ -569,8 +571,8 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) __HAL_DMA_DISABLE(hqspi->hdma); } -#if defined(QSPI1_V1_0) -/* Clear Busy bit */ +#if defined(QSPI1_V1_0) + /* Clear Busy bit */ HAL_QSPI_Abort_IT(hqspi); #endif @@ -586,7 +588,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) } else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX) { - if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET) + if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U) { /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */ CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); @@ -597,12 +599,13 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) else { data_reg = &hqspi->Instance->DR; - while(READ_BIT(hqspi->Instance->SR, QUADSPI_SR_FLEVEL) != 0) + while(READ_BIT(hqspi->Instance->SR, QUADSPI_SR_FLEVEL) != 0U) { - if (hqspi->RxXferCount > 0) + if (hqspi->RxXferCount > 0U) { /* Read the last data received in the FIFO until it is empty */ - *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg; + *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg); + hqspi->pRxBuffPtr++; hqspi->RxXferCount--; } else @@ -612,10 +615,11 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) } } } -#if defined(QSPI1_V1_0) + +#if defined(QSPI1_V1_0) /* Workaround - Extra data written in the FIFO at the end of a read transfer */ HAL_QSPI_Abort_IT(hqspi); -#endif /* QSPI_V1_0*/ +#endif /* Change state of QSPI */ hqspi->State = HAL_QSPI_STATE_READY; @@ -641,6 +645,9 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) } else if(hqspi->State == HAL_QSPI_STATE_ABORT) { + /* Reset functional mode configuration to indirect write mode by default */ + CLEAR_BIT(hqspi->Instance->CCR, QUADSPI_CCR_FMODE); + /* Change state of QSPI */ hqspi->State = HAL_QSPI_STATE_READY; @@ -667,16 +674,20 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) #endif } } + else + { + /* Nothing to do */ + } } /* QSPI Status Match interrupt occurred ------------------------------------*/ - else if(((flag & QSPI_FLAG_SM)!= RESET) && ((itsource & QSPI_IT_SM)!= RESET)) + else if(((flag & QSPI_FLAG_SM) != 0U) && ((itsource & QSPI_IT_SM) != 0U)) { /* Clear interrupt */ WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_SM); /* Check if the automatic poll mode stop is activated */ - if(READ_BIT(hqspi->Instance->CR, QUADSPI_CR_APMS) != 0) + if(READ_BIT(hqspi->Instance->CR, QUADSPI_CR_APMS) != 0U) { /* Disable the QSPI Transfer Error and Status Match Interrupts */ __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE)); @@ -694,7 +705,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) } /* QSPI Transfer Error interrupt occurred ----------------------------------*/ - else if(((flag & QSPI_FLAG_TE)!= RESET) && ((itsource & QSPI_IT_TE)!= RESET)) + else if(((flag & QSPI_FLAG_TE) != 0U) && ((itsource & QSPI_IT_TE) != 0U)) { /* Clear interrupt */ WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TE); @@ -705,7 +716,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) /* Set error code */ hqspi->ErrorCode |= HAL_QSPI_ERROR_TRANSFER; - if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET) + if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U) { /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */ CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); @@ -743,31 +754,36 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) } /* QSPI Timeout interrupt occurred -----------------------------------------*/ - else if(((flag & QSPI_FLAG_TO)!= RESET) && ((itsource & QSPI_IT_TO)!= RESET)) + else if(((flag & QSPI_FLAG_TO) != 0U) && ((itsource & QSPI_IT_TO) != 0U)) { /* Clear interrupt */ WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TO); - /* Time out callback */ + /* Timeout callback */ #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) hqspi->TimeOutCallback(hqspi); #else HAL_QSPI_TimeOutCallback(hqspi); #endif } + + else + { + /* Nothing to do */ + } } /** - * @brief Sets the command configuration. - * @param hqspi QSPI handle - * @param cmd structure that contains the command configuration information - * @param Timeout Time out duration + * @brief Set the command configuration. + * @param hqspi : QSPI handle + * @param cmd : structure that contains the command configuration information + * @param Timeout : Timeout duration * @note This function is used only in Indirect Read or Write Modes * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout) { - HAL_StatusTypeDef status = HAL_ERROR; + HAL_StatusTypeDef status; uint32_t tickstart = HAL_GetTick(); /* Check the parameters */ @@ -827,7 +843,6 @@ HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDe /* Update QSPI state */ hqspi->State = HAL_QSPI_STATE_READY; } - } else { @@ -849,15 +864,15 @@ HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDe } /** - * @brief Sets the command configuration in interrupt mode. - * @param hqspi QSPI handle - * @param cmd structure that contains the command configuration information + * @brief Set the command configuration in interrupt mode. + * @param hqspi : QSPI handle + * @param cmd : structure that contains the command configuration information * @note This function is used only in Indirect Read or Write Modes * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd) { - HAL_StatusTypeDef status = HAL_ERROR; + HAL_StatusTypeDef status; uint32_t tickstart = HAL_GetTick(); /* Check the parameters */ @@ -949,15 +964,15 @@ HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTyp /** * @brief Transmit an amount of data in blocking mode. - * @param hqspi QSPI handle - * @param pData pointer to data buffer - * @param Timeout Time out duration + * @param hqspi : QSPI handle + * @param pData : pointer to data buffer + * @param Timeout : Timeout duration * @note This function is used only in Indirect Write Mode * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout) { - HAL_StatusTypeDef status = HAL_OK; + HAL_StatusTypeDef status = HAL_OK; uint32_t tickstart = HAL_GetTick(); __IO uint32_t *data_reg = &hqspi->Instance->DR; @@ -974,14 +989,14 @@ HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, u hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX; /* Configure counters and size of the handle */ - hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1; - hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1; + hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1U; + hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U; hqspi->pTxBuffPtr = pData; /* Configure QSPI: CCR register with functional as indirect write */ MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); - while(hqspi->TxXferCount > 0) + while(hqspi->TxXferCount > 0U) { /* Wait until FT flag is set to send data */ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_FT, SET, tickstart, Timeout); @@ -991,7 +1006,8 @@ HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, u break; } - *(__IO uint8_t *)data_reg = *hqspi->pTxBuffPtr++; + *((__IO uint8_t *)data_reg) = *hqspi->pTxBuffPtr; + hqspi->pTxBuffPtr++; hqspi->TxXferCount--; } @@ -1005,10 +1021,10 @@ HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, u /* Clear Transfer Complete bit */ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); -#if defined(QSPI1_V1_0) +#if defined(QSPI1_V1_0) /* Clear Busy bit */ status = HAL_QSPI_Abort(hqspi); -#endif /* QSPI_V1_0 */ +#endif } } @@ -1034,10 +1050,10 @@ HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, u /** - * @brief Receive an amount of data in blocking mode - * @param hqspi QSPI handle - * @param pData pointer to data buffer - * @param Timeout Time out duration + * @brief Receive an amount of data in blocking mode. + * @param hqspi : QSPI handle + * @param pData : pointer to data buffer + * @param Timeout : Timeout duration * @note This function is used only in Indirect Read Mode * @retval HAL status */ @@ -1054,14 +1070,15 @@ HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, ui if(hqspi->State == HAL_QSPI_STATE_READY) { hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; + if(pData != NULL ) { /* Update state */ hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX; /* Configure counters and size of the handle */ - hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1; - hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1; + hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1U; + hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U; hqspi->pRxBuffPtr = pData; /* Configure QSPI: CCR register with functional as indirect read */ @@ -1070,7 +1087,7 @@ HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, ui /* Start the transfer by re-writing the address in AR register */ WRITE_REG(hqspi->Instance->AR, addr_reg); - while(hqspi->RxXferCount > 0) + while(hqspi->RxXferCount > 0U) { /* Wait until FT or TC flag is set to read received data */ status = QSPI_WaitFlagStateUntilTimeout(hqspi, (QSPI_FLAG_FT | QSPI_FLAG_TC), SET, tickstart, Timeout); @@ -1080,7 +1097,8 @@ HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, ui break; } - *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg; + *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg); + hqspi->pRxBuffPtr++; hqspi->RxXferCount--; } @@ -1094,10 +1112,10 @@ HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, ui /* Clear Transfer Complete bit */ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); -#if defined(QSPI1_V1_0) - /* Workaround - Extra data written in the FIFO at the end of a read transfer */ - status = HAL_QSPI_Abort(hqspi); -#endif /* QSPI_V1_0 */ +#if defined(QSPI1_V1_0) + /* Workaround - Extra data written in the FIFO at the end of a read transfer */ + status = HAL_QSPI_Abort(hqspi); +#endif } } @@ -1122,9 +1140,9 @@ HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, ui } /** - * @brief Send an amount of data in interrupt mode - * @param hqspi QSPI handle - * @param pData pointer to data buffer + * @brief Send an amount of data in non-blocking mode with interrupt. + * @param hqspi : QSPI handle + * @param pData : pointer to data buffer * @note This function is used only in Indirect Write Mode * @retval HAL status */ @@ -1138,28 +1156,28 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData if(hqspi->State == HAL_QSPI_STATE_READY) { hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; + if(pData != NULL ) { /* Update state */ hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX; /* Configure counters and size of the handle */ - hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1; - hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1; + hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1U; + hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U; hqspi->pTxBuffPtr = pData; - /* Configure QSPI: CCR register with functional as indirect write */ - MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); - /* Clear interrupt */ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC); + /* Configure QSPI: CCR register with functional as indirect write */ + MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); + /* Process unlocked */ __HAL_UNLOCK(hqspi); /* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */ __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC); - } else { @@ -1182,9 +1200,9 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData } /** - * @brief Receive an amount of data in no-blocking mode with Interrupt - * @param hqspi QSPI handle - * @param pData pointer to data buffer + * @brief Receive an amount of data in non-blocking mode with interrupt. + * @param hqspi : QSPI handle + * @param pData : pointer to data buffer * @note This function is used only in Indirect Read Mode * @retval HAL status */ @@ -1206,19 +1224,19 @@ HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData) hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX; /* Configure counters and size of the handle */ - hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1; - hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1; + hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1U; + hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U; hqspi->pRxBuffPtr = pData; + /* Clear interrupt */ + __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC); + /* Configure QSPI: CCR register with functional as indirect read */ MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ); /* Start the transfer by re-writing the address in AR register */ WRITE_REG(hqspi->Instance->AR, addr_reg); - /* Clear interrupt */ - __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC); - /* Process unlocked */ __HAL_UNLOCK(hqspi); @@ -1246,9 +1264,9 @@ HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData) } /** - * @brief Sends an amount of data in non blocking mode with DMA. - * @param hqspi QSPI handle - * @param pData pointer to data buffer + * @brief Send an amount of data in non-blocking mode with DMA. + * @param hqspi : QSPI handle + * @param pData : pointer to data buffer * @note This function is used only in Indirect Write Mode * @note If DMA peripheral access is configured as halfword, the number * of data and the fifo threshold should be aligned on halfword @@ -1259,8 +1277,7 @@ HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData) HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData) { HAL_StatusTypeDef status = HAL_OK; - uint32_t *tmp; - uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1); + uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1U); /* Process locked */ __HAL_LOCK(hqspi); @@ -1279,7 +1296,7 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pDat } else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_HALFWORD) { - if (((data_size % 2) != 0) || ((hqspi->Init.FifoThreshold % 2) != 0)) + if (((data_size % 2U) != 0U) || ((hqspi->Init.FifoThreshold % 2U) != 0U)) { /* The number of data or the fifo threshold is not aligned on halfword => no transfer possible with DMA peripheral access configured as halfword */ @@ -1291,12 +1308,12 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pDat } else { - hqspi->TxXferCount = (data_size >> 1); + hqspi->TxXferCount = (data_size >> 1U); } } else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD) { - if (((data_size % 4) != 0) || ((hqspi->Init.FifoThreshold % 4) != 0)) + if (((data_size % 4U) != 0U) || ((hqspi->Init.FifoThreshold % 4U) != 0U)) { /* The number of data or the fifo threshold is not aligned on word => no transfer possible with DMA peripheral access configured as word */ @@ -1308,60 +1325,71 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pDat } else { - hqspi->TxXferCount = (data_size >> 2); + hqspi->TxXferCount = (data_size >> 2U); } } + else + { + /* Nothing to do */ + } if (status == HAL_OK) { + /* Update state */ + hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX; - /* Update state */ - hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX; - - /* Clear interrupt */ - __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC)); + /* Clear interrupt */ + __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC)); - /* Configure size and pointer of the handle */ - hqspi->TxXferSize = hqspi->TxXferCount; - hqspi->pTxBuffPtr = pData; + /* Configure size and pointer of the handle */ + hqspi->TxXferSize = hqspi->TxXferCount; + hqspi->pTxBuffPtr = pData; - /* Configure QSPI: CCR register with functional mode as indirect write */ - MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); + /* Configure QSPI: CCR register with functional mode as indirect write */ + MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); - /* Set the QSPI DMA transfer complete callback */ - hqspi->hdma->XferCpltCallback = QSPI_DMATxCplt; + /* Set the QSPI DMA transfer complete callback */ + hqspi->hdma->XferCpltCallback = QSPI_DMATxCplt; - /* Set the QSPI DMA Half transfer complete callback */ - hqspi->hdma->XferHalfCpltCallback = QSPI_DMATxHalfCplt; + /* Set the QSPI DMA Half transfer complete callback */ + hqspi->hdma->XferHalfCpltCallback = QSPI_DMATxHalfCplt; - /* Set the DMA error callback */ - hqspi->hdma->XferErrorCallback = QSPI_DMAError; + /* Set the DMA error callback */ + hqspi->hdma->XferErrorCallback = QSPI_DMAError; - /* Clear the DMA abort callback */ - hqspi->hdma->XferAbortCallback = NULL; + /* Clear the DMA abort callback */ + hqspi->hdma->XferAbortCallback = NULL; - /* Configure the direction of the DMA */ - hqspi->hdma->Init.Direction = DMA_MEMORY_TO_PERIPH; - MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction); + /* Configure the direction of the DMA */ + hqspi->hdma->Init.Direction = DMA_MEMORY_TO_PERIPH; + MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction); - /* Enable the QSPI transmit DMA Channel */ - tmp = (uint32_t*)&pData; - HAL_DMA_Start_IT(hqspi->hdma, *(uint32_t*)tmp, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSize); + /* Enable the QSPI transmit DMA Channel */ + if (HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)pData, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSize) == HAL_OK) + { + /* Process unlocked */ + __HAL_UNLOCK(hqspi); - /* Process unlocked */ - __HAL_UNLOCK(hqspi); + /* Enable the QSPI transfer error Interrupt */ + __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE); - /* Enable the QSPI transfer error Interrupt */ - __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE); + /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */ + SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); + } + else + { + status = HAL_ERROR; + hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; + hqspi->State = HAL_QSPI_STATE_READY; - /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */ - SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); - } + /* Process unlocked */ + __HAL_UNLOCK(hqspi); + } + } } else { hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; - status = HAL_ERROR; /* Process unlocked */ @@ -1380,9 +1408,9 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pDat } /** - * @brief Receives an amount of data in non blocking mode with DMA. - * @param hqspi QSPI handle - * @param pData pointer to data buffer. + * @brief Receive an amount of data in non-blocking mode with DMA. + * @param hqspi : QSPI handle + * @param pData : pointer to data buffer. * @note This function is used only in Indirect Read Mode * @note If DMA peripheral access is configured as halfword, the number * of data and the fifo threshold should be aligned on halfword @@ -1393,15 +1421,15 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pDat HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData) { HAL_StatusTypeDef status = HAL_OK; - uint32_t *tmp; uint32_t addr_reg = READ_REG(hqspi->Instance->AR); - uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1); + uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1U); /* Process locked */ __HAL_LOCK(hqspi); if(hqspi->State == HAL_QSPI_STATE_READY) { + /* Clear the error code */ hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; if(pData != NULL ) @@ -1413,10 +1441,10 @@ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData } else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_HALFWORD) { - if (((data_size % 2) != 0) || ((hqspi->Init.FifoThreshold % 2) != 0)) + if (((data_size % 2U) != 0U) || ((hqspi->Init.FifoThreshold % 2U) != 0U)) { /* The number of data or the fifo threshold is not aligned on halfword - => no transfer possible with DMA peripheral access configured as halfword */ + => no transfer possible with DMA peripheral access configured as halfword */ hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; status = HAL_ERROR; @@ -1425,15 +1453,15 @@ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData } else { - hqspi->RxXferCount = (data_size >> 1); + hqspi->RxXferCount = (data_size >> 1U); } } else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD) { - if (((data_size % 4) != 0) || ((hqspi->Init.FifoThreshold % 4) != 0)) + if (((data_size % 4U) != 0U) || ((hqspi->Init.FifoThreshold % 4U) != 0U)) { /* The number of data or the fifo threshold is not aligned on word - => no transfer possible with DMA peripheral access configured as word */ + => no transfer possible with DMA peripheral access configured as word */ hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; status = HAL_ERROR; @@ -1442,13 +1470,16 @@ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData } else { - hqspi->RxXferCount = (data_size >> 2); + hqspi->RxXferCount = (data_size >> 2U); } } + else + { + /* Nothing to do */ + } if (status == HAL_OK) { - /* Update state */ hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX; @@ -1476,23 +1507,32 @@ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction); /* Enable the DMA Channel */ - tmp = (uint32_t*)&pData; - HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, *(uint32_t*)tmp, hqspi->RxXferSize); + if (HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, (uint32_t)pData, hqspi->RxXferSize) == HAL_OK) + { + /* Configure QSPI: CCR register with functional as indirect read */ + MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ); - /* Configure QSPI: CCR register with functional as indirect read */ - MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ); + /* Start the transfer by re-writing the address in AR register */ + WRITE_REG(hqspi->Instance->AR, addr_reg); - /* Start the transfer by re-writing the address in AR register */ - WRITE_REG(hqspi->Instance->AR, addr_reg); + /* Process unlocked */ + __HAL_UNLOCK(hqspi); - /* Process unlocked */ - __HAL_UNLOCK(hqspi); + /* Enable the QSPI transfer error Interrupt */ + __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE); - /* Enable the QSPI transfer error Interrupt */ - __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE); + /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */ + SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); + } + else + { + status = HAL_ERROR; + hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; + hqspi->State = HAL_QSPI_STATE_READY; - /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */ - SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); + /* Process unlocked */ + __HAL_UNLOCK(hqspi); + } } } else @@ -1517,16 +1557,16 @@ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData /** * @brief Configure the QSPI Automatic Polling Mode in blocking mode. - * @param hqspi QSPI handle - * @param cmd structure that contains the command configuration information. - * @param cfg structure that contains the polling configuration information. - * @param Timeout Time out duration + * @param hqspi : QSPI handle + * @param cmd : structure that contains the command configuration information. + * @param cfg : structure that contains the polling configuration information. + * @param Timeout : Timeout duration * @note This function is used only in Automatic Polling Mode * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout) { - HAL_StatusTypeDef status = HAL_ERROR; + HAL_StatusTypeDef status; uint32_t tickstart = HAL_GetTick(); /* Check the parameters */ @@ -1564,7 +1604,6 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTy if(hqspi->State == HAL_QSPI_STATE_READY) { - hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; /* Update state */ @@ -1609,6 +1648,7 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTy { status = HAL_BUSY; } + /* Process unlocked */ __HAL_UNLOCK(hqspi); @@ -1618,15 +1658,15 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTy /** * @brief Configure the QSPI Automatic Polling Mode in non-blocking mode. - * @param hqspi QSPI handle - * @param cmd structure that contains the command configuration information. - * @param cfg structure that contains the polling configuration information. + * @param hqspi : QSPI handle + * @param cmd : structure that contains the command configuration information. + * @param cfg : structure that contains the polling configuration information. * @note This function is used only in Automatic Polling Mode * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg) { - HAL_StatusTypeDef status = HAL_ERROR; + HAL_StatusTypeDef status; uint32_t tickstart = HAL_GetTick(); /* Check the parameters */ @@ -1722,15 +1762,15 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_Comman /** * @brief Configure the Memory Mapped mode. - * @param hqspi QSPI handle - * @param cmd structure that contains the command configuration information. - * @param cfg structure that contains the memory mapped configuration information. + * @param hqspi : QSPI handle + * @param cmd : structure that contains the command configuration information. + * @param cfg : structure that contains the memory mapped configuration information. * @note This function is used only in Memory mapped Mode * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg) { - HAL_StatusTypeDef status = HAL_ERROR; + HAL_StatusTypeDef status; uint32_t tickstart = HAL_GetTick(); /* Check the parameters */ @@ -1810,8 +1850,8 @@ HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandT } /** - * @brief Transfer Error callbacks - * @param hqspi QSPI handle + * @brief Transfer Error callback. + * @param hqspi : QSPI handle * @retval None */ __weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi) @@ -1819,14 +1859,14 @@ __weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi) /* Prevent unused argument(s) compilation warning */ UNUSED(hqspi); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_QSPI_ErrorCallback could be implemented in the user file */ } /** * @brief Abort completed callback. - * @param hqspi QSPI handle + * @param hqspi : QSPI handle * @retval None */ __weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi) @@ -1841,7 +1881,7 @@ __weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Command completed callback. - * @param hqspi QSPI handle + * @param hqspi : QSPI handle * @retval None */ __weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi) @@ -1849,14 +1889,14 @@ __weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi) /* Prevent unused argument(s) compilation warning */ UNUSED(hqspi); - /* NOTE: This function Should not be modified, when the callback is needed, + /* NOTE: This function should not be modified, when the callback is needed, the HAL_QSPI_CmdCpltCallback could be implemented in the user file */ } /** - * @brief Rx Transfer completed callbacks. - * @param hqspi QSPI handle + * @brief Rx Transfer completed callback. + * @param hqspi : QSPI handle * @retval None */ __weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi) @@ -1864,29 +1904,29 @@ __weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi) /* Prevent unused argument(s) compilation warning */ UNUSED(hqspi); - /* NOTE: This function Should not be modified, when the callback is needed, + /* NOTE: This function should not be modified, when the callback is needed, the HAL_QSPI_RxCpltCallback could be implemented in the user file */ } /** - * @brief Tx Transfer completed callbacks. - * @param hqspi QSPI handle + * @brief Tx Transfer completed callback. + * @param hqspi : QSPI handle * @retval None */ - __weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi) +__weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi) { /* Prevent unused argument(s) compilation warning */ UNUSED(hqspi); - /* NOTE: This function Should not be modified, when the callback is needed, + /* NOTE: This function should not be modified, when the callback is needed, the HAL_QSPI_TxCpltCallback could be implemented in the user file */ } /** - * @brief Rx Half Transfer completed callbacks. - * @param hqspi QSPI handle + * @brief Rx Half Transfer completed callback. + * @param hqspi : QSPI handle * @retval None */ __weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi) @@ -1894,29 +1934,29 @@ __weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi) /* Prevent unused argument(s) compilation warning */ UNUSED(hqspi); - /* NOTE: This function Should not be modified, when the callback is needed, + /* NOTE: This function should not be modified, when the callback is needed, the HAL_QSPI_RxHalfCpltCallback could be implemented in the user file */ } /** - * @brief Tx Half Transfer completed callbacks. - * @param hqspi QSPI handle + * @brief Tx Half Transfer completed callback. + * @param hqspi : QSPI handle * @retval None */ - __weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi) +__weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi) { /* Prevent unused argument(s) compilation warning */ UNUSED(hqspi); - /* NOTE: This function Should not be modified, when the callback is needed, + /* NOTE: This function should not be modified, when the callback is needed, the HAL_QSPI_TxHalfCpltCallback could be implemented in the user file */ } /** - * @brief FIFO Threshold callbacks - * @param hqspi QSPI handle + * @brief FIFO Threshold callback. + * @param hqspi : QSPI handle * @retval None */ __weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi) @@ -1924,14 +1964,14 @@ __weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi) /* Prevent unused argument(s) compilation warning */ UNUSED(hqspi); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_QSPI_FIFOThresholdCallback could be implemented in the user file */ } /** - * @brief Status Match callbacks - * @param hqspi QSPI handle + * @brief Status Match callback. + * @param hqspi : QSPI handle * @retval None */ __weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi) @@ -1939,14 +1979,14 @@ __weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi) /* Prevent unused argument(s) compilation warning */ UNUSED(hqspi); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_QSPI_StatusMatchCallback could be implemented in the user file */ } /** - * @brief Timeout callbacks - * @param hqspi QSPI handle + * @brief Timeout callback. + * @param hqspi : QSPI handle * @retval None */ __weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi) @@ -1954,7 +1994,7 @@ __weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi) /* Prevent unused argument(s) compilation warning */ UNUSED(hqspi); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_QSPI_TimeOutCallback could be implemented in the user file */ } @@ -2196,14 +2236,15 @@ HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QS (+) Check in run-time the state of the driver. (+) Check the error code set during last operation. (+) Abort any operation. -..... + + @endverbatim * @{ */ /** * @brief Return the QSPI handle state. - * @param hqspi QSPI handle + * @param hqspi : QSPI handle * @retval HAL state */ HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi) @@ -2213,8 +2254,8 @@ HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi) } /** -* @brief Return the QSPI error code -* @param hqspi QSPI handle +* @brief Return the QSPI error code. +* @param hqspi : QSPI handle * @retval QSPI Error Code */ uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi) @@ -2223,8 +2264,8 @@ uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi) } /** -* @brief Abort the current transmission -* @param hqspi QSPI handle +* @brief Abort the current transmission. +* @param hqspi : QSPI handle * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi) @@ -2233,12 +2274,12 @@ HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi) uint32_t tickstart = HAL_GetTick(); /* Check if the state is in one of the busy states */ - if ((hqspi->State & 0x2) != 0) + if (((uint32_t)hqspi->State & 0x2U) != 0U) { /* Process unlocked */ __HAL_UNLOCK(hqspi); - if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET) + if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U) { /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */ CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); @@ -2257,7 +2298,7 @@ HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi) /* Wait until TC flag is set to go back in idle state */ status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, hqspi->Timeout); - if(status == HAL_OK) + if (status == HAL_OK) { __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); @@ -2267,6 +2308,9 @@ HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi) if (status == HAL_OK) { + /* Reset functional mode configuration to indirect write mode by default */ + CLEAR_BIT(hqspi->Instance->CCR, QUADSPI_CCR_FMODE); + /* Update state */ hqspi->State = HAL_QSPI_STATE_READY; } @@ -2277,7 +2321,7 @@ HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi) /** * @brief Abort the current transmission (non-blocking function) -* @param hqspi QSPI handle +* @param hqspi : QSPI handle * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi) @@ -2285,7 +2329,7 @@ HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi) HAL_StatusTypeDef status = HAL_OK; /* Check if the state is in one of the busy states */ - if ((hqspi->State & 0x2) != 0) + if (((uint32_t)hqspi->State & 0x2U) != 0U) { /* Process unlocked */ __HAL_UNLOCK(hqspi); @@ -2296,7 +2340,7 @@ HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi) /* Disable all interrupts */ __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_TO | QSPI_IT_SM | QSPI_IT_FT | QSPI_IT_TC | QSPI_IT_TE)); - if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET) + if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U) { /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */ CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); @@ -2328,13 +2372,12 @@ HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi) SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT); } } - return status; } -/** @brief Set QSPI timeout - * @param hqspi QSPI handle. - * @param Timeout Timeout for the QSPI memory access. +/** @brief Set QSPI timeout. + * @param hqspi : QSPI handle. + * @param Timeout : Timeout for the QSPI memory access. * @retval None */ void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout) @@ -2343,8 +2386,8 @@ void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout) } /** @brief Set QSPI Fifo threshold. - * @param hqspi QSPI handle. - * @param Threshold Threshold of the Fifo (value between 1 and 16). + * @param hqspi : QSPI handle. + * @param Threshold : Threshold of the Fifo (value between 1 and 16). * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold) @@ -2361,7 +2404,7 @@ HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t /* Configure QSPI FIFO Threshold */ MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES, - ((hqspi->Init.FifoThreshold - 1) << QUADSPI_CR_FTHRES_Pos)); + ((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos)); } else { @@ -2376,29 +2419,72 @@ HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t } /** @brief Get QSPI Fifo threshold. - * @param hqspi QSPI handle. + * @param hqspi : QSPI handle. * @retval Fifo threshold (value between 1 and 16) */ uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi) { - return ((READ_BIT(hqspi->Instance->CR, QUADSPI_CR_FTHRES) >> QUADSPI_CR_FTHRES_Pos) + 1); + return ((READ_BIT(hqspi->Instance->CR, QUADSPI_CR_FTHRES) >> QUADSPI_CR_FTHRES_Pos) + 1U); } +/** @brief Set FlashID. + * @param hqspi : QSPI handle. + * @param FlashID : Index of the flash memory to be accessed. + * This parameter can be a value of @ref QSPI_Flash_Select. + * @note The FlashID is ignored when dual flash mode is enabled. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_QSPI_SetFlashID(QSPI_HandleTypeDef *hqspi, uint32_t FlashID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameter */ + assert_param(IS_QSPI_FLASH_ID(FlashID)); + + /* Process locked */ + __HAL_LOCK(hqspi); + + if(hqspi->State == HAL_QSPI_STATE_READY) + { + /* Synchronize init structure with new FlashID value */ + hqspi->Init.FlashID = FlashID; + + /* Configure QSPI FlashID */ + MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FSEL, FlashID); + } + else + { + status = HAL_BUSY; + } + + /* Process unlocked */ + __HAL_UNLOCK(hqspi); + + /* Return function status */ + return status; +} + +/** + * @} + */ + /** * @} */ -/* Private functions ---------------------------------------------------------*/ +/** @defgroup QSPI_Private_Functions QSPI Private Functions + * @{ + */ /** * @brief DMA QSPI receive process complete callback. - * @param hdma DMA handle + * @param hdma : DMA handle * @retval None */ static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma) { - QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - hqspi->RxXferCount = 0; + QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent); + hqspi->RxXferCount = 0U; /* Enable the QSPI transfer complete Interrupt */ __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC); @@ -2406,26 +2492,26 @@ static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA QSPI transmit process complete callback. - * @param hdma DMA handle + * @param hdma : DMA handle * @retval None */ static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma) { - QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - hqspi->TxXferCount = 0; + QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent); + hqspi->TxXferCount = 0U; /* Enable the QSPI transfer complete Interrupt */ __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC); } /** - * @brief DMA QSPI receive process half complete callback - * @param hdma DMA handle + * @brief DMA QSPI receive process half complete callback. + * @param hdma : DMA handle * @retval None */ static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma) { - QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent); #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) hqspi->RxHalfCpltCallback(hqspi); @@ -2435,13 +2521,13 @@ static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma) } /** - * @brief DMA QSPI transmit process half complete callback - * @param hdma DMA handle + * @brief DMA QSPI transmit process half complete callback. + * @param hdma : DMA handle * @retval None */ static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma) { - QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent); #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) hqspi->TxHalfCpltCallback(hqspi); @@ -2452,39 +2538,40 @@ static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA QSPI communication error callback. - * @param hdma DMA handle + * @param hdma : DMA handle * @retval None */ static void QSPI_DMAError(DMA_HandleTypeDef *hdma) { - QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )(hdma->Parent); /* if DMA error is FIFO error ignore it */ if(HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE) { - hqspi->RxXferCount = 0; - hqspi->TxXferCount = 0; - hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; + hqspi->RxXferCount = 0U; + hqspi->TxXferCount = 0U; + hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; + + /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */ + CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); - /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */ - CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); + /* Abort the QSPI */ + (void)HAL_QSPI_Abort_IT(hqspi); - /* Abort the QSPI */ - HAL_QSPI_Abort_IT(hqspi); } } /** * @brief DMA QSPI abort complete callback. - * @param hdma DMA handle + * @param hdma : DMA handle * @retval None */ static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma) { - QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )(hdma->Parent); - hqspi->RxXferCount = 0; - hqspi->TxXferCount = 0; + hqspi->RxXferCount = 0U; + hqspi->TxXferCount = 0U; if(hqspi->State == HAL_QSPI_STATE_ABORT) { @@ -2515,23 +2602,23 @@ static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma) /** * @brief Wait for a flag state until timeout. - * @param hqspi QSPI handle - * @param Flag Flag checked - * @param State Value of the flag expected - * @param tickstart Start tick value - * @param Timeout Duration of the time out + * @param hqspi : QSPI handle + * @param Flag : Flag checked + * @param State : Value of the flag expected + * @param Tickstart : Tick start value + * @param Timeout : Duration of the timeout * @retval HAL status */ static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, - FlagStatus State, uint32_t tickstart, uint32_t Timeout) + FlagStatus State, uint32_t Tickstart, uint32_t Timeout) { /* Wait until flag is in expected state */ - while((FlagStatus)(__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State) + while((__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State) { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) + if(((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { hqspi->State = HAL_QSPI_STATE_ERROR; hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT; @@ -2545,9 +2632,9 @@ static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqsp /** * @brief Configure the communication registers. - * @param hqspi QSPI handle - * @param cmd structure that contains the command configuration information - * @param FunctionalMode functional mode to configured + * @param hqspi : QSPI handle + * @param cmd : structure that contains the command configuration information + * @param FunctionalMode : functional mode to configured * This parameter can be one of the following values: * @arg QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE: Indirect write mode * @arg QSPI_FUNCTIONAL_MODE_INDIRECT_READ: Indirect read mode @@ -2562,7 +2649,7 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin if ((cmd->DataMode != QSPI_DATA_NONE) && (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)) { /* Configure QSPI: DLR register with the number of data to read or write */ - WRITE_REG(hqspi->Instance->DLR, (cmd->NbData - 1)); + WRITE_REG(hqspi->Instance->DLR, (cmd->NbData - 1U)); } if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE) @@ -2577,9 +2664,10 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin /*---- Command with instruction, address and alternate bytes ----*/ /* Configure QSPI: CCR register with all communications parameters */ WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | - cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateBytesSize | - cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMode | - cmd->InstructionMode | cmd->Instruction | FunctionalMode)); + cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | + cmd->AlternateBytesSize | cmd->AlternateByteMode | + cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode | + cmd->Instruction | FunctionalMode)); if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED) { @@ -2592,8 +2680,9 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin /*---- Command with instruction and alternate bytes ----*/ /* Configure QSPI: CCR register with all communications parameters */ WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | - cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateBytesSize | - cmd->AlternateByteMode | cmd->AddressMode | cmd->InstructionMode | + cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | + cmd->AlternateBytesSize | cmd->AlternateByteMode | + cmd->AddressMode | cmd->InstructionMode | cmd->Instruction | FunctionalMode)); } } @@ -2604,9 +2693,9 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin /*---- Command with instruction and address ----*/ /* Configure QSPI: CCR register with all communications parameters */ WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | - cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateByteMode | - cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode | - cmd->Instruction | FunctionalMode)); + cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | + cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMode | + cmd->InstructionMode | cmd->Instruction | FunctionalMode)); if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED) { @@ -2619,9 +2708,9 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin /*---- Command with only instruction ----*/ /* Configure QSPI: CCR register with all communications parameters */ WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | - cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateByteMode | - cmd->AddressMode | cmd->InstructionMode | cmd->Instruction | - FunctionalMode)); + cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | + cmd->AlternateByteMode | cmd->AddressMode | + cmd->InstructionMode | cmd->Instruction | FunctionalMode)); } } } @@ -2637,8 +2726,9 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin /*---- Command with address and alternate bytes ----*/ /* Configure QSPI: CCR register with all communications parameters */ WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | - cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateBytesSize | - cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMode | + cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | + cmd->AlternateBytesSize | cmd->AlternateByteMode | + cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode | FunctionalMode)); if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED) @@ -2652,9 +2742,9 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin /*---- Command with only alternate bytes ----*/ /* Configure QSPI: CCR register with all communications parameters */ WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | - cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateBytesSize | - cmd->AlternateByteMode | cmd->AddressMode | cmd->InstructionMode | - FunctionalMode)); + cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | + cmd->AlternateBytesSize | cmd->AlternateByteMode | + cmd->AddressMode | cmd->InstructionMode | FunctionalMode)); } } else @@ -2664,9 +2754,9 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin /*---- Command with only address ----*/ /* Configure QSPI: CCR register with all communications parameters */ WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | - cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateByteMode | - cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode | - FunctionalMode)); + cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | + cmd->AlternateByteMode | cmd->AddressSize | + cmd->AddressMode | cmd->InstructionMode | FunctionalMode)); if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED) { @@ -2681,13 +2771,19 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin { /* Configure QSPI: CCR register with all communications parameters */ WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | - cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateByteMode | - cmd->AddressMode | cmd->InstructionMode | FunctionalMode)); + cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | + cmd->AlternateByteMode | cmd->AddressMode | + cmd->InstructionMode | FunctionalMode)); } } } } } + +/** + * @} + */ + /** * @} */ @@ -2701,4 +2797,6 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin * @} */ +#endif /* defined(QUADSPI) || defined(QUADSPI1) || defined(QUADSPI2) */ + /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c index c8290a82a6..d7132c0454 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c @@ -317,7 +317,7 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void) SystemCoreClock = HSI_VALUE; /* Adapt Systick interrupt period */ - if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) + if (HAL_InitTick(uwTickPrio) != HAL_OK) { return HAL_ERROR; } @@ -344,10 +344,11 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void) HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { uint32_t tickstart; + uint32_t pll_config; FlagStatus pwrclkchanged = RESET; /* Check Null pointer */ - if(RCC_OscInitStruct == NULL) + if (RCC_OscInitStruct == NULL) { return HAL_ERROR; } @@ -356,15 +357,15 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ - if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL, It can not be disabled */ - if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) - || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) + if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) + || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) { - if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) { return HAL_ERROR; } @@ -375,15 +376,15 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); /* Check the HSE State */ - if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF) + if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) { /* Get Start Tick*/ tickstart = HAL_GetTick(); /* Wait till HSE is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) { - if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -395,9 +396,9 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) tickstart = HAL_GetTick(); /* Wait till HSE is bypassed or disabled */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) { - if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -406,18 +407,18 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) } } /*----------------------------- HSI Configuration --------------------------*/ - if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) { /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ - if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) - || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) + if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) + || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) { /* When HSI is used as system clock it will not disabled */ - if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) + if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) { return HAL_ERROR; } @@ -431,7 +432,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) else { /* Check the HSI State */ - if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF) + if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF) { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); @@ -440,9 +441,9 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) tickstart = HAL_GetTick(); /* Wait till HSI is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) { - if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -460,9 +461,9 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) tickstart = HAL_GetTick(); /* Wait till HSI is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) { - if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -471,13 +472,13 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) } } /*------------------------------ LSI Configuration -------------------------*/ - if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ - if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF) + if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF) { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); @@ -486,9 +487,9 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) tickstart = HAL_GetTick(); /* Wait till LSI is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) { - if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -503,9 +504,9 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) tickstart = HAL_GetTick(); /* Wait till LSI is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) { - if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -513,21 +514,21 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) } } /*------------------------------ LSE Configuration -------------------------*/ - if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) { /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ - if(__HAL_RCC_PWR_IS_CLK_DISABLED()) + if (__HAL_RCC_PWR_IS_CLK_DISABLED()) { /* Enable Power Clock*/ __HAL_RCC_PWR_CLK_ENABLE(); pwrclkchanged = SET; } - if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) + if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) { /* Enable write access to Backup domain */ PWR->CR1 |= PWR_CR1_DBP; @@ -535,9 +536,9 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); - while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) + while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) { - if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -547,15 +548,15 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); /* Check the LSE State */ - if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF) + if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF) { /* Get Start Tick*/ tickstart = HAL_GetTick(); /* Wait till LSE is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) { - if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -567,9 +568,9 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) tickstart = HAL_GetTick(); /* Wait till LSE is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) { - if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -577,7 +578,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) } /* Restore clock configuration if changed */ - if(pwrclkchanged == SET) + if (pwrclkchanged == SET) { __HAL_RCC_PWR_CLK_DISABLE(); } @@ -588,9 +589,9 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) { /* Check if the PLL is used as system clock or not */ - if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) { - if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) + if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) { /* Check the parameters */ assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); @@ -609,9 +610,9 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) tickstart = HAL_GetTick(); /* Wait till PLL is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) { - if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -640,9 +641,9 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) tickstart = HAL_GetTick(); /* Wait till PLL is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) { - if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -657,9 +658,9 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) tickstart = HAL_GetTick(); /* Wait till PLL is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) { - if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -668,7 +669,27 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) } else { - return HAL_ERROR; + /* Do not return HAL_ERROR if request repeats the current configuration */ + pll_config = RCC->PLLCFGR; +#if defined (RCC_PLLCFGR_PLLR) + if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((((RCC_OscInitStruct->PLL.PLLP) >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos)) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos))) +#else + if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((((RCC_OscInitStruct->PLL.PLLP) >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos)) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos))) +#endif + { + return HAL_ERROR; + } } } return HAL_OK; @@ -705,7 +726,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui uint32_t tickstart = 0; /* Check Null pointer */ - if(RCC_ClkInitStruct == NULL) + if (RCC_ClkInitStruct == NULL) { return HAL_ERROR; } @@ -719,30 +740,30 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui (HCLK) and the supply voltage of the device. */ /* Increasing the CPU frequency */ - if(FLatency > __HAL_FLASH_GET_LATENCY()) + if (FLatency > __HAL_FLASH_GET_LATENCY()) { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ - if(__HAL_FLASH_GET_LATENCY() != FLatency) + if (__HAL_FLASH_GET_LATENCY() != FLatency) { return HAL_ERROR; } } /*-------------------------- HCLK Configuration --------------------------*/ - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) { /* Set the highest APBx dividers in order to ensure that we do not go through a non-spec phase whatever we decrease or increase HCLK. */ - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); } - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); } @@ -753,24 +774,24 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui } /*------------------------- SYSCLK Configuration ---------------------------*/ - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* HSE is selected as System Clock Source */ - if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) { /* Check the HSE ready flag */ - if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) { return HAL_ERROR; } } /* PLL is selected as System Clock Source */ - else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) { /* Check the PLL ready flag */ - if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) { return HAL_ERROR; } @@ -779,7 +800,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui else { /* Check the HSI ready flag */ - if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) { return HAL_ERROR; } @@ -800,38 +821,38 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui } /* Decreasing the number of wait states because of lower CPU frequency */ - if(FLatency < __HAL_FLASH_GET_LATENCY()) + if (FLatency < __HAL_FLASH_GET_LATENCY()) { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ - if(__HAL_FLASH_GET_LATENCY() != FLatency) + if (__HAL_FLASH_GET_LATENCY() != FLatency) { return HAL_ERROR; } } /*-------------------------- PCLK1 Configuration ---------------------------*/ - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); } /*-------------------------- PCLK2 Configuration ---------------------------*/ - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3)); } /* Update the SystemCoreClock global variable */ - SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos]; + SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]; /* Configure the source of time base considering new system clocks settings*/ - HAL_InitTick (TICK_INT_PRIORITY); + HAL_InitTick(uwTickPrio); return HAL_OK; } @@ -888,7 +909,7 @@ void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_M assert_param(IS_RCC_MCO(RCC_MCOx)); assert_param(IS_RCC_MCODIV(RCC_MCODiv)); /* RCC_MCO1 */ - if(RCC_MCOx == RCC_MCO1) + if (RCC_MCOx == RCC_MCO1) { assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource)); @@ -990,7 +1011,7 @@ uint32_t HAL_RCC_GetSysClockFreq(void) case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ { sysclockfreq = HSI_VALUE; - break; + break; } case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock source */ { @@ -1005,16 +1026,16 @@ uint32_t HAL_RCC_GetSysClockFreq(void) if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLCFGR_PLLSRC_HSI) { /* HSE used as PLL clock source */ - pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); + pllvco = (uint32_t)((((uint64_t) HSE_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); } else { /* HSI used as PLL clock source */ - pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); + pllvco = (uint32_t)((((uint64_t) HSI_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); } - pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1 ) *2); + pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1) * 2); - sysclockfreq = pllvco/pllp; + sysclockfreq = pllvco / pllp; break; } default: @@ -1047,7 +1068,7 @@ uint32_t HAL_RCC_GetHCLKFreq(void) uint32_t HAL_RCC_GetPCLK1Freq(void) { /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ - return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> RCC_CFGR_PPRE1_Pos]); + return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]); } /** @@ -1059,7 +1080,7 @@ uint32_t HAL_RCC_GetPCLK1Freq(void) uint32_t HAL_RCC_GetPCLK2Freq(void) { /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ - return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> RCC_CFGR_PPRE2_Pos]); + return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]); } /** @@ -1075,11 +1096,11 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI; /* Get the HSE configuration -----------------------------------------------*/ - if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP) + if ((RCC->CR & RCC_CR_HSEBYP) == RCC_CR_HSEBYP) { RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS; } - else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON) + else if ((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON) { RCC_OscInitStruct->HSEState = RCC_HSE_ON; } @@ -1089,7 +1110,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) } /* Get the HSI configuration -----------------------------------------------*/ - if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION) + if ((RCC->CR & RCC_CR_HSION) == RCC_CR_HSION) { RCC_OscInitStruct->HSIState = RCC_HSI_ON; } @@ -1098,14 +1119,14 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) RCC_OscInitStruct->HSIState = RCC_HSI_OFF; } - RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos); + RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR & RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos); /* Get the LSE configuration -----------------------------------------------*/ - if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP) + if ((RCC->BDCR & RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP) { RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS; } - else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON) + else if ((RCC->BDCR & RCC_BDCR_LSEON) == RCC_BDCR_LSEON) { RCC_OscInitStruct->LSEState = RCC_LSE_ON; } @@ -1115,7 +1136,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) } /* Get the LSI configuration -----------------------------------------------*/ - if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION) + if ((RCC->CSR & RCC_CSR_LSION) == RCC_CSR_LSION) { RCC_OscInitStruct->LSIState = RCC_LSI_ON; } @@ -1125,7 +1146,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) } /* Get the PLL configuration -----------------------------------------------*/ - if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON) + if ((RCC->CR & RCC_CR_PLLON) == RCC_CR_PLLON) { RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON; } @@ -1180,7 +1201,7 @@ void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pF void HAL_RCC_NMI_IRQHandler(void) { /* Check RCC CSSF flag */ - if(__HAL_RCC_GET_IT(RCC_IT_CSS)) + if (__HAL_RCC_GET_IT(RCC_IT_CSS)) { /* RCC Clock Security System interrupt user callback */ HAL_RCC_CSSCallback(); diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rng.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rng.c index 3e073e291d..ceabe3e90f 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rng.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rng.c @@ -532,8 +532,16 @@ HAL_StatusTypeDef HAL_RNG_UnRegisterReadyDataCallback(RNG_HandleTypeDef *hrng) /** * @brief Generates a 32-bit random number. - * @note Each time the random number data is read the RNG_FLAG_DRDY flag - * is automatically cleared. + * @note This function checks value of RNG_FLAG_DRDY flag to know if valid + * random number is available in the DR register (RNG_FLAG_DRDY flag set + * whenever a random number is available through the RNG_DR register). + * After transitioning from 0 to 1 (random number available), + * RNG_FLAG_DRDY flag remains high until output buffer becomes empty after reading + * four words from the RNG_DR register, i.e. further function calls + * will immediately return a new u32 random number (additional words are + * available and can be read by the application, till RNG_FLAG_DRDY flag remains high). + * @note When no more random number data is available in DR register, RNG_FLAG_DRDY + * flag is automatically cleared. * @param hrng pointer to a RNG_HandleTypeDef structure that contains * the configuration information for RNG. * @param random32bit pointer to generated random number variable if successful. @@ -697,13 +705,13 @@ void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng) if (__HAL_RNG_GET_IT(hrng, RNG_IT_CEI) != RESET) { /* Update the error code */ - hrng->ErrorCode = HAL_RNG_ERROR_SEED; + hrng->ErrorCode = HAL_RNG_ERROR_CLOCK; rngclockerror = 1U; } else if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET) { /* Update the error code */ - hrng->ErrorCode = HAL_RNG_ERROR_CLOCK; + hrng->ErrorCode = HAL_RNG_ERROR_SEED; rngclockerror = 1U; } else @@ -768,6 +776,11 @@ uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng) /** * @brief Data Ready callback in non-blocking mode. + * @note When RNG_FLAG_DRDY flag value is set, first random number has been read + * from DR register in IRQ Handler and is provided as callback parameter. + * Depending on valid data available in the conditioning output buffer, + * additional words can be read by the application from DR register till + * DRDY bit remains high. * @param hrng pointer to a RNG_HandleTypeDef structure that contains * the configuration information for RNG. * @param random32bit generated random number. diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.c index de5a34aad1..dad8655fda 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.c @@ -1586,10 +1586,11 @@ HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA */ void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc) { - if(__HAL_RTC_ALARM_GET_IT(hrtc, RTC_IT_ALRA)) + /* Get the AlarmA interrupt source enable status */ + if(__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRA) != (uint32_t)RESET) { - /* Get the status of the Interrupt */ - if((uint32_t)(hrtc->Instance->CR & RTC_IT_ALRA) != (uint32_t)RESET) + /* Get the pending status of the AlarmA Interrupt */ + if(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) != (uint32_t)RESET) { /* AlarmA callback */ #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) @@ -1598,15 +1599,16 @@ void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc) HAL_RTC_AlarmAEventCallback(hrtc); #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ - /* Clear the Alarm interrupt pending bit */ + /* Clear the AlarmA interrupt pending bit */ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc,RTC_FLAG_ALRAF); } } - if(__HAL_RTC_ALARM_GET_IT(hrtc, RTC_IT_ALRB)) + /* Get the AlarmB interrupt source enable status */ + if(__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRB) != (uint32_t)RESET) { - /* Get the status of the Interrupt */ - if((uint32_t)(hrtc->Instance->CR & RTC_IT_ALRB) != (uint32_t)RESET) + /* Get the pending status of the AlarmB Interrupt */ + if(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) != (uint32_t)RESET) { /* AlarmB callback */ #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) @@ -1615,7 +1617,7 @@ void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc) HAL_RTCEx_AlarmBEventCallback(hrtc); #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ - /* Clear the Alarm interrupt pending bit */ + /* Clear the AlarmB interrupt pending bit */ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc,RTC_FLAG_ALRBF); } } diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.c index c98f0af748..93592802c1 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.c @@ -656,10 +656,11 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t T */ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) { - if(__HAL_RTC_TIMESTAMP_GET_IT(hrtc, RTC_IT_TS)) + /* Get the TimeStamp interrupt source enable status */ + if(__HAL_RTC_TIMESTAMP_GET_IT_SOURCE(hrtc, RTC_IT_TS) != (uint32_t)RESET) { - /* Get the status of the Interrupt */ - if((uint32_t)(hrtc->Instance->CR & RTC_IT_TS) != (uint32_t)RESET) + /* Get the pending status of the TIMESTAMP Interrupt */ + if(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) != (uint32_t)RESET) { /* TIMESTAMP callback */ #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) @@ -673,12 +674,11 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) } } - /* Get the status of the Interrupt */ - if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F)== SET) + /* Get the Tamper1 interrupt source enable status */ + if(__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP1) != (uint32_t)RESET) { - /* Get the TAMPER Interrupt enable bit and pending bit */ - if((((hrtc->Instance->TAMPCR & RTC_TAMPCR_TAMPIE)) != (uint32_t)RESET) || \ - (((hrtc->Instance->TAMPCR & RTC_TAMPCR_TAMP1IE)) != (uint32_t)RESET)) + /* Get the pending status of the Tamper1 Interrupt */ + if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F) != (uint32_t)RESET) { /* Tamper callback */ #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) @@ -692,12 +692,11 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) } } - /* Get the status of the Interrupt */ - if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F)== SET) + /* Get the Tamper2 interrupt source enable status */ + if(__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP2) != (uint32_t)RESET) { - /* Get the TAMPER Interrupt enable bit and pending bit */ - if((((hrtc->Instance->TAMPCR & RTC_TAMPCR_TAMPIE)) != (uint32_t)RESET) || \ - (((hrtc->Instance->TAMPCR & RTC_TAMPCR_TAMP2IE)) != (uint32_t)RESET)) + /* Get the pending status of the Tamper2 Interrupt */ + if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) != (uint32_t)RESET) { /* Tamper callback */ #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) @@ -711,12 +710,11 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) } } - /* Get the status of the Interrupt */ - if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F)== SET) + /* Get the Tamper3 interrupt source enable status */ + if(__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP3) != (uint32_t)RESET) { - /* Get the TAMPER Interrupt enable bit and pending bit */ - if((((hrtc->Instance->TAMPCR & RTC_TAMPCR_TAMPIE)) != (uint32_t)RESET) || \ - (((hrtc->Instance->TAMPCR & RTC_TAMPCR_TAMP3IE)) != (uint32_t)RESET)) + /* Get the pending status of the Tamper3 Interrupt */ + if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F) != (uint32_t)RESET) { /* Tamper callback */ #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) @@ -1211,27 +1209,29 @@ uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc) /** * @brief This function handles Wake Up Timer interrupt request. + * @note Unlike alarm interrupt line (shared by AlarmA and AlarmB) and tamper + * interrupt line (shared by timestamp and tampers) wakeup timer + * interrupt line is exclusive to the wakeup timer. + * There is no need in this case to check on the interrupt enable + * status via __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(). * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval None */ void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc) { - if(__HAL_RTC_WAKEUPTIMER_GET_IT(hrtc, RTC_IT_WUT)) + /* Get the pending status of the WAKEUPTIMER Interrupt */ + if(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) != (uint32_t)RESET) { - /* Get the status of the Interrupt */ - if((uint32_t)(hrtc->Instance->CR & RTC_IT_WUT) != (uint32_t)RESET) - { - /* WAKEUPTIMER callback */ + /* WAKEUPTIMER callback */ #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - hrtc->WakeUpTimerEventCallback(hrtc); + hrtc->WakeUpTimerEventCallback(hrtc); #else - HAL_RTCEx_WakeUpTimerEventCallback(hrtc); + HAL_RTCEx_WakeUpTimerEventCallback(hrtc); #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ - /* Clear the WAKEUPTIMER interrupt pending bit */ - __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF); - } + /* Clear the WAKEUPTIMER interrupt pending bit */ + __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF); } /* Clear the EXTI's line Flag for RTC WakeUpTimer */ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sai.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sai.c index 3c2cddee7a..e8022f4b92 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sai.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sai.c @@ -132,12 +132,13 @@ *** Callback registration *** ============================= - + [..] The compilation define USE_HAL_SAI_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use functions @ref HAL_SAI_RegisterCallback() to register a user callback. + Use functions HAL_SAI_RegisterCallback() to register a user callback. - Function @ref HAL_SAI_RegisterCallback() allows to register following callbacks: + [..] + Function HAL_SAI_RegisterCallback() allows to register following callbacks: (+) RxCpltCallback : SAI receive complete. (+) RxHalfCpltCallback : SAI receive half complete. (+) TxCpltCallback : SAI transmit complete. @@ -145,13 +146,16 @@ (+) ErrorCallback : SAI error. (+) MspInitCallback : SAI MspInit. (+) MspDeInitCallback : SAI MspDeInit. + [..] This function takes as parameters the HAL peripheral handle, the callback ID and a pointer to the user callback function. - Use function @ref HAL_SAI_UnRegisterCallback() to reset a callback to the default + [..] + Use function HAL_SAI_UnRegisterCallback() to reset a callback to the default weak (surcharged) function. - @ref HAL_SAI_UnRegisterCallback() takes as parameters the HAL peripheral handle, + HAL_SAI_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the callback ID. + [..] This function allows to reset following callbacks: (+) RxCpltCallback : SAI receive complete. (+) RxHalfCpltCallback : SAI receive half complete. @@ -161,23 +165,26 @@ (+) MspInitCallback : SAI MspInit. (+) MspDeInitCallback : SAI MspDeInit. - By default, after the @ref HAL_SAI_Init and if the state is HAL_SAI_STATE_RESET + [..] + By default, after the HAL_SAI_Init and if the state is HAL_SAI_STATE_RESET all callbacks are reset to the corresponding legacy weak (surcharged) functions: - examples @ref HAL_SAI_RxCpltCallback(), @ref HAL_SAI_ErrorCallback(). + examples HAL_SAI_RxCpltCallback(), HAL_SAI_ErrorCallback(). Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_SAI_Init - and @ref HAL_SAI_DeInit only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the @ref HAL_SAI_Init and @ref HAL_SAI_DeInit + reset to the legacy weak (surcharged) functions in the HAL_SAI_Init + and HAL_SAI_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_SAI_Init and HAL_SAI_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand). + [..] Callbacks can be registered/unregistered in READY state only. Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_SAI_RegisterCallback before calling @ref HAL_SAI_DeInit - or @ref HAL_SAI_Init function. + using HAL_SAI_RegisterCallback before calling HAL_SAI_DeInit + or HAL_SAI_Init function. + [..] When the compilation define USE_HAL_SAI_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available and weak (surcharged) callbacks are used. @@ -228,7 +235,6 @@ typedef enum { /** @defgroup SAI_Private_Constants SAI Private Constants * @{ */ -#define SAI_FIFO_SIZE 8 #define SAI_DEFAULT_TIMEOUT 4 /* 4ms */ /** * @} @@ -507,6 +513,8 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai) hsai->Init.Mckdiv+= 1; } } + /* Check the SAI Block master clock divider parameter */ + assert_param(IS_SAI_BLOCK_MASTER_DIVIDER(hsai->Init.Mckdiv)); /* Compute CKSTR bits of SAI CR1 according ClockStrobing and AudioMode */ if((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX)) @@ -2344,7 +2352,7 @@ static void SAI_DMATxCplt(DMA_HandleTypeDef *hdma) { SAI_HandleTypeDef* hsai = (SAI_HandleTypeDef*)((DMA_HandleTypeDef* )hdma)->Parent; - if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0) + if (hdma->Init.Mode != DMA_CIRCULAR) { hsai->XferCount = 0; @@ -2390,7 +2398,7 @@ static void SAI_DMARxCplt(DMA_HandleTypeDef *hdma) { SAI_HandleTypeDef* hsai = ( SAI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0) + if (hdma->Init.Mode != DMA_CIRCULAR) { /* Disable Rx DMA Request */ hsai->Instance->CR1 &= (uint32_t)(~SAI_xCR1_DMAEN); diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c index ecef3963a1..e6c84fb261 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c @@ -8,7 +8,7 @@ * + Initialization and de-initialization functions * + IO operation functions * + Peripheral Control functions - * + SD card Control functions + * + Peripheral State functions * @verbatim ============================================================================== @@ -27,13 +27,13 @@ SDMMC driver functions to interface with SD and uSD cards devices. It is used as follows: - (#)Initialize the SDMMC low level resources by implement the HAL_SD_MspInit() API: + (#)Initialize the SDMMC low level resources by implementing the HAL_SD_MspInit() API: (##) Enable the SDMMC interface clock using __HAL_RCC_SDMMC_CLK_ENABLE(); (##) SDMMC pins configuration for SD card (+++) Enable the clock for the SDMMC GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE(); (+++) Configure these SDMMC pins as alternate function pull-up using HAL_GPIO_Init() and according to your pin assignment; - (##) DMA Configuration if you need to use DMA process (HAL_SD_ReadBlocks_DMA() + (##) DMA configuration if you need to use DMA process (HAL_SD_ReadBlocks_DMA() and HAL_SD_WriteBlocks_DMA() APIs). (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE(); (+++) Configure the DMA using the function HAL_DMA_Init() with predeclared and filled. @@ -47,8 +47,7 @@ and __HAL_SD_CLEAR_IT() (##) NVIC configuration if you need to use interrupt process (HAL_SD_ReadBlocks_IT() and HAL_SD_WriteBlocks_IT() APIs). - (+++) Configure the SDMMC interrupt priorities using function - HAL_NVIC_SetPriority(); + (+++) Configure the SDMMC interrupt priorities using function HAL_NVIC_SetPriority(); (+++) Enable the NVIC SDMMC IRQs using function HAL_NVIC_EnableIRQ() (+++) SDMMC interrupts are managed using the macros __HAL_SD_ENABLE_IT() and __HAL_SD_DISABLE_IT() inside the communication process. @@ -61,12 +60,12 @@ ================================================ [..] To initialize the SD Card, use the HAL_SD_Init() function. It Initializes - SDMMC IP (STM32 side) and the SD Card, and put it into StandBy State (Ready for data transfer). + SDMMC Peripheral(STM32 side) and the SD Card, and put it into StandBy State (Ready for data transfer). This function provide the following operations: - (#) Initialize the SDMMC peripheral interface with defaullt configuration. - The initialization process is done at 400KHz. You can change or adapt - this frequency by adjusting the "ClockDiv" field. + (#) Apply the SD Card initialization process at 400KHz and check the SD Card + type (Standard Capacity or High Capacity). You can change or adapt this + frequency by adjusting the "ClockDiv" field. The SD Card frequency (SDMMC_CK) is computed as follows: SDMMC_CK = SDMMCCLK / (ClockDiv + 2) @@ -85,9 +84,8 @@ This API (HAL_SD_InitCard()) could be used also to reinitialize the card in case of plug-off plug-in. - (#) Configure the SD Card Data transfer frequency. By Default, the card transfer - frequency is set to 24MHz. You can change or adapt this frequency by adjusting - the "ClockDiv" field. + (#) Configure the SD Card Data transfer frequency. You can change or adapt this + frequency by adjusting the "ClockDiv" field. In transfer mode and according to the SD Card standard, make sure that the SDMMC_CK frequency doesn't exceed 25MHz and 50MHz in High-speed mode switch. To be able to use a frequency higher than 24MHz, you should use the SDMMC @@ -102,14 +100,16 @@ ============================== [..] (+) You can read from SD card in polling mode by using function HAL_SD_ReadBlocks(). - This function allows the read of 512 bytes blocks. + This function support only 512-bytes block length (the block size should be + chosen as 512 bytes). You can choose either one block read operation or multiple block read operation by adjusting the "NumberOfBlocks" parameter. After this, you have to ensure that the transfer is done correctly. The check is done through HAL_SD_GetCardState() function for SD card state. (+) You can read from SD card in DMA mode by using function HAL_SD_ReadBlocks_DMA(). - This function allows the read of 512 bytes blocks. + This function support only 512-bytes block length (the block size should be + chosen as 512 bytes). You can choose either one block read operation or multiple block read operation by adjusting the "NumberOfBlocks" parameter. After this, you have to ensure that the transfer is done correctly. The check is done @@ -117,7 +117,8 @@ You could also check the DMA transfer process through the SD Rx interrupt event. (+) You can read from SD card in Interrupt mode by using function HAL_SD_ReadBlocks_IT(). - This function allows the read of 512 bytes blocks. + This function support only 512-bytes block length (the block size should be + chosen as 512 bytes). You can choose either one block read operation or multiple block read operation by adjusting the "NumberOfBlocks" parameter. After this, you have to ensure that the transfer is done correctly. The check is done @@ -128,14 +129,16 @@ =============================== [..] (+) You can write to SD card in polling mode by using function HAL_SD_WriteBlocks(). - This function allows the read of 512 bytes blocks. + This function support only 512-bytes block length (the block size should be + chosen as 512 bytes). You can choose either one block read operation or multiple block read operation by adjusting the "NumberOfBlocks" parameter. After this, you have to ensure that the transfer is done correctly. The check is done through HAL_SD_GetCardState() function for SD card state. (+) You can write to SD card in DMA mode by using function HAL_SD_WriteBlocks_DMA(). - This function allows the read of 512 bytes blocks. + This function support only 512-bytes block length (the block size should be + chosen as 512 bytes). You can choose either one block read operation or multiple block read operation by adjusting the "NumberOfBlocks" parameter. After this, you have to ensure that the transfer is done correctly. The check is done @@ -143,7 +146,8 @@ You could also check the DMA transfer process through the SD Tx interrupt event. (+) You can write to SD card in Interrupt mode by using function HAL_SD_WriteBlocks_IT(). - This function allows the read of 512 bytes blocks. + This function support only 512-bytes block length (the block size should be + chosen as 512 bytes). You can choose either one block read operation or multiple block read operation by adjusting the "NumberOfBlocks" parameter. After this, you have to ensure that the transfer is done correctly. The check is done @@ -165,13 +169,11 @@ *** SD card CSD register *** ============================ - [..] (+) The HAL_SD_GetCardCSD() API allows to get the parameters of the CSD register. Some of the CSD parameters are useful for card initialization and identification. *** SD card CID register *** ============================ - [..] (+) The HAL_SD_GetCardCID() API allows to get the parameters of the CID register. Some of the CSD parameters are useful for card initialization and identification. @@ -189,7 +191,6 @@ (+) __HAL_SD_GET_FLAG:Check whether the specified SD flag is set or not (+) __HAL_SD_CLEAR_FLAG: Clear the SD's pending flags - [..] (@) You can refer to the SD HAL driver header file for more useful macros *** Callback registration *** @@ -249,7 +250,7 @@ * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -257,6 +258,8 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32f7xx_hal.h" +#if defined(SDMMC1) + /** @addtogroup STM32F7xx_HAL_Driver * @{ */ @@ -291,9 +294,9 @@ static uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus); static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd); static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd); static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR); -static HAL_StatusTypeDef SD_PowerOFF(SD_HandleTypeDef *hsd); -static HAL_StatusTypeDef SD_Write_IT(SD_HandleTypeDef *hsd); -static HAL_StatusTypeDef SD_Read_IT(SD_HandleTypeDef *hsd); +static void SD_PowerOFF(SD_HandleTypeDef *hsd); +static void SD_Write_IT(SD_HandleTypeDef *hsd); +static void SD_Read_IT(SD_HandleTypeDef *hsd); static void SD_DMATransmitCplt(DMA_HandleTypeDef *hdma); static void SD_DMAReceiveCplt(DMA_HandleTypeDef *hdma); static void SD_DMAError(DMA_HandleTypeDef *hdma); @@ -326,7 +329,7 @@ static void SD_DMARxAbort(DMA_HandleTypeDef *hdma); /** * @brief Initializes the SD according to the specified parameters in the SD_HandleTypeDef and create the associated handle. - * @param hsd Pointer to the SD handle + * @param hsd: Pointer to the SD handle * @retval HAL status */ HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd) @@ -350,7 +353,7 @@ HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd) { /* Allocate lock resource and initialize it */ hsd->Lock = HAL_UNLOCKED; -#if (USE_HAL_SD_REGISTER_CALLBACKS == 1) +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) /* Reset Callback pointers in HAL_SD_STATE_RESET only */ hsd->TxCpltCallback = HAL_SD_TxCpltCallback; hsd->RxCpltCallback = HAL_SD_RxCpltCallback; @@ -367,16 +370,19 @@ HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd) #else /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ HAL_SD_MspInit(hsd); -#endif +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ } hsd->State = HAL_SD_STATE_BUSY; /* Initialize the Card parameters */ - HAL_SD_InitCard(hsd); + if (HAL_SD_InitCard(hsd) != HAL_OK) + { + return HAL_ERROR; + } /* Initialize the error code */ - hsd->ErrorCode = HAL_DMA_ERROR_NONE; + hsd->ErrorCode = HAL_SD_ERROR_NONE; /* Initialize the SD operation */ hsd->Context = SD_CONTEXT_NONE; @@ -389,14 +395,15 @@ HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd) /** * @brief Initializes the SD Card. - * @param hsd Pointer to SD handle + * @param hsd: Pointer to SD handle * @note This function initializes the SD card. It could be used when a card re-initialization is needed. * @retval HAL status */ HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd) { - uint32_t errorstate = HAL_SD_ERROR_NONE; + uint32_t errorstate; + HAL_StatusTypeDef status; SD_InitTypeDef Init; /* Default SDMMC peripheral configuration for SD card initialization */ @@ -408,20 +415,21 @@ HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd) Init.ClockDiv = SDMMC_INIT_CLK_DIV; /* Initialize SDMMC peripheral interface with default configuration */ - SDMMC_Init(hsd->Instance, Init); + status = SDMMC_Init(hsd->Instance, Init); + if(status != HAL_OK) + { + return HAL_ERROR; + } /* Disable SDMMC Clock */ __HAL_SD_DISABLE(hsd); /* Set Power State to ON */ - SDMMC_PowerState_ON(hsd->Instance); + (void)SDMMC_PowerState_ON(hsd->Instance); /* Enable SDMMC Clock */ __HAL_SD_ENABLE(hsd); - /* Required power up waiting time before starting the SD initialization sequence */ - HAL_Delay(2); - /* Identify card operating voltage */ errorstate = SD_PowerON(hsd); if(errorstate != HAL_SD_ERROR_NONE) @@ -445,7 +453,7 @@ HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd) /** * @brief De-Initializes the SD card. - * @param hsd Pointer to SD handle + * @param hsd: Pointer to SD handle * @retval HAL status */ HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd) @@ -464,7 +472,7 @@ HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd) /* Set SD power state to off */ SD_PowerOFF(hsd); -#if (USE_HAL_SD_REGISTER_CALLBACKS == 1) +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) if(hsd->MspDeInitCallback == NULL) { hsd->MspDeInitCallback = HAL_SD_MspDeInit; @@ -475,7 +483,7 @@ HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd) #else /* De-Initialize the MSP layer */ HAL_SD_MspDeInit(hsd); -#endif +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ hsd->ErrorCode = HAL_SD_ERROR_NONE; hsd->State = HAL_SD_STATE_RESET; @@ -486,7 +494,7 @@ HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd) /** * @brief Initializes the SD MSP. - * @param hsd Pointer to SD handle + * @param hsd: Pointer to SD handle * @retval None */ __weak void HAL_SD_MspInit(SD_HandleTypeDef *hsd) @@ -494,14 +502,14 @@ __weak void HAL_SD_MspInit(SD_HandleTypeDef *hsd) /* Prevent unused argument(s) compilation warning */ UNUSED(hsd); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_SD_MspInit could be implemented in the user file */ } /** * @brief De-Initialize SD MSP. - * @param hsd Pointer to SD handle + * @param hsd: Pointer to SD handle * @retval None */ __weak void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd) @@ -509,7 +517,7 @@ __weak void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd) /* Prevent unused argument(s) compilation warning */ UNUSED(hsd); - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_SD_MspDeInit could be implemented in the user file */ } @@ -538,19 +546,21 @@ __weak void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd) * is managed by polling mode. * @note This API should be followed by a check on the card state through * HAL_SD_GetCardState(). - * @param hsd Pointer to SD handle - * @param pData pointer to the buffer that will contain the received data - * @param BlockAdd Block Address from where data is to be read - * @param NumberOfBlocks Number of SD blocks to read - * @param Timeout Specify timeout value + * @param hsd: Pointer to SD handle + * @param pData: pointer to the buffer that will contain the received data + * @param BlockAdd: Block Address from where data is to be read + * @param NumberOfBlocks: Number of SD blocks to read + * @param Timeout: Specify timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout) { SDMMC_DataInitTypeDef config; - uint32_t errorstate = HAL_SD_ERROR_NONE; + uint32_t errorstate; uint32_t tickstart = HAL_GetTick(); - uint32_t count = 0, *tempbuff = (uint32_t *)pData; + uint32_t count, data, dataremaining; + uint32_t add = BlockAdd; + uint8_t *tempbuff = pData; if(NULL == pData) { @@ -560,9 +570,9 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3 if(hsd->State == HAL_SD_STATE_READY) { - hsd->ErrorCode = HAL_DMA_ERROR_NONE; + hsd->ErrorCode = HAL_SD_ERROR_NONE; - if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) + if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) { hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; return HAL_ERROR; @@ -571,11 +581,11 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3 hsd->State = HAL_SD_STATE_BUSY; /* Initialize data control register */ - hsd->Instance->DCTRL = 0; + hsd->Instance->DCTRL = 0U; if(hsd->SdCard.CardType != CARD_SDHC_SDXC) { - BlockAdd *= 512; + add *= 512U; } /* Set Block Size for Card */ @@ -596,22 +606,22 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3 config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; config.DPSM = SDMMC_DPSM_ENABLE; - SDMMC_ConfigData(hsd->Instance, &config); + (void)SDMMC_ConfigData(hsd->Instance, &config); /* Read block(s) in polling mode */ - if(NumberOfBlocks > 1) + if(NumberOfBlocks > 1U) { hsd->Context = SD_CONTEXT_READ_MULTIPLE_BLOCK; /* Read Multi Block command */ - errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, BlockAdd); + errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add); } else { hsd->Context = SD_CONTEXT_READ_SINGLE_BLOCK; /* Read Single Block command */ - errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, BlockAdd); + errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add); } if(errorstate != HAL_SD_ERROR_NONE) { @@ -619,28 +629,42 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3 __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); hsd->ErrorCode |= errorstate; hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; return HAL_ERROR; } /* Poll on SDMMC flags */ + dataremaining = config.DataLength; while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) { - if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF)) + if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF) && (dataremaining > 0U)) { /* Read data from SDMMC Rx FIFO */ for(count = 0U; count < 8U; count++) { - *(tempbuff + count) = SDMMC_ReadFIFO(hsd->Instance); + data = SDMMC_ReadFIFO(hsd->Instance); + *tempbuff = (uint8_t)(data & 0xFFU); + tempbuff++; + dataremaining--; + *tempbuff = (uint8_t)((data >> 8U) & 0xFFU); + tempbuff++; + dataremaining--; + *tempbuff = (uint8_t)((data >> 16U) & 0xFFU); + tempbuff++; + dataremaining--; + *tempbuff = (uint8_t)((data >> 24U) & 0xFFU); + tempbuff++; + dataremaining--; } - tempbuff += 8U; } - if((Timeout == 0U)||((HAL_GetTick()-tickstart) >= Timeout)) + if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U)) { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); hsd->ErrorCode |= HAL_SD_ERROR_TIMEOUT; hsd->State= HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; return HAL_TIMEOUT; } } @@ -658,6 +682,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3 __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); hsd->ErrorCode |= errorstate; hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; return HAL_ERROR; } } @@ -670,6 +695,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3 __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT; hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; return HAL_ERROR; } else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL)) @@ -678,6 +704,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3 __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL; hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; return HAL_ERROR; } else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR)) @@ -686,27 +713,44 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3 __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); hsd->ErrorCode |= HAL_SD_ERROR_RX_OVERRUN; hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; return HAL_ERROR; } + else + { + /* Nothing to do */ + } /* Empty FIFO if there is still any data */ - while ((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL))) + while ((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL)) && (dataremaining > 0U)) { - *tempbuff = SDMMC_ReadFIFO(hsd->Instance); + data = SDMMC_ReadFIFO(hsd->Instance); + *tempbuff = (uint8_t)(data & 0xFFU); + tempbuff++; + dataremaining--; + *tempbuff = (uint8_t)((data >> 8U) & 0xFFU); + tempbuff++; + dataremaining--; + *tempbuff = (uint8_t)((data >> 16U) & 0xFFU); + tempbuff++; + dataremaining--; + *tempbuff = (uint8_t)((data >> 24U) & 0xFFU); tempbuff++; + dataremaining--; - if((Timeout == 0U)||((HAL_GetTick()-tickstart) >= Timeout)) + if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U)) { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); hsd->ErrorCode |= HAL_SD_ERROR_TIMEOUT; hsd->State= HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; return HAL_ERROR; } } /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); hsd->State = HAL_SD_STATE_READY; @@ -724,20 +768,21 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3 * transfer is managed by polling mode. * @note This API should be followed by a check on the card state through * HAL_SD_GetCardState(). - * @param hsd Pointer to SD handle - * @param pData pointer to the buffer that will contain the data to transmit - * @param BlockAdd Block Address where data will be written - * @param NumberOfBlocks Number of SD blocks to write - * @param Timeout Specify timeout value + * @param hsd: Pointer to SD handle + * @param pData: pointer to the buffer that will contain the data to transmit + * @param BlockAdd: Block Address where data will be written + * @param NumberOfBlocks: Number of SD blocks to write + * @param Timeout: Specify timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout) { SDMMC_DataInitTypeDef config; - uint32_t errorstate = HAL_SD_ERROR_NONE; + uint32_t errorstate; uint32_t tickstart = HAL_GetTick(); - uint32_t count = 0; - uint32_t *tempbuff = (uint32_t *)pData; + uint32_t count, data, dataremaining; + uint32_t add = BlockAdd; + uint8_t *tempbuff = pData; if(NULL == pData) { @@ -747,9 +792,9 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint if(hsd->State == HAL_SD_STATE_READY) { - hsd->ErrorCode = HAL_DMA_ERROR_NONE; + hsd->ErrorCode = HAL_SD_ERROR_NONE; - if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) + if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) { hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; return HAL_ERROR; @@ -758,11 +803,11 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint hsd->State = HAL_SD_STATE_BUSY; /* Initialize data control register */ - hsd->Instance->DCTRL = 0; + hsd->Instance->DCTRL = 0U; if(hsd->SdCard.CardType != CARD_SDHC_SDXC) { - BlockAdd *= 512; + add *= 512U; } /* Set Block Size for Card */ @@ -776,20 +821,29 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint return HAL_ERROR; } + /* Configure the SD DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = NumberOfBlocks * BLOCKSIZE; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_ENABLE; + (void)SDMMC_ConfigData(hsd->Instance, &config); + /* Write Blocks in Polling mode */ if(NumberOfBlocks > 1U) { hsd->Context = SD_CONTEXT_WRITE_MULTIPLE_BLOCK; /* Write Multi Block command */ - errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, BlockAdd); + errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add); } else { hsd->Context = SD_CONTEXT_WRITE_SINGLE_BLOCK; /* Write Single Block command */ - errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, BlockAdd); + errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add); } if(errorstate != HAL_SD_ERROR_NONE) { @@ -797,37 +851,42 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); hsd->ErrorCode |= errorstate; hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; return HAL_ERROR; } - /* Configure the SD DPSM (Data Path State Machine) */ - config.DataTimeOut = SDMMC_DATATIMEOUT; - config.DataLength = NumberOfBlocks * BLOCKSIZE; - config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; - config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; - config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; - config.DPSM = SDMMC_DPSM_ENABLE; - SDMMC_ConfigData(hsd->Instance, &config); - /* Write block(s) in polling mode */ + dataremaining = config.DataLength; while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) { - if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE)) + if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE) && (dataremaining > 0U)) { /* Write data to SDMMC Tx FIFO */ for(count = 0U; count < 8U; count++) { - SDMMC_WriteFIFO(hsd->Instance, (tempbuff + count)); + data = (uint32_t)(*tempbuff); + tempbuff++; + dataremaining--; + data |= ((uint32_t)(*tempbuff) << 8U); + tempbuff++; + dataremaining--; + data |= ((uint32_t)(*tempbuff) << 16U); + tempbuff++; + dataremaining--; + data |= ((uint32_t)(*tempbuff) << 24U); + tempbuff++; + dataremaining--; + (void)SDMMC_WriteFIFO(hsd->Instance, &data); } - tempbuff += 8U; } - if((Timeout == 0U)||((HAL_GetTick()-tickstart) >= Timeout)) + if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U)) { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); hsd->ErrorCode |= errorstate; hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; return HAL_TIMEOUT; } } @@ -845,6 +904,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); hsd->ErrorCode |= errorstate; hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; return HAL_ERROR; } } @@ -857,6 +917,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT; hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; return HAL_ERROR; } else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL)) @@ -865,6 +926,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL; hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; return HAL_ERROR; } else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR)) @@ -873,11 +935,16 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); hsd->ErrorCode |= HAL_SD_ERROR_TX_UNDERRUN; hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; return HAL_ERROR; } + else + { + /* Nothing to do */ + } /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); hsd->State = HAL_SD_STATE_READY; @@ -897,16 +964,17 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint * HAL_SD_GetCardState(). * @note You could also check the IT transfer process through the SD Rx * interrupt event. - * @param hsd Pointer to SD handle - * @param pData Pointer to the buffer that will contain the received data - * @param BlockAdd Block Address from where data is to be read - * @param NumberOfBlocks Number of blocks to read. + * @param hsd: Pointer to SD handle + * @param pData: Pointer to the buffer that will contain the received data + * @param BlockAdd: Block Address from where data is to be read + * @param NumberOfBlocks: Number of blocks to read. * @retval HAL status */ HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) { SDMMC_DataInitTypeDef config; - uint32_t errorstate = HAL_SD_ERROR_NONE; + uint32_t errorstate; + uint32_t add = BlockAdd; if(NULL == pData) { @@ -916,9 +984,9 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, ui if(hsd->State == HAL_SD_STATE_READY) { - hsd->ErrorCode = HAL_DMA_ERROR_NONE; + hsd->ErrorCode = HAL_SD_ERROR_NONE; - if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) + if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) { hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; return HAL_ERROR; @@ -929,25 +997,16 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, ui /* Initialize data control register */ hsd->Instance->DCTRL = 0U; - hsd->pRxBuffPtr = (uint32_t *)pData; + hsd->pRxBuffPtr = pData; hsd->RxXferSize = BLOCKSIZE * NumberOfBlocks; __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND | SDMMC_FLAG_RXFIFOHF)); if(hsd->SdCard.CardType != CARD_SDHC_SDXC) { - BlockAdd *= 512U; + add *= 512U; } - /* Configure the SD DPSM (Data Path State Machine) */ - config.DataTimeOut = SDMMC_DATATIMEOUT; - config.DataLength = BLOCKSIZE * NumberOfBlocks; - config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; - config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; - config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; - config.DPSM = SDMMC_DPSM_ENABLE; - SDMMC_ConfigData(hsd->Instance, &config); - /* Set Block Size for Card */ errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); if(errorstate != HAL_SD_ERROR_NONE) @@ -959,20 +1018,29 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, ui return HAL_ERROR; } + /* Configure the SD DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = BLOCKSIZE * NumberOfBlocks; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_ENABLE; + (void)SDMMC_ConfigData(hsd->Instance, &config); + /* Read Blocks in IT mode */ if(NumberOfBlocks > 1U) { hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_IT); /* Read Multi Block command */ - errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, BlockAdd); + errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add); } else { hsd->Context = (SD_CONTEXT_READ_SINGLE_BLOCK | SD_CONTEXT_IT); /* Read Single Block command */ - errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, BlockAdd); + errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add); } if(errorstate != HAL_SD_ERROR_NONE) { @@ -980,6 +1048,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, ui __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); hsd->ErrorCode |= errorstate; hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; return HAL_ERROR; } @@ -998,16 +1067,17 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, ui * HAL_SD_GetCardState(). * @note You could also check the IT transfer process through the SD Tx * interrupt event. - * @param hsd Pointer to SD handle - * @param pData Pointer to the buffer that will contain the data to transmit - * @param BlockAdd Block Address where data will be written - * @param NumberOfBlocks Number of blocks to write + * @param hsd: Pointer to SD handle + * @param pData: Pointer to the buffer that will contain the data to transmit + * @param BlockAdd: Block Address where data will be written + * @param NumberOfBlocks: Number of blocks to write * @retval HAL status */ HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) { SDMMC_DataInitTypeDef config; - uint32_t errorstate = HAL_SD_ERROR_NONE; + uint32_t errorstate; + uint32_t add = BlockAdd; if(NULL == pData) { @@ -1017,9 +1087,9 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, u if(hsd->State == HAL_SD_STATE_READY) { - hsd->ErrorCode = HAL_DMA_ERROR_NONE; + hsd->ErrorCode = HAL_SD_ERROR_NONE; - if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) + if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) { hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; return HAL_ERROR; @@ -1030,7 +1100,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, u /* Initialize data control register */ hsd->Instance->DCTRL = 0U; - hsd->pTxBuffPtr = (uint32_t *)pData; + hsd->pTxBuffPtr = pData; hsd->TxXferSize = BLOCKSIZE * NumberOfBlocks; /* Enable transfer interrupts */ @@ -1038,7 +1108,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, u if(hsd->SdCard.CardType != CARD_SDHC_SDXC) { - BlockAdd *= 512U; + add *= 512U; } /* Set Block Size for Card */ @@ -1058,14 +1128,14 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, u hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK| SD_CONTEXT_IT); /* Write Multi Block command */ - errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, BlockAdd); + errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add); } else { hsd->Context = (SD_CONTEXT_WRITE_SINGLE_BLOCK | SD_CONTEXT_IT); /* Write Single Block command */ - errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, BlockAdd); + errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add); } if(errorstate != HAL_SD_ERROR_NONE) { @@ -1073,6 +1143,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, u __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); hsd->ErrorCode |= errorstate; hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; return HAL_ERROR; } @@ -1083,7 +1154,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, u config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; config.DPSM = SDMMC_DPSM_ENABLE; - SDMMC_ConfigData(hsd->Instance, &config); + (void)SDMMC_ConfigData(hsd->Instance, &config); return HAL_OK; } @@ -1100,16 +1171,17 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, u * HAL_SD_GetCardState(). * @note You could also check the DMA transfer process through the SD Rx * interrupt event. - * @param hsd Pointer SD handle - * @param pData Pointer to the buffer that will contain the received data - * @param BlockAdd Block Address from where data is to be read - * @param NumberOfBlocks Number of blocks to read. + * @param hsd: Pointer SD handle + * @param pData: Pointer to the buffer that will contain the received data + * @param BlockAdd: Block Address from where data is to be read + * @param NumberOfBlocks: Number of blocks to read. * @retval HAL status */ HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) { SDMMC_DataInitTypeDef config; - uint32_t errorstate = HAL_SD_ERROR_NONE; + uint32_t errorstate; + uint32_t add = BlockAdd; if(NULL == pData) { @@ -1119,9 +1191,9 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, u if(hsd->State == HAL_SD_STATE_READY) { - hsd->ErrorCode = HAL_DMA_ERROR_NONE; + hsd->ErrorCode = HAL_SD_ERROR_NONE; - if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) + if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) { hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; return HAL_ERROR; @@ -1144,61 +1216,71 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, u hsd->hdmarx->XferAbortCallback = NULL; /* Enable the DMA Channel */ - HAL_DMA_Start_IT(hsd->hdmarx, (uint32_t)&hsd->Instance->FIFO, (uint32_t)pData, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4); - - /* Enable SD DMA transfer */ - __HAL_SD_DMA_ENABLE(hsd); - - if(hsd->SdCard.CardType != CARD_SDHC_SDXC) - { - BlockAdd *= 512U; - } - - /* Configure the SD DPSM (Data Path State Machine) */ - config.DataTimeOut = SDMMC_DATATIMEOUT; - config.DataLength = BLOCKSIZE * NumberOfBlocks; - config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; - config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; - config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; - config.DPSM = SDMMC_DPSM_ENABLE; - SDMMC_ConfigData(hsd->Instance, &config); - - /* Set Block Size for Card */ - errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); - if(errorstate != HAL_SD_ERROR_NONE) + if(HAL_DMA_Start_IT(hsd->hdmarx, (uint32_t)&hsd->Instance->FIFO, (uint32_t)pData, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4U) != HAL_OK) { - /* Clear all the static flags */ + __HAL_SD_DISABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND)); __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - hsd->ErrorCode |= errorstate; + hsd->ErrorCode |= HAL_SD_ERROR_DMA; hsd->State = HAL_SD_STATE_READY; return HAL_ERROR; } - - /* Read Blocks in DMA mode */ - if(NumberOfBlocks > 1U) - { - hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA); - - /* Read Multi Block command */ - errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, BlockAdd); - } else { - hsd->Context = (SD_CONTEXT_READ_SINGLE_BLOCK | SD_CONTEXT_DMA); + /* Enable SD DMA transfer */ + __HAL_SD_DMA_ENABLE(hsd); - /* Read Single Block command */ - errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, BlockAdd); - } - if(errorstate != HAL_SD_ERROR_NONE) - { - /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - hsd->ErrorCode |= errorstate; - hsd->State = HAL_SD_STATE_READY; - return HAL_ERROR; - } + if(hsd->SdCard.CardType != CARD_SDHC_SDXC) + { + add *= 512U; + } - return HAL_OK; + /* Set Block Size for Card */ + errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); + if(errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; + } + + /* Configure the SD DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = BLOCKSIZE * NumberOfBlocks; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_ENABLE; + (void)SDMMC_ConfigData(hsd->Instance, &config); + + /* Read Blocks in DMA mode */ + if(NumberOfBlocks > 1U) + { + hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA); + + /* Read Multi Block command */ + errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add); + } + else + { + hsd->Context = (SD_CONTEXT_READ_SINGLE_BLOCK | SD_CONTEXT_DMA); + + /* Read Single Block command */ + errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add); + } + if(errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; + return HAL_ERROR; + } + + return HAL_OK; + } } else { @@ -1213,16 +1295,17 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, u * HAL_SD_GetCardState(). * @note You could also check the DMA transfer process through the SD Tx * interrupt event. - * @param hsd Pointer to SD handle - * @param pData Pointer to the buffer that will contain the data to transmit - * @param BlockAdd Block Address where data will be written - * @param NumberOfBlocks Number of blocks to write + * @param hsd: Pointer to SD handle + * @param pData: Pointer to the buffer that will contain the data to transmit + * @param BlockAdd: Block Address where data will be written + * @param NumberOfBlocks: Number of blocks to write * @retval HAL status */ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) { SDMMC_DataInitTypeDef config; - uint32_t errorstate = HAL_SD_ERROR_NONE; + uint32_t errorstate; + uint32_t add = BlockAdd; if(NULL == pData) { @@ -1232,9 +1315,9 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, if(hsd->State == HAL_SD_STATE_READY) { - hsd->ErrorCode = HAL_DMA_ERROR_NONE; + hsd->ErrorCode = HAL_SD_ERROR_NONE; - if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) + if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) { hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; return HAL_ERROR; @@ -1259,7 +1342,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, if(hsd->SdCard.CardType != CARD_SDHC_SDXC) { - BlockAdd *= 512U; + add *= 512U; } /* Set Block Size for Card */ @@ -1279,14 +1362,14 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK | SD_CONTEXT_DMA); /* Write Multi Block command */ - errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, BlockAdd); + errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add); } else { hsd->Context = (SD_CONTEXT_WRITE_SINGLE_BLOCK | SD_CONTEXT_DMA); /* Write Single Block command */ - errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, BlockAdd); + errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add); } if(errorstate != HAL_SD_ERROR_NONE) { @@ -1294,6 +1377,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); hsd->ErrorCode |= errorstate; hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; return HAL_ERROR; } @@ -1301,18 +1385,28 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, __HAL_SD_DMA_ENABLE(hsd); /* Enable the DMA Channel */ - HAL_DMA_Start_IT(hsd->hdmatx, (uint32_t)pData, (uint32_t)&hsd->Instance->FIFO, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4); - - /* Configure the SD DPSM (Data Path State Machine) */ - config.DataTimeOut = SDMMC_DATATIMEOUT; - config.DataLength = BLOCKSIZE * NumberOfBlocks; - config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; - config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; - config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; - config.DPSM = SDMMC_DPSM_ENABLE; - SDMMC_ConfigData(hsd->Instance, &config); + if(HAL_DMA_Start_IT(hsd->hdmatx, (uint32_t)pData, (uint32_t)&hsd->Instance->FIFO, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4U) != HAL_OK) + { + __HAL_SD_DISABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR)); + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= HAL_SD_ERROR_DMA; + hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; + return HAL_ERROR; + } + else + { + /* Configure the SD DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = BLOCKSIZE * NumberOfBlocks; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_ENABLE; + (void)SDMMC_ConfigData(hsd->Instance, &config); - return HAL_OK; + return HAL_OK; + } } else { @@ -1324,26 +1418,28 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, * @brief Erases the specified memory area of the given SD card. * @note This API should be followed by a check on the card state through * HAL_SD_GetCardState(). - * @param hsd Pointer to SD handle - * @param BlockStartAdd Start Block address - * @param BlockEndAdd End Block address + * @param hsd: Pointer to SD handle + * @param BlockStartAdd: Start Block address + * @param BlockEndAdd: End Block address * @retval HAL status */ HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd) { - uint32_t errorstate = HAL_SD_ERROR_NONE; + uint32_t errorstate; + uint32_t start_add = BlockStartAdd; + uint32_t end_add = BlockEndAdd; if(hsd->State == HAL_SD_STATE_READY) { - hsd->ErrorCode = HAL_DMA_ERROR_NONE; + hsd->ErrorCode = HAL_SD_ERROR_NONE; - if(BlockEndAdd < BlockStartAdd) + if(end_add < start_add) { hsd->ErrorCode |= HAL_SD_ERROR_PARAM; return HAL_ERROR; } - if(BlockEndAdd > (hsd->SdCard.LogBlockNbr)) + if(end_add > (hsd->SdCard.LogBlockNbr)) { hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; return HAL_ERROR; @@ -1373,15 +1469,15 @@ HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, ui /* Get start and end block for high capacity cards */ if(hsd->SdCard.CardType != CARD_SDHC_SDXC) { - BlockStartAdd *= 512U; - BlockEndAdd *= 512U; + start_add *= 512U; + end_add *= 512U; } /* According to sd-card spec 1.0 ERASE_GROUP_START (CMD32) and erase_group_end(CMD33) */ if(hsd->SdCard.CardType != CARD_SECURED) { /* Send CMD32 SD_ERASE_GRP_START with argument as addr */ - errorstate = SDMMC_CmdSDEraseStartAdd(hsd->Instance, BlockStartAdd); + errorstate = SDMMC_CmdSDEraseStartAdd(hsd->Instance, start_add); if(errorstate != HAL_SD_ERROR_NONE) { /* Clear all the static flags */ @@ -1392,7 +1488,7 @@ HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, ui } /* Send CMD33 SD_ERASE_GRP_END with argument as addr */ - errorstate = SDMMC_CmdSDEraseEndAdd(hsd->Instance, BlockEndAdd); + errorstate = SDMMC_CmdSDEraseEndAdd(hsd->Instance, end_add); if(errorstate != HAL_SD_ERROR_NONE) { /* Clear all the static flags */ @@ -1426,74 +1522,84 @@ HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, ui /** * @brief This function handles SD card interrupt request. - * @param hsd Pointer to SD handle + * @param hsd: Pointer to SD handle * @retval None */ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) { - uint32_t errorstate = HAL_SD_ERROR_NONE; + uint32_t errorstate; + uint32_t context = hsd->Context; /* Check for SDMMC interrupt flags */ - if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_DATAEND) != RESET) + if((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF) != RESET) && ((context & SD_CONTEXT_IT) != 0U)) + { + SD_Read_IT(hsd); + } + + else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) != RESET) { __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DATAEND); - __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\ - SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR); + __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\ + SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR | SDMMC_IT_TXFIFOHE |\ + SDMMC_IT_RXFIFOHF); + + hsd->Instance->DCTRL &= ~(SDMMC_DCTRL_DTEN); - if((hsd->Context & SD_CONTEXT_IT) != RESET) + if((context & SD_CONTEXT_IT) != 0U) { - if(((hsd->Context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != RESET) || ((hsd->Context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != RESET)) + if(((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)) { errorstate = SDMMC_CmdStopTransfer(hsd->Instance); if(errorstate != HAL_SD_ERROR_NONE) { hsd->ErrorCode |= errorstate; -#if (USE_HAL_SD_REGISTER_CALLBACKS == 1) +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) hsd->ErrorCallback(hsd); #else HAL_SD_ErrorCallback(hsd); -#endif +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ } } /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); hsd->State = HAL_SD_STATE_READY; - if(((hsd->Context & SD_CONTEXT_READ_SINGLE_BLOCK) != RESET) || ((hsd->Context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != RESET)) + hsd->Context = SD_CONTEXT_NONE; + if(((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U)) { -#if (USE_HAL_SD_REGISTER_CALLBACKS == 1) +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) hsd->RxCpltCallback(hsd); #else HAL_SD_RxCpltCallback(hsd); -#endif +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ } else { -#if (USE_HAL_SD_REGISTER_CALLBACKS == 1) +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) hsd->TxCpltCallback(hsd); #else HAL_SD_TxCpltCallback(hsd); -#endif +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ } } - else if((hsd->Context & SD_CONTEXT_DMA) != RESET) + else if((context & SD_CONTEXT_DMA) != 0U) { - if((hsd->Context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != RESET) + if((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U) { errorstate = SDMMC_CmdStopTransfer(hsd->Instance); if(errorstate != HAL_SD_ERROR_NONE) { hsd->ErrorCode |= errorstate; -#if (USE_HAL_SD_REGISTER_CALLBACKS == 1) +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) hsd->ErrorCallback(hsd); #else HAL_SD_ErrorCallback(hsd); -#endif +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ } } - if(((hsd->Context & SD_CONTEXT_READ_SINGLE_BLOCK) == RESET) && ((hsd->Context & SD_CONTEXT_READ_MULTIPLE_BLOCK) == RESET)) + if(((context & SD_CONTEXT_READ_SINGLE_BLOCK) == 0U) && ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) == 0U)) { /* Disable the DMA transfer for transmit request by setting the DMAEN bit in the SD DCTRL register */ @@ -1501,60 +1607,68 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) hsd->State = HAL_SD_STATE_READY; -#if (USE_HAL_SD_REGISTER_CALLBACKS == 1) +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) hsd->TxCpltCallback(hsd); #else HAL_SD_TxCpltCallback(hsd); -#endif +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ } } + else + { + /* Nothing to do */ + } } - else if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_TXFIFOHE) != RESET) + else if((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE) != RESET) && ((context & SD_CONTEXT_IT) != 0U)) { - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_TXFIFOHE); - SD_Write_IT(hsd); } - else if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_RXFIFOHF) != RESET) - { - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_RXFIFOHF); - - SD_Read_IT(hsd); - } - - else if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_TXUNDERR) != RESET) + else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_RXOVERR | SDMMC_FLAG_TXUNDERR) != RESET) { /* Set Error code */ - if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_DCRCFAIL) != RESET) + if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL) != RESET) { hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL; } - if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_DTIMEOUT) != RESET) + if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT) != RESET) { hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT; } - if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_RXOVERR) != RESET) + if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR) != RESET) { hsd->ErrorCode |= HAL_SD_ERROR_RX_OVERRUN; } - if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_TXUNDERR) != RESET) + if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR) != RESET) { hsd->ErrorCode |= HAL_SD_ERROR_TX_UNDERRUN; } /* Clear All flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); /* Disable all interrupts */ __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\ SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR); - if((hsd->Context & SD_CONTEXT_DMA) != RESET) + hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance); + + if((context & SD_CONTEXT_IT) != 0U) { - /* Abort the SD DMA Streams */ - if(hsd->hdmatx != NULL) + /* Set the SD state to ready to be able to start again the process */ + hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + hsd->ErrorCallback(hsd); +#else + HAL_SD_ErrorCallback(hsd); +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ + } + else if((context & SD_CONTEXT_DMA) != 0U) + { + /* Abort the SD DMA channel */ + if(((context & SD_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)) { /* Set the DMA Tx abort callback */ hsd->hdmatx->XferAbortCallback = SD_DMATxAbort; @@ -1564,7 +1678,7 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) SD_DMATxAbort(hsd->hdmatx); } } - else if(hsd->hdmarx != NULL) + else if(((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U)) { /* Set the DMA Rx abort callback */ hsd->hdmarx->XferAbortCallback = SD_DMARxAbort; @@ -1578,29 +1692,28 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) { hsd->ErrorCode = HAL_SD_ERROR_NONE; hsd->State = HAL_SD_STATE_READY; -#if (USE_HAL_SD_REGISTER_CALLBACKS == 1) + hsd->Context = SD_CONTEXT_NONE; +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) hsd->AbortCpltCallback(hsd); #else HAL_SD_AbortCallback(hsd); -#endif +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ } } - else if((hsd->Context & SD_CONTEXT_IT) != RESET) + else { - /* Set the SD state to ready to be able to start again the process */ - hsd->State = HAL_SD_STATE_READY; -#if (USE_HAL_SD_REGISTER_CALLBACKS == 1) - hsd->ErrorCallback(hsd); -#else - HAL_SD_ErrorCallback(hsd); -#endif + /* Nothing to do */ } } + else + { + /* Nothing to do */ + } } /** * @brief return the SD state - * @param hsd Pointer to sd handle + * @param hsd: Pointer to sd handle * @retval HAL state */ HAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd) @@ -1610,7 +1723,7 @@ HAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd) /** * @brief Return the SD error code -* @param hsd Pointer to a SD_HandleTypeDef structure that contains +* @param hsd : Pointer to a SD_HandleTypeDef structure that contains * the configuration information. * @retval SD Error Code */ @@ -1621,10 +1734,10 @@ uint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd) /** * @brief Tx Transfer completed callbacks - * @param hsd Pointer to SD handle + * @param hsd: Pointer to SD handle * @retval None */ - __weak void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd) +__weak void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsd); @@ -1636,7 +1749,7 @@ uint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd) /** * @brief Rx Transfer completed callbacks - * @param hsd Pointer SD handle + * @param hsd: Pointer SD handle * @retval None */ __weak void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd) @@ -1651,7 +1764,7 @@ __weak void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd) /** * @brief SD error callbacks - * @param hsd Pointer SD handle + * @param hsd: Pointer SD handle * @retval None */ __weak void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd) @@ -1666,7 +1779,7 @@ __weak void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd) /** * @brief SD Abort callbacks - * @param hsd Pointer SD handle + * @param hsd: Pointer SD handle * @retval None */ __weak void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd) @@ -1675,16 +1788,16 @@ __weak void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd) UNUSED(hsd); /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SD_ErrorCallback can be implemented in the user file + the HAL_SD_AbortCallback can be implemented in the user file */ } -#if (USE_HAL_SD_REGISTER_CALLBACKS == 1) +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) /** * @brief Register a User SD Callback * To be used instead of the weak (surcharged) predefined callback * @param hsd : SD handle - * @param CallbackId : Id of the callback to be registered + * @param CallbackID : ID of the callback to be registered * This parameter can be one of the following values: * @arg @ref HAL_SD_TX_CPLT_CB_ID SD Tx Complete Callback ID * @arg @ref HAL_SD_RX_CPLT_CB_ID SD Rx Complete Callback ID @@ -1695,7 +1808,7 @@ __weak void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd) * @param pCallback : pointer to the Callback function * @retval status */ -HAL_StatusTypeDef HAL_SD_RegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackId, pSD_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_SD_RegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID, pSD_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -1711,7 +1824,7 @@ HAL_StatusTypeDef HAL_SD_RegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_Callback if(hsd->State == HAL_SD_STATE_READY) { - switch (CallbackId) + switch (CallbackID) { case HAL_SD_TX_CPLT_CB_ID : hsd->TxCpltCallback = pCallback; @@ -1741,7 +1854,7 @@ HAL_StatusTypeDef HAL_SD_RegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_Callback } else if (hsd->State == HAL_SD_STATE_RESET) { - switch (CallbackId) + switch (CallbackID) { case HAL_SD_MSP_INIT_CB_ID : hsd->MspInitCallback = pCallback; @@ -1774,7 +1887,7 @@ HAL_StatusTypeDef HAL_SD_RegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_Callback * @brief Unregister a User SD Callback * SD Callback is redirected to the weak (surcharged) predefined callback * @param hsd : SD handle - * @param CallbackId : Id of the callback to be unregistered + * @param CallbackID : ID of the callback to be unregistered * This parameter can be one of the following values: * @arg @ref HAL_SD_TX_CPLT_CB_ID SD Tx Complete Callback ID * @arg @ref HAL_SD_RX_CPLT_CB_ID SD Rx Complete Callback ID @@ -1784,7 +1897,7 @@ HAL_StatusTypeDef HAL_SD_RegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_Callback * @arg @ref HAL_SD_MSP_DEINIT_CB_ID SD MspDeInit Callback ID * @retval status */ -HAL_StatusTypeDef HAL_SD_UnRegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackId) +HAL_StatusTypeDef HAL_SD_UnRegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID) { HAL_StatusTypeDef status = HAL_OK; @@ -1793,7 +1906,7 @@ HAL_StatusTypeDef HAL_SD_UnRegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_Callba if(hsd->State == HAL_SD_STATE_READY) { - switch (CallbackId) + switch (CallbackID) { case HAL_SD_TX_CPLT_CB_ID : hsd->TxCpltCallback = HAL_SD_TxCpltCallback; @@ -1823,7 +1936,7 @@ HAL_StatusTypeDef HAL_SD_UnRegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_Callba } else if (hsd->State == HAL_SD_STATE_RESET) { - switch (CallbackId) + switch (CallbackID) { case HAL_SD_MSP_INIT_CB_ID : hsd->MspInitCallback = HAL_SD_MspInit; @@ -1851,7 +1964,7 @@ HAL_StatusTypeDef HAL_SD_UnRegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_Callba __HAL_UNLOCK(hsd); return status; } -#endif +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ /** * @} @@ -1875,80 +1988,32 @@ HAL_StatusTypeDef HAL_SD_UnRegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_Callba /** * @brief Returns information the information of the card which are stored on * the CID register. - * @param hsd Pointer to SD handle - * @param pCID Pointer to a HAL_SD_CardCIDTypeDef structure that + * @param hsd: Pointer to SD handle + * @param pCID: Pointer to a HAL_SD_CardCIDTypeDef structure that * contains all CID register parameters * @retval HAL status */ HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID) { - uint32_t tmp = 0; - - /* Byte 0 */ - tmp = (uint8_t)((hsd->CID[0] & 0xFF000000U) >> 24); - pCID->ManufacturerID = tmp; - - /* Byte 1 */ - tmp = (uint8_t)((hsd->CID[0] & 0x00FF0000) >> 16); - pCID->OEM_AppliID = tmp << 8; + pCID->ManufacturerID = (uint8_t)((hsd->CID[0] & 0xFF000000U) >> 24U); - /* Byte 2 */ - tmp = (uint8_t)((hsd->CID[0] & 0x000000FF00) >> 8); - pCID->OEM_AppliID |= tmp; + pCID->OEM_AppliID = (uint16_t)((hsd->CID[0] & 0x00FFFF00U) >> 8U); - /* Byte 3 */ - tmp = (uint8_t)(hsd->CID[0] & 0x000000FF); - pCID->ProdName1 = tmp << 24; + pCID->ProdName1 = (((hsd->CID[0] & 0x000000FFU) << 24U) | ((hsd->CID[1] & 0xFFFFFF00U) >> 8U)); - /* Byte 4 */ - tmp = (uint8_t)((hsd->CID[1] & 0xFF000000U) >> 24); - pCID->ProdName1 |= tmp << 16; + pCID->ProdName2 = (uint8_t)(hsd->CID[1] & 0x000000FFU); - /* Byte 5 */ - tmp = (uint8_t)((hsd->CID[1] & 0x00FF0000) >> 16); - pCID->ProdName1 |= tmp << 8; + pCID->ProdRev = (uint8_t)((hsd->CID[2] & 0xFF000000U) >> 24U); - /* Byte 6 */ - tmp = (uint8_t)((hsd->CID[1] & 0x0000FF00) >> 8); - pCID->ProdName1 |= tmp; + pCID->ProdSN = (((hsd->CID[2] & 0x00FFFFFFU) << 8U) | ((hsd->CID[3] & 0xFF000000U) >> 24U)); - /* Byte 7 */ - tmp = (uint8_t)(hsd->CID[1] & 0x000000FF); - pCID->ProdName2 = tmp; + pCID->Reserved1 = (uint8_t)((hsd->CID[3] & 0x00F00000U) >> 20U); - /* Byte 8 */ - tmp = (uint8_t)((hsd->CID[2] & 0xFF000000U) >> 24); - pCID->ProdRev = tmp; + pCID->ManufactDate = (uint16_t)((hsd->CID[3] & 0x000FFF00U) >> 8U); - /* Byte 9 */ - tmp = (uint8_t)((hsd->CID[2] & 0x00FF0000) >> 16); - pCID->ProdSN = tmp << 24; + pCID->CID_CRC = (uint8_t)((hsd->CID[3] & 0x000000FEU) >> 1U); - /* Byte 10 */ - tmp = (uint8_t)((hsd->CID[2] & 0x0000FF00) >> 8); - pCID->ProdSN |= tmp << 16; - - /* Byte 11 */ - tmp = (uint8_t)(hsd->CID[2] & 0x000000FF); - pCID->ProdSN |= tmp << 8; - - /* Byte 12 */ - tmp = (uint8_t)((hsd->CID[3] & 0xFF000000U) >> 24); - pCID->ProdSN |= tmp; - - /* Byte 13 */ - tmp = (uint8_t)((hsd->CID[3] & 0x00FF0000) >> 16); - pCID->Reserved1 |= (tmp & 0xF0) >> 4; - pCID->ManufactDate = (tmp & 0x0F) << 8; - - /* Byte 14 */ - tmp = (uint8_t)((hsd->CID[3] & 0x0000FF00) >> 8); - pCID->ManufactDate |= tmp; - - /* Byte 15 */ - tmp = (uint8_t)(hsd->CID[3] & 0x000000FF); - pCID->CID_CRC = (tmp & 0xFE) >> 1; - pCID->Reserved2 = 1; + pCID->Reserved2 = 1U; return HAL_OK; } @@ -1956,102 +2021,69 @@ HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef /** * @brief Returns information the information of the card which are stored on * the CSD register. - * @param hsd Pointer to SD handle - * @param pCSD Pointer to a HAL_SD_CardCSDTypeDef structure that + * @param hsd: Pointer to SD handle + * @param pCSD: Pointer to a HAL_SD_CardCSDTypeDef structure that * contains all CSD register parameters * @retval HAL status */ HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD) { - uint32_t tmp = 0; - - /* Byte 0 */ - tmp = (hsd->CSD[0] & 0xFF000000U) >> 24; - pCSD->CSDStruct = (uint8_t)((tmp & 0xC0) >> 6); - pCSD->SysSpecVersion = (uint8_t)((tmp & 0x3C) >> 2); - pCSD->Reserved1 = tmp & 0x03; - - /* Byte 1 */ - tmp = (hsd->CSD[0] & 0x00FF0000) >> 16; - pCSD->TAAC = (uint8_t)tmp; - - /* Byte 2 */ - tmp = (hsd->CSD[0] & 0x0000FF00) >> 8; - pCSD->NSAC = (uint8_t)tmp; - - /* Byte 3 */ - tmp = hsd->CSD[0] & 0x000000FF; - pCSD->MaxBusClkFrec = (uint8_t)tmp; - - /* Byte 4 */ - tmp = (hsd->CSD[1] & 0xFF000000U) >> 24; - pCSD->CardComdClasses = (uint16_t)(tmp << 4); - - /* Byte 5 */ - tmp = (hsd->CSD[1] & 0x00FF0000U) >> 16; - pCSD->CardComdClasses |= (uint16_t)((tmp & 0xF0) >> 4); - pCSD->RdBlockLen = (uint8_t)(tmp & 0x0F); - - /* Byte 6 */ - tmp = (hsd->CSD[1] & 0x0000FF00U) >> 8; - pCSD->PartBlockRead = (uint8_t)((tmp & 0x80) >> 7); - pCSD->WrBlockMisalign = (uint8_t)((tmp & 0x40) >> 6); - pCSD->RdBlockMisalign = (uint8_t)((tmp & 0x20) >> 5); - pCSD->DSRImpl = (uint8_t)((tmp & 0x10) >> 4); - pCSD->Reserved2 = 0; /*!< Reserved */ + pCSD->CSDStruct = (uint8_t)((hsd->CSD[0] & 0xC0000000U) >> 30U); - if(hsd->SdCard.CardType == CARD_SDSC) - { - pCSD->DeviceSize = (tmp & 0x03) << 10; + pCSD->SysSpecVersion = (uint8_t)((hsd->CSD[0] & 0x3C000000U) >> 26U); - /* Byte 7 */ - tmp = (uint8_t)(hsd->CSD[1] & 0x000000FFU); - pCSD->DeviceSize |= (tmp) << 2; + pCSD->Reserved1 = (uint8_t)((hsd->CSD[0] & 0x03000000U) >> 24U); - /* Byte 8 */ - tmp = (uint8_t)((hsd->CSD[2] & 0xFF000000U) >> 24); - pCSD->DeviceSize |= (tmp & 0xC0) >> 6; + pCSD->TAAC = (uint8_t)((hsd->CSD[0] & 0x00FF0000U) >> 16U); - pCSD->MaxRdCurrentVDDMin = (tmp & 0x38) >> 3; - pCSD->MaxRdCurrentVDDMax = (tmp & 0x07); + pCSD->NSAC = (uint8_t)((hsd->CSD[0] & 0x0000FF00U) >> 8U); - /* Byte 9 */ - tmp = (uint8_t)((hsd->CSD[2] & 0x00FF0000U) >> 16); - pCSD->MaxWrCurrentVDDMin = (tmp & 0xE0) >> 5; - pCSD->MaxWrCurrentVDDMax = (tmp & 0x1C) >> 2; - pCSD->DeviceSizeMul = (tmp & 0x03) << 1; - /* Byte 10 */ - tmp = (uint8_t)((hsd->CSD[2] & 0x0000FF00U) >> 8); - pCSD->DeviceSizeMul |= (tmp & 0x80) >> 7; + pCSD->MaxBusClkFrec = (uint8_t)(hsd->CSD[0] & 0x000000FFU); - hsd->SdCard.BlockNbr = (pCSD->DeviceSize + 1) ; - hsd->SdCard.BlockNbr *= (1 << (pCSD->DeviceSizeMul + 2)); - hsd->SdCard.BlockSize = 1 << (pCSD->RdBlockLen); + pCSD->CardComdClasses = (uint16_t)((hsd->CSD[1] & 0xFFF00000U) >> 20U); - hsd->SdCard.LogBlockNbr = (hsd->SdCard.BlockNbr) * ((hsd->SdCard.BlockSize) / 512); - hsd->SdCard.LogBlockSize = 512; - } - else if(hsd->SdCard.CardType == CARD_SDHC_SDXC) + pCSD->RdBlockLen = (uint8_t)((hsd->CSD[1] & 0x000F0000U) >> 16U); + + pCSD->PartBlockRead = (uint8_t)((hsd->CSD[1] & 0x00008000U) >> 15U); + + pCSD->WrBlockMisalign = (uint8_t)((hsd->CSD[1] & 0x00004000U) >> 14U); + + pCSD->RdBlockMisalign = (uint8_t)((hsd->CSD[1] & 0x00002000U) >> 13U); + + pCSD->DSRImpl = (uint8_t)((hsd->CSD[1] & 0x00001000U) >> 12U); + + pCSD->Reserved2 = 0U; /*!< Reserved */ + + if(hsd->SdCard.CardType == CARD_SDSC) { - /* Byte 7 */ - tmp = (uint8_t)(hsd->CSD[1] & 0x000000FFU); - pCSD->DeviceSize = (tmp & 0x3F) << 16; + pCSD->DeviceSize = (((hsd->CSD[1] & 0x000003FFU) << 2U) | ((hsd->CSD[2] & 0xC0000000U) >> 30U)); + + pCSD->MaxRdCurrentVDDMin = (uint8_t)((hsd->CSD[2] & 0x38000000U) >> 27U); - /* Byte 8 */ - tmp = (uint8_t)((hsd->CSD[2] & 0xFF000000U) >> 24); + pCSD->MaxRdCurrentVDDMax = (uint8_t)((hsd->CSD[2] & 0x07000000U) >> 24U); - pCSD->DeviceSize |= (tmp << 8); + pCSD->MaxWrCurrentVDDMin = (uint8_t)((hsd->CSD[2] & 0x00E00000U) >> 21U); - /* Byte 9 */ - tmp = (uint8_t)((hsd->CSD[2] & 0x00FF0000U) >> 16); + pCSD->MaxWrCurrentVDDMax = (uint8_t)((hsd->CSD[2] & 0x001C0000U) >> 18U); - pCSD->DeviceSize |= (tmp); + pCSD->DeviceSizeMul = (uint8_t)((hsd->CSD[2] & 0x00038000U) >> 15U); - /* Byte 10 */ - tmp = (uint8_t)((hsd->CSD[2] & 0x0000FF00U) >> 8); + hsd->SdCard.BlockNbr = (pCSD->DeviceSize + 1U) ; + hsd->SdCard.BlockNbr *= (1UL << ((pCSD->DeviceSizeMul & 0x07U) + 2U)); + hsd->SdCard.BlockSize = (1UL << (pCSD->RdBlockLen & 0x0FU)); - hsd->SdCard.LogBlockNbr = hsd->SdCard.BlockNbr = (((uint64_t)pCSD->DeviceSize + 1) * 1024); - hsd->SdCard.LogBlockSize = hsd->SdCard.BlockSize = 512; + hsd->SdCard.LogBlockNbr = (hsd->SdCard.BlockNbr) * ((hsd->SdCard.BlockSize) / 512U); + hsd->SdCard.LogBlockSize = 512U; + } + else if(hsd->SdCard.CardType == CARD_SDHC_SDXC) + { + /* Byte 7 */ + pCSD->DeviceSize = (((hsd->CSD[1] & 0x0000003FU) << 16U) | ((hsd->CSD[2] & 0xFFFF0000U) >> 16U)); + + hsd->SdCard.BlockNbr = ((pCSD->DeviceSize + 1U) * 1024U); + hsd->SdCard.LogBlockNbr = hsd->SdCard.BlockNbr; + hsd->SdCard.BlockSize = 512U; + hsd->SdCard.LogBlockSize = hsd->SdCard.BlockSize; } else { @@ -2062,40 +2094,40 @@ HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef return HAL_ERROR; } - pCSD->EraseGrSize = (tmp & 0x40) >> 6; - pCSD->EraseGrMul = (tmp & 0x3F) << 1; - - /* Byte 11 */ - tmp = (uint8_t)(hsd->CSD[2] & 0x000000FF); - pCSD->EraseGrMul |= (tmp & 0x80) >> 7; - pCSD->WrProtectGrSize = (tmp & 0x7F); - - /* Byte 12 */ - tmp = (uint8_t)((hsd->CSD[3] & 0xFF000000U) >> 24); - pCSD->WrProtectGrEnable = (tmp & 0x80) >> 7; - pCSD->ManDeflECC = (tmp & 0x60) >> 5; - pCSD->WrSpeedFact = (tmp & 0x1C) >> 2; - pCSD->MaxWrBlockLen = (tmp & 0x03) << 2; - - /* Byte 13 */ - tmp = (uint8_t)((hsd->CSD[3] & 0x00FF0000) >> 16); - pCSD->MaxWrBlockLen |= (tmp & 0xC0) >> 6; - pCSD->WriteBlockPaPartial = (tmp & 0x20) >> 5; - pCSD->Reserved3 = 0; - pCSD->ContentProtectAppli = (tmp & 0x01); - - /* Byte 14 */ - tmp = (uint8_t)((hsd->CSD[3] & 0x0000FF00) >> 8); - pCSD->FileFormatGrouop = (tmp & 0x80) >> 7; - pCSD->CopyFlag = (tmp & 0x40) >> 6; - pCSD->PermWrProtect = (tmp & 0x20) >> 5; - pCSD->TempWrProtect = (tmp & 0x10) >> 4; - pCSD->FileFormat = (tmp & 0x0C) >> 2; - pCSD->ECC = (tmp & 0x03); - - /* Byte 15 */ - tmp = (uint8_t)(hsd->CSD[3] & 0x000000FF); - pCSD->CSD_CRC = (tmp & 0xFE) >> 1; + pCSD->EraseGrSize = (uint8_t)((hsd->CSD[2] & 0x00004000U) >> 14U); + + pCSD->EraseGrMul = (uint8_t)((hsd->CSD[2] & 0x00003F80U) >> 7U); + + pCSD->WrProtectGrSize = (uint8_t)(hsd->CSD[2] & 0x0000007FU); + + pCSD->WrProtectGrEnable = (uint8_t)((hsd->CSD[3] & 0x80000000U) >> 31U); + + pCSD->ManDeflECC = (uint8_t)((hsd->CSD[3] & 0x60000000U) >> 29U); + + pCSD->WrSpeedFact = (uint8_t)((hsd->CSD[3] & 0x1C000000U) >> 26U); + + pCSD->MaxWrBlockLen= (uint8_t)((hsd->CSD[3] & 0x03C00000U) >> 22U); + + pCSD->WriteBlockPaPartial = (uint8_t)((hsd->CSD[3] & 0x00200000U) >> 21U); + + pCSD->Reserved3 = 0; + + pCSD->ContentProtectAppli = (uint8_t)((hsd->CSD[3] & 0x00010000U) >> 16U); + + pCSD->FileFormatGroup = (uint8_t)((hsd->CSD[3] & 0x00008000U) >> 15U); + + pCSD->CopyFlag = (uint8_t)((hsd->CSD[3] & 0x00004000U) >> 14U); + + pCSD->PermWrProtect = (uint8_t)((hsd->CSD[3] & 0x00002000U) >> 13U); + + pCSD->TempWrProtect = (uint8_t)((hsd->CSD[3] & 0x00001000U) >> 12U); + + pCSD->FileFormat = (uint8_t)((hsd->CSD[3] & 0x00000C00U) >> 10U); + + pCSD->ECC= (uint8_t)((hsd->CSD[3] & 0x00000300U) >> 8U); + + pCSD->CSD_CRC = (uint8_t)((hsd->CSD[3] & 0x000000FEU) >> 1U); + pCSD->Reserved4 = 1; return HAL_OK; @@ -2103,19 +2135,18 @@ HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef /** * @brief Gets the SD status info. - * @param hsd Pointer to SD handle - * @param pStatus Pointer to the HAL_SD_CardStatusTypeDef structure that + * @param hsd: Pointer to SD handle + * @param pStatus: Pointer to the HAL_SD_CardStatusTypeDef structure that * will contain the SD card status information * @retval HAL status */ HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus) { - uint32_t tmp = 0; uint32_t sd_status[16]; - uint32_t errorstate = HAL_SD_ERROR_NONE; + uint32_t errorstate; errorstate = SD_SendSDStatus(hsd, sd_status); - if(errorstate != HAL_OK) + if(errorstate != HAL_SD_ERROR_NONE) { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); @@ -2125,65 +2156,26 @@ HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusT } else { - /* Byte 0 */ - tmp = (sd_status[0] & 0xC0) >> 6; - pStatus->DataBusWidth = (uint8_t)tmp; - - /* Byte 0 */ - tmp = (sd_status[0] & 0x20) >> 5; - pStatus->SecuredMode = (uint8_t)tmp; - - /* Byte 2 */ - tmp = (sd_status[0] & 0x00FF0000U) >> 16; - pStatus->CardType = (uint16_t)(tmp << 8); + pStatus->DataBusWidth = (uint8_t)((sd_status[0] & 0xC0U) >> 6U); - /* Byte 3 */ - tmp = (sd_status[0] & 0xFF000000U) >> 24; - pStatus->CardType |= (uint16_t)tmp; + pStatus->SecuredMode = (uint8_t)((sd_status[0] & 0x20U) >> 5U); - /* Byte 4 */ - tmp = (sd_status[1] & 0xFF); - pStatus->ProtectedAreaSize = (uint32_t)(tmp << 24); + pStatus->CardType = (uint16_t)(((sd_status[0] & 0x00FF0000U) >> 8U) | ((sd_status[0] & 0xFF000000U) >> 24U)); - /* Byte 5 */ - tmp = (sd_status[1] & 0xFF00) >> 8; - pStatus->ProtectedAreaSize |= (uint32_t)(tmp << 16); - - /* Byte 6 */ - tmp = (sd_status[1] & 0xFF0000) >> 16; - pStatus->ProtectedAreaSize |= (uint32_t)(tmp << 8); - - /* Byte 7 */ - tmp = (sd_status[1] & 0xFF000000U) >> 24; - pStatus->ProtectedAreaSize |= (uint32_t)tmp; + pStatus->ProtectedAreaSize = (((sd_status[1] & 0xFFU) << 24U) | ((sd_status[1] & 0xFF00U) << 8U) | + ((sd_status[1] & 0xFF0000U) >> 8U) | ((sd_status[1] & 0xFF000000U) >> 24U)); - /* Byte 8 */ - tmp = (sd_status[2] & 0xFF); - pStatus->SpeedClass = (uint8_t)tmp; + pStatus->SpeedClass = (uint8_t)(sd_status[2] & 0xFFU); - /* Byte 9 */ - tmp = (sd_status[2] & 0xFF00) >> 8; - pStatus->PerformanceMove = (uint8_t)tmp; + pStatus->PerformanceMove = (uint8_t)((sd_status[2] & 0xFF00U) >> 8U); - /* Byte 10 */ - tmp = (sd_status[2] & 0xF00000) >> 20; - pStatus->AllocationUnitSize = (uint8_t)tmp; + pStatus->AllocationUnitSize = (uint8_t)((sd_status[2] & 0xF00000U) >> 20U); - /* Byte 11 */ - tmp = (sd_status[2] & 0xFF000000U) >> 24; - pStatus->EraseSize = (uint16_t)(tmp << 8); + pStatus->EraseSize = (uint16_t)(((sd_status[2] & 0xFF000000U) >> 16U) | (sd_status[3] & 0xFFU)); - /* Byte 12 */ - tmp = (sd_status[3] & 0xFF); - pStatus->EraseSize |= (uint16_t)tmp; + pStatus->EraseTimeout = (uint8_t)((sd_status[3] & 0xFC00U) >> 10U); - /* Byte 13 */ - tmp = (sd_status[3] & 0xFC00) >> 10; - pStatus->EraseTimeout = (uint8_t)tmp; - - /* Byte 13 */ - tmp = (sd_status[3] & 0x0300) >> 8; - pStatus->EraseOffset = (uint8_t)tmp; + pStatus->EraseOffset = (uint8_t)((sd_status[3] & 0x0300U) >> 8U); } return HAL_OK; @@ -2191,8 +2183,8 @@ HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusT /** * @brief Gets the SD card info. - * @param hsd Pointer to SD handle - * @param pCardInfo Pointer to the HAL_SD_CardInfoTypeDef structure that + * @param hsd: Pointer to SD handle + * @param pCardInfo: Pointer to the HAL_SD_CardInfoTypeDef structure that * will contain the SD card status information * @retval HAL status */ @@ -2213,8 +2205,8 @@ HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeD /** * @brief Enables wide bus operation for the requested card if supported by * card. - * @param hsd Pointer to SD handle - * @param WideMode Specifies the SD card wide bus mode + * @param hsd: Pointer to SD handle + * @param WideMode: Specifies the SD card wide bus mode * This parameter can be one of the following values: * @arg SDMMC_BUS_WIDE_8B: 8-bit data transfer * @arg SDMMC_BUS_WIDE_4B: 4-bit data transfer @@ -2224,12 +2216,12 @@ HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeD HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t WideMode) { SDMMC_InitTypeDef Init; - uint32_t errorstate = HAL_SD_ERROR_NONE; + uint32_t errorstate; /* Check the parameters */ assert_param(IS_SDMMC_BUS_WIDE(WideMode)); - /* Chnage Satte */ + /* Change State */ hsd->State = HAL_SD_STATE_BUSY; if(hsd->SdCard.CardType != CARD_SECURED) @@ -2278,7 +2270,7 @@ HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t Init.BusWide = WideMode; Init.HardwareFlowControl = hsd->Init.HardwareFlowControl; Init.ClockDiv = hsd->Init.ClockDiv; - SDMMC_Init(hsd->Instance, Init); + (void)SDMMC_Init(hsd->Instance, Init); } /* Change State */ @@ -2287,64 +2279,80 @@ HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t return HAL_OK; } - /** * @brief Gets the current sd card data state. - * @param hsd pointer to SD handle + * @param hsd: pointer to SD handle * @retval Card state */ HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd) { - HAL_SD_CardStateTypeDef cardstate = HAL_SD_CARD_TRANSFER; - uint32_t errorstate = HAL_SD_ERROR_NONE; + uint32_t cardstate; + uint32_t errorstate; uint32_t resp1 = 0; errorstate = SD_SendStatus(hsd, &resp1); - if(errorstate != HAL_OK) + if(errorstate != HAL_SD_ERROR_NONE) { hsd->ErrorCode |= errorstate; } - cardstate = (HAL_SD_CardStateTypeDef)((resp1 >> 9) & 0x0F); + cardstate = ((resp1 >> 9U) & 0x0FU); - return cardstate; + return (HAL_SD_CardStateTypeDef)cardstate; } /** * @brief Abort the current transfer and disable the SD. - * @param hsd pointer to a SD_HandleTypeDef structure that contains + * @param hsd: pointer to a SD_HandleTypeDef structure that contains * the configuration information for SD module. * @retval HAL status */ HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd) { HAL_SD_CardStateTypeDef CardState; + uint32_t context = hsd->Context; /* DIsable All interrupts */ __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\ SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR); /* Clear All flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); - if((hsd->hdmatx != NULL) || (hsd->hdmarx != NULL)) + CLEAR_BIT(hsd->Instance->DCTRL, SDMMC_DCTRL_DTEN); + + if ((context & SD_CONTEXT_DMA) != 0U) { /* Disable the SD DMA request */ hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDMMC_DCTRL_DMAEN); - /* Abort the SD DMA Tx Stream */ - if(hsd->hdmatx != NULL) + /* Abort the SD DMA Tx channel */ + if (((context & SD_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)) { - HAL_DMA_Abort(hsd->hdmatx); + if(HAL_DMA_Abort(hsd->hdmatx) != HAL_OK) + { + hsd->ErrorCode |= HAL_SD_ERROR_DMA; + } } - /* Abort the SD DMA Rx Stream */ - if(hsd->hdmarx != NULL) + /* Abort the SD DMA Rx channel */ + else if (((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U)) { - HAL_DMA_Abort(hsd->hdmarx); + if(HAL_DMA_Abort(hsd->hdmarx) != HAL_OK) + { + hsd->ErrorCode |= HAL_SD_ERROR_DMA; + } + } + else + { + /* Nothing to do */ } } hsd->State = HAL_SD_STATE_READY; + + /* Initialize the SD operation */ + hsd->Context = SD_CONTEXT_NONE; + CardState = HAL_SD_GetCardState(hsd); if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) { @@ -2359,51 +2367,58 @@ HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd) /** * @brief Abort the current transfer and disable the SD (IT mode). - * @param hsd pointer to a SD_HandleTypeDef structure that contains + * @param hsd: pointer to a SD_HandleTypeDef structure that contains * the configuration information for SD module. * @retval HAL status */ HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd) { HAL_SD_CardStateTypeDef CardState; + uint32_t context = hsd->Context; - /* DIsable All interrupts */ + /* Disable All interrupts */ __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\ SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR); - /* Clear All flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + CLEAR_BIT(hsd->Instance->DCTRL, SDMMC_DCTRL_DTEN); - if((hsd->hdmatx != NULL) || (hsd->hdmarx != NULL)) + if ((context & SD_CONTEXT_DMA) != 0U) { /* Disable the SD DMA request */ hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDMMC_DCTRL_DMAEN); - /* Abort the SD DMA Tx Stream */ - if(hsd->hdmatx != NULL) + /* Abort the SD DMA Tx channel */ + if (((context & SD_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)) { - hsd->hdmatx->XferAbortCallback = SD_DMATxAbort; + hsd->hdmatx->XferAbortCallback = SD_DMATxAbort; if(HAL_DMA_Abort_IT(hsd->hdmatx) != HAL_OK) { hsd->hdmatx = NULL; } } - /* Abort the SD DMA Rx Stream */ - if(hsd->hdmarx != NULL) + /* Abort the SD DMA Rx channel */ + else if (((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U)) { - hsd->hdmarx->XferAbortCallback = SD_DMARxAbort; + hsd->hdmarx->XferAbortCallback = SD_DMARxAbort; if(HAL_DMA_Abort_IT(hsd->hdmarx) != HAL_OK) { hsd->hdmarx = NULL; } } + else + { + /* Nothing to do */ + } } - /* No transfer ongoing on both DMA channels*/ - if((hsd->hdmatx == NULL) && (hsd->hdmarx == NULL)) + else { + /* Clear All flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); + CardState = HAL_SD_GetCardState(hsd); hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) { hsd->ErrorCode = SDMMC_CmdStopTransfer(hsd->Instance); @@ -2414,11 +2429,11 @@ HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd) } else { -#if (USE_HAL_SD_REGISTER_CALLBACKS == 1) +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) hsd->AbortCpltCallback(hsd); #else HAL_SD_AbortCallback(hsd); -#endif +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ } } @@ -2440,7 +2455,7 @@ HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd) /** * @brief DMA SD transmit process complete callback - * @param hdma DMA handle + * @param hdma: DMA handle * @retval None */ static void SD_DMATransmitCplt(DMA_HandleTypeDef *hdma) @@ -2453,13 +2468,13 @@ static void SD_DMATransmitCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SD receive process complete callback - * @param hdma DMA handle + * @param hdma: DMA handle * @retval None */ static void SD_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent); - uint32_t errorstate = HAL_SD_ERROR_NONE; + uint32_t errorstate; /* Send stop command in multiblock write */ if(hsd->Context == (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA)) @@ -2481,9 +2496,10 @@ static void SD_DMAReceiveCplt(DMA_HandleTypeDef *hdma) hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDMMC_DCTRL_DMAEN); /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; #if (USE_HAL_SD_REGISTER_CALLBACKS == 1) hsd->RxCpltCallback(hsd); @@ -2493,19 +2509,22 @@ static void SD_DMAReceiveCplt(DMA_HandleTypeDef *hdma) } /** -* @brief DMA SD communication error callback -* @param hdma DMA handle -* @retval None -*/ + * @brief DMA SD communication error callback + * @param hdma: DMA handle + * @retval None + */ static void SD_DMAError(DMA_HandleTypeDef *hdma) { SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent); HAL_SD_CardStateTypeDef CardState; + uint32_t RxErrorCode, TxErrorCode; /* if DMA error is FIFO error ignore it */ if(HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE) { - if((hsd->hdmarx->ErrorCode == HAL_DMA_ERROR_TE) || (hsd->hdmatx->ErrorCode == HAL_DMA_ERROR_TE)) + RxErrorCode = hsd->hdmarx->ErrorCode; + TxErrorCode = hsd->hdmatx->ErrorCode; + if((RxErrorCode == HAL_DMA_ERROR_TE) || (TxErrorCode == HAL_DMA_ERROR_TE)) { /* Clear All flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); @@ -2522,6 +2541,7 @@ static void SD_DMAError(DMA_HandleTypeDef *hdma) } hsd->State= HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; } #if (USE_HAL_SD_REGISTER_CALLBACKS == 1) @@ -2534,7 +2554,7 @@ static void SD_DMAError(DMA_HandleTypeDef *hdma) /** * @brief DMA SD Tx Abort callback - * @param hdma DMA handle + * @param hdma: DMA handle * @retval None */ static void SD_DMATxAbort(DMA_HandleTypeDef *hdma) @@ -2542,44 +2562,38 @@ static void SD_DMATxAbort(DMA_HandleTypeDef *hdma) SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent); HAL_SD_CardStateTypeDef CardState; - if(hsd->hdmatx != NULL) + /* Clear All flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); + + CardState = HAL_SD_GetCardState(hsd); + hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; + if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) { - hsd->hdmatx = NULL; + hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance); } - /* All DMA channels are aborted */ - if(hsd->hdmarx == NULL) + if(hsd->ErrorCode == HAL_SD_ERROR_NONE) { - CardState = HAL_SD_GetCardState(hsd); - hsd->ErrorCode = HAL_SD_ERROR_NONE; - hsd->State = HAL_SD_STATE_READY; - if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) - { - hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance); - - if(hsd->ErrorCode != HAL_SD_ERROR_NONE) - { #if (USE_HAL_SD_REGISTER_CALLBACKS == 1) - hsd->AbortCpltCallback(hsd); + hsd->AbortCpltCallback(hsd); #else - HAL_SD_AbortCallback(hsd); + HAL_SD_AbortCallback(hsd); #endif - } - else - { + } + else + { #if (USE_HAL_SD_REGISTER_CALLBACKS == 1) - hsd->ErrorCallback(hsd); + hsd->ErrorCallback(hsd); #else - HAL_SD_ErrorCallback(hsd); + HAL_SD_ErrorCallback(hsd); #endif - } - } } } /** * @brief DMA SD Rx Abort callback - * @param hdma DMA handle + * @param hdma: DMA handle * @retval None */ static void SD_DMARxAbort(DMA_HandleTypeDef *hdma) @@ -2587,55 +2601,48 @@ static void SD_DMARxAbort(DMA_HandleTypeDef *hdma) SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent); HAL_SD_CardStateTypeDef CardState; - if(hsd->hdmarx != NULL) + /* Clear All flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); + + CardState = HAL_SD_GetCardState(hsd); + hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; + if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) { - hsd->hdmarx = NULL; + hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance); } - /* All DMA channels are aborted */ - if(hsd->hdmatx == NULL) + if(hsd->ErrorCode == HAL_SD_ERROR_NONE) { - CardState = HAL_SD_GetCardState(hsd); - hsd->ErrorCode = HAL_SD_ERROR_NONE; - hsd->State = HAL_SD_STATE_READY; - if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) - { - hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance); - - if(hsd->ErrorCode != HAL_SD_ERROR_NONE) - { #if (USE_HAL_SD_REGISTER_CALLBACKS == 1) - hsd->AbortCpltCallback(hsd); + hsd->AbortCpltCallback(hsd); #else - HAL_SD_AbortCallback(hsd); + HAL_SD_AbortCallback(hsd); #endif - } - else - { + } + else + { #if (USE_HAL_SD_REGISTER_CALLBACKS == 1) - hsd->ErrorCallback(hsd); + hsd->ErrorCallback(hsd); #else - HAL_SD_ErrorCallback(hsd); + HAL_SD_ErrorCallback(hsd); #endif - } - } } } - /** * @brief Initializes the sd card. - * @param hsd Pointer to SD handle + * @param hsd: Pointer to SD handle * @retval SD Card error state */ static uint32_t SD_InitCard(SD_HandleTypeDef *hsd) { HAL_SD_CardCSDTypeDef CSD; - uint32_t errorstate = HAL_SD_ERROR_NONE; - uint16_t sd_rca = 1; + uint32_t errorstate; + uint16_t sd_rca = 1U; /* Check the power State */ - if(SDMMC_GetPowerState(hsd->Instance) == 0) + if(SDMMC_GetPowerState(hsd->Instance) == 0U) { /* Power off */ return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE; @@ -2652,10 +2659,10 @@ static uint32_t SD_InitCard(SD_HandleTypeDef *hsd) else { /* Get Card identification number data */ - hsd->CID[0] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1); - hsd->CID[1] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2); - hsd->CID[2] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3); - hsd->CID[3] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4); + hsd->CID[0U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1); + hsd->CID[1U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2); + hsd->CID[2U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3); + hsd->CID[3U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4); } } @@ -2691,20 +2698,23 @@ static uint32_t SD_InitCard(SD_HandleTypeDef *hsd) } /* Get the Card Class */ - hsd->SdCard.Class = (SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2) >> 20); + hsd->SdCard.Class = (SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2) >> 20U); /* Get CSD parameters */ - HAL_SD_GetCardCSD(hsd, &CSD); + if (HAL_SD_GetCardCSD(hsd, &CSD) != HAL_OK) + { + return HAL_SD_ERROR_UNSUPPORTED_FEATURE; + } /* Select the Card */ - errorstate = SDMMC_CmdSelDesel(hsd->Instance, (uint32_t)(((uint32_t)hsd->SdCard.RelCardAdd) << 16)); + errorstate = SDMMC_CmdSelDesel(hsd->Instance, (uint32_t)(((uint32_t)hsd->SdCard.RelCardAdd) << 16U)); if(errorstate != HAL_SD_ERROR_NONE) { return errorstate; } /* Configure SDMMC peripheral interface */ - SDMMC_Init(hsd->Instance, hsd->Init); + (void)SDMMC_Init(hsd->Instance, hsd->Init); /* All cards are initialized */ return HAL_SD_ERROR_NONE; @@ -2714,14 +2724,14 @@ static uint32_t SD_InitCard(SD_HandleTypeDef *hsd) * @brief Enquires cards about their operating voltage and configures clock * controls and stores SD information that will be needed in future * in the SD handle. - * @param hsd Pointer to SD handle + * @param hsd: Pointer to SD handle * @retval error state */ static uint32_t SD_PowerON(SD_HandleTypeDef *hsd) { - __IO uint32_t count = 0; - uint32_t response = 0, validvoltage = 0; - uint32_t errorstate = HAL_SD_ERROR_NONE; + __IO uint32_t count = 0U; + uint32_t response = 0U, validvoltage = 0U; + uint32_t errorstate; /* CMD0: GO_IDLE_STATE */ errorstate = SDMMC_CmdGoIdleState(hsd->Instance); @@ -2735,110 +2745,98 @@ static uint32_t SD_PowerON(SD_HandleTypeDef *hsd) if(errorstate != HAL_SD_ERROR_NONE) { hsd->SdCard.CardVersion = CARD_V1_X; - - /* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */ - while(validvoltage == 0) + /* CMD0: GO_IDLE_STATE */ + errorstate = SDMMC_CmdGoIdleState(hsd->Instance); + if(errorstate != HAL_SD_ERROR_NONE) { - if(count++ == SDMMC_MAX_VOLT_TRIAL) - { - return HAL_SD_ERROR_INVALID_VOLTRANGE; - } - - /* SEND CMD55 APP_CMD with RCA as 0 */ - errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0); - if(errorstate != HAL_SD_ERROR_NONE) - { - return HAL_SD_ERROR_UNSUPPORTED_FEATURE; - } - - /* Send CMD41 */ - errorstate = SDMMC_CmdAppOperCommand(hsd->Instance, SDMMC_STD_CAPACITY); - if(errorstate != HAL_SD_ERROR_NONE) - { - return HAL_SD_ERROR_UNSUPPORTED_FEATURE; - } - - /* Get command response */ - response = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1); - - /* Get operating voltage*/ - validvoltage = (((response >> 31) == 1) ? 1 : 0); + return errorstate; } - /* Card type is SDSC */ - hsd->SdCard.CardType = CARD_SDSC; + } else { hsd->SdCard.CardVersion = CARD_V2_X; + } - /* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */ - while(validvoltage == 0) + if( hsd->SdCard.CardVersion == CARD_V2_X) + { + /* SEND CMD55 APP_CMD with RCA as 0 */ + errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0); + if(errorstate != HAL_SD_ERROR_NONE) { - if(count++ == SDMMC_MAX_VOLT_TRIAL) - { - return HAL_SD_ERROR_INVALID_VOLTRANGE; - } - - /* SEND CMD55 APP_CMD with RCA as 0 */ - errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0); - if(errorstate != HAL_SD_ERROR_NONE) - { - return errorstate; - } - - /* Send CMD41 */ - errorstate = SDMMC_CmdAppOperCommand(hsd->Instance, SDMMC_HIGH_CAPACITY); - if(errorstate != HAL_SD_ERROR_NONE) - { - return errorstate; - } - - /* Get command response */ - response = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1); - - /* Get operating voltage*/ - validvoltage = (((response >> 31) == 1) ? 1 : 0); + return HAL_SD_ERROR_UNSUPPORTED_FEATURE; } - - if((response & SDMMC_HIGH_CAPACITY) == SDMMC_HIGH_CAPACITY) /* (response &= SD_HIGH_CAPACITY) */ + } + /* SD CARD */ + /* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */ + while((count < SDMMC_MAX_VOLT_TRIAL) && (validvoltage == 0U)) + { + /* SEND CMD55 APP_CMD with RCA as 0 */ + errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0); + if(errorstate != HAL_SD_ERROR_NONE) { - hsd->SdCard.CardType = CARD_SDHC_SDXC; + return errorstate; } - else + + /* Send CMD41 */ + errorstate = SDMMC_CmdAppOperCommand(hsd->Instance, SDMMC_VOLTAGE_WINDOW_SD | SDMMC_HIGH_CAPACITY | SD_SWITCH_1_8V_CAPACITY); + if(errorstate != HAL_SD_ERROR_NONE) { - hsd->SdCard.CardType = CARD_SDSC; + return HAL_SD_ERROR_UNSUPPORTED_FEATURE; } + + /* Get command response */ + response = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1); + + /* Get operating voltage*/ + validvoltage = (((response >> 31U) == 1U) ? 1U : 0U); + + count++; + } + + if(count >= SDMMC_MAX_VOLT_TRIAL) + { + return HAL_SD_ERROR_INVALID_VOLTRANGE; } + if((response & SDMMC_HIGH_CAPACITY) == SDMMC_HIGH_CAPACITY) /* (response &= SD_HIGH_CAPACITY) */ + { + hsd->SdCard.CardType = CARD_SDHC_SDXC; + } + else + { + hsd->SdCard.CardType = CARD_SDSC; + } + + return HAL_SD_ERROR_NONE; } /** * @brief Turns the SDMMC output signals off. - * @param hsd Pointer to SD handle - * @retval HAL status + * @param hsd: Pointer to SD handle + * @retval None */ -static HAL_StatusTypeDef SD_PowerOFF(SD_HandleTypeDef *hsd) +static void SD_PowerOFF(SD_HandleTypeDef *hsd) { /* Set Power State to OFF */ - SDMMC_PowerState_OFF(hsd->Instance); - - return HAL_OK; + (void)SDMMC_PowerState_OFF(hsd->Instance); } /** * @brief Send Status info command. - * @param hsd pointer to SD handle - * @param pSDstatus Pointer to the buffer that will contain the SD card status + * @param hsd: pointer to SD handle + * @param pSDstatus: Pointer to the buffer that will contain the SD card status * SD Status register) * @retval error state */ static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus) { SDMMC_DataInitTypeDef config; - uint32_t errorstate = HAL_SD_ERROR_NONE; + uint32_t errorstate; uint32_t tickstart = HAL_GetTick(); - uint32_t count = 0; + uint32_t count; + uint32_t *pData = pSDstatus; /* Check SD response */ if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) @@ -2847,7 +2845,7 @@ static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus) } /* Set block size for card if it is not equal to current block size for card */ - errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64); + errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64U); if(errorstate != HAL_SD_ERROR_NONE) { hsd->ErrorCode |= HAL_SD_ERROR_NONE; @@ -2855,7 +2853,7 @@ static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus) } /* Send CMD55 */ - errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16)); + errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U)); if(errorstate != HAL_SD_ERROR_NONE) { hsd->ErrorCode |= HAL_SD_ERROR_NONE; @@ -2864,12 +2862,12 @@ static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus) /* Configure the SD DPSM (Data Path State Machine) */ config.DataTimeOut = SDMMC_DATATIMEOUT; - config.DataLength = 64; + config.DataLength = 64U; config.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B; config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; config.DPSM = SDMMC_DPSM_ENABLE; - SDMMC_ConfigData(hsd->Instance, &config); + (void)SDMMC_ConfigData(hsd->Instance, &config); /* Send ACMD13 (SD_APP_STAUS) with argument as card's RCA */ errorstate = SDMMC_CmdStatusRegister(hsd->Instance); @@ -2884,12 +2882,11 @@ static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus) { if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF)) { - for(count = 0; count < 8; count++) + for(count = 0U; count < 8U; count++) { - *(pSDstatus + count) = SDMMC_ReadFIFO(hsd->Instance); + *pData = SDMMC_ReadFIFO(hsd->Instance); + pData++; } - - pSDstatus += 8; } if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) @@ -2910,11 +2907,15 @@ static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus) { return HAL_SD_ERROR_RX_OVERRUN; } + else + { + /* Nothing to do */ + } while ((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL))) { - *pSDstatus = SDMMC_ReadFIFO(hsd->Instance); - pSDstatus++; + *pData = SDMMC_ReadFIFO(hsd->Instance); + pData++; if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) { @@ -2923,21 +2924,21 @@ static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus) } /* Clear all the static status flags*/ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); return HAL_SD_ERROR_NONE; } /** * @brief Returns the current card's status. - * @param hsd Pointer to SD handle - * @param pCardStatus pointer to the buffer that will contain the SD card + * @param hsd: Pointer to SD handle + * @param pCardStatus: pointer to the buffer that will contain the SD card * status (Card Status register) * @retval error state */ static uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus) { - uint32_t errorstate = HAL_SD_ERROR_NONE; + uint32_t errorstate; if(pCardStatus == NULL) { @@ -2945,8 +2946,8 @@ static uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus) } /* Send Status command */ - errorstate = SDMMC_CmdSendStatus(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16)); - if(errorstate != HAL_OK) + errorstate = SDMMC_CmdSendStatus(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U)); + if(errorstate != HAL_SD_ERROR_NONE) { return errorstate; } @@ -2959,13 +2960,13 @@ static uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus) /** * @brief Enables the SDMMC wide bus mode. - * @param hsd pointer to SD handle + * @param hsd: pointer to SD handle * @retval error state */ static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd) { - uint32_t scr[2] = {0, 0}; - uint32_t errorstate = HAL_SD_ERROR_NONE; + uint32_t scr[2U] = {0U, 0U}; + uint32_t errorstate; if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) { @@ -2974,24 +2975,24 @@ static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd) /* Get SCR Register */ errorstate = SD_FindSCR(hsd, scr); - if(errorstate != HAL_OK) + if(errorstate != HAL_SD_ERROR_NONE) { return errorstate; } /* If requested card supports wide bus operation */ - if((scr[1] & SDMMC_WIDE_BUS_SUPPORT) != SDMMC_ALLZERO) + if((scr[1U] & SDMMC_WIDE_BUS_SUPPORT) != SDMMC_ALLZERO) { /* Send CMD55 APP_CMD with argument as card's RCA.*/ - errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16)); - if(errorstate != HAL_OK) + errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U)); + if(errorstate != HAL_SD_ERROR_NONE) { return errorstate; } /* Send ACMD6 APP_CMD with argument as 2 for wide bus mode */ - errorstate = SDMMC_CmdBusWidth(hsd->Instance, 2); - if(errorstate != HAL_OK) + errorstate = SDMMC_CmdBusWidth(hsd->Instance, 2U); + if(errorstate != HAL_SD_ERROR_NONE) { return errorstate; } @@ -3006,13 +3007,13 @@ static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd) /** * @brief Disables the SDMMC wide bus mode. - * @param hsd Pointer to SD handle + * @param hsd: Pointer to SD handle * @retval error state */ static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd) { - uint32_t scr[2] = {0, 0}; - uint32_t errorstate = HAL_SD_ERROR_NONE; + uint32_t scr[2U] = {0U, 0U}; + uint32_t errorstate; if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) { @@ -3021,24 +3022,24 @@ static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd) /* Get SCR Register */ errorstate = SD_FindSCR(hsd, scr); - if(errorstate != HAL_OK) + if(errorstate != HAL_SD_ERROR_NONE) { return errorstate; } /* If requested card supports 1 bit mode operation */ - if((scr[1] & SDMMC_SINGLE_BUS_SUPPORT) != SDMMC_ALLZERO) + if((scr[1U] & SDMMC_SINGLE_BUS_SUPPORT) != SDMMC_ALLZERO) { /* Send CMD55 APP_CMD with argument as card's RCA */ - errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16)); - if(errorstate != HAL_OK) + errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U)); + if(errorstate != HAL_SD_ERROR_NONE) { return errorstate; } /* Send ACMD6 APP_CMD with argument as 0 for single bus mode */ - errorstate = SDMMC_CmdBusWidth(hsd->Instance, 0); - if(errorstate != HAL_OK) + errorstate = SDMMC_CmdBusWidth(hsd->Instance, 0U); + if(errorstate != HAL_SD_ERROR_NONE) { return errorstate; } @@ -3054,43 +3055,44 @@ static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd) /** * @brief Finds the SD card SCR register value. - * @param hsd Pointer to SD handle - * @param pSCR pointer to the buffer that will contain the SCR value + * @param hsd: Pointer to SD handle + * @param pSCR: pointer to the buffer that will contain the SCR value * @retval error state */ static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR) { SDMMC_DataInitTypeDef config; - uint32_t errorstate = HAL_SD_ERROR_NONE; + uint32_t errorstate; uint32_t tickstart = HAL_GetTick(); - uint32_t index = 0; - uint32_t tempscr[2] = {0, 0}; + uint32_t index = 0U; + uint32_t tempscr[2U] = {0U, 0U}; + uint32_t *scr = pSCR; /* Set Block Size To 8 Bytes */ - errorstate = SDMMC_CmdBlockLength(hsd->Instance, 8); - if(errorstate != HAL_OK) + errorstate = SDMMC_CmdBlockLength(hsd->Instance, 8U); + if(errorstate != HAL_SD_ERROR_NONE) { return errorstate; } /* Send CMD55 APP_CMD with argument as card's RCA */ - errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)((hsd->SdCard.RelCardAdd) << 16)); - if(errorstate != HAL_OK) + errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)((hsd->SdCard.RelCardAdd) << 16U)); + if(errorstate != HAL_SD_ERROR_NONE) { return errorstate; } config.DataTimeOut = SDMMC_DATATIMEOUT; - config.DataLength = 8; + config.DataLength = 8U; config.DataBlockSize = SDMMC_DATABLOCK_SIZE_8B; config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; config.DPSM = SDMMC_DPSM_ENABLE; - SDMMC_ConfigData(hsd->Instance, &config); + (void)SDMMC_ConfigData(hsd->Instance, &config); /* Send ACMD51 SD_APP_SEND_SCR with argument as 0 */ errorstate = SDMMC_CmdSendSCR(hsd->Instance); - if(errorstate != HAL_OK) + if(errorstate != HAL_SD_ERROR_NONE) { return errorstate; } @@ -3131,13 +3133,14 @@ static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR) { /* No error flag set */ /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); - *(pSCR + 1) = ((tempscr[0] & SDMMC_0TO7BITS) << 24) | ((tempscr[0] & SDMMC_8TO15BITS) << 8) |\ - ((tempscr[0] & SDMMC_16TO23BITS) >> 8) | ((tempscr[0] & SDMMC_24TO31BITS) >> 24); + *scr = (((tempscr[1] & SDMMC_0TO7BITS) << 24) | ((tempscr[1] & SDMMC_8TO15BITS) << 8) |\ + ((tempscr[1] & SDMMC_16TO23BITS) >> 8) | ((tempscr[1] & SDMMC_24TO31BITS) >> 24)); + scr++; + *scr = (((tempscr[0] & SDMMC_0TO7BITS) << 24) | ((tempscr[0] & SDMMC_8TO15BITS) << 8) |\ + ((tempscr[0] & SDMMC_16TO23BITS) >> 8) | ((tempscr[0] & SDMMC_24TO31BITS) >> 24)); - *(pSCR) = ((tempscr[1] & SDMMC_0TO7BITS) << 24) | ((tempscr[1] & SDMMC_8TO15BITS) << 8) |\ - ((tempscr[1] & SDMMC_16TO23BITS) >> 8) | ((tempscr[1] & SDMMC_24TO31BITS) >> 24); } return HAL_SD_ERROR_NONE; @@ -3145,50 +3148,80 @@ static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR) /** * @brief Wrap up reading in non-blocking mode. - * @param hsd pointer to a SD_HandleTypeDef structure that contains + * @param hsd: pointer to a SD_HandleTypeDef structure that contains * the configuration information. - * @retval HAL status + * @retval None */ -static HAL_StatusTypeDef SD_Read_IT(SD_HandleTypeDef *hsd) +static void SD_Read_IT(SD_HandleTypeDef *hsd) { - uint32_t count = 0; - uint32_t* tmp; + uint32_t count, data, dataremaining; + uint8_t* tmp; - tmp = (uint32_t*)hsd->pRxBuffPtr; + tmp = hsd->pRxBuffPtr; + dataremaining = hsd->RxXferSize; - /* Read data from SDMMC Rx FIFO */ - for(count = 0; count < 8; count++) + if (dataremaining > 0U) { - *(tmp + count) = SDMMC_ReadFIFO(hsd->Instance); - } - - hsd->pRxBuffPtr += 8; + /* Read data from SDMMC Rx FIFO */ + for(count = 0U; count < 8U; count++) + { + data = SDMMC_ReadFIFO(hsd->Instance); + *tmp = (uint8_t)(data & 0xFFU); + tmp++; + dataremaining--; + *tmp = (uint8_t)((data >> 8U) & 0xFFU); + tmp++; + dataremaining--; + *tmp = (uint8_t)((data >> 16U) & 0xFFU); + tmp++; + dataremaining--; + *tmp = (uint8_t)((data >> 24U) & 0xFFU); + tmp++; + dataremaining--; + } - return HAL_OK; + hsd->pRxBuffPtr = tmp; + hsd->RxXferSize = dataremaining; + } } /** * @brief Wrap up writing in non-blocking mode. - * @param hsd pointer to a SD_HandleTypeDef structure that contains + * @param hsd: pointer to a SD_HandleTypeDef structure that contains * the configuration information. - * @retval HAL status + * @retval None */ -static HAL_StatusTypeDef SD_Write_IT(SD_HandleTypeDef *hsd) +static void SD_Write_IT(SD_HandleTypeDef *hsd) { - uint32_t count = 0; - uint32_t* tmp; + uint32_t count, data, dataremaining; + uint8_t* tmp; - tmp = (uint32_t*)hsd->pTxBuffPtr; + tmp = hsd->pTxBuffPtr; + dataremaining = hsd->TxXferSize; - /* Write data to SDMMC Tx FIFO */ - for(count = 0; count < 8; count++) + if (dataremaining > 0U) { - SDMMC_WriteFIFO(hsd->Instance, (tmp + count)); - } - - hsd->pTxBuffPtr += 8; + /* Write data to SDMMC Tx FIFO */ + for(count = 0U; count < 8U; count++) + { + data = (uint32_t)(*tmp); + tmp++; + dataremaining--; + data |= ((uint32_t)(*tmp) << 8U); + tmp++; + dataremaining--; + data |= ((uint32_t)(*tmp) << 16U); + tmp++; + dataremaining--; + data |= ((uint32_t)(*tmp) << 24U); + tmp++; + dataremaining--; + (void)SDMMC_WriteFIFO(hsd->Instance, &data); + } - return HAL_OK; + hsd->pTxBuffPtr = tmp; + hsd->TxXferSize = dataremaining; + } } /** @@ -3205,4 +3238,6 @@ static HAL_StatusTypeDef SD_Write_IT(SD_HandleTypeDef *hsd) * @} */ +#endif /* SDMMC1 */ + /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_smartcard.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_smartcard.c index e475985160..c964ad0ab4 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_smartcard.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_smartcard.c @@ -192,8 +192,8 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants - * @{ - */ + * @{ + */ #define SMARTCARD_TEACK_REACK_TIMEOUT 1000U /*!< SMARTCARD TX or RX enable acknowledge time-out value */ #define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \ @@ -225,7 +225,8 @@ void SMARTCARD_InitCallbacksToDefault(SMARTCARD_HandleTypeDef *hsmartcard); static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard); static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard); static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmartcard); -static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout); +static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, + FlagStatus Status, uint32_t Tickstart, uint32_t Timeout); static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsmartcard); static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsmartcard); static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma); @@ -471,7 +472,8 @@ __weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard) * @param pCallback pointer to the Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, + HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -584,7 +586,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmart * @arg @ref HAL_SMARTCARD_MSPDEINIT_CB_ID MspDeInit Callback ID * @retval HAL status */ -HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, HAL_SMARTCARD_CallbackIDTypeDef CallbackID) +HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, + HAL_SMARTCARD_CallbackIDTypeDef CallbackID) { HAL_StatusTypeDef status = HAL_OK; @@ -728,29 +731,30 @@ HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsma (++) HAL_SMARTCARD_RxCpltCallback() (++) HAL_SMARTCARD_ErrorCallback() + [..] (#) Non-Blocking mode transfers could be aborted using Abort API's : - (+) HAL_SMARTCARD_Abort() - (+) HAL_SMARTCARD_AbortTransmit() - (+) HAL_SMARTCARD_AbortReceive() - (+) HAL_SMARTCARD_Abort_IT() - (+) HAL_SMARTCARD_AbortTransmit_IT() - (+) HAL_SMARTCARD_AbortReceive_IT() + (++) HAL_SMARTCARD_Abort() + (++) HAL_SMARTCARD_AbortTransmit() + (++) HAL_SMARTCARD_AbortReceive() + (++) HAL_SMARTCARD_Abort_IT() + (++) HAL_SMARTCARD_AbortTransmit_IT() + (++) HAL_SMARTCARD_AbortReceive_IT() (#) For Abort services based on interrupts (HAL_SMARTCARD_Abortxxx_IT), a set of Abort Complete Callbacks are provided: - (+) HAL_SMARTCARD_AbortCpltCallback() - (+) HAL_SMARTCARD_AbortTransmitCpltCallback() - (+) HAL_SMARTCARD_AbortReceiveCpltCallback() + (++) HAL_SMARTCARD_AbortCpltCallback() + (++) HAL_SMARTCARD_AbortTransmitCpltCallback() + (++) HAL_SMARTCARD_AbortReceiveCpltCallback() (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. Errors are handled as follows : - (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is - to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception . - Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type, - and HAL_SMARTCARD_ErrorCallback() user callback is executed. Transfer is kept ongoing on SMARTCARD side. - If user wants to abort it, Abort services should be called by user. - (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted. - This concerns Frame Error in Interrupt mode tranmission, Overrun Error in Interrupt mode reception and all errors in DMA mode. - Error code is set to allow user to identify error type, and HAL_SMARTCARD_ErrorCallback() user callback is executed. + (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is + to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception . + Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type, + and HAL_SMARTCARD_ErrorCallback() user callback is executed. Transfer is kept ongoing on SMARTCARD side. + If user wants to abort it, Abort services should be called by user. + (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted. + This concerns Frame Error in Interrupt mode tranmission, Overrun Error in Interrupt mode reception and all errors in DMA mode. + Error code is set to allow user to identify error type, and HAL_SMARTCARD_ErrorCallback() user callback is executed. @endverbatim * @{ @@ -765,7 +769,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsma * @param Timeout Timeout duration. * @retval HAL status */ -HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, + uint32_t Timeout) { uint32_t tickstart; uint8_t *ptmpdata = pData; @@ -811,7 +816,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, ui hsmartcard->Instance->TDR = (uint8_t)(*ptmpdata & 0xFFU); ptmpdata++; } - if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_TRANSMISSION_COMPLETION_FLAG(hsmartcard), RESET, tickstart, Timeout) != HAL_OK) + if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_TRANSMISSION_COMPLETION_FLAG(hsmartcard), RESET, tickstart, + Timeout) != HAL_OK) { return HAL_TIMEOUT; } @@ -848,7 +854,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, ui * @param Timeout Timeout duration. * @retval HAL status */ -HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, + uint32_t Timeout) { uint32_t tickstart; uint8_t *ptmpdata = pData; @@ -1059,7 +1066,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard hsmartcard->hdmatx->XferAbortCallback = NULL; /* Enable the SMARTCARD transmit DMA channel */ - if (HAL_DMA_Start_IT(hsmartcard->hdmatx, (uint32_t)hsmartcard->pTxBuffPtr, (uint32_t)&hsmartcard->Instance->TDR, Size) == HAL_OK) + if (HAL_DMA_Start_IT(hsmartcard->hdmatx, (uint32_t)hsmartcard->pTxBuffPtr, (uint32_t)&hsmartcard->Instance->TDR, + Size) == HAL_OK) { /* Clear the TC flag in the ICR register */ CLEAR_BIT(hsmartcard->Instance->ICR, USART_ICR_TCCF); @@ -1135,7 +1143,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, hsmartcard->hdmarx->XferAbortCallback = NULL; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(hsmartcard->hdmarx, (uint32_t)&hsmartcard->Instance->RDR, (uint32_t)hsmartcard->pRxBuffPtr, Size) == HAL_OK) + if (HAL_DMA_Start_IT(hsmartcard->hdmarx, (uint32_t)&hsmartcard->Instance->RDR, (uint32_t)hsmartcard->pRxBuffPtr, + Size) == HAL_OK) { /* Process Unlocked */ __HAL_UNLOCK(hsmartcard); @@ -1188,7 +1197,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard) { /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RTOIE | USART_CR1_EOBIE)); + CLEAR_BIT(hsmartcard->Instance->CR1, + (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RTOIE | USART_CR1_EOBIE)); CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); /* Disable the SMARTCARD DMA Tx request if enabled */ @@ -1246,7 +1256,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard) hsmartcard->RxXferCount = 0U; /* Clear the Error flags in the ICR register */ - __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); + __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | + SMARTCARD_CLEAR_EOBF); /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */ hsmartcard->gState = HAL_SMARTCARD_STATE_READY; @@ -1375,7 +1387,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard hsmartcard->RxXferCount = 0U; /* Clear the Error flags in the ICR register */ - __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); + __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | + SMARTCARD_CLEAR_EOBF); /* Restore hsmartcard->RxState to Ready */ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; @@ -1403,7 +1417,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard) uint32_t abortcplt = 1U; /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RTOIE | USART_CR1_EOBIE)); + CLEAR_BIT(hsmartcard->Instance->CR1, + (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RTOIE | USART_CR1_EOBIE)); CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); /* If DMA Tx and/or DMA Rx Handles are associated to SMARTCARD Handle, DMA Abort complete callbacks should be initialised @@ -1500,7 +1515,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard) hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; /* Clear the Error flags in the ICR register */ - __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); + __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | + SMARTCARD_CLEAR_EOBF); /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */ hsmartcard->gState = HAL_SMARTCARD_STATE_READY; @@ -1627,7 +1644,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmart * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be * considered as completed only when user abort complete callback is executed (not when exiting function). * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartcard) { /* Disable RTOIE, EOBIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ @@ -1669,7 +1686,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartc hsmartcard->RxISR = NULL; /* Clear the Error flags in the ICR register */ - __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); + __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | + SMARTCARD_CLEAR_EOBF); /* Restore hsmartcard->RxState to Ready */ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; @@ -1693,7 +1712,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartc hsmartcard->RxISR = NULL; /* Clear the Error flags in the ICR register */ - __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); + __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | + SMARTCARD_CLEAR_EOBF); /* Restore hsmartcard->RxState to Ready */ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; @@ -1731,7 +1752,7 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard) { /* SMARTCARD in mode Receiver ---------------------------------------------------*/ if (((isrflags & USART_ISR_RXNE) != 0U) - && ((cr1its & USART_CR1_RXNEIE) != 0U)) + && ((cr1its & USART_CR1_RXNEIE) != 0U)) { if (hsmartcard->RxISR != NULL) { @@ -1793,7 +1814,7 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard) { /* SMARTCARD in mode Receiver ---------------------------------------------------*/ if (((isrflags & USART_ISR_RXNE) != 0U) - && ((cr1its & USART_CR1_RXNEIE) != 0U)) + && ((cr1its & USART_CR1_RXNEIE) != 0U)) { if (hsmartcard->RxISR != NULL) { @@ -1946,7 +1967,7 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard) /* SMARTCARD in mode Transmitter ------------------------------------------------*/ if (((isrflags & USART_ISR_TXE) != 0U) - && ((cr1its & USART_CR1_TXEIE) != 0U)) + && ((cr1its & USART_CR1_TXEIE) != 0U)) { if (hsmartcard->TxISR != NULL) { @@ -1958,7 +1979,7 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard) /* SMARTCARD in mode Transmitter (transmission end) ------------------------*/ if (__HAL_SMARTCARD_GET_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication) != RESET) { - if(__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication) != RESET) + if (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication) != RESET) { SMARTCARD_EndTransmit_IT(hsmartcard); return; @@ -2095,7 +2116,8 @@ __weak void HAL_SMARTCARD_AbortReceiveCpltCallback(SMARTCARD_HandleTypeDef *hsma HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard) { /* Return SMARTCARD handle state */ - uint32_t temp1, temp2; + uint32_t temp1; + uint32_t temp2; temp1 = (uint32_t)hsmartcard->gState; temp2 = (uint32_t)hsmartcard->RxState; @@ -2155,6 +2177,7 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard uint32_t tmpreg; SMARTCARD_ClockSourceTypeDef clocksource; HAL_StatusTypeDef ret = HAL_OK; + uint32_t pclk; /* Check the parameters */ assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance)); @@ -2177,7 +2200,7 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard * Configure the Parity and Mode: * set PS bit according to hsmartcard->Init.Parity value * set TE and RE bits according to hsmartcard->Init.Mode value */ - tmpreg = (uint32_t) (hsmartcard->Init.Parity | hsmartcard->Init.Mode | hsmartcard->Init.WordLength); + tmpreg = (uint32_t)(hsmartcard->Init.Parity | hsmartcard->Init.Mode | hsmartcard->Init.WordLength); MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_FIELDS, tmpreg); /*-------------------------- USART CR2 Configuration -----------------------*/ @@ -2220,16 +2243,19 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard switch (clocksource) { case SMARTCARD_CLOCKSOURCE_PCLK1: - tmpreg = (uint16_t)((HAL_RCC_GetPCLK1Freq() + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); + pclk = HAL_RCC_GetPCLK1Freq(); + tmpreg = (uint16_t)((pclk + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); break; case SMARTCARD_CLOCKSOURCE_PCLK2: - tmpreg = (uint16_t)((HAL_RCC_GetPCLK2Freq() + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); + pclk = HAL_RCC_GetPCLK2Freq(); + tmpreg = (uint16_t)((pclk + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); break; case SMARTCARD_CLOCKSOURCE_HSI: tmpreg = (uint16_t)((HSI_VALUE + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); break; case SMARTCARD_CLOCKSOURCE_SYSCLK: - tmpreg = (uint16_t)((HAL_RCC_GetSysClockFreq() + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); + pclk = HAL_RCC_GetSysClockFreq(); + tmpreg = (uint16_t)((pclk + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); break; case SMARTCARD_CLOCKSOURCE_LSE: tmpreg = (uint16_t)((LSE_VALUE + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); @@ -2340,7 +2366,8 @@ static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmar if ((hsmartcard->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) { /* Wait until TEACK flag is set */ - if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_TEACK, RESET, tickstart, SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK) + if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_TEACK, RESET, tickstart, + SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK) { /* Timeout occurred */ return HAL_TIMEOUT; @@ -2367,7 +2394,8 @@ static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmar * @param Timeout Timeout duration. * @retval HAL status */ -static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) +static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, + FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) { /* Wait until flag is set */ while ((__HAL_SMARTCARD_GET_FLAG(hsmartcard, Flag) ? SET : RESET) == Status) @@ -2491,7 +2519,7 @@ static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma) /* Stop SMARTCARD DMA Tx request if ongoing */ if (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX) { - if(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) + if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) { hsmartcard->TxXferCount = 0U; SMARTCARD_EndTxTransfer(hsmartcard); @@ -2570,7 +2598,9 @@ static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma) hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; /* Clear the Error flags in the ICR register */ - __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); + __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | + SMARTCARD_CLEAR_EOBF); /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */ hsmartcard->gState = HAL_SMARTCARD_STATE_READY; @@ -2617,7 +2647,9 @@ static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma) hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; /* Clear the Error flags in the ICR register */ - __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); + __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | + SMARTCARD_CLEAR_EOBF); /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */ hsmartcard->gState = HAL_SMARTCARD_STATE_READY; @@ -2677,7 +2709,9 @@ static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) hsmartcard->RxXferCount = 0U; /* Clear the Error flags in the ICR register */ - __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); + __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | + SMARTCARD_CLEAR_EOBF); /* Restore hsmartcard->RxState to Ready */ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_smartcard_ex.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_smartcard_ex.c index a5881e2b45..c919c03a6d 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_smartcard_ex.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_smartcard_ex.c @@ -165,12 +165,6 @@ HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef /** @defgroup SMARTCARDEx_Exported_Functions_Group2 Extended Peripheral IO operation functions * @brief SMARTCARD Transmit and Receive functions * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - [..] -@endverbatim * @{ */ @@ -178,28 +172,12 @@ HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef * @} */ -/** @defgroup SMARTCARD_Exported_Functions_Group3 Extended Peripheral Peripheral Control functions - * @brief SMARTCARD control functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] -@endverbatim - * @{ - */ - - -/** - * @} - */ /** * @} */ -/** @defgroup SMARTCARDEx_Private_Functions SMARTCARD Extended private Functions +/** @defgroup SMARTCARDEx_Private_Functions SMARTCARD Extended Private Functions * @{ */ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_smbus.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_smbus.c index f23105d9ed..a01d9f8c61 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_smbus.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_smbus.c @@ -89,12 +89,12 @@ *** Callback registration *** ============================================= - + [..] The compilation flag USE_HAL_SMBUS_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. Use Functions @ref HAL_SMBUS_RegisterCallback() or @ref HAL_SMBUS_RegisterAddrCallback() to register an interrupt callback. - + [..] Function @ref HAL_SMBUS_RegisterCallback() allows to register following callbacks: (+) MasterTxCpltCallback : callback for Master transmission end of transfer. (+) MasterRxCpltCallback : callback for Master reception end of transfer. @@ -106,9 +106,9 @@ (+) MspDeInitCallback : callback for Msp DeInit. This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. - + [..] For specific callback AddrCallback use dedicated register callbacks : @ref HAL_SMBUS_RegisterAddrCallback. - + [..] Use function @ref HAL_SMBUS_UnRegisterCallback to reset a callback to the default weak function. @ref HAL_SMBUS_UnRegisterCallback takes as parameters the HAL peripheral handle, @@ -122,9 +122,9 @@ (+) ErrorCallback : callback for error detection. (+) MspInitCallback : callback for Msp Init. (+) MspDeInitCallback : callback for Msp DeInit. - + [..] For callback AddrCallback use dedicated register callbacks : @ref HAL_SMBUS_UnRegisterAddrCallback. - + [..] By default, after the @ref HAL_SMBUS_Init() and when the state is @ref HAL_I2C_STATE_RESET all callbacks are set to the corresponding weak functions: examples @ref HAL_SMBUS_MasterTxCpltCallback(), @ref HAL_SMBUS_MasterRxCpltCallback(). @@ -133,7 +133,7 @@ these callbacks are null (not registered beforehand). If MspInit or MspDeInit are not null, the @ref HAL_SMBUS_Init()/ @ref HAL_SMBUS_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. - + [..] Callbacks can be registered/unregistered in @ref HAL_I2C_STATE_READY state only. Exception done MspInit/MspDeInit functions that can be registered/unregistered in @ref HAL_I2C_STATE_READY or @ref HAL_I2C_STATE_RESET state, @@ -141,7 +141,7 @@ Then, the user first registers the MspInit/MspDeInit user callbacks using @ref HAL_SMBUS_RegisterCallback() before calling @ref HAL_SMBUS_DeInit() or @ref HAL_SMBUS_Init() function. - + [..] When the compilation flag USE_HAL_SMBUS_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available and all callbacks are set to the corresponding weak functions. diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c index c26b99d789..5ee114fa3d 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c @@ -98,18 +98,22 @@ *** Callback registration *** ============================================= + [..] The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. + [..] Use Function @ref HAL_TIM_RegisterCallback() to register a callback. @ref HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. + [..] Use function @ref HAL_TIM_UnRegisterCallback() to reset a callback to the default weak function. @ref HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle, and the Callback ID. + [..] These functions allow to register/unregister following callbacks: (+) Base_MspInitCallback : TIM Base Msp Init Callback. (+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback. @@ -140,15 +144,18 @@ (+) BreakCallback : TIM Break Callback. (+) Break2Callback : TIM Break2 Callback. + [..] By default, after the Init and when the state is HAL_TIM_STATE_RESET all interrupt callbacks are set to the corresponding weak functions: examples @ref HAL_TIM_TriggerCallback(), @ref HAL_TIM_ErrorCallback(). + [..] Exception done for MspInit and MspDeInit functions that are reset to the legacy weak functionalities in the Init / DeInit only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit keep and use the user MspInit / MspDeInit callbacks(registered beforehand) + [..] Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only. Exception done MspInit / MspDeInit that can be registered / unregistered in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state, @@ -156,6 +163,7 @@ all interrupt callbacks are set to the corresponding weak functions: In that case first register the MspInit/MspDeInit user callbacks using @ref HAL_TIM_RegisterCallback() before calling DeInit or Init function. + [..] When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available and all callbacks are set to the corresponding weak functions. @@ -216,7 +224,7 @@ static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma); static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma); static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma); static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, - TIM_SlaveConfigTypeDef *sSlaveConfig); + TIM_SlaveConfigTypeDef *sSlaveConfig); /** * @} */ @@ -227,8 +235,8 @@ static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, */ /** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions - * @brief Time Base functions - * + * @brief Time Base functions + * @verbatim ============================================================================== ##### Time Base functions ##### @@ -482,11 +490,11 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat /* Check the parameters */ assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); - if ((htim->State == HAL_TIM_STATE_BUSY)) + if (htim->State == HAL_TIM_STATE_BUSY) { return HAL_BUSY; } - else if ((htim->State == HAL_TIM_STATE_READY)) + else if (htim->State == HAL_TIM_STATE_READY) { if ((pData == NULL) && (Length > 0U)) { @@ -559,8 +567,8 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) */ /** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions - * @brief TIM Output Compare functions - * + * @brief TIM Output Compare functions + * @verbatim ============================================================================== ##### TIM Output Compare functions ##### @@ -929,16 +937,16 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) */ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) { - uint32_t tmpsmcr; + uint32_t tmpsmcr; /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - if ((htim->State == HAL_TIM_STATE_BUSY)) + if (htim->State == HAL_TIM_STATE_BUSY) { return HAL_BUSY; } - else if ((htim->State == HAL_TIM_STATE_READY)) + else if (htim->State == HAL_TIM_STATE_READY) { if ((pData == NULL) && (Length > 0U)) { @@ -1136,8 +1144,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) */ /** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions - * @brief TIM PWM functions - * + * @brief TIM PWM functions + * @verbatim ============================================================================== ##### TIM PWM functions ##### @@ -1513,11 +1521,11 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - if ((htim->State == HAL_TIM_STATE_BUSY)) + if (htim->State == HAL_TIM_STATE_BUSY) { return HAL_BUSY; } - else if ((htim->State == HAL_TIM_STATE_READY)) + else if (htim->State == HAL_TIM_STATE_READY) { if ((pData == NULL) && (Length > 0U)) { @@ -1714,8 +1722,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel */ /** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions - * @brief TIM Input Capture functions - * + * @brief TIM Input Capture functions + * @verbatim ============================================================================== ##### TIM Input Capture functions ##### @@ -2061,11 +2069,11 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); - if ((htim->State == HAL_TIM_STATE_BUSY)) + if (htim->State == HAL_TIM_STATE_BUSY) { return HAL_BUSY; } - else if ((htim->State == HAL_TIM_STATE_READY)) + else if (htim->State == HAL_TIM_STATE_READY) { if ((pData == NULL) && (Length > 0U)) { @@ -2249,8 +2257,8 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) */ /** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions - * @brief TIM One Pulse functions - * + * @brief TIM One Pulse functions + * @verbatim ============================================================================== ##### TIM One Pulse functions ##### @@ -2563,8 +2571,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out */ /** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions - * @brief TIM Encoder functions - * + * @brief TIM Encoder functions + * @verbatim ============================================================================== ##### TIM Encoder functions ##### @@ -2609,15 +2617,15 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini } /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode)); assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection)); assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection)); - assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); - assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity)); + assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity)); + assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity)); assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler)); assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); @@ -2775,7 +2783,7 @@ __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); /* Enable the encoder interface channels */ switch (Channel) @@ -2819,7 +2827,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channe HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); /* Disable the Input Capture channels 1 and 2 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ @@ -2865,7 +2873,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); /* Enable the encoder interface channels */ /* Enable the capture compare Interrupts 1 and/or 2 */ @@ -2915,7 +2923,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Cha HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); /* Disable the Input Capture channels 1 and 2 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ @@ -2966,16 +2974,17 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chan * @param Length The length of data to be transferred from TIM peripheral to memory. * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length) +HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, + uint32_t *pData2, uint16_t Length) { /* Check the parameters */ - assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); - if ((htim->State == HAL_TIM_STATE_BUSY)) + if (htim->State == HAL_TIM_STATE_BUSY) { return HAL_BUSY; } - else if ((htim->State == HAL_TIM_STATE_READY)) + else if (htim->State == HAL_TIM_STATE_READY) { if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U)) { @@ -3103,7 +3112,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ - assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); /* Disable the Input Capture channels 1 and 2 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ @@ -3149,8 +3158,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Cha * @} */ /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management - * @brief TIM IRQ handler management - * + * @brief TIM IRQ handler management + * @verbatim ============================================================================== ##### IRQ handler management ##### @@ -3363,8 +3372,8 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) */ /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions - * @brief TIM Peripheral Control functions - * + * @brief TIM Peripheral Control functions + * @verbatim ============================================================================== ##### Peripheral Control functions ##### @@ -3738,9 +3747,14 @@ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @note To output a waveform with a minimum delay user can enable the fast + * mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx + * output is forced in response to the edge detection on TIx input, + * without taking in account the comparison. * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel) +HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, + uint32_t OutputChannel, uint32_t InputChannel) { TIM_OC_InitTypeDef temp1; @@ -3894,11 +3908,11 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); assert_param(IS_TIM_DMA_LENGTH(BurstLength)); - if ((htim->State == HAL_TIM_STATE_BUSY)) + if (htim->State == HAL_TIM_STATE_BUSY) { return HAL_BUSY; } - else if ((htim->State == HAL_TIM_STATE_READY)) + else if (htim->State == HAL_TIM_STATE_READY) { if ((BurstBuffer == NULL) && (BurstLength > 0U)) { @@ -3941,7 +3955,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) { return HAL_ERROR; } @@ -3957,7 +3972,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) { return HAL_ERROR; } @@ -3973,7 +3989,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) { return HAL_ERROR; } @@ -3989,7 +4006,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) { return HAL_ERROR; } @@ -4005,7 +4023,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) { return HAL_ERROR; } @@ -4021,7 +4040,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) { return HAL_ERROR; } @@ -4151,8 +4171,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B * @note This function should be used only when BurstLength is equal to DMA data transfer length. * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, - uint32_t *BurstBuffer, uint32_t BurstLength) +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength) { /* Check the parameters */ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); @@ -4160,11 +4180,11 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); assert_param(IS_TIM_DMA_LENGTH(BurstLength)); - if ((htim->State == HAL_TIM_STATE_BUSY)) + if (htim->State == HAL_TIM_STATE_BUSY) { return HAL_BUSY; } - else if ((htim->State == HAL_TIM_STATE_READY)) + else if (htim->State == HAL_TIM_STATE_READY) { if ((BurstBuffer == NULL) && (BurstLength > 0U)) { @@ -4465,7 +4485,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */ if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1) { - htim->State = HAL_TIM_STATE_READY; + htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); return HAL_ERROR; } @@ -4780,9 +4800,9 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveC htim->State = HAL_TIM_STATE_BUSY; - if(TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) + if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) { - htim->State = HAL_TIM_STATE_READY; + htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); return HAL_ERROR; } @@ -4810,7 +4830,7 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveC * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, - TIM_SlaveConfigTypeDef *sSlaveConfig) + TIM_SlaveConfigTypeDef *sSlaveConfig) { /* Check the parameters */ assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); @@ -4821,9 +4841,9 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, htim->State = HAL_TIM_STATE_BUSY; - if(TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) + if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) { - htim->State = HAL_TIM_STATE_READY; + htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); return HAL_ERROR; } @@ -4913,8 +4933,8 @@ uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel) */ /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions - * @brief TIM Callbacks functions - * + * @brief TIM Callbacks functions + * @verbatim ============================================================================== ##### TIM Callbacks functions ##### @@ -5118,7 +5138,8 @@ __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) * @param pCallback pointer to the callback function * @retval status */ -HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, pTIM_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, + pTIM_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -5578,8 +5599,8 @@ HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Ca */ /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions - * @brief TIM Peripheral State functions - * + * @brief TIM Peripheral State functions + * @verbatim ============================================================================== ##### Peripheral State functions ##### @@ -6365,7 +6386,7 @@ static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, * @retval None */ static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, - TIM_SlaveConfigTypeDef *sSlaveConfig) + TIM_SlaveConfigTypeDef *sSlaveConfig) { uint32_t tmpsmcr; uint32_t tmpccmr1; diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c index 1895414e10..7dd91df446 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c @@ -73,7 +73,7 @@ * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** -*/ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f7xx_hal.h" @@ -397,11 +397,11 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32 /* Check the parameters */ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); - if ((htim->State == HAL_TIM_STATE_BUSY)) + if (htim->State == HAL_TIM_STATE_BUSY) { return HAL_BUSY; } - else if ((htim->State == HAL_TIM_STATE_READY)) + else if (htim->State == HAL_TIM_STATE_READY) { if (((uint32_t)pData == 0U) && (Length > 0U)) { @@ -709,11 +709,11 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - if ((htim->State == HAL_TIM_STATE_BUSY)) + if (htim->State == HAL_TIM_STATE_BUSY) { return HAL_BUSY; } - else if ((htim->State == HAL_TIM_STATE_READY)) + else if (htim->State == HAL_TIM_STATE_READY) { if (((uint32_t)pData == 0U) && (Length > 0U)) { @@ -1117,11 +1117,11 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - if ((htim->State == HAL_TIM_STATE_BUSY)) + if (htim->State == HAL_TIM_STATE_BUSY) { return HAL_BUSY; } - else if ((htim->State == HAL_TIM_STATE_READY)) + else if (htim->State == HAL_TIM_STATE_READY) { if (((uint32_t)pData == 0U) && (Length > 0U)) { @@ -1466,7 +1466,8 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit * @retval HAL status */ -HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource) +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource) { /* Check the parameters */ assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); @@ -1521,7 +1522,8 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit * @retval HAL status */ -HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource) +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource) { /* Check the parameters */ assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); @@ -1577,7 +1579,8 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit * @retval HAL status */ -HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource) +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource) { /* Check the parameters */ assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); @@ -1632,7 +1635,7 @@ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, uint32_t tmpsmcr; /* Check the parameters */ - assert_param(IS_TIM_SYNCHRO_INSTANCE(htim->Instance)); + assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); @@ -1665,16 +1668,19 @@ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, /* Select the TRGO source */ tmpcr2 |= sMasterConfig->MasterOutputTrigger; - /* Reset the MSM Bit */ - tmpsmcr &= ~TIM_SMCR_MSM; - /* Set master mode */ - tmpsmcr |= sMasterConfig->MasterSlaveMode; - /* Update TIMx CR2 */ htim->Instance->CR2 = tmpcr2; - /* Update TIMx SMCR */ - htim->Instance->SMCR = tmpsmcr; + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + /* Reset the MSM Bit */ + tmpsmcr &= ~TIM_SMCR_MSM; + /* Set master mode */ + tmpsmcr |= sMasterConfig->MasterSlaveMode; + + /* Update TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + } /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; @@ -1690,6 +1696,9 @@ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, * @param htim TIM handle * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that * contains the BDTR Register configuration information for the TIM peripheral. + * @note Interrupts can be generated when an active level is detected on the + * break input, the break 2 input or the system break input. Break + * interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, @@ -1763,10 +1772,10 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, { uint32_t tmporx; - uint32_t bkin_enable_mask = 0U; - uint32_t bkin_polarity_mask = 0U; - uint32_t bkin_enable_bitpos = 0U; - uint32_t bkin_polarity_bitpos = 0U; + uint32_t bkin_enable_mask; + uint32_t bkin_polarity_mask; + uint32_t bkin_enable_bitpos; + uint32_t bkin_polarity_bitpos; /* Check the parameters */ assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); @@ -1800,11 +1809,19 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, { bkin_enable_mask = TIM1_AF1_BKDF1BKE; bkin_enable_bitpos = 8; + bkin_polarity_mask = 0U; + bkin_polarity_bitpos = 0U; break; } default: + { + bkin_enable_mask = 0U; + bkin_polarity_mask = 0U; + bkin_enable_bitpos = 0U; + bkin_polarity_bitpos = 0U; break; + } } switch (BreakInput) @@ -2054,7 +2071,7 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) */ /* Private functions ---------------------------------------------------------*/ -/** @defgroup TIMEx_Private_Functions TIM Extended Private Functions +/** @defgroup TIMEx_Private_Functions TIMEx Private Functions * @{ */ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c index 9b09bdb460..fad875c0f2 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c @@ -326,7 +326,6 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) huart->gState = HAL_UART_STATE_BUSY; - /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); /* Set the UART Communication parameters */ @@ -346,7 +345,6 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); - /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ @@ -393,7 +391,6 @@ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) huart->gState = HAL_UART_STATE_BUSY; - /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); /* Set the UART Communication parameters */ @@ -416,7 +413,6 @@ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */ SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL); - /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ @@ -481,7 +477,6 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe huart->gState = HAL_UART_STATE_BUSY; - /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); /* Set the UART Communication parameters */ @@ -507,7 +502,6 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe /* Set the USART LIN Break detection length. */ MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength); - /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ @@ -567,7 +561,6 @@ HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Add huart->gState = HAL_UART_STATE_BUSY; - /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); /* Set the UART Communication parameters */ @@ -596,7 +589,6 @@ HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Add /* Set the wake up method by setting the WAKE bit in the CR1 register */ MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod); - /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ @@ -622,7 +614,6 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) huart->gState = HAL_UART_STATE_BUSY; - /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); huart->Instance->CR1 = 0x0U; @@ -645,7 +636,6 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) huart->gState = HAL_UART_STATE_RESET; huart->RxState = HAL_UART_STATE_RESET; - /* Process Unlock */ __HAL_UNLOCK(huart); return HAL_OK; @@ -704,18 +694,18 @@ __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) * @param pCallback pointer to the Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, pUART_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, + pUART_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; if (pCallback == NULL) { - /* Update the error code */ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; return HAL_ERROR; } - /* Process locked */ + __HAL_LOCK(huart); if (huart->gState == HAL_UART_STATE_READY) @@ -768,10 +758,8 @@ HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_ break; default : - /* Update the error code */ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; - /* Return error status */ status = HAL_ERROR; break; } @@ -789,24 +777,19 @@ HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_ break; default : - /* Update the error code */ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; - /* Return error status */ status = HAL_ERROR; break; } } else { - /* Update the error code */ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; - /* Return error status */ status = HAL_ERROR; } - /* Release Lock */ __HAL_UNLOCK(huart); return status; @@ -837,7 +820,6 @@ HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UAR { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ __HAL_LOCK(huart); if (HAL_UART_STATE_READY == huart->gState) @@ -876,6 +858,12 @@ HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UAR huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */ break; +#if defined(USART_CR1_UESM) + case HAL_UART_WAKEUP_CB_ID : + huart->WakeupCallback = HAL_UARTEx_WakeupCallback; /* Legacy weak WakeupCallback */ + break; + +#endif /* USART_CR1_UESM */ case HAL_UART_MSPINIT_CB_ID : huart->MspInitCallback = HAL_UART_MspInit; /* Legacy weak MspInitCallback */ break; @@ -885,10 +873,8 @@ HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UAR break; default : - /* Update the error code */ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; - /* Return error status */ status = HAL_ERROR; break; } @@ -906,24 +892,19 @@ HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UAR break; default : - /* Update the error code */ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; - /* Return error status */ status = HAL_ERROR; break; } } else { - /* Update the error code */ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; - /* Return error status */ status = HAL_ERROR; } - /* Release Lock */ __HAL_UNLOCK(huart); return status; @@ -992,6 +973,11 @@ HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UAR (+) HAL_UART_AbortCpltCallback() (+) HAL_UART_AbortTransmitCpltCallback() (+) HAL_UART_AbortReceiveCpltCallback() +#if defined(USART_CR1_UESM) + + (#) Wakeup from Stop mode Callback: + (+) HAL_UARTEx_WakeupCallback() +#endif (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. Errors are handled as follows : @@ -1013,9 +999,12 @@ HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UAR /** * @brief Send an amount of data in blocking mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pData. * @param huart UART handle. - * @param pData Pointer to data buffer. - * @param Size Amount of data to be sent. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent. * @param Timeout Timeout duration. * @retval HAL status */ @@ -1033,7 +1022,6 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u return HAL_ERROR; } - /* Process Locked */ __HAL_LOCK(huart); huart->ErrorCode = HAL_UART_ERROR_NONE; @@ -1045,7 +1033,7 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u huart->TxXferSize = Size; huart->TxXferCount = Size; - /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */ + /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) { pdata8bits = NULL; @@ -1057,6 +1045,8 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u pdata16bits = NULL; } + __HAL_UNLOCK(huart); + while (huart->TxXferCount > 0U) { if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) @@ -1084,9 +1074,6 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u /* At end of Tx process, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(huart); - return HAL_OK; } else @@ -1097,9 +1084,12 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u /** * @brief Receive an amount of data in blocking mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pData. * @param huart UART handle. - * @param pData Pointer to data buffer. - * @param Size Amount of data to be received. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. * @param Timeout Timeout duration. * @retval HAL status */ @@ -1118,7 +1108,6 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui return HAL_ERROR; } - /* Process Locked */ __HAL_LOCK(huart); huart->ErrorCode = HAL_UART_ERROR_NONE; @@ -1146,6 +1135,8 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui pdata16bits = NULL; } + __HAL_UNLOCK(huart); + /* as long as data have to be received */ while (huart->RxXferCount > 0U) { @@ -1169,9 +1160,6 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(huart); - return HAL_OK; } else @@ -1182,9 +1170,12 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui /** * @brief Send an amount of data in interrupt mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pData. * @param huart UART handle. - * @param pData Pointer to data buffer. - * @param Size Amount of data to be sent. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) @@ -1197,7 +1188,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData return HAL_ERROR; } - /* Process Locked */ __HAL_LOCK(huart); huart->pTxBuffPtr = pData; @@ -1218,7 +1208,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData huart->TxISR = UART_TxISR_8BIT; } - /* Process Unlocked */ __HAL_UNLOCK(huart); /* Enable the Transmit Data Register Empty interrupt */ @@ -1234,9 +1223,12 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData /** * @brief Receive an amount of data in interrupt mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pData. * @param huart UART handle. - * @param pData Pointer to data buffer. - * @param Size Amount of data to be received. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) @@ -1249,7 +1241,6 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, return HAL_ERROR; } - /* Process Locked */ __HAL_LOCK(huart); huart->pRxBuffPtr = pData; @@ -1276,7 +1267,6 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, huart->RxISR = UART_RxISR_8BIT; } - /* Process Unlocked */ __HAL_UNLOCK(huart); /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */ @@ -1292,9 +1282,12 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, /** * @brief Send an amount of data in DMA mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pData. * @param huart UART handle. - * @param pData Pointer to data buffer. - * @param Size Amount of data to be sent. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) @@ -1307,7 +1300,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat return HAL_ERROR; } - /* Process Locked */ __HAL_LOCK(huart); huart->pTxBuffPtr = pData; @@ -1337,7 +1329,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat /* Set error code to DMA */ huart->ErrorCode = HAL_UART_ERROR_DMA; - /* Process Unlocked */ __HAL_UNLOCK(huart); /* Restore huart->gState to ready */ @@ -1349,7 +1340,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat /* Clear the TC flag in the ICR register */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF); - /* Process Unlocked */ __HAL_UNLOCK(huart); /* Enable the DMA transfer for transmit request by setting the DMAT bit @@ -1368,9 +1358,12 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat * @brief Receive an amount of data in DMA mode. * @note When the UART parity is enabled (PCE = 1), the received data contain * the parity bit (MSB position). + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pData. * @param huart UART handle. - * @param pData Pointer to data buffer. - * @param Size Amount of data to be received. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) @@ -1383,7 +1376,6 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData return HAL_ERROR; } - /* Process Locked */ __HAL_LOCK(huart); huart->pRxBuffPtr = pData; @@ -1412,7 +1404,6 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData /* Set error code to DMA */ huart->ErrorCode = HAL_UART_ERROR_DMA; - /* Process Unlocked */ __HAL_UNLOCK(huart); /* Restore huart->gState to ready */ @@ -1421,7 +1412,6 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData return HAL_ERROR; } } - /* Process Unlocked */ __HAL_UNLOCK(huart); /* Enable the UART Parity Error Interrupt */ @@ -1452,7 +1442,6 @@ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) const HAL_UART_StateTypeDef gstate = huart->gState; const HAL_UART_StateTypeDef rxstate = huart->RxState; - /* Process Locked */ __HAL_LOCK(huart); if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && @@ -1472,7 +1461,6 @@ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); } - /* Process Unlocked */ __HAL_UNLOCK(huart); return HAL_OK; @@ -1485,7 +1473,6 @@ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) */ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) { - /* Process Locked */ __HAL_LOCK(huart); if (huart->gState == HAL_UART_STATE_BUSY_TX) @@ -1506,7 +1493,6 @@ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); } - /* Process Unlocked */ __HAL_UNLOCK(huart); return HAL_OK; @@ -1591,7 +1577,7 @@ HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) * - Set handle State to READY * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) { /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ @@ -1663,7 +1649,6 @@ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; - /* Reset Handle ErrorCode to No Error */ huart->ErrorCode = HAL_UART_ERROR_NONE; return HAL_OK; @@ -1680,7 +1665,7 @@ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) * - Set handle State to READY * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) { /* Disable TXEIE and TCIE interrupts */ @@ -1732,7 +1717,7 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) * - Set handle State to READY * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) { /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ @@ -1792,7 +1777,7 @@ HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be * considered as completed only when user abort complete callback is executed (not when exiting function). * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) { uint32_t abortcplt = 1U; @@ -1931,7 +1916,7 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be * considered as completed only when user abort complete callback is executed (not when exiting function). * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) { /* Disable interrupts */ @@ -2015,7 +2000,7 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be * considered as completed only when user abort complete callback is executed (not when exiting function). * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) { /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ @@ -2110,7 +2095,7 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) uint32_t errorcode; /* If no error occurs */ - errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE)); + errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF)); if (errorflags == 0U) { /* UART in mode Receiver ---------------------------------------------------*/ @@ -2164,10 +2149,18 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) huart->ErrorCode |= HAL_UART_ERROR_ORE; } - /* Call UART Error Call back function if need be --------------------------*/ + /* UART Receiver Timeout interrupt occurred ---------------------------------*/ + if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); + + huart->ErrorCode |= HAL_UART_ERROR_RTO; + } + + /* Call UART Error Call back function if need be ----------------------------*/ if (huart->ErrorCode != HAL_UART_ERROR_NONE) { - /* UART in mode Receiver ---------------------------------------------------*/ + /* UART in mode Receiver --------------------------------------------------*/ if (((isrflags & USART_ISR_RXNE) != 0U) && ((cr1its & USART_CR1_RXNEIE) != 0U)) { @@ -2177,11 +2170,14 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) } } - /* If Overrun error occurs, or if any error occurs in DMA mode reception, - consider error as blocking */ + /* If Error is to be considered as blocking : + - Receiver Timeout error in Reception + - Overrun error in Reception + - any error occurs in DMA mode reception + */ errorcode = huart->ErrorCode; if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) || - ((errorcode & HAL_UART_ERROR_ORE) != 0U)) + ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U)) { /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, @@ -2249,6 +2245,26 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) return; } /* End if some error occurs */ +#if defined(USART_CR1_UESM) + + /* UART wakeup from Stop mode interrupt occurred ---------------------------*/ + if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF); + + /* UART Rx state is not reset as a reception process might be ongoing. + If UART handle state fields need to be reset to READY, this could be done in Wakeup callback */ + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Wakeup Callback */ + huart->WakeupCallback(huart); +#else + /* Call legacy weak Wakeup Callback */ + HAL_UARTEx_WakeupCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + return; + } +#endif /* USART_CR1_UESM */ /* UART in mode Transmitter ------------------------------------------------*/ if (((isrflags & USART_ISR_TXE) != 0U) @@ -2390,6 +2406,23 @@ __weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart) */ } +#if defined(USART_CR1_UESM) +/** + * @brief UART wakeup from Stop mode callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UARTEx_WakeupCallback can be implemented in the user file. + */ +} + +#endif /* USART_CR1_UESM */ /** * @} */ @@ -2403,6 +2436,9 @@ __weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart) =============================================================================== [..] This subsection provides a set of functions allowing to control the UART. + (+) HAL_UART_ReceiverTimeout_Config() API allows to configure the receiver timeout value on the fly + (+) HAL_UART_EnableReceiverTimeout() API enables the receiver timeout feature + (+) HAL_UART_DisableReceiverTimeout() API disables the receiver timeout feature (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode (+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode (+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode @@ -2416,6 +2452,82 @@ __weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart) * @{ */ +/** + * @brief Update on the fly the receiver timeout value in RTOR register. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @param TimeoutValue receiver timeout value in number of baud blocks. The timeout + * value must be less or equal to 0x0FFFFFFFF. + * @retval None + */ +void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue) +{ + assert_param(IS_UART_RECEIVER_TIMEOUT_VALUE(TimeoutValue)); + MODIFY_REG(huart->Instance->RTOR, USART_RTOR_RTO, TimeoutValue); +} + +/** + * @brief Enable the UART receiver timeout feature. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart) +{ + if (huart->gState == HAL_UART_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Set the USART RTOEN bit */ + SET_BIT(huart->Instance->CR2, USART_CR2_RTOEN); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Disable the UART receiver timeout feature. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart) +{ + if (huart->gState == HAL_UART_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Clear the USART RTOEN bit */ + CLEAR_BIT(huart->Instance->CR2, USART_CR2_RTOEN); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + /** * @brief Enable UART in mute mode (does not mean UART enters mute mode; * to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called). @@ -2424,7 +2536,6 @@ __weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart) */ HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart) { - /* Process Locked */ __HAL_LOCK(huart); huart->gState = HAL_UART_STATE_BUSY; @@ -2445,7 +2556,6 @@ HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart) */ HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart) { - /* Process Locked */ __HAL_LOCK(huart); huart->gState = HAL_UART_STATE_BUSY; @@ -2476,7 +2586,6 @@ void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart) */ HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart) { - /* Process Locked */ __HAL_LOCK(huart); huart->gState = HAL_UART_STATE_BUSY; @@ -2488,7 +2597,6 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart) huart->gState = HAL_UART_STATE_READY; - /* Process Unlocked */ __HAL_UNLOCK(huart); return HAL_OK; @@ -2501,7 +2609,6 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart) */ HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart) { - /* Process Locked */ __HAL_LOCK(huart); huart->gState = HAL_UART_STATE_BUSY; @@ -2513,7 +2620,6 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart) huart->gState = HAL_UART_STATE_READY; - /* Process Unlocked */ __HAL_UNLOCK(huart); return HAL_OK; @@ -2530,7 +2636,6 @@ HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) /* Check the parameters */ assert_param(IS_UART_LIN_INSTANCE(huart->Instance)); - /* Process Locked */ __HAL_LOCK(huart); huart->gState = HAL_UART_STATE_BUSY; @@ -2540,7 +2645,6 @@ HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) huart->gState = HAL_UART_STATE_READY; - /* Process Unlocked */ __HAL_UNLOCK(huart); return HAL_OK; @@ -2551,8 +2655,8 @@ HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) */ /** @defgroup UART_Exported_Functions_Group4 Peripheral State and Error functions - * @brief UART Peripheral State functions - * + * @brief UART Peripheral State functions + * @verbatim ============================================================================== ##### Peripheral State and Error functions ##### @@ -2574,7 +2678,8 @@ HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) */ HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart) { - uint32_t temp1, temp2; + uint32_t temp1; + uint32_t temp2; temp1 = huart->gState; temp2 = huart->RxState; @@ -2586,7 +2691,7 @@ HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart) * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART. * @retval UART Error Code -*/ + */ uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart) { return huart->ErrorCode; @@ -2620,6 +2725,9 @@ void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart) huart->AbortCpltCallback = HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */ huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */ +#if defined(USART_CR1_UESM) + huart->WakeupCallback = HAL_UARTEx_WakeupCallback; /* Legacy weak WakeupCallback */ +#endif /* USART_CR1_UESM */ } #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ @@ -2636,6 +2744,7 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) UART_ClockSourceTypeDef clocksource; uint32_t usartdiv = 0x00000000U; HAL_StatusTypeDef ret = HAL_OK; + uint32_t pclk; /* Check the parameters */ assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate)); @@ -2683,21 +2792,23 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) switch (clocksource) { case UART_CLOCKSOURCE_PCLK1: - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate)); + pclk = HAL_RCC_GetPCLK1Freq(); + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate)); break; case UART_CLOCKSOURCE_PCLK2: - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate)); + pclk = HAL_RCC_GetPCLK2Freq(); + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate)); break; case UART_CLOCKSOURCE_HSI: usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate)); break; case UART_CLOCKSOURCE_SYSCLK: - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate)); + pclk = HAL_RCC_GetSysClockFreq(); + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate)); break; case UART_CLOCKSOURCE_LSE: usartdiv = (uint16_t)(UART_DIV_SAMPLING8(LSE_VALUE, huart->Init.BaudRate)); break; - case UART_CLOCKSOURCE_UNDEFINED: default: ret = HAL_ERROR; break; @@ -2720,21 +2831,23 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) switch (clocksource) { case UART_CLOCKSOURCE_PCLK1: - usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate)); + pclk = HAL_RCC_GetPCLK1Freq(); + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate)); break; case UART_CLOCKSOURCE_PCLK2: - usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate)); + pclk = HAL_RCC_GetPCLK2Freq(); + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate)); break; case UART_CLOCKSOURCE_HSI: usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate)); break; case UART_CLOCKSOURCE_SYSCLK: - usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate)); + pclk = HAL_RCC_GetSysClockFreq(); + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate)); break; case UART_CLOCKSOURCE_LSE: usartdiv = (uint16_t)(UART_DIV_SAMPLING16(LSE_VALUE, huart->Init.BaudRate)); break; - case UART_CLOCKSOURCE_UNDEFINED: default: ret = HAL_ERROR; break; @@ -2858,12 +2971,24 @@ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) return HAL_TIMEOUT; } } +#if defined(USART_ISR_REACK) + + /* Check if the Receiver is enabled */ + if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) + { + /* Wait until REACK flag is set */ + if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) + { + /* Timeout occurred */ + return HAL_TIMEOUT; + } + } +#endif /* Initialize the UART State */ huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; - /* Process Unlocked */ __HAL_UNLOCK(huart); return HAL_OK; @@ -2878,7 +3003,8 @@ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) +HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout) { /* Wait until flag is set */ while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) @@ -2895,11 +3021,32 @@ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_ huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; - /* Process Unlocked */ __HAL_UNLOCK(huart); return HAL_TIMEOUT; } + + if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) + { + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET) + { + /* Clear Receiver Timeout flag*/ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); + + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + huart->ErrorCode = HAL_UART_ERROR_RTO; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_TIMEOUT; + } + } } } return HAL_OK; diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c index 254fe252f8..cdc535c511 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c @@ -57,6 +57,9 @@ /** @defgroup UARTEx_Private_Functions UARTEx Private Functions * @{ */ +#if defined(USART_CR1_UESM) +static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection); +#endif /* USART_CR1_UESM */ /** * @} */ @@ -144,7 +147,8 @@ * oversampling rate). * @retval HAL status */ -HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime) +HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, + uint32_t DeassertionTime) { uint32_t temp; @@ -224,42 +228,74 @@ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, * @} */ -/** @defgroup UARTEx_Exported_Functions_Group2 IO operation functions - * @brief Extended functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - This subsection provides a set of Wakeup and FIFO mode related callback functions. - -@endverbatim - * @{ - */ - - -/** - * @} - */ /** @defgroup UARTEx_Exported_Functions_Group3 Peripheral Control functions * @brief Extended Peripheral Control functions - * + * @verbatim =============================================================================== ##### Peripheral Control functions ##### =============================================================================== [..] This section provides the following functions: + (+) HAL_UARTEx_EnableClockStopMode() API enables the UART clock (HSI or LSE only) during stop mode + (+) HAL_UARTEx_DisableClockStopMode() API disables the above functionality (+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address detection length to more than 4 bits for multiprocessor address mark wake up. +#if defined(USART_CR1_UESM) + (+) HAL_UARTEx_StopModeWakeUpSourceConfig() API defines the wake-up from stop mode + trigger: address match, Start Bit detection or RXNE bit status. + (+) HAL_UARTEx_EnableStopMode() API enables the UART to wake up the MCU from stop mode + (+) HAL_UARTEx_DisableStopMode() API disables the above functionality +#endif @endverbatim * @{ */ +#if defined(USART_CR3_UCESM) +/** + * @brief Keep UART Clock enabled when in Stop Mode. + * @note When the USART clock source is configured to be LSE or HSI, it is possible to keep enabled + * this clock during STOP mode by setting the UCESM bit in USART_CR3 control register. + * @note When LPUART is used to wakeup from stop with LSE is selected as LPUART clock source, + * and desired baud rate is 9600 baud, the bit UCESM bit in LPUART_CR3 control register must be set. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_EnableClockStopMode(UART_HandleTypeDef *huart) +{ + /* Process Locked */ + __HAL_LOCK(huart); + + /* Set UCESM bit */ + SET_BIT(huart->Instance->CR3, USART_CR3_UCESM); + /* Process Unlocked */ + __HAL_UNLOCK(huart); + return HAL_OK; +} +/** + * @brief Disable UART Clock when in Stop Mode. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_DisableClockStopMode(UART_HandleTypeDef *huart) +{ + /* Process Locked */ + __HAL_LOCK(huart); + + /* Clear UCESM bit */ + CLEAR_BIT(huart->Instance->CR3, USART_CR3_UCESM); + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +#endif /* USART_CR3_UCESM */ /** * @brief By default in multiprocessor mode, when the wake up method is set * to address mark, the UART handles only 4-bit long addresses detection; @@ -299,8 +335,108 @@ HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *hua return (UART_CheckIdleState(huart)); } +#if defined(USART_CR1_UESM) +/** + * @brief Set Wakeup from Stop mode interrupt flag selection. + * @note It is the application responsibility to enable the interrupt used as + * usart_wkup interrupt source before entering low-power mode. + * @param huart UART handle. + * @param WakeUpSelection Address match, Start Bit detection or RXNE/RXFNE bit status. + * This parameter can be one of the following values: + * @arg @ref UART_WAKEUP_ON_ADDRESS + * @arg @ref UART_WAKEUP_ON_STARTBIT + * @arg @ref UART_WAKEUP_ON_READDATA_NONEMPTY + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tickstart; + + /* check the wake-up from stop mode UART instance */ + assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance)); + /* check the wake-up selection parameter */ + assert_param(IS_UART_WAKEUP_SELECTION(WakeUpSelection.WakeUpEvent)); + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_UART_DISABLE(huart); + /* Set the wake-up selection scheme */ + MODIFY_REG(huart->Instance->CR3, USART_CR3_WUS, WakeUpSelection.WakeUpEvent); + if (WakeUpSelection.WakeUpEvent == UART_WAKEUP_ON_ADDRESS) + { + UARTEx_Wakeup_AddressConfig(huart, WakeUpSelection); + } + + /* Enable the Peripheral */ + __HAL_UART_ENABLE(huart); + + /* Init tickstart for timeout managment*/ + tickstart = HAL_GetTick(); + + /* Wait until REACK flag is set */ + if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) + { + status = HAL_TIMEOUT; + } + else + { + /* Initialize the UART State */ + huart->gState = HAL_UART_STATE_READY; + } + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return status; +} + +/** + * @brief Enable UART Stop Mode. + * @note The UART is able to wake up the MCU from Stop 1 mode as long as UART clock is HSI or LSE. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart) +{ + /* Process Locked */ + __HAL_LOCK(huart); + + /* Set UESM bit */ + SET_BIT(huart->Instance->CR1, USART_CR1_UESM); + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Disable UART Stop Mode. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart) +{ + /* Process Locked */ + __HAL_LOCK(huart); + + /* Clear UESM bit */ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM); + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +#endif /* USART_CR1_UESM */ /** * @} */ @@ -312,6 +448,25 @@ HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *hua /** @addtogroup UARTEx_Private_Functions * @{ */ +#if defined(USART_CR1_UESM) + +/** + * @brief Initialize the UART wake-up from stop mode parameters when triggered by address detection. + * @param huart UART handle. + * @param WakeUpSelection UART wake up from stop mode parameters. + * @retval None + */ +static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection) +{ + assert_param(IS_UART_ADDRESSLENGTH_DETECT(WakeUpSelection.AddressLength)); + + /* Set the USART address length */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, WakeUpSelection.AddressLength); + + /* Set the USART address node */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)WakeUpSelection.Address << UART_CR2_ADDRESS_LSB_POS)); +} +#endif /* USART_CR1_UESM */ /** * @} diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_usart.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_usart.c index a8969dabea..92f27abb68 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_usart.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_usart.c @@ -181,7 +181,8 @@ static void USART_DMAError(DMA_HandleTypeDef *hdma); static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma); static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma); static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma); -static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout); +static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout); static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart); static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart); static void USART_TxISR_8BIT(USART_HandleTypeDef *husart); @@ -303,14 +304,15 @@ HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart) /* In Synchronous mode, the following bits must be kept cleared: - LINEN bit in the USART_CR2 register - - HDSEL, SCEN and IREN bits in the USART_CR3 register.*/ + - HDSEL, SCEN and IREN bits in the USART_CR3 register. + */ husart->Instance->CR2 &= ~USART_CR2_LINEN; husart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN); /* Enable the Peripheral */ __HAL_USART_ENABLE(husart); - /* TEACK to check before moving husart->State to Ready */ + /* TEACK and/or REACK to check before moving husart->State to Ready */ return (USART_CheckIdleState(husart)); } @@ -406,7 +408,8 @@ __weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart) * @param pCallback pointer to the Callback function * @retval HAL status + */ -HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID, pUSART_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID, + pUSART_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -701,9 +704,12 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_ /** * @brief Simplex send an amount of data in blocking mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pTxData. * @param husart USART handle. - * @param pTxData Pointer to data buffer. - * @param Size Amount of data to be sent. + * @param pTxData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent. * @param Timeout Timeout duration. * @retval HAL status */ @@ -794,10 +800,13 @@ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxDa /** * @brief Receive an amount of data in blocking mode. - * @note To receive synchronous data, dummy data are simultaneously transmitted. + * @note To receive synchronous data, dummy data are simultaneously transmitted. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pRxData. * @param husart USART handle. - * @param pRxData Pointer to data buffer. - * @param Size Amount of data to be received. + * @param pRxData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. * @param Timeout Timeout duration. * @retval HAL status */ @@ -896,14 +905,18 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat /** * @brief Full-Duplex Send and Receive an amount of data in blocking mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number + * of u16 available through pTxData and through pRxData. * @param husart USART handle. - * @param pTxData pointer to TX data buffer. - * @param pRxData pointer to RX data buffer. - * @param Size amount of data to be sent (same amount to be received). + * @param pTxData pointer to TX data buffer (u8 or u16 data elements). + * @param pRxData pointer to RX data buffer (u8 or u16 data elements). + * @param Size amount of data elements (u8 or u16) to be sent (same amount to be received). * @param Timeout Timeout duration. * @retval HAL status */ -HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size, uint32_t Timeout) { uint8_t *prxdata8bits; uint16_t *prxdata16bits; @@ -1041,9 +1054,12 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t /** * @brief Send an amount of data in interrupt mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pTxData. * @param husart USART handle. - * @param pTxData pointer to data buffer. - * @param Size amount of data to be sent. + * @param pTxData pointer to data buffer (u8 or u16 data elements). + * @param Size amount of data elements (u8 or u16) to be sent. * @retval HAL status */ HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size) @@ -1100,10 +1116,13 @@ HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pT /** * @brief Receive an amount of data in interrupt mode. - * @note To receive synchronous data, dummy data are simultaneously transmitted. + * @note To receive synchronous data, dummy data are simultaneously transmitted. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pRxData. * @param husart USART handle. - * @param pRxData pointer to data buffer. - * @param Size amount of data to be received. + * @param pRxData pointer to data buffer (u8 or u16 data elements). + * @param Size amount of data elements (u8 or u16) to be received. * @retval HAL status */ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size) @@ -1168,13 +1187,17 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx /** * @brief Full-Duplex Send and Receive an amount of data in interrupt mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number + * of u16 available through pTxData and through pRxData. * @param husart USART handle. - * @param pTxData pointer to TX data buffer. - * @param pRxData pointer to RX data buffer. - * @param Size amount of data to be sent (same amount to be received). + * @param pTxData pointer to TX data buffer (u8 or u16 data elements). + * @param pRxData pointer to RX data buffer (u8 or u16 data elements). + * @param Size amount of data elements (u8 or u16) to be sent (same amount to be received). * @retval HAL status */ -HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) +HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size) { if (husart->State == HAL_USART_STATE_READY) @@ -1235,9 +1258,12 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint /** * @brief Send an amount of data in DMA mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pTxData. * @param husart USART handle. - * @param pTxData pointer to data buffer. - * @param Size amount of data to be sent. + * @param pTxData pointer to data buffer (u8 or u16 data elements). + * @param Size amount of data elements (u8 or u16) to be sent. * @retval HAL status */ HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size) @@ -1316,10 +1342,13 @@ HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *p * @brief Receive an amount of data in DMA mode. * @note When the USART parity is enabled (PCE = 1), the received data contain * the parity bit (MSB position). - * @note The USART DMA transmit channel must be configured in order to generate the clock for the slave. + * @note The USART DMA transmit channel must be configured in order to generate the clock for the slave. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pRxData. * @param husart USART handle. - * @param pRxData pointer to data buffer. - * @param Size amount of data to be received. + * @param pRxData pointer to data buffer (u8 or u16 data elements). + * @param Size amount of data elements (u8 or u16) to be received. * @retval HAL status */ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size) @@ -1428,13 +1457,17 @@ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pR /** * @brief Full-Duplex Transmit Receive an amount of data in non-blocking mode. * @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number + * of u16 available through pTxData and through pRxData. * @param husart USART handle. - * @param pTxData pointer to TX data buffer. - * @param pRxData pointer to RX data buffer. - * @param Size amount of data to be received/sent. + * @param pTxData pointer to TX data buffer (u8 or u16 data elements). + * @param pRxData pointer to RX data buffer (u8 or u16 data elements). + * @param Size amount of data elements (u8 or u16) to be received/sent. * @retval HAL status */ -HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) +HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size) { HAL_StatusTypeDef status; uint32_t *tmp; @@ -1700,7 +1733,7 @@ HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart) * - Set handle State to READY * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart) { CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); @@ -1789,7 +1822,7 @@ HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart) * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be * considered as completed only when user abort complete callback is executed (not when exiting function). * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart) { uint32_t abortcplt = 1U; @@ -1924,7 +1957,7 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) uint32_t errorcode; /* If no error occurs */ - errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE)); + errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF)); if (errorflags == 0U) { /* USART in mode Receiver ---------------------------------------------------*/ @@ -1978,6 +2011,14 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) husart->ErrorCode |= HAL_USART_ERROR_ORE; } + /* USART Receiver Timeout interrupt occurred ---------------------------------*/ + if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U)) + { + __HAL_USART_CLEAR_IT(husart, USART_CLEAR_RTOF); + + husart->ErrorCode |= HAL_USART_ERROR_RTO; + } + /* Call USART Error Call back function if need be --------------------------*/ if (husart->ErrorCode != HAL_USART_ERROR_NONE) @@ -2206,8 +2247,8 @@ __weak void HAL_USART_AbortCpltCallback(USART_HandleTypeDef *husart) */ /** @defgroup USART_Exported_Functions_Group4 Peripheral State and Error functions - * @brief USART Peripheral State and Error functions - * + * @brief USART Peripheral State and Error functions + * @verbatim ============================================================================== ##### Peripheral State and Error functions ##### @@ -2253,8 +2294,8 @@ uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart) */ /** @defgroup USART_Private_Functions USART Private Functions - * @{ - */ + * @{ + */ /** * @brief Initialize the callbacks to their default values. @@ -2591,7 +2632,8 @@ static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) * @param Timeout timeout duration. * @retval HAL status */ -static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) +static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout) { /* Wait until flag is set */ while ((__HAL_USART_GET_FLAG(husart, Flag) ? SET : RESET) == Status) @@ -2625,6 +2667,7 @@ static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart) HAL_StatusTypeDef ret = HAL_OK; uint16_t brrtemp; uint32_t usartdiv = 0x00000000; + uint32_t pclk; /* Check the parameters */ assert_param(IS_USART_POLARITY(husart->Init.CLKPolarity)); @@ -2666,16 +2709,19 @@ static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart) switch (clocksource) { case USART_CLOCKSOURCE_PCLK1: - usartdiv = (uint32_t)(USART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), husart->Init.BaudRate)); + pclk = HAL_RCC_GetPCLK1Freq(); + usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pclk, husart->Init.BaudRate)); break; case USART_CLOCKSOURCE_PCLK2: - usartdiv = (uint32_t)(USART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), husart->Init.BaudRate)); + pclk = HAL_RCC_GetPCLK2Freq(); + usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pclk, husart->Init.BaudRate)); break; case USART_CLOCKSOURCE_HSI: usartdiv = (uint32_t)(USART_DIV_SAMPLING8(HSI_VALUE, husart->Init.BaudRate)); break; case USART_CLOCKSOURCE_SYSCLK: - usartdiv = (uint32_t)(USART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), husart->Init.BaudRate)); + pclk = HAL_RCC_GetSysClockFreq(); + usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pclk, husart->Init.BaudRate)); break; case USART_CLOCKSOURCE_LSE: usartdiv = (uint32_t)(USART_DIV_SAMPLING8(LSE_VALUE, husart->Init.BaudRate)); @@ -2730,6 +2776,18 @@ static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart) return HAL_TIMEOUT; } } +#if defined(USART_ISR_REACK) + /* Check if the Receiver is enabled */ + if ((husart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) + { + /* Wait until REACK flag is set */ + if (USART_WaitOnFlagUntilTimeout(husart, USART_ISR_REACK, RESET, tickstart, USART_TEACK_REACK_TIMEOUT) != HAL_OK) + { + /* Timeout occurred */ + return HAL_TIMEOUT; + } + } +#endif /* Initialize the USART state*/ husart->State = HAL_USART_STATE_READY; diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_wwdg.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_wwdg.c index b1fcde2387..82af5e2ed7 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_wwdg.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_wwdg.c @@ -32,17 +32,19 @@ (++) min time (mS) = 1000 * (Counter - Window) / WWDG clock (++) max time (mS) = 1000 * (Counter - 0x40) / WWDG clock (+) Typical values: - (++) Counter min (T[5;0] = 0x00) @56MHz (PCLK1) with zero prescaler: - max timeout before reset: ~73.14�s - (++) Counter max (T[5;0] = 0x3F) @56MHz (PCLK1) with prescaler dividing by 128: - max timeout before reset: ~599.18ms + (++) Counter min (T[5;0] = 0x00) @54MHz (PCLK1) with zero prescaler: + max timeout before reset: approximately 75.85�s + (++) Counter max (T[5;0] = 0x3F) @54MHz (PCLK1) with prescaler dividing by 8: + max timeout before reset: approximately 38.83ms ============================================================================== ##### How to use this driver ##### ============================================================================== - [..] + *** Common driver usage *** =========================== + + [..] (+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE(). (+) Set the WWDG prescaler, refresh window and counter value using HAL_WWDG_Init() function. @@ -59,9 +61,10 @@ HAL_WWDG_Refresh() function. This operation must occur only when the counter is lower than the refresh window value already programmed. - [..] *** Callback registration *** ============================= + + [..] The compilation define USE_HAL_WWDG_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. Use Functions @ref HAL_WWDG_RegisterCallback() to register a user callback. @@ -80,11 +83,13 @@ (++) EwiCallback : callback for Early WakeUp Interrupt. (++) MspInitCallback : WWDG MspInit. + [..] When calling @ref HAL_WWDG_Init function, callbacks are reset to the corresponding legacy weak (surcharged) functions: @ref HAL_WWDG_EarlyWakeupCallback() and HAL_WWDG_MspInit() only if they have not been registered before. + [..] When compilation define USE_HAL_WWDG_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available and weak (surcharged) callbacks are used. @@ -138,8 +143,8 @@ */ /** @defgroup WWDG_Exported_Functions_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions. - * + * @brief Initialization and Configuration functions. + * @verbatim ============================================================================== ##### Initialization and Configuration functions ##### @@ -178,12 +183,12 @@ HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg) #if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1) /* Reset Callback pointers */ - if(hwwdg->EwiCallback == NULL) + if (hwwdg->EwiCallback == NULL) { hwwdg->EwiCallback = HAL_WWDG_EarlyWakeupCallback; } - if(hwwdg->MspInitCallback == NULL) + if (hwwdg->MspInitCallback == NULL) { hwwdg->MspInitCallback = HAL_WWDG_MspInit; } @@ -242,13 +247,13 @@ HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_ { HAL_StatusTypeDef status = HAL_OK; - if(pCallback == NULL) + if (pCallback == NULL) { status = HAL_ERROR; } else { - switch(CallbackID) + switch (CallbackID) { case HAL_WWDG_EWI_CB_ID: hwwdg->EwiCallback = pCallback; @@ -282,7 +287,7 @@ HAL_StatusTypeDef HAL_WWDG_UnRegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWD { HAL_StatusTypeDef status = HAL_OK; - switch(CallbackID) + switch (CallbackID) { case HAL_WWDG_EWI_CB_ID: hwwdg->EwiCallback = HAL_WWDG_EarlyWakeupCallback; @@ -306,8 +311,8 @@ HAL_StatusTypeDef HAL_WWDG_UnRegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWD */ /** @defgroup WWDG_Exported_Functions_Group2 IO operation functions - * @brief IO operation functions - * + * @brief IO operation functions + * @verbatim ============================================================================== ##### IO operation functions ##### diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c index ba55800b00..86f9996ee1 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c @@ -220,9 +220,6 @@ ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStru if (currentpin) { - /* Pin Mode configuration */ - LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode); - if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)) { /* Check Speed mode parameters */ @@ -230,6 +227,12 @@ ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStru /* Speed mode configuration */ LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed); + + /* Check Output mode parameters */ + assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType)); + + /* Output mode configuration*/ + LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType); } /* Pull-up Pull down resistor configuration*/ @@ -250,19 +253,11 @@ ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStru LL_GPIO_SetAFPin_8_15(GPIOx, currentpin, GPIO_InitStruct->Alternate); } } + /* Pin Mode configuration */ + LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode); } pinpos++; } - - if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)) - { - /* Check Output mode parameters */ - assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType)); - - /* Output mode configuration*/ - LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType); - - } return (SUCCESS); } diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_lptim.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_lptim.c index 137335d1ba..63c8a55cff 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_lptim.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_lptim.c @@ -21,18 +21,20 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32f7xx_ll_lptim.h" #include "stm32f7xx_ll_bus.h" +#include "stm32f7xx_ll_rcc.h" + #ifdef USE_FULL_ASSERT - #include "stm32_assert.h" +#include "stm32_assert.h" #else - #define assert_param(expr) ((void)0U) +#define assert_param(expr) ((void)0U) #endif /** @addtogroup STM32F7xx_LL_Driver * @{ */ -#if defined (LPTIM1) || defined (LPTIM2) +#if defined (LPTIM1) /** @addtogroup LPTIM_LL * @{ @@ -46,28 +48,35 @@ * @{ */ #define IS_LL_LPTIM_CLOCK_SOURCE(__VALUE__) (((__VALUE__) == LL_LPTIM_CLK_SOURCE_INTERNAL) \ - || ((__VALUE__) == LL_LPTIM_CLK_SOURCE_EXTERNAL)) + || ((__VALUE__) == LL_LPTIM_CLK_SOURCE_EXTERNAL)) #define IS_LL_LPTIM_CLOCK_PRESCALER(__VALUE__) (((__VALUE__) == LL_LPTIM_PRESCALER_DIV1) \ - || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV2) \ - || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV4) \ - || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV8) \ - || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV16) \ - || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV32) \ - || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV64) \ - || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV128)) + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV2) \ + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV4) \ + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV8) \ + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV16) \ + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV32) \ + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV64) \ + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV128)) #define IS_LL_LPTIM_WAVEFORM(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_PWM) \ - || ((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_SETONCE)) + || ((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_SETONCE)) #define IS_LL_LPTIM_OUTPUT_POLARITY(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_REGULAR) \ - || ((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_INVERSE)) + || ((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_INVERSE)) /** * @} */ /* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/** @defgroup LPTIM_Private_Functions LPTIM Private Functions + * @{ + */ +/** + * @} + */ /* Exported functions --------------------------------------------------------*/ /** @addtogroup LPTIM_LL_Exported_Functions * @{ @@ -84,7 +93,7 @@ * - SUCCESS: LPTIMx registers are de-initialized * - ERROR: invalid LPTIMx instance */ -ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef* LPTIMx) +ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef *LPTIMx) { ErrorStatus result = SUCCESS; @@ -96,13 +105,6 @@ ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef* LPTIMx) LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_LPTIM1); LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_LPTIM1); } -#if defined(LPTIM2) - else if (LPTIMx == LPTIM2) - { - LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_LPTIM2); - LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_LPTIM2); - } -#endif else { result = ERROR; @@ -117,7 +119,7 @@ ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef* LPTIMx) * @param LPTIM_InitStruct pointer to a @ref LL_LPTIM_InitTypeDef structure * @retval None */ -void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef* LPTIM_InitStruct) +void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct) { /* Set the default configuration */ LPTIM_InitStruct->ClockSource = LL_LPTIM_CLK_SOURCE_INTERNAL; @@ -136,39 +138,141 @@ void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef* LPTIM_InitStruct) * - SUCCESS: LPTIMx instance has been initialized * - ERROR: LPTIMx instance hasn't been initialized */ -ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef * LPTIMx, LL_LPTIM_InitTypeDef* LPTIM_InitStruct) +ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, LL_LPTIM_InitTypeDef *LPTIM_InitStruct) { ErrorStatus result = SUCCESS; + /* Check the parameters */ + assert_param(IS_LPTIM_INSTANCE(LPTIMx)); + assert_param(IS_LL_LPTIM_CLOCK_SOURCE(LPTIM_InitStruct->ClockSource)); + assert_param(IS_LL_LPTIM_CLOCK_PRESCALER(LPTIM_InitStruct->Prescaler)); + assert_param(IS_LL_LPTIM_WAVEFORM(LPTIM_InitStruct->Waveform)); + assert_param(IS_LL_LPTIM_OUTPUT_POLARITY(LPTIM_InitStruct->Polarity)); /* The LPTIMx_CFGR register must only be modified when the LPTIM is disabled (ENABLE bit is reset to 0). */ - if (LL_LPTIM_IsEnabled(LPTIMx)) + if (LL_LPTIM_IsEnabled(LPTIMx) == 1UL) { result = ERROR; } else { + /* Set CKSEL bitfield according to ClockSource value */ + /* Set PRESC bitfield according to Prescaler value */ + /* Set WAVE bitfield according to Waveform value */ + /* Set WAVEPOL bitfield according to Polarity value */ + MODIFY_REG(LPTIMx->CFGR, + (LPTIM_CFGR_CKSEL | LPTIM_CFGR_PRESC | LPTIM_CFGR_WAVE | LPTIM_CFGR_WAVPOL), + LPTIM_InitStruct->ClockSource | \ + LPTIM_InitStruct->Prescaler | \ + LPTIM_InitStruct->Waveform | \ + LPTIM_InitStruct->Polarity); + } + + return result; +} + +/** + * @brief Disable the LPTIM instance + * @rmtoll CR ENABLE LL_LPTIM_Disable + * @param LPTIMx Low-Power Timer instance + * @note The following sequence is required to solve LPTIM disable HW limitation. + * Please check Errata Sheet ES0335 for more details under "MCU may remain + * stuck in LPTIM interrupt when entering Stop mode" section. + * @retval None + */ +void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx) +{ + LL_RCC_ClocksTypeDef rcc_clock; + uint32_t tmpclksource = 0; + uint32_t tmpIER; + uint32_t tmpCFGR; + uint32_t tmpCMP; + uint32_t tmpARR; + /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(LPTIMx)); - assert_param(IS_LL_LPTIM_CLOCK_SOURCE(LPTIM_InitStruct->ClockSource)); - assert_param(IS_LL_LPTIM_CLOCK_PRESCALER(LPTIM_InitStruct->Prescaler)); - assert_param(IS_LL_LPTIM_WAVEFORM(LPTIM_InitStruct->Waveform)); - assert_param(IS_LL_LPTIM_OUTPUT_POLARITY(LPTIM_InitStruct->Polarity)); - /* Set CKSEL bitfield according to ClockSource value */ - /* Set PRESC bitfield according to Prescaler value */ - /* Set WAVE bitfield according to Waveform value */ - /* Set WAVEPOL bitfield according to Polarity value */ - MODIFY_REG(LPTIMx->CFGR, - (LPTIM_CFGR_CKSEL | LPTIM_CFGR_PRESC | LPTIM_CFGR_WAVE| LPTIM_CFGR_WAVPOL), - LPTIM_InitStruct->ClockSource | \ - LPTIM_InitStruct->Prescaler | \ - LPTIM_InitStruct->Waveform | \ - LPTIM_InitStruct->Polarity); + __disable_irq(); + + /********** Save LPTIM Config *********/ + /* Save LPTIM source clock */ + switch ((uint32_t)LPTIMx) + { + case LPTIM1_BASE: + tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE); + break; + default: + break; } - return result; + /* Save LPTIM configuration registers */ + tmpIER = LPTIMx->IER; + tmpCFGR = LPTIMx->CFGR; + tmpCMP = LPTIMx->CMP; + tmpARR = LPTIMx->ARR; + + /************* Reset LPTIM ************/ + (void)LL_LPTIM_DeInit(LPTIMx); + + /********* Restore LPTIM Config *******/ + LL_RCC_GetSystemClocksFreq(&rcc_clock); + + if ((tmpCMP != 0UL) || (tmpARR != 0UL)) + { + /* Force LPTIM source kernel clock from APB */ + switch ((uint32_t)LPTIMx) + { + case LPTIM1_BASE: + LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE_PCLK1); + break; + default: + break; + } + + if (tmpCMP != 0UL) + { + /* Restore CMP and ARR registers (LPTIM should be enabled first) */ + LPTIMx->CR |= LPTIM_CR_ENABLE; + LPTIMx->CMP = tmpCMP; + + /* Polling on CMP write ok status after above restore operation */ + do + { + rcc_clock.SYSCLK_Frequency--; /* Used for timeout */ + } + while (((LL_LPTIM_IsActiveFlag_CMPOK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL)); + + LL_LPTIM_ClearFlag_CMPOK(LPTIMx); + } + + if (tmpARR != 0UL) + { + LPTIMx->CR |= LPTIM_CR_ENABLE; + LPTIMx->ARR = tmpARR; + + LL_RCC_GetSystemClocksFreq(&rcc_clock); + /* Polling on ARR write ok status after above restore operation */ + do + { + rcc_clock.SYSCLK_Frequency--; /* Used for timeout */ + } + while (((LL_LPTIM_IsActiveFlag_ARROK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL)); + + LL_LPTIM_ClearFlag_ARROK(LPTIMx); + } + + + /* Restore LPTIM source kernel clock */ + LL_RCC_SetLPTIMClockSource(tmpclksource); + } + + /* Restore configuration registers (LPTIM should be disabled first) */ + LPTIMx->CR &= ~(LPTIM_CR_ENABLE); + LPTIMx->IER = tmpIER; + LPTIMx->CFGR = tmpCFGR; + + __enable_irq(); } /** @@ -183,7 +287,7 @@ ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef * LPTIMx, LL_LPTIM_InitTypeDef* LPTIM_In * @} */ -#endif /* defined (LPTIM1) || defined (LPTIM2) */ +#endif /* LPTIM1 */ /** * @} diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c index 9c03d56572..eb5eff69cf 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c @@ -163,7 +163,7 @@ uint32_t RCC_PLLI2S_GetFreqDomain_SPDIFRX(void); */ ErrorStatus LL_RCC_DeInit(void) { - uint32_t vl_mask = 0xFFFFFFFFU; + __IO uint32_t vl_mask; /* Set HSION bit */ LL_RCC_HSI_Enable(); @@ -175,10 +175,13 @@ ErrorStatus LL_RCC_DeInit(void) /* Reset CFGR register */ LL_RCC_WriteReg(CFGR, 0x00000000U); + /* Read CR register */ + vl_mask = LL_RCC_ReadReg(CR); + /* Reset HSEON, HSEBYP, PLLON, CSSON, PLLI2SON and PLLSAION bits */ CLEAR_BIT(vl_mask, (RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_PLLSAION | RCC_CR_PLLI2SON)); - /* Write new mask in CR register */ + /* Write new value in CR register */ LL_RCC_WriteReg(CR, vl_mask); /* Set HSITRIM bits to the reset value*/ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c index a225e1d25f..46840fff80 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c @@ -15,7 +15,7 @@ ============================================================================== ##### SDMMC peripheral features ##### ============================================================================== - [..] The SD/SDMMC MMC card host interface (SDMMC) provides an interface between the APB2 + [..] The SD/SDMMC MMC card host interface (SDMMC) provides an interface between the AHB peripheral bus and MultiMedia cards (MMCs), SD memory cards, SDMMC cards and CE-ATA devices. @@ -29,8 +29,7 @@ (+) Full support of the CE-ATA features (full compliance with CE-ATA digital protocol Rev1.1) (+) Data transfer up to 48 MHz for the 8 bit mode - (+) Data and command output enable signals to control external bidirectional drivers. - + (+) Data and command output enable signals to control external bidirectional drivers ##### How to use this driver ##### ============================================================================== @@ -44,8 +43,8 @@ functionalities of the external device. [..] - (+) The SDMMC clock (SDMMCCLK = 48 MHz) is coming from a specific output of PLL - (PLL48CLK). Before start working with SDMMC peripheral make sure that the + (+) The SDMMC clock (SDMMCCLK = 48 MHz) is coming from a specific output (MSI, PLLUSB1CLK, + PLLUSB2CLK). Before start working with SDMMC peripheral make sure that the PLL is well configured. The SDMMC peripheral uses two clock signals: (++) SDMMC adapter clock (SDMMCCLK = 48 MHz) @@ -57,13 +56,13 @@ (+) Enable/Disable peripheral clock using RCC peripheral macros related to SDMMC peripheral. - (+) Enable the Power ON State using the SDMMC_PowerState_ON(SDMMCx) - function and disable it using the function SDMMC_PowerState_OFF(SDMMCx). + (+) Enable the Power ON State using the SDMMC_PowerState_ON() + function and disable it using the function SDMMC_PowerState_OFF(). (+) Enable/Disable the clock using the __SDMMC_ENABLE()/__SDMMC_DISABLE() macros. - (+) Enable/Disable the peripheral interrupts using the macros __SDMMC_ENABLE_IT(hSDMMC, IT) - and __SDMMC_DISABLE_IT(hSDMMC, IT) if you need to use interrupt mode. + (+) Enable/Disable the peripheral interrupts using the macros __SDMMC_ENABLE_IT() + and __SDMMC_DISABLE_IT() if you need to use interrupt mode. (+) When using the DMA mode (++) Configure the DMA in the MSP layer of the external device @@ -72,7 +71,7 @@ __SDMMC_DMA_DISABLE(). (+) To control the CPSM (Command Path State Machine) and send - commands to the card use the SDMMC_SendCommand(SDMMCx), + commands to the card use the SDMMC_SendCommand(), SDMMC_GetCommandResponse() and SDMMC_GetResponse() functions. First, user has to fill the command structure (pointer to SDMMC_CmdInitTypeDef) according to the selected command to be sent. @@ -135,7 +134,7 @@ *** Command management operations *** ===================================== [..] - (#) The commands used for Read/Write//Erase operations are managed in + (#) The commands used for Read/Write/Erase operations are managed in separate functions. Each function allows to send the needed command with the related argument, then check the response. @@ -151,7 +150,7 @@ * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ @@ -159,6 +158,8 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32f7xx_hal.h" +#if defined(SDMMC1) + /** @addtogroup STM32F7xx_HAL_Driver * @{ */ @@ -168,7 +169,7 @@ * @{ */ -#if defined (HAL_SD_MODULE_ENABLED) || defined(HAL_MMC_MODULE_ENABLED) +#if defined(HAL_SD_MODULE_ENABLED) || defined(HAL_MMC_MODULE_ENABLED) /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ @@ -204,8 +205,8 @@ static uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_ /** * @brief Initializes the SDMMC according to the specified * parameters in the SDMMC_InitTypeDef and create the associated handle. - * @param SDMMCx Pointer to SDMMC register base - * @param Init SDMMC initialization structure + * @param SDMMCx: Pointer to SDMMC register base + * @param Init: SDMMC initialization structure * @retval HAL status */ HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init) @@ -258,7 +259,7 @@ HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init) /** * @brief Read data (word) from Rx FIFO in blocking mode (polling) - * @param SDMMCx Pointer to SDMMC register base + * @param SDMMCx: Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx) @@ -269,8 +270,8 @@ uint32_t SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx) /** * @brief Write data (word) to Tx FIFO in blocking mode (polling) - * @param SDMMCx Pointer to SDMMC register base - * @param pWriteData pointer to data to write + * @param SDMMCx: Pointer to SDMMC register base + * @param pWriteData: pointer to data to write * @retval HAL status */ HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData) @@ -302,7 +303,7 @@ HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData) /** * @brief Set SDMMC Power state to ON. - * @param SDMMCx Pointer to SDMMC register base + * @param SDMMCx: Pointer to SDMMC register base * @retval HAL status */ HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx) @@ -310,12 +311,16 @@ HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx) /* Set power state to ON */ SDMMCx->POWER = SDMMC_POWER_PWRCTRL; + /* 1ms: required power up waiting time before starting the SD initialization + sequence */ + HAL_Delay(2); + return HAL_OK; } /** * @brief Set SDMMC Power state to OFF. - * @param SDMMCx Pointer to SDMMC register base + * @param SDMMCx: Pointer to SDMMC register base * @retval HAL status */ HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx) @@ -328,7 +333,7 @@ HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx) /** * @brief Get SDMMC Power state. - * @param SDMMCx Pointer to SDMMC register base + * @param SDMMCx: Pointer to SDMMC register base * @retval Power status of the controller. The returned value can be one of the * following values: * - 0x00: Power OFF @@ -343,8 +348,8 @@ uint32_t SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx) /** * @brief Configure the SDMMC command path according to the specified parameters in * SDMMC_CmdInitTypeDef structure and send the command - * @param SDMMCx Pointer to SDMMC register base - * @param Command pointer to a SDMMC_CmdInitTypeDef structure that contains + * @param SDMMCx: Pointer to SDMMC register base + * @param Command: pointer to a SDMMC_CmdInitTypeDef structure that contains * the configuration information for the SDMMC command * @retval HAL status */ @@ -375,7 +380,7 @@ HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef /** * @brief Return the command index of last command for which response received - * @param SDMMCx Pointer to SDMMC register base + * @param SDMMCx: Pointer to SDMMC register base * @retval Command index of the last command response received */ uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx) @@ -386,8 +391,8 @@ uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx) /** * @brief Return the response received from the card for the last command - * @param SDMMCx Pointer to SDMMC register base - * @param Response Specifies the SDMMC response register. + * @param SDMMCx: Pointer to SDMMC register base + * @param Response: Specifies the SDMMC response register. * This parameter can be one of the following values: * @arg SDMMC_RESP1: Response Register 1 * @arg SDMMC_RESP2: Response Register 2 @@ -397,13 +402,13 @@ uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx) */ uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response) { - __IO uint32_t tmp = 0; + uint32_t tmp; /* Check the parameters */ assert_param(IS_SDMMC_RESP(Response)); /* Get the response */ - tmp = (uint32_t)&(SDMMCx->RESP1) + Response; + tmp = (uint32_t)(&(SDMMCx->RESP1)) + Response; return (*(__IO uint32_t *) tmp); } @@ -411,8 +416,8 @@ uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response) /** * @brief Configure the SDMMC data path according to the specified * parameters in the SDMMC_DataInitTypeDef. - * @param SDMMCx Pointer to SDMMC register base - * @param Data pointer to a SDMMC_DataInitTypeDef structure + * @param SDMMCx: Pointer to SDMMC register base + * @param Data : pointer to a SDMMC_DataInitTypeDef structure * that contains the configuration information for the SDMMC data. * @retval HAL status */ @@ -448,7 +453,7 @@ HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef* /** * @brief Returns number of remaining data bytes to be transferred. - * @param SDMMCx Pointer to SDMMC register base + * @param SDMMCx: Pointer to SDMMC register base * @retval Number of remaining data bytes to be transferred */ uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx) @@ -458,7 +463,7 @@ uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx) /** * @brief Get the FIFO data - * @param SDMMCx Pointer to SDMMC register base + * @param SDMMCx: Pointer to SDMMC register base * @retval Data received */ uint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx) @@ -468,8 +473,8 @@ uint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx) /** * @brief Sets one of the two options of inserting read wait interval. - * @param SDMMCx Pointer to SDMMC register base - * @param SDMMC_ReadWaitMode SDMMC Read Wait operation mode. + * @param SDMMCx: Pointer to SDMMC register base + * @param SDMMC_ReadWaitMode: SDMMC Read Wait operation mode. * This parameter can be: * @arg SDMMC_READ_WAIT_MODE_CLK: Read Wait control by stopping SDMMCCLK * @arg SDMMC_READ_WAIT_MODE_DATA2: Read Wait control using SDMMC_DATA2 @@ -507,13 +512,13 @@ HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDM /** * @brief Send the Data Block Lenght command and check the response - * @param SDMMCx Pointer to SDMMC register base + * @param SDMMCx: Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_CmdBlockLength(SDMMC_TypeDef *SDMMCx, uint32_t BlockSize) { SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate = SDMMC_ERROR_NONE; + uint32_t errorstate; /* Set Block Size for Card */ sdmmc_cmdinit.Argument = (uint32_t)BlockSize; @@ -521,7 +526,7 @@ uint32_t SDMMC_CmdBlockLength(SDMMC_TypeDef *SDMMCx, uint32_t BlockSize) sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SET_BLOCKLEN, SDMMC_CMDTIMEOUT); @@ -531,13 +536,13 @@ uint32_t SDMMC_CmdBlockLength(SDMMC_TypeDef *SDMMCx, uint32_t BlockSize) /** * @brief Send the Read Single Block command and check the response - * @param SDMMCx Pointer to SDMMC register base + * @param SDMMCx: Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_CmdReadSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd) { SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate = SDMMC_ERROR_NONE; + uint32_t errorstate; /* Set Block Size for Card */ sdmmc_cmdinit.Argument = (uint32_t)ReadAdd; @@ -545,7 +550,7 @@ uint32_t SDMMC_CmdReadSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd) sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_READ_SINGLE_BLOCK, SDMMC_CMDTIMEOUT); @@ -555,13 +560,13 @@ uint32_t SDMMC_CmdReadSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd) /** * @brief Send the Read Multi Block command and check the response - * @param SDMMCx Pointer to SDMMC register base + * @param SDMMCx: Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_CmdReadMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd) { SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate = SDMMC_ERROR_NONE; + uint32_t errorstate; /* Set Block Size for Card */ sdmmc_cmdinit.Argument = (uint32_t)ReadAdd; @@ -569,7 +574,7 @@ uint32_t SDMMC_CmdReadMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd) sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_READ_MULT_BLOCK, SDMMC_CMDTIMEOUT); @@ -579,13 +584,13 @@ uint32_t SDMMC_CmdReadMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd) /** * @brief Send the Write Single Block command and check the response - * @param SDMMCx Pointer to SDMMC register base + * @param SDMMCx: Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_CmdWriteSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd) { SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate = SDMMC_ERROR_NONE; + uint32_t errorstate; /* Set Block Size for Card */ sdmmc_cmdinit.Argument = (uint32_t)WriteAdd; @@ -593,7 +598,7 @@ uint32_t SDMMC_CmdWriteSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd) sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_WRITE_SINGLE_BLOCK, SDMMC_CMDTIMEOUT); @@ -603,13 +608,13 @@ uint32_t SDMMC_CmdWriteSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd) /** * @brief Send the Write Multi Block command and check the response - * @param SDMMCx Pointer to SDMMC register base + * @param SDMMCx: Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_CmdWriteMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd) { SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate = SDMMC_ERROR_NONE; + uint32_t errorstate; /* Set Block Size for Card */ sdmmc_cmdinit.Argument = (uint32_t)WriteAdd; @@ -617,7 +622,7 @@ uint32_t SDMMC_CmdWriteMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd) sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_WRITE_MULT_BLOCK, SDMMC_CMDTIMEOUT); @@ -627,13 +632,13 @@ uint32_t SDMMC_CmdWriteMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd) /** * @brief Send the Start Address Erase command for SD and check the response - * @param SDMMCx Pointer to SDMMC register base + * @param SDMMCx: Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_CmdSDEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd) { SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate = SDMMC_ERROR_NONE; + uint32_t errorstate; /* Set Block Size for Card */ sdmmc_cmdinit.Argument = (uint32_t)StartAdd; @@ -641,7 +646,7 @@ uint32_t SDMMC_CmdSDEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd) sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_ERASE_GRP_START, SDMMC_CMDTIMEOUT); @@ -651,13 +656,13 @@ uint32_t SDMMC_CmdSDEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd) /** * @brief Send the End Address Erase command for SD and check the response - * @param SDMMCx Pointer to SDMMC register base + * @param SDMMCx: Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_CmdSDEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd) { SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate = SDMMC_ERROR_NONE; + uint32_t errorstate; /* Set Block Size for Card */ sdmmc_cmdinit.Argument = (uint32_t)EndAdd; @@ -665,7 +670,7 @@ uint32_t SDMMC_CmdSDEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd) sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_ERASE_GRP_END, SDMMC_CMDTIMEOUT); @@ -675,13 +680,13 @@ uint32_t SDMMC_CmdSDEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd) /** * @brief Send the Start Address Erase command and check the response - * @param SDMMCx Pointer to SDMMC register base + * @param SDMMCx: Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_CmdEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd) { SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate = SDMMC_ERROR_NONE; + uint32_t errorstate; /* Set Block Size for Card */ sdmmc_cmdinit.Argument = (uint32_t)StartAdd; @@ -689,7 +694,7 @@ uint32_t SDMMC_CmdEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd) sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_ERASE_GRP_START, SDMMC_CMDTIMEOUT); @@ -699,13 +704,13 @@ uint32_t SDMMC_CmdEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd) /** * @brief Send the End Address Erase command and check the response - * @param SDMMCx Pointer to SDMMC register base + * @param SDMMCx: Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_CmdEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd) { SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate = SDMMC_ERROR_NONE; + uint32_t errorstate; /* Set Block Size for Card */ sdmmc_cmdinit.Argument = (uint32_t)EndAdd; @@ -713,7 +718,7 @@ uint32_t SDMMC_CmdEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd) sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_ERASE_GRP_END, SDMMC_CMDTIMEOUT); @@ -723,21 +728,21 @@ uint32_t SDMMC_CmdEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd) /** * @brief Send the Erase command and check the response - * @param SDMMCx Pointer to SDMMC register base + * @param SDMMCx: Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_CmdErase(SDMMC_TypeDef *SDMMCx) { SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate = SDMMC_ERROR_NONE; + uint32_t errorstate; /* Set Block Size for Card */ - sdmmc_cmdinit.Argument = 0; + sdmmc_cmdinit.Argument = 0U; sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ERASE; sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_ERASE, SDMMC_MAXERASETIMEOUT); @@ -747,38 +752,38 @@ uint32_t SDMMC_CmdErase(SDMMC_TypeDef *SDMMCx) /** * @brief Send the Stop Transfer command and check the response. - * @param SDMMCx Pointer to SDMMC register base + * @param SDMMCx: Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_CmdStopTransfer(SDMMC_TypeDef *SDMMCx) { SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate = SDMMC_ERROR_NONE; + uint32_t errorstate; /* Send CMD12 STOP_TRANSMISSION */ - sdmmc_cmdinit.Argument = 0; + sdmmc_cmdinit.Argument = 0U; sdmmc_cmdinit.CmdIndex = SDMMC_CMD_STOP_TRANSMISSION; sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); /* Check for error conditions */ - errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_STOP_TRANSMISSION, 100000000/*SDMMC_CMDTIMEOUT*/); + errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_STOP_TRANSMISSION, SDMMC_STOPTRANSFERTIMEOUT); return errorstate; } /** * @brief Send the Select Deselect command and check the response. - * @param SDMMCx Pointer to SDMMC register base - * @param addr Address of the card to be selected + * @param SDMMCx: Pointer to SDMMC register base + * @param addr: Address of the card to be selected * @retval HAL status */ uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint64_t Addr) { SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate = SDMMC_ERROR_NONE; + uint32_t errorstate; /* Send CMD7 SDMMC_SEL_DESEL_CARD */ sdmmc_cmdinit.Argument = (uint32_t)Addr; @@ -786,7 +791,7 @@ uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint64_t Addr) sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SEL_DESEL_CARD, SDMMC_CMDTIMEOUT); @@ -796,20 +801,20 @@ uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint64_t Addr) /** * @brief Send the Go Idle State command and check the response. - * @param SDMMCx Pointer to SDMMC register base + * @param SDMMCx: Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_CmdGoIdleState(SDMMC_TypeDef *SDMMCx) { SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate = SDMMC_ERROR_NONE; + uint32_t errorstate; - sdmmc_cmdinit.Argument = 0; + sdmmc_cmdinit.Argument = 0U; sdmmc_cmdinit.CmdIndex = SDMMC_CMD_GO_IDLE_STATE; sdmmc_cmdinit.Response = SDMMC_RESPONSE_NO; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); /* Check for error conditions */ errorstate = SDMMC_GetCmdError(SDMMCx); @@ -819,13 +824,13 @@ uint32_t SDMMC_CmdGoIdleState(SDMMC_TypeDef *SDMMCx) /** * @brief Send the Operating Condition command and check the response. - * @param SDMMCx Pointer to SDMMC register base + * @param SDMMCx: Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_CmdOperCond(SDMMC_TypeDef *SDMMCx) { SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate = SDMMC_ERROR_NONE; + uint32_t errorstate; /* Send CMD8 to verify SD card interface operating condition */ /* Argument: - [31:12]: Reserved (shall be set to '0') @@ -837,7 +842,7 @@ uint32_t SDMMC_CmdOperCond(SDMMC_TypeDef *SDMMCx) sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); /* Check for error conditions */ errorstate = SDMMC_GetCmdResp7(SDMMCx); @@ -849,20 +854,21 @@ uint32_t SDMMC_CmdOperCond(SDMMC_TypeDef *SDMMCx) * @brief Send the Application command to verify that that the next command * is an application specific com-mand rather than a standard command * and check the response. - * @param SDMMCx Pointer to SDMMC register base + * @param SDMMCx: Pointer to SDMMC register base + * @param Argument: Command Argument * @retval HAL status */ uint32_t SDMMC_CmdAppCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument) { SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate = SDMMC_ERROR_NONE; + uint32_t errorstate; sdmmc_cmdinit.Argument = (uint32_t)Argument; sdmmc_cmdinit.CmdIndex = SDMMC_CMD_APP_CMD; sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); /* Check for error conditions */ /* If there is a HAL_ERROR, it is a MMC card, else @@ -876,20 +882,21 @@ uint32_t SDMMC_CmdAppCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument) /** * @brief Send the command asking the accessed card to send its operating * condition register (OCR) - * @param SDMMCx Pointer to SDMMC register base + * @param SDMMCx: Pointer to SDMMC register base + * @param Argument: Command Argument * @retval HAL status */ -uint32_t SDMMC_CmdAppOperCommand(SDMMC_TypeDef *SDMMCx, uint32_t SdType) +uint32_t SDMMC_CmdAppOperCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument) { SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate = SDMMC_ERROR_NONE; + uint32_t errorstate; - sdmmc_cmdinit.Argument = SDMMC_VOLTAGE_WINDOW_SD | SdType; + sdmmc_cmdinit.Argument = SDMMC_VOLTAGE_WINDOW_SD | Argument; sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_OP_COND; sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); /* Check for error conditions */ errorstate = SDMMC_GetCmdResp3(SDMMCx); @@ -899,20 +906,21 @@ uint32_t SDMMC_CmdAppOperCommand(SDMMC_TypeDef *SDMMCx, uint32_t SdType) /** * @brief Send the Bus Width command and check the response. - * @param SDMMCx Pointer to SDMMC register base + * @param SDMMCx: Pointer to SDMMC register base + * @param BusWidth: BusWidth * @retval HAL status */ uint32_t SDMMC_CmdBusWidth(SDMMC_TypeDef *SDMMCx, uint32_t BusWidth) { SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate = SDMMC_ERROR_NONE; + uint32_t errorstate; sdmmc_cmdinit.Argument = (uint32_t)BusWidth; sdmmc_cmdinit.CmdIndex = SDMMC_CMD_APP_SD_SET_BUSWIDTH; sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_APP_SD_SET_BUSWIDTH, SDMMC_CMDTIMEOUT); @@ -922,21 +930,21 @@ uint32_t SDMMC_CmdBusWidth(SDMMC_TypeDef *SDMMCx, uint32_t BusWidth) /** * @brief Send the Send SCR command and check the response. - * @param SDMMCx Pointer to SDMMC register base + * @param SDMMCx: Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_CmdSendSCR(SDMMC_TypeDef *SDMMCx) { SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate = SDMMC_ERROR_NONE; + uint32_t errorstate; /* Send CMD51 SD_APP_SEND_SCR */ - sdmmc_cmdinit.Argument = 0; + sdmmc_cmdinit.Argument = 0U; sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_SEND_SCR; sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_APP_SEND_SCR, SDMMC_CMDTIMEOUT); @@ -946,21 +954,21 @@ uint32_t SDMMC_CmdSendSCR(SDMMC_TypeDef *SDMMCx) /** * @brief Send the Send CID command and check the response. - * @param SDMMCx Pointer to SDMMC register base + * @param SDMMCx: Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_CmdSendCID(SDMMC_TypeDef *SDMMCx) { SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate = SDMMC_ERROR_NONE; + uint32_t errorstate; /* Send CMD2 ALL_SEND_CID */ - sdmmc_cmdinit.Argument = 0; + sdmmc_cmdinit.Argument = 0U; sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ALL_SEND_CID; sdmmc_cmdinit.Response = SDMMC_RESPONSE_LONG; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); /* Check for error conditions */ errorstate = SDMMC_GetCmdResp2(SDMMCx); @@ -970,21 +978,22 @@ uint32_t SDMMC_CmdSendCID(SDMMC_TypeDef *SDMMCx) /** * @brief Send the Send CSD command and check the response. - * @param SDMMCx Pointer to SDMMC register base + * @param SDMMCx: Pointer to SDMMC register base + * @param Argument: Command Argument * @retval HAL status */ uint32_t SDMMC_CmdSendCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument) { SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate = SDMMC_ERROR_NONE; + uint32_t errorstate; /* Send CMD9 SEND_CSD */ - sdmmc_cmdinit.Argument = (uint32_t)Argument; + sdmmc_cmdinit.Argument = Argument; sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEND_CSD; sdmmc_cmdinit.Response = SDMMC_RESPONSE_LONG; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); /* Check for error conditions */ errorstate = SDMMC_GetCmdResp2(SDMMCx); @@ -994,21 +1003,22 @@ uint32_t SDMMC_CmdSendCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument) /** * @brief Send the Send CSD command and check the response. - * @param SDMMCx Pointer to SDMMC register base + * @param SDMMCx: Pointer to SDMMC register base + * @param pRCA: Card RCA * @retval HAL status */ uint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef *SDMMCx, uint16_t *pRCA) { SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate = SDMMC_ERROR_NONE; + uint32_t errorstate; /* Send CMD3 SD_CMD_SET_REL_ADDR */ - sdmmc_cmdinit.Argument = 0; + sdmmc_cmdinit.Argument = 0U; sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SET_REL_ADDR; sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); /* Check for error conditions */ errorstate = SDMMC_GetCmdResp6(SDMMCx, SDMMC_CMD_SET_REL_ADDR, pRCA); @@ -1018,20 +1028,21 @@ uint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef *SDMMCx, uint16_t *pRCA) /** * @brief Send the Status command and check the response. - * @param SDMMCx Pointer to SDMMC register base + * @param SDMMCx: Pointer to SDMMC register base + * @param Argument: Command Argument * @retval HAL status */ uint32_t SDMMC_CmdSendStatus(SDMMC_TypeDef *SDMMCx, uint32_t Argument) { SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate = SDMMC_ERROR_NONE; + uint32_t errorstate; - sdmmc_cmdinit.Argument = (uint32_t)Argument; + sdmmc_cmdinit.Argument = Argument; sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEND_STATUS; sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SEND_STATUS, SDMMC_CMDTIMEOUT); @@ -1041,20 +1052,20 @@ uint32_t SDMMC_CmdSendStatus(SDMMC_TypeDef *SDMMCx, uint32_t Argument) /** * @brief Send the Status register command and check the response. - * @param SDMMCx Pointer to SDMMC register base + * @param SDMMCx: Pointer to SDMMC register base * @retval HAL status */ uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx) { SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate = SDMMC_ERROR_NONE; + uint32_t errorstate; - sdmmc_cmdinit.Argument = 0; + sdmmc_cmdinit.Argument = 0U; sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_STATUS; sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_APP_STATUS, SDMMC_CMDTIMEOUT); @@ -1065,21 +1076,21 @@ uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx) /** * @brief Sends host capacity support information and activates the card's * initialization process. Send SDMMC_CMD_SEND_OP_COND command - * @param SDIOx Pointer to SDIO register base - * @parame Argument Argument used for the command + * @param SDMMCx: Pointer to SDMMC register base + * @parame Argument: Argument used for the command * @retval HAL status */ uint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument) { SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate = SDMMC_ERROR_NONE; + uint32_t errorstate; sdmmc_cmdinit.Argument = Argument; sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEND_OP_COND; sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); /* Check for error conditions */ errorstate = SDMMC_GetCmdResp3(SDMMCx); @@ -1089,21 +1100,23 @@ uint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument) /** * @brief Checks switchable function and switch card function. SDMMC_CMD_HS_SWITCH comand - * @param SDIOx Pointer to SDIO register base - * @parame Argument Argument used for the command + * @param SDMMCx: Pointer to SDMMC register base + * @parame Argument: Argument used for the command * @retval HAL status */ uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument) { SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate = SDMMC_ERROR_NONE; + uint32_t errorstate; - sdmmc_cmdinit.Argument = Argument; + /* Send CMD6 to activate SDR50 Mode and Power Limit 1.44W */ + /* CMD Response: R1 */ + sdmmc_cmdinit.Argument = Argument; /* SDMMC_SDR25_SWITCH_PATTERN */ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_HS_SWITCH; sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); /* Check for error conditions */ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_HS_SWITCH, SDMMC_CMDTIMEOUT); @@ -1122,18 +1135,18 @@ uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument) /** * @brief Checks for error conditions for CMD0. - * @param hsd SD handle + * @param hsd: SD handle * @retval SD Card error state */ static uint32_t SDMMC_GetCmdError(SDMMC_TypeDef *SDMMCx) { /* 8 is the number of required instructions cycles for the below loop statement. The SDMMC_CMDTIMEOUT is expressed in ms */ - register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8 /1000); + register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); do { - if (count-- == 0) + if (count-- == 0U) { return SDMMC_ERROR_TIMEOUT; } @@ -1141,33 +1154,35 @@ static uint32_t SDMMC_GetCmdError(SDMMC_TypeDef *SDMMCx) }while(!__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CMDSENT)); /* Clear all the static flags */ - __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_FLAGS); + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS); return SDMMC_ERROR_NONE; } /** * @brief Checks for error conditions for R1 response. - * @param hsd SD handle - * @param SD_CMD The sent command index + * @param hsd: SD handle + * @param SD_CMD: The sent command index * @retval SD Card error state */ static uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_t Timeout) { uint32_t response_r1; + uint32_t sta_reg; /* 8 is the number of required instructions cycles for the below loop statement. The Timeout is expressed in ms */ - register uint32_t count = Timeout * (SystemCoreClock / 8 /1000); + register uint32_t count = Timeout * (SystemCoreClock / 8U /1000U); do { - if (count-- == 0) + if (count-- == 0U) { return SDMMC_ERROR_TIMEOUT; } - - }while(!__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)); + sta_reg = SDMMCx->STA; + }while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) || + ((sta_reg & SDMMC_FLAG_CMDACT) != 0U )); if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT)) { @@ -1181,6 +1196,13 @@ static uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_ return SDMMC_ERROR_CMD_CRC_FAIL; } + else + { + /* Nothing to do */ + } + + /* Clear all the static flags */ + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS); /* Check response received is of desired command */ if(SDMMC_GetCommandResponse(SDMMCx) != SD_CMD) @@ -1188,9 +1210,6 @@ static uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_ return SDMMC_ERROR_CMD_CRC_FAIL; } - /* Clear all the static flags */ - __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_FLAGS); - /* We have received response, retrieve it for analysis */ response_r1 = SDMMC_GetResponse(SDMMCx, SDMMC_RESP1); @@ -1278,23 +1297,25 @@ static uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_ /** * @brief Checks for error conditions for R2 (CID or CSD) response. - * @param hsd SD handle + * @param hsd: SD handle * @retval SD Card error state */ static uint32_t SDMMC_GetCmdResp2(SDMMC_TypeDef *SDMMCx) { + uint32_t sta_reg; /* 8 is the number of required instructions cycles for the below loop statement. The SDMMC_CMDTIMEOUT is expressed in ms */ - register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8 /1000); + register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); do { - if (count-- == 0) + if (count-- == 0U) { return SDMMC_ERROR_TIMEOUT; } - - }while(!__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)); + sta_reg = SDMMCx->STA; + }while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) || + ((sta_reg & SDMMC_FLAG_CMDACT) != 0U )); if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT)) { @@ -1312,7 +1333,7 @@ static uint32_t SDMMC_GetCmdResp2(SDMMC_TypeDef *SDMMCx) { /* No error flag set */ /* Clear all the static flags */ - __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_FLAGS); + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS); } return SDMMC_ERROR_NONE; @@ -1320,23 +1341,25 @@ static uint32_t SDMMC_GetCmdResp2(SDMMC_TypeDef *SDMMCx) /** * @brief Checks for error conditions for R3 (OCR) response. - * @param hsd SD handle + * @param hsd: SD handle * @retval SD Card error state */ static uint32_t SDMMC_GetCmdResp3(SDMMC_TypeDef *SDMMCx) { + uint32_t sta_reg; /* 8 is the number of required instructions cycles for the below loop statement. The SDMMC_CMDTIMEOUT is expressed in ms */ - register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8 /1000); + register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); do { - if (count-- == 0) + if (count-- == 0U) { return SDMMC_ERROR_TIMEOUT; } - - }while(!__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)); + sta_reg = SDMMCx->STA; + }while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) || + ((sta_reg & SDMMC_FLAG_CMDACT) != 0U )); if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT)) { @@ -1345,10 +1368,9 @@ static uint32_t SDMMC_GetCmdResp3(SDMMC_TypeDef *SDMMCx) return SDMMC_ERROR_CMD_RSP_TIMEOUT; } else - { /* Clear all the static flags */ - __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_FLAGS); + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS); } return SDMMC_ERROR_NONE; @@ -1356,28 +1378,30 @@ static uint32_t SDMMC_GetCmdResp3(SDMMC_TypeDef *SDMMCx) /** * @brief Checks for error conditions for R6 (RCA) response. - * @param hsd SD handle - * @param SD_CMD The sent command index - * @param pRCA Pointer to the variable that will contain the SD card relative + * @param hsd: SD handle + * @param SD_CMD: The sent command index + * @param pRCA: Pointer to the variable that will contain the SD card relative * address RCA * @retval SD Card error state */ static uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_t *pRCA) { uint32_t response_r1; + uint32_t sta_reg; /* 8 is the number of required instructions cycles for the below loop statement. The SDMMC_CMDTIMEOUT is expressed in ms */ - register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8 /1000); + register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); do { - if (count-- == 0) + if (count-- == 0U) { return SDMMC_ERROR_TIMEOUT; } - - }while(!__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)); + sta_reg = SDMMCx->STA; + }while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) || + ((sta_reg & SDMMC_FLAG_CMDACT) != 0U )); if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT)) { @@ -1391,6 +1415,10 @@ static uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_ return SDMMC_ERROR_CMD_CRC_FAIL; } + else + { + /* Nothing to do */ + } /* Check response received is of desired command */ if(SDMMC_GetCommandResponse(SDMMCx) != SD_CMD) @@ -1399,7 +1427,7 @@ static uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_ } /* Clear all the static flags */ - __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_FLAGS); + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS); /* We have received response, retrieve it. */ response_r1 = SDMMC_GetResponse(SDMMCx, SDMMC_RESP1); @@ -1426,31 +1454,44 @@ static uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_ /** * @brief Checks for error conditions for R7 response. - * @param hsd SD handle + * @param hsd: SD handle * @retval SD Card error state */ static uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx) { + uint32_t sta_reg; /* 8 is the number of required instructions cycles for the below loop statement. The SDMMC_CMDTIMEOUT is expressed in ms */ - register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8 /1000); + register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); do { - if (count-- == 0) + if (count-- == 0U) { return SDMMC_ERROR_TIMEOUT; } - - }while(!__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)); + sta_reg = SDMMCx->STA; + }while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) || + ((sta_reg & SDMMC_FLAG_CMDACT) != 0U )); if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT)) { /* Card is SD V2.0 compliant */ - __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CMDREND); + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT); return SDMMC_ERROR_CMD_RSP_TIMEOUT; } + else if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL)) + { + /* Card is SD V2.0 compliant */ + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL); + + return SDMMC_ERROR_CMD_CRC_FAIL; + } + else + { + /* Nothing to do */ + } if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CMDREND)) { @@ -1466,17 +1507,15 @@ static uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx) * @} */ +#endif /* HAL_SD_MODULE_ENABLED || HAL_MMC_MODULE_ENABLED */ /** * @} */ -#endif /* (HAL_SD_MODULE_ENABLED) */ /** * @} */ -/** - * @} - */ +#endif /* SDMMC1 */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c index 8bd622a660..d3a992d33f 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c @@ -26,7 +26,7 @@ #include "stm32_assert.h" #else #define assert_param(expr) ((void)0U) -#endif +#endif /* USE_FULL_ASSERT */ /** @addtogroup STM32F7xx_LL_Driver * @{ @@ -46,135 +46,135 @@ * @{ */ #define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \ - || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \ - || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \ - || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \ - || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN)) + || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \ + || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \ + || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \ + || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN)) #define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \ - || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \ - || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4)) + || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \ + || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4)) #define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \ - || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \ - || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \ - || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \ - || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \ - || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \ - || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \ - || ((__VALUE__) == LL_TIM_OCMODE_PWM2) \ - || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM1) \ - || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \ - || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \ - || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \ - || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM1) \ - || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM2)) + || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \ + || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \ + || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \ + || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \ + || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \ + || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \ + || ((__VALUE__) == LL_TIM_OCMODE_PWM2) \ + || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM1) \ + || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \ + || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \ + || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \ + || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM1) \ + || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM2)) #define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \ - || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE)) + || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE)) #define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \ - || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW)) + || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW)) #define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \ - || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH)) + || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH)) #define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \ - || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \ - || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC)) + || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \ + || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC)) #define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \ - || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \ - || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \ - || ((__VALUE__) == LL_TIM_ICPSC_DIV8)) + || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \ + || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \ + || ((__VALUE__) == LL_TIM_ICPSC_DIV8)) #define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8)) + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8)) #define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \ - || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \ - || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE)) + || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \ + || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE)) #define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \ - || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \ - || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12)) + || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \ + || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12)) #define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \ - || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING)) + || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING)) #define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \ - || ((__VALUE__) == LL_TIM_OSSR_ENABLE)) + || ((__VALUE__) == LL_TIM_OSSR_ENABLE)) #define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \ - || ((__VALUE__) == LL_TIM_OSSI_ENABLE)) + || ((__VALUE__) == LL_TIM_OSSI_ENABLE)) #define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \ - || ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \ - || ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \ - || ((__VALUE__) == LL_TIM_LOCKLEVEL_3)) + || ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \ + || ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \ + || ((__VALUE__) == LL_TIM_LOCKLEVEL_3)) #define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \ - || ((__VALUE__) == LL_TIM_BREAK_ENABLE)) + || ((__VALUE__) == LL_TIM_BREAK_ENABLE)) #define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \ - || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH)) + || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH)) #define IS_LL_TIM_BREAK_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1) \ - || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N2) \ - || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N4) \ - || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N8) \ - || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N6) \ - || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N8) \ - || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N6) \ - || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N8) \ - || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N6) \ - || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N8) \ - || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N5) \ - || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N6) \ - || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N8) \ - || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N5) \ - || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N6) \ - || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N8)) + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N2) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N4) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N8) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N6) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N8) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N6) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N8) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N6) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N8) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N5) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N6) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N8) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N5) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N6) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N8)) #define IS_LL_TIM_BREAK2_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_DISABLE) \ - || ((__VALUE__) == LL_TIM_BREAK2_ENABLE)) + || ((__VALUE__) == LL_TIM_BREAK2_ENABLE)) #define IS_LL_TIM_BREAK2_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_POLARITY_LOW) \ - || ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH)) + || ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH)) #define IS_LL_TIM_BREAK2_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8)) + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8)) #define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \ - || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE)) + || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE)) /** * @} */ @@ -336,7 +336,7 @@ void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct) TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP; TIM_InitStruct->Autoreload = 0xFFFFFFFFU; TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; - TIM_InitStruct->RepetitionCounter = (uint8_t)0x00; + TIM_InitStruct->RepetitionCounter = 0x00000000U; } /** @@ -728,9 +728,9 @@ void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct) * and DTG[7:0] can be write-locked depending on the LOCK configuration, it * can be necessary to configure all of them during the first write access to * the TIMx_BDTR register. - * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a break input. - * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a second break input. * @param TIMx Timer Instance * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure) @@ -795,7 +795,7 @@ ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDT */ /** @addtogroup TIM_LL_Private_Functions TIM Private Functions - * @brief Private functions + * @brief Private functions * @{ */ /** diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c index 028c704918..d7f367518e 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c @@ -22,11 +22,11 @@ #include "stm32f7xx_ll_usart.h" #include "stm32f7xx_ll_rcc.h" #include "stm32f7xx_ll_bus.h" -#ifdef USE_FULL_ASSERT +#ifdef USE_FULL_ASSERT #include "stm32_assert.h" #else #define assert_param(expr) ((void)0U) -#endif +#endif /* USE_FULL_ASSERT */ /** @addtogroup STM32F7xx_LL_Driver * @{ @@ -41,14 +41,6 @@ /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ -/** @addtogroup USART_LL_Private_Constants - * @{ - */ - -/** - * @} - */ - /* Private macros ------------------------------------------------------------*/ /** @addtogroup USART_LL_Private_Macros * @{ @@ -65,42 +57,42 @@ #define IS_LL_USART_BRR_MAX(__VALUE__) ((__VALUE__) <= 0x0000FFFFU) #define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \ - || ((__VALUE__) == LL_USART_DIRECTION_RX) \ - || ((__VALUE__) == LL_USART_DIRECTION_TX) \ - || ((__VALUE__) == LL_USART_DIRECTION_TX_RX)) + || ((__VALUE__) == LL_USART_DIRECTION_RX) \ + || ((__VALUE__) == LL_USART_DIRECTION_TX) \ + || ((__VALUE__) == LL_USART_DIRECTION_TX_RX)) #define IS_LL_USART_PARITY(__VALUE__) (((__VALUE__) == LL_USART_PARITY_NONE) \ - || ((__VALUE__) == LL_USART_PARITY_EVEN) \ - || ((__VALUE__) == LL_USART_PARITY_ODD)) + || ((__VALUE__) == LL_USART_PARITY_EVEN) \ + || ((__VALUE__) == LL_USART_PARITY_ODD)) #define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_7B) \ - || ((__VALUE__) == LL_USART_DATAWIDTH_8B) \ - || ((__VALUE__) == LL_USART_DATAWIDTH_9B)) + || ((__VALUE__) == LL_USART_DATAWIDTH_8B) \ + || ((__VALUE__) == LL_USART_DATAWIDTH_9B)) #define IS_LL_USART_OVERSAMPLING(__VALUE__) (((__VALUE__) == LL_USART_OVERSAMPLING_16) \ - || ((__VALUE__) == LL_USART_OVERSAMPLING_8)) + || ((__VALUE__) == LL_USART_OVERSAMPLING_8)) #define IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \ - || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT)) + || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT)) #define IS_LL_USART_CLOCKPHASE(__VALUE__) (((__VALUE__) == LL_USART_PHASE_1EDGE) \ - || ((__VALUE__) == LL_USART_PHASE_2EDGE)) + || ((__VALUE__) == LL_USART_PHASE_2EDGE)) #define IS_LL_USART_CLOCKPOLARITY(__VALUE__) (((__VALUE__) == LL_USART_POLARITY_LOW) \ - || ((__VALUE__) == LL_USART_POLARITY_HIGH)) + || ((__VALUE__) == LL_USART_POLARITY_HIGH)) #define IS_LL_USART_CLOCKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_CLOCK_DISABLE) \ - || ((__VALUE__) == LL_USART_CLOCK_ENABLE)) + || ((__VALUE__) == LL_USART_CLOCK_ENABLE)) #define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_0_5) \ - || ((__VALUE__) == LL_USART_STOPBITS_1) \ - || ((__VALUE__) == LL_USART_STOPBITS_1_5) \ - || ((__VALUE__) == LL_USART_STOPBITS_2)) + || ((__VALUE__) == LL_USART_STOPBITS_1) \ + || ((__VALUE__) == LL_USART_STOPBITS_1_5) \ + || ((__VALUE__) == LL_USART_STOPBITS_2)) #define IS_LL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_USART_HWCONTROL_NONE) \ - || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \ - || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \ - || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS)) + || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \ + || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \ + || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS)) /** * @} diff --git a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usb.c b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usb.c index b6659ae1e2..cb59bad1a7 100644 --- a/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usb.c +++ b/system/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usb.c @@ -94,6 +94,11 @@ HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c /* Init The ULPI Interface */ USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL); +#if defined(STM32F722xx) || defined(STM32F723xx) || defined(STM32F730xx) || defined(STM32F732xx) || defined(STM32F733xx) + /* Select ULPI Interface */ + USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPI_UTMI_SEL; +#endif /* defined(STM32F722xx) || defined(STM32F723xx) || defined(STM32F730xx) || defined(STM32F732xx) || defined(STM32F733xx) */ + /* Select vbus source */ USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI); if (cfg.use_external_vbus == 1U) @@ -115,7 +120,7 @@ HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI); /* Select UTMI Interace */ - USBx->GUSBCFG &= ~ USB_OTG_GUSBCFG_ULPI_UTMI_SEL; + USBx->GUSBCFG &= ~USB_OTG_GUSBCFG_ULPI_UTMI_SEL; USBx->GCCFG |= USB_OTG_GCCFG_PHYHSEN; /* Enables control of a High Speed USB PHY */ @@ -169,7 +174,7 @@ HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx, used by application. In the low AHB frequency range it is used to stretch enough the USB response time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access latency to the Data FIFO */ - if (speed == USB_OTG_SPEED_FULL) + if (speed == USBD_FS_SPEED) { if ((hclk >= 14200000U) && (hclk < 15000000U)) { @@ -222,7 +227,7 @@ HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx, UsbTrd = 0x6U; } } - else if (speed == USB_OTG_SPEED_HIGH) + else if (speed == USBD_HS_SPEED) { UsbTrd = USBD_HS_TRDT_VALUE; } @@ -314,6 +319,8 @@ HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cf /* VBUS Sensing setup */ if (cfg.vbus_sensing_enable == 0U) { + USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS; + /* Deactivate VBUS Sensing B */ USBx->GCCFG &= ~USB_OTG_GCCFG_VBDEN; @@ -335,33 +342,33 @@ HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cf if (cfg.phy_itface == USB_OTG_ULPI_PHY) { - if (cfg.speed == USB_OTG_SPEED_HIGH) + if (cfg.speed == USBD_HS_SPEED) { - /* Set High speed phy */ + /* Set Core speed to High speed mode */ (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH); } else { - /* set High speed phy in Full speed mode */ + /* Set Core speed to Full speed mode */ (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH_IN_FULL); } } else if (cfg.phy_itface == USB_OTG_HS_EMBEDDED_PHY) { - if (cfg.speed == USB_OTG_SPEED_HIGH) + if (cfg.speed == USBD_HS_SPEED) { - /* Set High speed phy */ + /* Set Core speed to High speed mode */ (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH); } else { - /* set High speed phy in Full speed mode */ + /* Set Core speed to Full speed mode */ (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH_IN_FULL); } } else { - /* Set Full speed phy */ + /* Set Core speed to Full speed mode */ (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_FULL); } @@ -427,17 +434,6 @@ HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cf USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM); - if (cfg.dma_enable == 1U) - { - /*Set threshold parameters */ - USBx_DEVICE->DTHRCTL = USB_OTG_DTHRCTL_TXTHRLEN_6 | - USB_OTG_DTHRCTL_RXTHRLEN_6; - - USBx_DEVICE->DTHRCTL |= USB_OTG_DTHRCTL_RXTHREN | - USB_OTG_DTHRCTL_ISOTHREN | - USB_OTG_DTHRCTL_NONISOTHREN; - } - /* Disable all interrupts. */ USBx->GINTMSK = 0U; @@ -542,8 +538,8 @@ HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed) * @param USBx Selected device * @retval speed device speed * This parameter can be one of these values: - * @arg USB_OTG_SPEED_HIGH: High speed mode - * @arg USB_OTG_SPEED_FULL: Full speed mode + * @arg PCD_SPEED_HIGH: High speed mode + * @arg PCD_SPEED_FULL: Full speed mode */ uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx) { @@ -553,16 +549,16 @@ uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx) if (DevEnumSpeed == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ) { - speed = USB_OTG_SPEED_HIGH; + speed = USBD_HS_SPEED; } else if ((DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ) || (DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_48MHZ)) { - speed = USB_OTG_SPEED_FULL; + speed = USBD_FS_SPEED; } else { - speed = 0U; + speed = 0xFU; } return speed; @@ -659,6 +655,12 @@ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EP /* Read DEPCTLn register */ if (ep->is_in == 1U) { + if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) + { + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK; + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_EPDIS; + } + USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_USBAEP | @@ -669,6 +671,12 @@ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EP } else { + if ((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) + { + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK; + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_EPDIS; + } + USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16)); USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16)); USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_USBAEP | @@ -694,11 +702,23 @@ HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, U /* Read DEPCTLn register */ if (ep->is_in == 1U) { + if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) + { + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK; + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_EPDIS; + } + USBx_INEP(epnum)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP; USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); } else { + if ((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) + { + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK; + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_EPDIS; + } + USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP; USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16)); } @@ -757,9 +777,27 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef { USBx_INEP(epnum)->DIEPDMA = (uint32_t)(ep->dma_addr); } + + if (ep->type == EP_TYPE_ISOC) + { + if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) + { + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM; + } + else + { + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; + } + } + + /* EP enable, IN data in FIFO */ + USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); } else { + /* EP enable, IN data in FIFO */ + USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); + if (ep->type != EP_TYPE_ISOC) { /* Enable the Tx FIFO Empty Interrupt for this EP */ @@ -768,26 +806,19 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK); } } - } - - if (ep->type == EP_TYPE_ISOC) - { - if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) - { - USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM; - } else { - USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; - } - } - - /* EP enable, IN data in FIFO */ - USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); + if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) + { + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM; + } + else + { + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; + } - if (ep->type == EP_TYPE_ISOC) - { - (void)USB_WritePacket(USBx, ep->xfer_buff, ep->num, (uint16_t)ep->xfer_len, dma); + (void)USB_WritePacket(USBx, ep->xfer_buff, ep->num, (uint16_t)ep->xfer_len, dma); + } } } else /* OUT endpoint */ @@ -886,18 +917,21 @@ HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDe { USBx_INEP(epnum)->DIEPDMA = (uint32_t)(ep->dma_addr); } + + /* EP enable, IN data in FIFO */ + USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); } else { + /* EP enable, IN data in FIFO */ + USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); + /* Enable the Tx FIFO Empty Interrupt for this EP */ if (ep->xfer_len > 0U) { USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK); } } - - /* EP enable, IN data in FIFO */ - USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); } else /* OUT endpoint */ { @@ -955,7 +989,7 @@ HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uin count32b = ((uint32_t)len + 3U) / 4U; for (i = 0U; i < count32b; i++) { - USBx_DFIFO((uint32_t)ch_ep_num) = *((__packed uint32_t *)pSrc); + USBx_DFIFO((uint32_t)ch_ep_num) = __UNALIGNED_UINT32_READ(pSrc); pSrc++; } } @@ -964,15 +998,10 @@ HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uin } /** - * @brief USB_ReadPacket : read a packet from the Tx FIFO associated - * with the EP/channel + * @brief USB_ReadPacket : read a packet from the RX FIFO * @param USBx Selected device * @param dest source pointer * @param len Number of bytes to read - * @param dma USB dma enabled or disabled - * This parameter can be one of these values: - * 0 : DMA feature not used - * 1 : DMA feature used * @retval pointer to destination buffer */ void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len) @@ -984,7 +1013,7 @@ void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len) for (i = 0U; i < count32b; i++) { - *(__packed uint32_t *)pDest = USBx_DFIFO(0U); + __UNALIGNED_UINT32_WRITE(pDest, USBx_DFIFO(0U)); pDest++; } @@ -1256,13 +1285,9 @@ HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx) { uint32_t USBx_BASE = (uint32_t)USBx; - /* Set the MPS of the IN EP based on the enumeration speed */ + /* Set the MPS of the IN EP0 to 64 bytes */ USBx_INEP(0U)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ; - if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_LS_PHY_6MHZ) - { - USBx_INEP(0U)->DIEPCTL |= 3U; - } USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK; return HAL_OK; @@ -1429,7 +1454,7 @@ HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c if ((USBx->CID & (0x1U << 8)) != 0U) { - if (cfg.speed == USB_OTG_SPEED_FULL) + if (cfg.speed == USBH_FSLS_SPEED) { /* Force Device Enumeration to FS/LS mode only */ USBx_HOST->HCFG |= USB_OTG_HCFG_FSLSS; @@ -1590,9 +1615,9 @@ HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state) * @param USBx Selected device * @retval speed : Host speed * This parameter can be one of these values: - * @arg USB_OTG_SPEED_HIGH: High speed mode - * @arg USB_OTG_SPEED_FULL: Full speed mode - * @arg USB_OTG_SPEED_LOW: Low speed mode + * @arg HCD_SPEED_HIGH: High speed mode + * @arg HCD_SPEED_FULL: Full speed mode + * @arg HCD_SPEED_LOW: Low speed mode */ uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef *USBx) { @@ -1770,7 +1795,7 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe uint16_t num_packets; uint16_t max_hc_pkt_count = 256U; - if (((USBx->CID & (0x1U << 8)) != 0U) && (hc->speed == USB_OTG_SPEED_HIGH)) + if (((USBx->CID & (0x1U << 8)) != 0U) && (hc->speed == USBH_HS_SPEED)) { if ((dma == 0U) && (hc->do_ping == 1U)) { @@ -1998,7 +2023,6 @@ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx) uint32_t value; uint32_t i; - (void)USB_DisableGlobalInt(USBx); /* Flush FIFO */ @@ -2037,6 +2061,7 @@ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx) /* Clear any pending Host interrupts */ USBx_HOST->HAINT = 0xFFFFFFFFU; USBx->GINTSTS = 0xFFFFFFFFU; + (void)USB_EnableGlobalInt(USBx); return HAL_OK; diff --git a/system/Drivers/STM32F7xx_HAL_Driver/_htmresc/mini-st.css b/system/Drivers/STM32F7xx_HAL_Driver/_htmresc/mini-st.css new file mode 100644 index 0000000000..3caf11c32e --- /dev/null +++ b/system/Drivers/STM32F7xx_HAL_Driver/_htmresc/mini-st.css @@ -0,0 +1,1700 @@ +@charset "UTF-8"; +/* + Flavor name: Default (mini-default) + Author: Angelos Chalaris (chalarangelo@gmail.com) + Maintainers: Angelos Chalaris + mini.css version: v3.0.0-alpha.3 +*/ +/* + Browsers resets and base typography. +*/ +/* Core module CSS variable definitions */ +:root { + --fore-color: #111; + --secondary-fore-color: #444; + --back-color: #f8f8f8; + --secondary-back-color: #f0f0f0; + --blockquote-color: #f57c00; + --pre-color: #1565c0; + --border-color: #aaa; + --secondary-border-color: #ddd; + --heading-ratio: 1.19; + --universal-margin: 0.5rem; + --universal-padding: 0.125rem; + --universal-border-radius: 0.125rem; + --a-link-color: #0277bd; + --a-visited-color: #01579b; } + +html { + font-size: 14px; } + +a, b, del, em, i, ins, q, span, strong, u { + font-size: 1em; } + +html, * { + font-family: -apple-system, BlinkMacSystemFont, "Segoe UI", Roboto, Ubuntu, "Helvetica Neue", Helvetica, sans-serif; + line-height: 1.4; + -webkit-text-size-adjust: 100%; } + +* { + font-size: 1rem; } + +body { + margin: 0; + color: var(--fore-color); + background: var(--back-color); } + +details { + display: block; } + +summary { + display: list-item; } + +abbr[title] { + border-bottom: none; + text-decoration: underline dotted; } + +input { + overflow: visible; } + +img { + max-width: 100%; + height: auto; } + +h1, h2, h3, h4, h5, h6 { + line-height: 1.2; + margin: calc(1.5 * var(--universal-margin)) var(--universal-margin); + font-weight: 500; } + h1 small, h2 small, h3 small, h4 small, h5 small, h6 small { + color: var(--secondary-fore-color); + display: block; + margin-top: -0.25rem; } + +h1 { + font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio) * var(--heading-ratio)); } + +h2 { + font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio); ); + background: var(--mark-back-color); + font-weight: 600; + padding: 0.1em 0.5em 0.2em 0.5em; + color: var(--mark-fore-color); } + +h3 { + font-size: calc(1rem * var(--heading-ratio)); + padding-left: calc(2 * var(--universal-margin)); + /* background: var(--border-color); */ + } + +h4 { + font-size: 1rem;); + padding-left: calc(4 * var(--universal-margin)); } + +h5 { + font-size: 1rem; } + +h6 { + font-size: calc(1rem / var(--heading-ratio)); } + +p { + margin: var(--universal-margin); } + +ol, ul { + margin: var(--universal-margin); + padding-left: calc(6 * var(--universal-margin)); } + +b, strong { + font-weight: 700; } + +hr { + box-sizing: content-box; + border: 0; + line-height: 1.25em; + margin: var(--universal-margin); + height: 0.0625rem; + background: linear-gradient(to right, transparent, var(--border-color) 20%, var(--border-color) 80%, transparent); } + +blockquote { + display: block; + position: relative; + font-style: italic; + color: var(--secondary-fore-color); + margin: var(--universal-margin); + padding: calc(3 * var(--universal-padding)); + border: 0.0625rem solid var(--secondary-border-color); + border-left: 0.375rem solid var(--blockquote-color); + border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; } + blockquote:before { + position: absolute; + top: calc(0rem - var(--universal-padding)); + left: 0; + font-family: sans-serif; + font-size: 3rem; + font-weight: 700; + content: "\201c"; + color: var(--blockquote-color); } + blockquote[cite]:after { + font-style: normal; + font-size: 0.75em; + font-weight: 700; + content: "\a— " attr(cite); + white-space: pre; } + +code, kbd, pre, samp { + font-family: Menlo, Consolas, monospace; + font-size: 0.85em; } + +code { + background: var(--secondary-back-color); + border-radius: var(--universal-border-radius); + padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); } + +kbd { + background: var(--fore-color); + color: var(--back-color); + border-radius: var(--universal-border-radius); + padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); } + +pre { + overflow: auto; + background: var(--secondary-back-color); + padding: calc(1.5 * var(--universal-padding)); + margin: var(--universal-margin); + border: 0.0625rem solid var(--secondary-border-color); + border-left: 0.25rem solid var(--pre-color); + border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; } + +sup, sub, code, kbd { + line-height: 0; + position: relative; + vertical-align: baseline; } + +small, sup, sub, figcaption { + font-size: 0.75em; } + +sup { + top: -0.5em; } + +sub { + bottom: -0.25em; } + +figure { + margin: var(--universal-margin); } + +figcaption { + color: var(--secondary-fore-color); } + +a { + text-decoration: none; } + a:link { + color: var(--a-link-color); } + a:visited { + color: var(--a-visited-color); } + a:hover, a:focus { + text-decoration: underline; } + +/* + Definitions for the grid system, cards and containers. +*/ +.container { + margin: 0 auto; + padding: 0 calc(1.5 * var(--universal-padding)); } + +.row { + box-sizing: border-box; + display: flex; + flex: 0 1 auto; + flex-flow: row wrap; } + +.col-sm, +[class^='col-sm-'], +[class^='col-sm-offset-'], +.row[class*='cols-sm-'] > * { + box-sizing: border-box; + flex: 0 0 auto; + padding: 0 calc(var(--universal-padding) / 2); } + +.col-sm, +.row.cols-sm > * { + max-width: 100%; + flex-grow: 1; + flex-basis: 0; } + +.col-sm-1, +.row.cols-sm-1 > * { + max-width: 8.3333333333%; + flex-basis: 8.3333333333%; } + +.col-sm-offset-0 { + margin-left: 0; } + +.col-sm-2, +.row.cols-sm-2 > * { + max-width: 16.6666666667%; + flex-basis: 16.6666666667%; } + +.col-sm-offset-1 { + margin-left: 8.3333333333%; } + +.col-sm-3, +.row.cols-sm-3 > * { + max-width: 25%; + flex-basis: 25%; } + +.col-sm-offset-2 { + margin-left: 16.6666666667%; } + +.col-sm-4, +.row.cols-sm-4 > * { + max-width: 33.3333333333%; + flex-basis: 33.3333333333%; } + +.col-sm-offset-3 { + margin-left: 25%; } + +.col-sm-5, +.row.cols-sm-5 > * { + max-width: 41.6666666667%; + flex-basis: 41.6666666667%; } + +.col-sm-offset-4 { + margin-left: 33.3333333333%; } + +.col-sm-6, +.row.cols-sm-6 > * { + max-width: 50%; + flex-basis: 50%; } + +.col-sm-offset-5 { + margin-left: 41.6666666667%; } + +.col-sm-7, +.row.cols-sm-7 > * { + max-width: 58.3333333333%; + flex-basis: 58.3333333333%; } + +.col-sm-offset-6 { + margin-left: 50%; } + +.col-sm-8, +.row.cols-sm-8 > * { + max-width: 66.6666666667%; + flex-basis: 66.6666666667%; } + +.col-sm-offset-7 { + margin-left: 58.3333333333%; } + +.col-sm-9, +.row.cols-sm-9 > * { + max-width: 75%; + flex-basis: 75%; } + +.col-sm-offset-8 { + margin-left: 66.6666666667%; } + +.col-sm-10, +.row.cols-sm-10 > * { + max-width: 83.3333333333%; + flex-basis: 83.3333333333%; } + +.col-sm-offset-9 { + margin-left: 75%; } + +.col-sm-11, +.row.cols-sm-11 > * { + max-width: 91.6666666667%; + flex-basis: 91.6666666667%; } + +.col-sm-offset-10 { + margin-left: 83.3333333333%; } + +.col-sm-12, +.row.cols-sm-12 > * { + max-width: 100%; + flex-basis: 100%; } + +.col-sm-offset-11 { + margin-left: 91.6666666667%; } + +.col-sm-normal { + order: initial; } + +.col-sm-first { + order: -999; } + +.col-sm-last { + order: 999; } + +@media screen and (min-width: 500px) { + .col-md, + [class^='col-md-'], + [class^='col-md-offset-'], + .row[class*='cols-md-'] > * { + box-sizing: border-box; + flex: 0 0 auto; + padding: 0 calc(var(--universal-padding) / 2); } + + .col-md, + .row.cols-md > * { + max-width: 100%; + flex-grow: 1; + flex-basis: 0; } + + .col-md-1, + .row.cols-md-1 > * { + max-width: 8.3333333333%; + flex-basis: 8.3333333333%; } + + .col-md-offset-0 { + margin-left: 0; } + + .col-md-2, + .row.cols-md-2 > * { + max-width: 16.6666666667%; + flex-basis: 16.6666666667%; } + + .col-md-offset-1 { + margin-left: 8.3333333333%; } + + .col-md-3, + .row.cols-md-3 > * { + max-width: 25%; + flex-basis: 25%; } + + .col-md-offset-2 { + margin-left: 16.6666666667%; } + + .col-md-4, + .row.cols-md-4 > * { + max-width: 33.3333333333%; + flex-basis: 33.3333333333%; } + + .col-md-offset-3 { + margin-left: 25%; } + + .col-md-5, + .row.cols-md-5 > * { + max-width: 41.6666666667%; + flex-basis: 41.6666666667%; } + + .col-md-offset-4 { + margin-left: 33.3333333333%; } + + .col-md-6, + .row.cols-md-6 > * { + max-width: 50%; + flex-basis: 50%; } + + .col-md-offset-5 { + margin-left: 41.6666666667%; } + + .col-md-7, + .row.cols-md-7 > * { + max-width: 58.3333333333%; + flex-basis: 58.3333333333%; } + + .col-md-offset-6 { + margin-left: 50%; } + + .col-md-8, + .row.cols-md-8 > * { + max-width: 66.6666666667%; + flex-basis: 66.6666666667%; } + + .col-md-offset-7 { + margin-left: 58.3333333333%; } + + .col-md-9, + .row.cols-md-9 > * { + max-width: 75%; + flex-basis: 75%; } + + .col-md-offset-8 { + margin-left: 66.6666666667%; } + + .col-md-10, + .row.cols-md-10 > * { + max-width: 83.3333333333%; + flex-basis: 83.3333333333%; } + + .col-md-offset-9 { + margin-left: 75%; } + + .col-md-11, + .row.cols-md-11 > * { + max-width: 91.6666666667%; + flex-basis: 91.6666666667%; } + + .col-md-offset-10 { + margin-left: 83.3333333333%; } + + .col-md-12, + .row.cols-md-12 > * { + max-width: 100%; + flex-basis: 100%; } + + .col-md-offset-11 { + margin-left: 91.6666666667%; } + + .col-md-normal { + order: initial; } + + .col-md-first { + order: -999; } + + .col-md-last { + order: 999; } } +@media screen and (min-width: 1280px) { + .col-lg, + [class^='col-lg-'], + [class^='col-lg-offset-'], + .row[class*='cols-lg-'] > * { + box-sizing: border-box; + flex: 0 0 auto; + padding: 0 calc(var(--universal-padding) / 2); } + + .col-lg, + .row.cols-lg > * { + max-width: 100%; + flex-grow: 1; + flex-basis: 0; } + + .col-lg-1, + .row.cols-lg-1 > * { + max-width: 8.3333333333%; + flex-basis: 8.3333333333%; } + + .col-lg-offset-0 { + margin-left: 0; } + + .col-lg-2, + .row.cols-lg-2 > * { + max-width: 16.6666666667%; + flex-basis: 16.6666666667%; } + + .col-lg-offset-1 { + margin-left: 8.3333333333%; } + + .col-lg-3, + .row.cols-lg-3 > * { + max-width: 25%; + flex-basis: 25%; } + + .col-lg-offset-2 { + margin-left: 16.6666666667%; } + + .col-lg-4, + .row.cols-lg-4 > * { + max-width: 33.3333333333%; + flex-basis: 33.3333333333%; } + + .col-lg-offset-3 { + margin-left: 25%; } + + .col-lg-5, + .row.cols-lg-5 > * { + max-width: 41.6666666667%; + flex-basis: 41.6666666667%; } + + .col-lg-offset-4 { + margin-left: 33.3333333333%; } + + .col-lg-6, + .row.cols-lg-6 > * { + max-width: 50%; + flex-basis: 50%; } + + .col-lg-offset-5 { + margin-left: 41.6666666667%; } + + .col-lg-7, + .row.cols-lg-7 > * { + max-width: 58.3333333333%; + flex-basis: 58.3333333333%; } + + .col-lg-offset-6 { + margin-left: 50%; } + + .col-lg-8, + .row.cols-lg-8 > * { + max-width: 66.6666666667%; + flex-basis: 66.6666666667%; } + + .col-lg-offset-7 { + margin-left: 58.3333333333%; } + + .col-lg-9, + .row.cols-lg-9 > * { + max-width: 75%; + flex-basis: 75%; } + + .col-lg-offset-8 { + margin-left: 66.6666666667%; } + + .col-lg-10, + .row.cols-lg-10 > * { + max-width: 83.3333333333%; + flex-basis: 83.3333333333%; } + + .col-lg-offset-9 { + margin-left: 75%; } + + .col-lg-11, + .row.cols-lg-11 > * { + max-width: 91.6666666667%; + flex-basis: 91.6666666667%; } + + .col-lg-offset-10 { + margin-left: 83.3333333333%; } + + .col-lg-12, + .row.cols-lg-12 > * { + max-width: 100%; + flex-basis: 100%; } + + .col-lg-offset-11 { + margin-left: 91.6666666667%; } + + .col-lg-normal { + order: initial; } + + .col-lg-first { + order: -999; } + + .col-lg-last { + order: 999; } } +/* Card component CSS variable definitions */ +:root { + --card-back-color: #f8f8f8; + --card-fore-color: #111; + --card-border-color: #ddd; } + +.card { + display: flex; + flex-direction: column; + justify-content: space-between; + align-self: center; + position: relative; + width: 100%; + background: var(--card-back-color); + color: var(--card-fore-color); + border: 0.0625rem solid var(--card-border-color); + border-radius: var(--universal-border-radius); + margin: var(--universal-margin); + overflow: hidden; } + @media screen and (min-width: 320px) { + .card { + max-width: 320px; } } + .card > .sectione { + background: var(--card-back-color); + color: var(--card-fore-color); + box-sizing: border-box; + margin: 0; + border: 0; + border-radius: 0; + border-bottom: 0.0625rem solid var(--card-border-color); + padding: var(--universal-padding); + width: 100%; } + .card > .sectione.media { + height: 200px; + padding: 0; + -o-object-fit: cover; + object-fit: cover; } + .card > .sectione:last-child { + border-bottom: 0; } + +/* + Custom elements for card elements. +*/ +@media screen and (min-width: 240px) { + .card.small { + max-width: 240px; } } +@media screen and (min-width: 480px) { + .card.large { + max-width: 480px; } } +.card.fluid { + max-width: 100%; + width: auto; } + +.card.warning { +/* --card-back-color: #ffca28; */ + --card-back-color: #e5b8b7; + --card-border-color: #e8b825; } + +.card.error { + --card-back-color: #b71c1c; + --card-fore-color: #f8f8f8; + --card-border-color: #a71a1a; } + +.card > .sectione.dark { + --card-back-color: #e0e0e0; } + +.card > .sectione.double-padded { + padding: calc(1.5 * var(--universal-padding)); } + +/* + Definitions for forms and input elements. +*/ +/* Input_control module CSS variable definitions */ +:root { + --form-back-color: #f0f0f0; + --form-fore-color: #111; + --form-border-color: #ddd; + --input-back-color: #f8f8f8; + --input-fore-color: #111; + --input-border-color: #ddd; + --input-focus-color: #0288d1; + --input-invalid-color: #d32f2f; + --button-back-color: #e2e2e2; + --button-hover-back-color: #dcdcdc; + --button-fore-color: #212121; + --button-border-color: transparent; + --button-hover-border-color: transparent; + --button-group-border-color: rgba(124, 124, 124, 0.54); } + +form { + background: var(--form-back-color); + color: var(--form-fore-color); + border: 0.0625rem solid var(--form-border-color); + border-radius: var(--universal-border-radius); + margin: var(--universal-margin); + padding: calc(2 * var(--universal-padding)) var(--universal-padding); } + +fieldset { + border: 0.0625rem solid var(--form-border-color); + border-radius: var(--universal-border-radius); + margin: calc(var(--universal-margin) / 4); + padding: var(--universal-padding); } + +legend { + box-sizing: border-box; + display: table; + max-width: 100%; + white-space: normal; + font-weight: 700; + padding: calc(var(--universal-padding) / 2); } + +label { + padding: calc(var(--universal-padding) / 2) var(--universal-padding); } + +.input-group { + display: inline-block; } + .input-group.fluid { + display: flex; + align-items: center; + justify-content: center; } + .input-group.fluid > input { + max-width: 100%; + flex-grow: 1; + flex-basis: 0px; } + @media screen and (max-width: 499px) { + .input-group.fluid { + align-items: stretch; + flex-direction: column; } } + .input-group.vertical { + display: flex; + align-items: stretch; + flex-direction: column; } + .input-group.vertical > input { + max-width: 100%; + flex-grow: 1; + flex-basis: 0px; } + +[type="number"]::-webkit-inner-spin-button, [type="number"]::-webkit-outer-spin-button { + height: auto; } + +[type="search"] { + -webkit-appearance: textfield; + outline-offset: -2px; } + +[type="search"]::-webkit-search-cancel-button, +[type="search"]::-webkit-search-decoration { + -webkit-appearance: none; } + +input:not([type]), [type="text"], [type="email"], [type="number"], [type="search"], +[type="password"], [type="url"], [type="tel"], [type="checkbox"], [type="radio"], textarea, select { + box-sizing: border-box; + background: var(--input-back-color); + color: var(--input-fore-color); + border: 0.0625rem solid var(--input-border-color); + border-radius: var(--universal-border-radius); + margin: calc(var(--universal-margin) / 2); + padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); } + +input:not([type="button"]):not([type="submit"]):not([type="reset"]):hover, input:not([type="button"]):not([type="submit"]):not([type="reset"]):focus, textarea:hover, textarea:focus, select:hover, select:focus { + border-color: var(--input-focus-color); + box-shadow: none; } +input:not([type="button"]):not([type="submit"]):not([type="reset"]):invalid, input:not([type="button"]):not([type="submit"]):not([type="reset"]):focus:invalid, textarea:invalid, textarea:focus:invalid, select:invalid, select:focus:invalid { + border-color: var(--input-invalid-color); + box-shadow: none; } +input:not([type="button"]):not([type="submit"]):not([type="reset"])[readonly], textarea[readonly], select[readonly] { + background: var(--secondary-back-color); } + +select { + max-width: 100%; } + +option { + overflow: hidden; + text-overflow: ellipsis; } + +[type="checkbox"], [type="radio"] { + -webkit-appearance: none; + -moz-appearance: none; + appearance: none; + position: relative; + height: calc(1rem + var(--universal-padding) / 2); + width: calc(1rem + var(--universal-padding) / 2); + vertical-align: text-bottom; + padding: 0; + flex-basis: calc(1rem + var(--universal-padding) / 2) !important; + flex-grow: 0 !important; } + [type="checkbox"]:checked:before, [type="radio"]:checked:before { + position: absolute; } + +[type="checkbox"]:checked:before { + content: '\2713'; + font-family: sans-serif; + font-size: calc(1rem + var(--universal-padding) / 2); + top: calc(0rem - var(--universal-padding)); + left: calc(var(--universal-padding) / 4); } + +[type="radio"] { + border-radius: 100%; } + [type="radio"]:checked:before { + border-radius: 100%; + content: ''; + top: calc(0.0625rem + var(--universal-padding) / 2); + left: calc(0.0625rem + var(--universal-padding) / 2); + background: var(--input-fore-color); + width: 0.5rem; + height: 0.5rem; } + +:placeholder-shown { + color: var(--input-fore-color); } + +::-ms-placeholder { + color: var(--input-fore-color); + opacity: 0.54; } + +button::-moz-focus-inner, [type="button"]::-moz-focus-inner, [type="reset"]::-moz-focus-inner, [type="submit"]::-moz-focus-inner { + border-style: none; + padding: 0; } + +button, html [type="button"], [type="reset"], [type="submit"] { + -webkit-appearance: button; } + +button { + overflow: visible; + text-transform: none; } + +button, [type="button"], [type="submit"], [type="reset"], +a.button, label.button, .button, +a[role="button"], label[role="button"], [role="button"] { + display: inline-block; + background: var(--button-back-color); + color: var(--button-fore-color); + border: 0.0625rem solid var(--button-border-color); + border-radius: var(--universal-border-radius); + padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); + margin: var(--universal-margin); + text-decoration: none; + cursor: pointer; + transition: background 0.3s; } + button:hover, button:focus, [type="button"]:hover, [type="button"]:focus, [type="submit"]:hover, [type="submit"]:focus, [type="reset"]:hover, [type="reset"]:focus, + a.button:hover, + a.button:focus, label.button:hover, label.button:focus, .button:hover, .button:focus, + a[role="button"]:hover, + a[role="button"]:focus, label[role="button"]:hover, label[role="button"]:focus, [role="button"]:hover, [role="button"]:focus { + background: var(--button-hover-back-color); + border-color: var(--button-hover-border-color); } + +input:disabled, input[disabled], textarea:disabled, textarea[disabled], select:disabled, select[disabled], button:disabled, button[disabled], .button:disabled, .button[disabled], [role="button"]:disabled, [role="button"][disabled] { + cursor: not-allowed; + opacity: 0.75; } + +.button-group { + display: flex; + border: 0.0625rem solid var(--button-group-border-color); + border-radius: var(--universal-border-radius); + margin: var(--universal-margin); } + .button-group > button, .button-group [type="button"], .button-group > [type="submit"], .button-group > [type="reset"], .button-group > .button, .button-group > [role="button"] { + margin: 0; + max-width: 100%; + flex: 1 1 auto; + text-align: center; + border: 0; + border-radius: 0; + box-shadow: none; } + .button-group > :not(:first-child) { + border-left: 0.0625rem solid var(--button-group-border-color); } + @media screen and (max-width: 499px) { + .button-group { + flex-direction: column; } + .button-group > :not(:first-child) { + border: 0; + border-top: 0.0625rem solid var(--button-group-border-color); } } + +/* + Custom elements for forms and input elements. +*/ +button.primary, [type="button"].primary, [type="submit"].primary, [type="reset"].primary, .button.primary, [role="button"].primary { + --button-back-color: #1976d2; + --button-fore-color: #f8f8f8; } + button.primary:hover, button.primary:focus, [type="button"].primary:hover, [type="button"].primary:focus, [type="submit"].primary:hover, [type="submit"].primary:focus, [type="reset"].primary:hover, [type="reset"].primary:focus, .button.primary:hover, .button.primary:focus, [role="button"].primary:hover, [role="button"].primary:focus { + --button-hover-back-color: #1565c0; } + +button.secondary, [type="button"].secondary, [type="submit"].secondary, [type="reset"].secondary, .button.secondary, [role="button"].secondary { + --button-back-color: #d32f2f; + --button-fore-color: #f8f8f8; } + button.secondary:hover, button.secondary:focus, [type="button"].secondary:hover, [type="button"].secondary:focus, [type="submit"].secondary:hover, [type="submit"].secondary:focus, [type="reset"].secondary:hover, [type="reset"].secondary:focus, .button.secondary:hover, .button.secondary:focus, [role="button"].secondary:hover, [role="button"].secondary:focus { + --button-hover-back-color: #c62828; } + +button.tertiary, [type="button"].tertiary, [type="submit"].tertiary, [type="reset"].tertiary, .button.tertiary, [role="button"].tertiary { + --button-back-color: #308732; + --button-fore-color: #f8f8f8; } + button.tertiary:hover, button.tertiary:focus, [type="button"].tertiary:hover, [type="button"].tertiary:focus, [type="submit"].tertiary:hover, [type="submit"].tertiary:focus, [type="reset"].tertiary:hover, [type="reset"].tertiary:focus, .button.tertiary:hover, .button.tertiary:focus, [role="button"].tertiary:hover, [role="button"].tertiary:focus { + --button-hover-back-color: #277529; } + +button.inverse, [type="button"].inverse, [type="submit"].inverse, [type="reset"].inverse, .button.inverse, [role="button"].inverse { + --button-back-color: #212121; + --button-fore-color: #f8f8f8; } + button.inverse:hover, button.inverse:focus, [type="button"].inverse:hover, [type="button"].inverse:focus, [type="submit"].inverse:hover, [type="submit"].inverse:focus, [type="reset"].inverse:hover, [type="reset"].inverse:focus, .button.inverse:hover, .button.inverse:focus, [role="button"].inverse:hover, [role="button"].inverse:focus { + --button-hover-back-color: #111; } + +button.small, [type="button"].small, [type="submit"].small, [type="reset"].small, .button.small, [role="button"].small { + padding: calc(0.5 * var(--universal-padding)) calc(0.75 * var(--universal-padding)); + margin: var(--universal-margin); } + +button.large, [type="button"].large, [type="submit"].large, [type="reset"].large, .button.large, [role="button"].large { + padding: calc(1.5 * var(--universal-padding)) calc(2 * var(--universal-padding)); + margin: var(--universal-margin); } + +/* + Definitions for navigation elements. +*/ +/* Navigation module CSS variable definitions */ +:root { + --header-back-color: #f8f8f8; + --header-hover-back-color: #f0f0f0; + --header-fore-color: #444; + --header-border-color: #ddd; + --nav-back-color: #f8f8f8; + --nav-hover-back-color: #f0f0f0; + --nav-fore-color: #444; + --nav-border-color: #ddd; + --nav-link-color: #0277bd; + --footer-fore-color: #444; + --footer-back-color: #f8f8f8; + --footer-border-color: #ddd; + --footer-link-color: #0277bd; + --drawer-back-color: #f8f8f8; + --drawer-hover-back-color: #f0f0f0; + --drawer-border-color: #ddd; + --drawer-close-color: #444; } + +header { + height: 3.1875rem; + background: var(--header-back-color); + color: var(--header-fore-color); + border-bottom: 0.0625rem solid var(--header-border-color); + padding: calc(var(--universal-padding) / 4) 0; + white-space: nowrap; + overflow-x: auto; + overflow-y: hidden; } + header.row { + box-sizing: content-box; } + header .logo { + color: var(--header-fore-color); + font-size: 1.75rem; + padding: var(--universal-padding) calc(2 * var(--universal-padding)); + text-decoration: none; } + header button, header [type="button"], header .button, header [role="button"] { + box-sizing: border-box; + position: relative; + top: calc(0rem - var(--universal-padding) / 4); + height: calc(3.1875rem + var(--universal-padding) / 2); + background: var(--header-back-color); + line-height: calc(3.1875rem - var(--universal-padding) * 1.5); + text-align: center; + color: var(--header-fore-color); + border: 0; + border-radius: 0; + margin: 0; + text-transform: uppercase; } + header button:hover, header button:focus, header [type="button"]:hover, header [type="button"]:focus, header .button:hover, header .button:focus, header [role="button"]:hover, header [role="button"]:focus { + background: var(--header-hover-back-color); } + +nav { + background: var(--nav-back-color); + color: var(--nav-fore-color); + border: 0.0625rem solid var(--nav-border-color); + border-radius: var(--universal-border-radius); + margin: var(--universal-margin); } + nav * { + padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); } + nav a, nav a:visited { + display: block; + color: var(--nav-link-color); + border-radius: var(--universal-border-radius); + transition: background 0.3s; } + nav a:hover, nav a:focus, nav a:visited:hover, nav a:visited:focus { + text-decoration: none; + background: var(--nav-hover-back-color); } + nav .sublink-1 { + position: relative; + margin-left: calc(2 * var(--universal-padding)); } + nav .sublink-1:before { + position: absolute; + left: calc(var(--universal-padding) - 1 * var(--universal-padding)); + top: -0.0625rem; + content: ''; + height: 100%; + border: 0.0625rem solid var(--nav-border-color); + border-left: 0; } + nav .sublink-2 { + position: relative; + margin-left: calc(4 * var(--universal-padding)); } + nav .sublink-2:before { + position: absolute; + left: calc(var(--universal-padding) - 3 * var(--universal-padding)); + top: -0.0625rem; + content: ''; + height: 100%; + border: 0.0625rem solid var(--nav-border-color); + border-left: 0; } + +footer { + background: var(--footer-back-color); + color: var(--footer-fore-color); + border-top: 0.0625rem solid var(--footer-border-color); + padding: calc(2 * var(--universal-padding)) var(--universal-padding); + font-size: 0.875rem; } + footer a, footer a:visited { + color: var(--footer-link-color); } + +header.sticky { + position: -webkit-sticky; + position: sticky; + z-index: 1101; + top: 0; } + +footer.sticky { + position: -webkit-sticky; + position: sticky; + z-index: 1101; + bottom: 0; } + +.drawer-toggle:before { + display: inline-block; + position: relative; + vertical-align: bottom; + content: '\00a0\2261\00a0'; + font-family: sans-serif; + font-size: 1.5em; } +@media screen and (min-width: 500px) { + .drawer-toggle:not(.persistent) { + display: none; } } + +[type="checkbox"].drawer { + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); } + [type="checkbox"].drawer + * { + display: block; + box-sizing: border-box; + position: fixed; + top: 0; + width: 320px; + height: 100vh; + overflow-y: auto; + background: var(--drawer-back-color); + border: 0.0625rem solid var(--drawer-border-color); + border-radius: 0; + margin: 0; + z-index: 1110; + right: -320px; + transition: right 0.3s; } + [type="checkbox"].drawer + * .drawer-close { + position: absolute; + top: var(--universal-margin); + right: var(--universal-margin); + z-index: 1111; + width: 2rem; + height: 2rem; + border-radius: var(--universal-border-radius); + padding: var(--universal-padding); + margin: 0; + cursor: pointer; + transition: background 0.3s; } + [type="checkbox"].drawer + * .drawer-close:before { + display: block; + content: '\00D7'; + color: var(--drawer-close-color); + position: relative; + font-family: sans-serif; + font-size: 2rem; + line-height: 1; + text-align: center; } + [type="checkbox"].drawer + * .drawer-close:hover, [type="checkbox"].drawer + * .drawer-close:focus { + background: var(--drawer-hover-back-color); } + @media screen and (max-width: 320px) { + [type="checkbox"].drawer + * { + width: 100%; } } + [type="checkbox"].drawer:checked + * { + right: 0; } + @media screen and (min-width: 500px) { + [type="checkbox"].drawer:not(.persistent) + * { + position: static; + height: 100%; + z-index: 1100; } + [type="checkbox"].drawer:not(.persistent) + * .drawer-close { + display: none; } } + +/* + Definitions for the responsive table component. +*/ +/* Table module CSS variable definitions. */ +:root { + --table-border-color: #aaa; + --table-border-separator-color: #666; + --table-head-back-color: #e6e6e6; + --table-head-fore-color: #111; + --table-body-back-color: #f8f8f8; + --table-body-fore-color: #111; + --table-body-alt-back-color: #eee; } + +table { + border-collapse: separate; + border-spacing: 0; + : margin: calc(1.5 * var(--universal-margin)) var(--universal-margin); + display: flex; + flex: 0 1 auto; + flex-flow: row wrap; + padding: var(--universal-padding); + padding-top: 0; + margin: calc(1.5 * var(--universal-margin)) var(--universal-margin); } + table caption { + font-size: 1.25 * rem; + margin: calc(2 * var(--universal-margin)) 0; + max-width: 100%; + flex: 0 0 100%; + text-align: left;} + table thead, table tbody { + display: flex; + flex-flow: row wrap; + border: 0.0625rem solid var(--table-border-color); } + table thead { + z-index: 999; + border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0; + border-bottom: 0.0625rem solid var(--table-border-separator-color); } + table tbody { + border-top: 0; + margin-top: calc(0 - var(--universal-margin)); + border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); } + table tr { + display: flex; + padding: 0; } + table th, table td { + padding: calc(0.5 * var(--universal-padding)); + font-size: 0.9rem; } + table th { + text-align: left; + background: var(--table-head-back-color); + color: var(--table-head-fore-color); } + table td { + background: var(--table-body-back-color); + color: var(--table-body-fore-color); + border-top: 0.0625rem solid var(--table-border-color); } + +table:not(.horizontal) { + overflow: auto; + max-height: 850px; } + table:not(.horizontal) thead, table:not(.horizontal) tbody { + max-width: 100%; + flex: 0 0 100%; } + table:not(.horizontal) tr { + flex-flow: row wrap; + flex: 0 0 100%; } + table:not(.horizontal) th, table:not(.horizontal) td { + flex: 1 0 0%; + overflow: hidden; + text-overflow: ellipsis; } + table:not(.horizontal) thead { + position: sticky; + top: 0; } + table:not(.horizontal) tbody tr:first-child td { + border-top: 0; } + +table.horizontal { + border: 0; } + table.horizontal thead, table.horizontal tbody { + border: 0; + flex-flow: row nowrap; } + table.horizontal tbody { + overflow: auto; + justify-content: space-between; + flex: 1 0 0; + margin-left: calc( 4 * var(--universal-margin)); + padding-bottom: calc(var(--universal-padding) / 4); } + table.horizontal tr { + flex-direction: column; + flex: 1 0 auto; } + table.horizontal th, table.horizontal td { + width: 100%; + border: 0; + border-bottom: 0.0625rem solid var(--table-border-color); } + table.horizontal th:not(:first-child), table.horizontal td:not(:first-child) { + border-top: 0; } + table.horizontal th { + text-align: right; + border-left: 0.0625rem solid var(--table-border-color); + border-right: 0.0625rem solid var(--table-border-separator-color); } + table.horizontal thead tr:first-child { + padding-left: 0; } + table.horizontal th:first-child, table.horizontal td:first-child { + border-top: 0.0625rem solid var(--table-border-color); } + table.horizontal tbody tr:last-child td { + border-right: 0.0625rem solid var(--table-border-color); } + table.horizontal tbody tr:last-child td:first-child { + border-top-right-radius: 0.25rem; } + table.horizontal tbody tr:last-child td:last-child { + border-bottom-right-radius: 0.25rem; } + table.horizontal thead tr:first-child th:first-child { + border-top-left-radius: 0.25rem; } + table.horizontal thead tr:first-child th:last-child { + border-bottom-left-radius: 0.25rem; } + +@media screen and (max-width: 499px) { + table, table.horizontal { + border-collapse: collapse; + border: 0; + width: 100%; + display: table; } + table thead, table th, table.horizontal thead, table.horizontal th { + border: 0; + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + padding: 0; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); } + table tbody, table.horizontal tbody { + border: 0; + display: table-row-group; } + table tr, table.horizontal tr { + display: block; + border: 0.0625rem solid var(--table-border-color); + border-radius: var(--universal-border-radius); + background: #fafafa; + padding: var(--universal-padding); + margin: var(--universal-margin); + margin-bottom: calc(2 * var(--universal-margin)); } + table th, table td, table.horizontal th, table.horizontal td { + width: auto; } + table td, table.horizontal td { + display: block; + border: 0; + text-align: right; } + table td:before, table.horizontal td:before { + content: attr(data-label); + float: left; + font-weight: 600; } + table th:first-child, table td:first-child, table.horizontal th:first-child, table.horizontal td:first-child { + border-top: 0; } + table tbody tr:last-child td, table.horizontal tbody tr:last-child td { + border-right: 0; } } +:root { + --table-body-alt-back-color: #eee; } + +table tr:nth-of-type(2n) > td { + background: var(--table-body-alt-back-color); } + +@media screen and (max-width: 500px) { + table tr:nth-of-type(2n) { + background: var(--table-body-alt-back-color); } } +:root { + --table-body-hover-back-color: #90caf9; } + +table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focus, table.hoverable tr:focus > td { + background: var(--table-body-hover-back-color); } + +@media screen and (max-width: 500px) { + table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focus, table.hoverable tr:focus > td { + background: var(--table-body-hover-back-color); } } +/* + Definitions for contextual background elements, toasts and tooltips. +*/ +/* Contextual module CSS variable definitions */ +:root { + --mark-back-color: #0277bd; + --mark-fore-color: #fafafa; } + +mark { + background: var(--mark-back-color); + color: var(--mark-fore-color); + font-size: 0.95em; + line-height: 1em; + border-radius: var(--universal-border-radius); + padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); } + mark.inline-block { + display: inline-block; + font-size: 1em; + line-height: 1.5; + padding: calc(var(--universal-padding) / 2) var(--universal-padding); } + +:root { + --toast-back-color: #424242; + --toast-fore-color: #fafafa; } + +.toast { + position: fixed; + bottom: calc(var(--universal-margin) * 3); + left: 50%; + transform: translate(-50%, -50%); + z-index: 1111; + color: var(--toast-fore-color); + background: var(--toast-back-color); + border-radius: calc(var(--universal-border-radius) * 16); + padding: var(--universal-padding) calc(var(--universal-padding) * 3); } + +:root { + --tooltip-back-color: #212121; + --tooltip-fore-color: #fafafa; } + +.tooltip { + position: relative; + display: inline-block; } + .tooltip:before, .tooltip:after { + position: absolute; + opacity: 0; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); + transition: all 0.3s; + z-index: 1010; + left: 50%; } + .tooltip:not(.bottom):before, .tooltip:not(.bottom):after { + bottom: 75%; } + .tooltip.bottom:before, .tooltip.bottom:after { + top: 75%; } + .tooltip:hover:before, .tooltip:hover:after, .tooltip:focus:before, .tooltip:focus:after { + opacity: 1; + clip: auto; + -webkit-clip-path: inset(0%); + clip-path: inset(0%); } + .tooltip:before { + content: ''; + background: transparent; + border: var(--universal-margin) solid transparent; + left: calc(50% - var(--universal-margin)); } + .tooltip:not(.bottom):before { + border-top-color: #212121; } + .tooltip.bottom:before { + border-bottom-color: #212121; } + .tooltip:after { + content: attr(aria-label); + color: var(--tooltip-fore-color); + background: var(--tooltip-back-color); + border-radius: var(--universal-border-radius); + padding: var(--universal-padding); + white-space: nowrap; + transform: translateX(-50%); } + .tooltip:not(.bottom):after { + margin-bottom: calc(2 * var(--universal-margin)); } + .tooltip.bottom:after { + margin-top: calc(2 * var(--universal-margin)); } + +:root { + --modal-overlay-color: rgba(0, 0, 0, 0.45); + --modal-close-color: #444; + --modal-close-hover-color: #f0f0f0; } + +[type="checkbox"].modal { + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); } + [type="checkbox"].modal + div { + position: fixed; + top: 0; + left: 0; + display: none; + width: 100vw; + height: 100vh; + background: var(--modal-overlay-color); } + [type="checkbox"].modal + div .card { + margin: 0 auto; + max-height: 50vh; + overflow: auto; } + [type="checkbox"].modal + div .card .modal-close { + position: absolute; + top: 0; + right: 0; + width: 1.75rem; + height: 1.75rem; + border-radius: var(--universal-border-radius); + padding: var(--universal-padding); + margin: 0; + cursor: pointer; + transition: background 0.3s; } + [type="checkbox"].modal + div .card .modal-close:before { + display: block; + content: '\00D7'; + color: var(--modal-close-color); + position: relative; + font-family: sans-serif; + font-size: 1.75rem; + line-height: 1; + text-align: center; } + [type="checkbox"].modal + div .card .modal-close:hover, [type="checkbox"].modal + div .card .modal-close:focus { + background: var(--modal-close-hover-color); } + [type="checkbox"].modal:checked + div { + display: flex; + flex: 0 1 auto; + z-index: 1200; } + [type="checkbox"].modal:checked + div .card .modal-close { + z-index: 1211; } + +:root { + --collapse-label-back-color: #e8e8e8; + --collapse-label-fore-color: #212121; + --collapse-label-hover-back-color: #f0f0f0; + --collapse-selected-label-back-color: #ececec; + --collapse-border-color: #ddd; + --collapse-content-back-color: #fafafa; + --collapse-selected-label-border-color: #0277bd; } + +.collapse { + width: calc(100% - 2 * var(--universal-margin)); + opacity: 1; + display: flex; + flex-direction: column; + margin: var(--universal-margin); + border-radius: var(--universal-border-radius); } + .collapse > [type="radio"], .collapse > [type="checkbox"] { + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); } + .collapse > label { + flex-grow: 1; + display: inline-block; + height: 1.5rem; + cursor: pointer; + transition: background 0.3s; + color: var(--collapse-label-fore-color); + background: var(--collapse-label-back-color); + border: 0.0625rem solid var(--collapse-border-color); + padding: calc(1.5 * var(--universal-padding)); } + .collapse > label:hover, .collapse > label:focus { + background: var(--collapse-label-hover-back-color); } + .collapse > label + div { + flex-basis: auto; + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); + transition: max-height 0.3s; + max-height: 1px; } + .collapse > :checked + label { + background: var(--collapse-selected-label-back-color); + border-bottom-color: var(--collapse-selected-label-border-color); } + .collapse > :checked + label + div { + box-sizing: border-box; + position: relative; + width: 100%; + height: auto; + overflow: auto; + margin: 0; + background: var(--collapse-content-back-color); + border: 0.0625rem solid var(--collapse-border-color); + border-top: 0; + padding: var(--universal-padding); + clip: auto; + -webkit-clip-path: inset(0%); + clip-path: inset(0%); + max-height: 850px; } + .collapse > label:not(:first-of-type) { + border-top: 0; } + .collapse > label:first-of-type { + border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0; } + .collapse > label:last-of-type:not(:first-of-type) { + border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); } + .collapse > label:last-of-type:first-of-type { + border-radius: var(--universal-border-radius); } + .collapse > :checked:last-of-type:not(:first-of-type) + label { + border-radius: 0; } + .collapse > :checked:last-of-type + label + div { + border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); } + +/* + Custom elements for contextual background elements, toasts and tooltips. +*/ +mark.secondary { + --mark-back-color: #d32f2f; } + +mark.tertiary { + --mark-back-color: #308732; } + +mark.tag { + padding: calc(var(--universal-padding)/2) var(--universal-padding); + border-radius: 1em; } + +/* + Definitions for progress elements and spinners. +*/ +/* Progess module CSS variable definitions */ +:root { + --progress-back-color: #ddd; + --progress-fore-color: #555; } + +progress { + display: block; + vertical-align: baseline; + -webkit-appearance: none; + -moz-appearance: none; + appearance: none; + height: 0.75rem; + width: calc(100% - 2 * var(--universal-margin)); + margin: var(--universal-margin); + border: 0; + border-radius: calc(2 * var(--universal-border-radius)); + background: var(--progress-back-color); + color: var(--progress-fore-color); } + progress::-webkit-progress-value { + background: var(--progress-fore-color); + border-top-left-radius: calc(2 * var(--universal-border-radius)); + border-bottom-left-radius: calc(2 * var(--universal-border-radius)); } + progress::-webkit-progress-bar { + background: var(--progress-back-color); } + progress::-moz-progress-bar { + background: var(--progress-fore-color); + border-top-left-radius: calc(2 * var(--universal-border-radius)); + border-bottom-left-radius: calc(2 * var(--universal-border-radius)); } + progress[value="1000"]::-webkit-progress-value { + border-radius: calc(2 * var(--universal-border-radius)); } + progress[value="1000"]::-moz-progress-bar { + border-radius: calc(2 * var(--universal-border-radius)); } + progress.inline { + display: inline-block; + vertical-align: middle; + width: 60%; } + +:root { + --spinner-back-color: #ddd; + --spinner-fore-color: #555; } + +@keyframes spinner-donut-anim { + 0% { + transform: rotate(0deg); } + 100% { + transform: rotate(360deg); } } +.spinner { + display: inline-block; + margin: var(--universal-margin); + border: 0.25rem solid var(--spinner-back-color); + border-left: 0.25rem solid var(--spinner-fore-color); + border-radius: 50%; + width: 1.25rem; + height: 1.25rem; + animation: spinner-donut-anim 1.2s linear infinite; } + +/* + Custom elements for progress bars and spinners. +*/ +progress.primary { + --progress-fore-color: #1976d2; } + +progress.secondary { + --progress-fore-color: #d32f2f; } + +progress.tertiary { + --progress-fore-color: #308732; } + +.spinner.primary { + --spinner-fore-color: #1976d2; } + +.spinner.secondary { + --spinner-fore-color: #d32f2f; } + +.spinner.tertiary { + --spinner-fore-color: #308732; } + +/* + Definitions for icons - powered by Feather (https://feathericons.com/). +*/ +span[class^='icon-'] { + display: inline-block; + height: 1em; + width: 1em; + vertical-align: -0.125em; + background-size: contain; + margin: 0 calc(var(--universal-margin) / 4); } + span[class^='icon-'].secondary { + -webkit-filter: invert(25%); + filter: invert(25%); } + span[class^='icon-'].inverse { + -webkit-filter: invert(100%); + filter: invert(100%); } + +span.icon-alert { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='8' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='16' x2='12' y2='16'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-bookmark { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M19 21l-7-5-7 5V5a2 2 0 0 1 2-2h10a2 2 0 0 1 2 2z'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-calendar { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='4' width='18' height='18' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='16' y1='2' x2='16' y2='6'%3E%3C/line%3E%3Cline x1='8' y1='2' x2='8' y2='6'%3E%3C/line%3E%3Cline x1='3' y1='10' x2='21' y2='10'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-credit { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='1' y='4' width='22' height='16' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='1' y1='10' x2='23' y2='10'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-edit { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 14.66V20a2 2 0 0 1-2 2H4a2 2 0 0 1-2-2V6a2 2 0 0 1 2-2h5.34'%3E%3C/path%3E%3Cpolygon points='18 2 22 6 12 16 8 16 8 12 18 2'%3E%3C/polygon%3E%3C/svg%3E"); } +span.icon-link { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M18 13v6a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2V8a2 2 0 0 1 2-2h6'%3E%3C/path%3E%3Cpolyline points='15 3 21 3 21 9'%3E%3C/polyline%3E%3Cline x1='10' y1='14' x2='21' y2='3'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-help { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M9.09 9a3 3 0 0 1 5.83 1c0 2-3 3-3 3'%3E%3C/path%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='17' x2='12' y2='17'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-home { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M3 9l9-7 9 7v11a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2z'%3E%3C/path%3E%3Cpolyline points='9 22 9 12 15 12 15 22'%3E%3C/polyline%3E%3C/svg%3E"); } +span.icon-info { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='16' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='8' x2='12' y2='8'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-lock { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='11' width='18' height='11' rx='2' ry='2'%3E%3C/rect%3E%3Cpath d='M7 11V7a5 5 0 0 1 10 0v4'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-mail { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 4h16c1.1 0 2 .9 2 2v12c0 1.1-.9 2-2 2H4c-1.1 0-2-.9-2-2V6c0-1.1.9-2 2-2z'%3E%3C/path%3E%3Cpolyline points='22,6 12,13 2,6'%3E%3C/polyline%3E%3C/svg%3E"); } +span.icon-location { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 10c0 7-9 13-9 13s-9-6-9-13a9 9 0 0 1 18 0z'%3E%3C/path%3E%3Ccircle cx='12' cy='10' r='3'%3E%3C/circle%3E%3C/svg%3E"); } +span.icon-phone { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M22 16.92v3a2 2 0 0 1-2.18 2 19.79 19.79 0 0 1-8.63-3.07 19.5 19.5 0 0 1-6-6 19.79 19.79 0 0 1-3.07-8.67A2 2 0 0 1 4.11 2h3a2 2 0 0 1 2 1.72 12.84 12.84 0 0 0 .7 2.81 2 2 0 0 1-.45 2.11L8.09 9.91a16 16 0 0 0 6 6l1.27-1.27a2 2 0 0 1 2.11-.45 12.84 12.84 0 0 0 2.81.7A2 2 0 0 1 22 16.92z'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-rss { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 11a9 9 0 0 1 9 9'%3E%3C/path%3E%3Cpath d='M4 4a16 16 0 0 1 16 16'%3E%3C/path%3E%3Ccircle cx='5' cy='19' r='1'%3E%3C/circle%3E%3C/svg%3E"); } +span.icon-search { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='11' cy='11' r='8'%3E%3C/circle%3E%3Cline x1='21' y1='21' x2='16.65' y2='16.65'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-settings { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='3'%3E%3C/circle%3E%3Cpath d='M19.4 15a1.65 1.65 0 0 0 .33 1.82l.06.06a2 2 0 0 1 0 2.83 2 2 0 0 1-2.83 0l-.06-.06a1.65 1.65 0 0 0-1.82-.33 1.65 1.65 0 0 0-1 1.51V21a2 2 0 0 1-2 2 2 2 0 0 1-2-2v-.09A1.65 1.65 0 0 0 9 19.4a1.65 1.65 0 0 0-1.82.33l-.06.06a2 2 0 0 1-2.83 0 2 2 0 0 1 0-2.83l.06-.06a1.65 1.65 0 0 0 .33-1.82 1.65 1.65 0 0 0-1.51-1H3a2 2 0 0 1-2-2 2 2 0 0 1 2-2h.09A1.65 1.65 0 0 0 4.6 9a1.65 1.65 0 0 0-.33-1.82l-.06-.06a2 2 0 0 1 0-2.83 2 2 0 0 1 2.83 0l.06.06a1.65 1.65 0 0 0 1.82.33H9a1.65 1.65 0 0 0 1-1.51V3a2 2 0 0 1 2-2 2 2 0 0 1 2 2v.09a1.65 1.65 0 0 0 1 1.51 1.65 1.65 0 0 0 1.82-.33l.06-.06a2 2 0 0 1 2.83 0 2 2 0 0 1 0 2.83l-.06.06a1.65 1.65 0 0 0-.33 1.82V9a1.65 1.65 0 0 0 1.51 1H21a2 2 0 0 1 2 2 2 2 0 0 1-2 2h-.09a1.65 1.65 0 0 0-1.51 1z'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-share { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='18' cy='5' r='3'%3E%3C/circle%3E%3Ccircle cx='6' cy='12' r='3'%3E%3C/circle%3E%3Ccircle cx='18' cy='19' r='3'%3E%3C/circle%3E%3Cline x1='8.59' y1='13.51' x2='15.42' y2='17.49'%3E%3C/line%3E%3Cline x1='15.41' y1='6.51' x2='8.59' y2='10.49'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-cart { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='9' cy='21' r='1'%3E%3C/circle%3E%3Ccircle cx='20' cy='21' r='1'%3E%3C/circle%3E%3Cpath d='M1 1h4l2.68 13.39a2 2 0 0 0 2 1.61h9.72a2 2 0 0 0 2-1.61L23 6H6'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-upload { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 15v4a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2v-4'%3E%3C/path%3E%3Cpolyline points='17 8 12 3 7 8'%3E%3C/polyline%3E%3Cline x1='12' y1='3' x2='12' y2='15'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-user { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 21v-2a4 4 0 0 0-4-4H8a4 4 0 0 0-4 4v2'%3E%3C/path%3E%3Ccircle cx='12' cy='7' r='4'%3E%3C/circle%3E%3C/svg%3E"); } + +/* + Definitions for utilities and helper classes. +*/ +/* Utility module CSS variable definitions */ +:root { + --generic-border-color: rgba(0, 0, 0, 0.3); + --generic-box-shadow: 0 0.25rem 0.25rem 0 rgba(0, 0, 0, 0.125), 0 0.125rem 0.125rem -0.125rem rgba(0, 0, 0, 0.25); } + +.hidden { + display: none !important; } + +.visually-hidden { + position: absolute !important; + width: 1px !important; + height: 1px !important; + margin: -1px !important; + border: 0 !important; + padding: 0 !important; + clip: rect(0 0 0 0) !important; + -webkit-clip-path: inset(100%) !important; + clip-path: inset(100%) !important; + overflow: hidden !important; } + +.bordered { + border: 0.0625rem solid var(--generic-border-color) !important; } + +.rounded { + border-radius: var(--universal-border-radius) !important; } + +.circular { + border-radius: 50% !important; } + +.shadowed { + box-shadow: var(--generic-box-shadow) !important; } + +.responsive-margin { + margin: calc(var(--universal-margin) / 4) !important; } + @media screen and (min-width: 500px) { + .responsive-margin { + margin: calc(var(--universal-margin) / 2) !important; } } + @media screen and (min-width: 1280px) { + .responsive-margin { + margin: var(--universal-margin) !important; } } + +.responsive-padding { + padding: calc(var(--universal-padding) / 4) !important; } + @media screen and (min-width: 500px) { + .responsive-padding { + padding: calc(var(--universal-padding) / 2) !important; } } + @media screen and (min-width: 1280px) { + .responsive-padding { + padding: var(--universal-padding) !important; } } + +@media screen and (max-width: 499px) { + .hidden-sm { + display: none !important; } } +@media screen and (min-width: 500px) and (max-width: 1279px) { + .hidden-md { + display: none !important; } } +@media screen and (min-width: 1280px) { + .hidden-lg { + display: none !important; } } +@media screen and (max-width: 499px) { + .visually-hidden-sm { + position: absolute !important; + width: 1px !important; + height: 1px !important; + margin: -1px !important; + border: 0 !important; + padding: 0 !important; + clip: rect(0 0 0 0) !important; + -webkit-clip-path: inset(100%) !important; + clip-path: inset(100%) !important; + overflow: hidden !important; } } +@media screen and (min-width: 500px) and (max-width: 1279px) { + .visually-hidden-md { + position: absolute !important; + width: 1px !important; + height: 1px !important; + margin: -1px !important; + border: 0 !important; + padding: 0 !important; + clip: rect(0 0 0 0) !important; + -webkit-clip-path: inset(100%) !important; + clip-path: inset(100%) !important; + overflow: hidden !important; } } +@media screen and (min-width: 1280px) { + .visually-hidden-lg { + position: absolute !important; + width: 1px !important; + height: 1px !important; + margin: -1px !important; + border: 0 !important; + padding: 0 !important; + clip: rect(0 0 0 0) !important; + -webkit-clip-path: inset(100%) !important; + clip-path: inset(100%) !important; + overflow: hidden !important; } } + +/*# sourceMappingURL=mini-default.css.map */ diff --git a/system/Drivers/STM32F7xx_HAL_Driver/_htmresc/st_logo.png b/system/Drivers/STM32F7xx_HAL_Driver/_htmresc/st_logo.png new file mode 100644 index 0000000000..8b80057fd3 Binary files /dev/null and b/system/Drivers/STM32F7xx_HAL_Driver/_htmresc/st_logo.png differ diff --git a/system/Drivers/STM32YYxx_HAL_Driver_version.md b/system/Drivers/STM32YYxx_HAL_Driver_version.md index 7417c0aea4..139edeb689 100644 --- a/system/Drivers/STM32YYxx_HAL_Driver_version.md +++ b/system/Drivers/STM32YYxx_HAL_Driver_version.md @@ -4,8 +4,8 @@ * STM32F1: 1.1.4 * STM32F2: 1.2.4 * STM32F3: 1.5.3 - * STM32F4: 1.7.7 - * STM32F7: 1.2.7 + * STM32F4: 1.7.8 + * STM32F7: 1.2.8 * STM32G0: 1.3.0 * STM32G4: 1.1.1 * STM32H7: 1.8.0 diff --git a/system/Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Inc/usbd_audio.h b/system/Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Inc/usbd_audio.h index df6e63bdf1..dbb71cd7ad 100644 --- a/system/Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Inc/usbd_audio.h +++ b/system/Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Inc/usbd_audio.h @@ -50,6 +50,14 @@ extern "C" { #define USBD_MAX_NUM_INTERFACES 1U #endif /* USBD_AUDIO_FREQ */ +#ifndef AUDIO_HS_BINTERVAL +#define AUDIO_HS_BINTERVAL 0x01U +#endif /* AUDIO_HS_BINTERVAL */ + +#ifndef AUDIO_FS_BINTERVAL +#define AUDIO_FS_BINTERVAL 0x01U +#endif /* AUDIO_FS_BINTERVAL */ + #define AUDIO_OUT_EP 0x01U #define USB_AUDIO_CONFIG_DESC_SIZ 0x6DU #define AUDIO_INTERFACE_DESC_SIZE 0x09U @@ -91,6 +99,9 @@ extern "C" { #define AUDIO_OUT_STREAMING_CTRL 0x02U +#define AUDIO_OUT_TC 0x01U +#define AUDIO_IN_TC 0x02U + #define AUDIO_OUT_PACKET (uint16_t)(((USBD_AUDIO_FREQ * 2U * 2U) / 1000U)) #define AUDIO_DEFAULT_VOLUME 70U @@ -116,8 +127,7 @@ typedef enum AUDIO_OFFSET_HALF, AUDIO_OFFSET_FULL, AUDIO_OFFSET_UNKNOWN, -} -AUDIO_OffsetTypeDef; +} AUDIO_OffsetTypeDef; /** * @} */ @@ -132,32 +142,29 @@ typedef struct uint8_t data[USB_MAX_EP0_SIZE]; uint8_t len; uint8_t unit; -} -USBD_AUDIO_ControlTypeDef; - +} USBD_AUDIO_ControlTypeDef; typedef struct { - uint32_t alt_setting; - uint8_t buffer[AUDIO_TOTAL_BUF_SIZE]; - AUDIO_OffsetTypeDef offset; - uint8_t rd_enable; - uint16_t rd_ptr; - uint16_t wr_ptr; + uint32_t alt_setting; + uint8_t buffer[AUDIO_TOTAL_BUF_SIZE]; + AUDIO_OffsetTypeDef offset; + uint8_t rd_enable; + uint16_t rd_ptr; + uint16_t wr_ptr; USBD_AUDIO_ControlTypeDef control; -} -USBD_AUDIO_HandleTypeDef; +} USBD_AUDIO_HandleTypeDef; typedef struct { - int8_t (*Init)(uint32_t AudioFreq, uint32_t Volume, uint32_t options); + int8_t (*Init)(uint32_t AudioFreq, uint32_t Volume, uint32_t options); int8_t (*DeInit)(uint32_t options); int8_t (*AudioCmd)(uint8_t *pbuf, uint32_t size, uint8_t cmd); int8_t (*VolumeCtl)(uint8_t vol); int8_t (*MuteCtl)(uint8_t cmd); - int8_t (*PeriodicTC)(uint8_t cmd); + int8_t (*PeriodicTC)(uint8_t *pbuf, uint32_t size, uint8_t cmd); int8_t (*GetState)(void); } USBD_AUDIO_ItfTypeDef; /** @@ -178,8 +185,8 @@ typedef struct * @{ */ -extern USBD_ClassTypeDef USBD_AUDIO; -#define USBD_AUDIO_CLASS &USBD_AUDIO +extern USBD_ClassTypeDef USBD_AUDIO; +#define USBD_AUDIO_CLASS &USBD_AUDIO /** * @} */ @@ -187,10 +194,10 @@ extern USBD_ClassTypeDef USBD_AUDIO; /** @defgroup USB_CORE_Exported_Functions * @{ */ -uint8_t USBD_AUDIO_RegisterInterface(USBD_HandleTypeDef *pdev, - USBD_AUDIO_ItfTypeDef *fops); +uint8_t USBD_AUDIO_RegisterInterface(USBD_HandleTypeDef *pdev, + USBD_AUDIO_ItfTypeDef *fops); -void USBD_AUDIO_Sync(USBD_HandleTypeDef *pdev, AUDIO_OffsetTypeDef offset); +void USBD_AUDIO_Sync(USBD_HandleTypeDef *pdev, AUDIO_OffsetTypeDef offset); /** * @} */ diff --git a/system/Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c b/system/Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c index 877b5f7b1b..1dce51a31a 100644 --- a/system/Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c +++ b/system/Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio.c @@ -133,7 +133,7 @@ static void AUDIO_REQ_SetCurrent(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef * @{ */ -USBD_ClassTypeDef USBD_AUDIO = +USBD_ClassTypeDef USBD_AUDIO = { USBD_AUDIO_Init, USBD_AUDIO_DeInit, @@ -231,8 +231,8 @@ __ALIGN_BEGIN static uint8_t USBD_AUDIO_CfgDesc[USB_AUDIO_CONFIG_DESC_SIZ] __ALI /* USB Speaker Standard AS Interface Descriptor - Audio Streaming Zero Bandwith */ /* Interface 1, Alternate Setting 0 */ - AUDIO_INTERFACE_DESC_SIZE, /* bLength */ - USB_DESC_TYPE_INTERFACE, /* bDescriptorType */ + AUDIO_INTERFACE_DESC_SIZE, /* bLength */ + USB_DESC_TYPE_INTERFACE, /* bDescriptorType */ 0x01, /* bInterfaceNumber */ 0x00, /* bAlternateSetting */ 0x00, /* bNumEndpoints */ @@ -244,8 +244,8 @@ __ALIGN_BEGIN static uint8_t USBD_AUDIO_CfgDesc[USB_AUDIO_CONFIG_DESC_SIZ] __ALI /* USB Speaker Standard AS Interface Descriptor - Audio Streaming Operational */ /* Interface 1, Alternate Setting 1 */ - AUDIO_INTERFACE_DESC_SIZE, /* bLength */ - USB_DESC_TYPE_INTERFACE, /* bDescriptorType */ + AUDIO_INTERFACE_DESC_SIZE, /* bLength */ + USB_DESC_TYPE_INTERFACE, /* bDescriptorType */ 0x01, /* bInterfaceNumber */ 0x01, /* bAlternateSetting */ 0x01, /* bNumEndpoints */ @@ -261,7 +261,7 @@ __ALIGN_BEGIN static uint8_t USBD_AUDIO_CfgDesc[USB_AUDIO_CONFIG_DESC_SIZ] __ALI AUDIO_STREAMING_GENERAL, /* bDescriptorSubtype */ 0x01, /* bTerminalLink */ 0x01, /* bDelay */ - 0x01, /* wFormatTag AUDIO_FORMAT_PCM 0x0001*/ + 0x01, /* wFormatTag AUDIO_FORMAT_PCM 0x0001 */ 0x00, /* 07 byte*/ @@ -269,21 +269,21 @@ __ALIGN_BEGIN static uint8_t USBD_AUDIO_CfgDesc[USB_AUDIO_CONFIG_DESC_SIZ] __ALI 0x0B, /* bLength */ AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ AUDIO_STREAMING_FORMAT_TYPE, /* bDescriptorSubtype */ - AUDIO_FORMAT_TYPE_I, /* bFormatType */ + AUDIO_FORMAT_TYPE_I, /* bFormatType */ 0x02, /* bNrChannels */ 0x02, /* bSubFrameSize : 2 Bytes per frame (16bits) */ 16, /* bBitResolution (16-bits per sample) */ 0x01, /* bSamFreqType only one frequency supported */ - AUDIO_SAMPLE_FREQ(USBD_AUDIO_FREQ), /* Audio sampling frequency coded on 3 bytes */ + AUDIO_SAMPLE_FREQ(USBD_AUDIO_FREQ), /* Audio sampling frequency coded on 3 bytes */ /* 11 byte*/ /* Endpoint 1 - Standard Descriptor */ AUDIO_STANDARD_ENDPOINT_DESC_SIZE, /* bLength */ USB_DESC_TYPE_ENDPOINT, /* bDescriptorType */ - AUDIO_OUT_EP, /* bEndpointAddress 1 out endpoint*/ + AUDIO_OUT_EP, /* bEndpointAddress 1 out endpoint */ USBD_EP_TYPE_ISOC, /* bmAttributes */ AUDIO_PACKET_SZE(USBD_AUDIO_FREQ), /* wMaxPacketSize in Bytes (Freq(Samples)*2(Stereo)*2(HalfWord)) */ - 0x01, /* bInterval */ + AUDIO_FS_BINTERVAL, /* bInterval */ 0x00, /* bRefresh */ 0x00, /* bSynchAddress */ /* 09 byte*/ @@ -329,44 +329,54 @@ __ALIGN_BEGIN static uint8_t USBD_AUDIO_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIE * @param cfgidx: Configuration index * @retval status */ -static uint8_t USBD_AUDIO_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx) +static uint8_t USBD_AUDIO_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { - USBD_AUDIO_HandleTypeDef *haudio; + UNUSED(cfgidx); + USBD_AUDIO_HandleTypeDef *haudio; - /* Open EP OUT */ - USBD_LL_OpenEP(pdev, AUDIO_OUT_EP, USBD_EP_TYPE_ISOC, AUDIO_OUT_PACKET); - pdev->ep_out[AUDIO_OUT_EP & 0xFU].is_used = 1U; + /* Allocate Audio structure */ + haudio = USBD_malloc(sizeof(USBD_AUDIO_HandleTypeDef)); + + if (haudio == NULL) + { + pdev->pClassData = NULL; + return (uint8_t)USBD_EMEM; + } - /* Allocate Audio structure */ - pdev->pClassData = USBD_malloc(sizeof(USBD_AUDIO_HandleTypeDef)); + pdev->pClassData = (void *)haudio; - if (pdev->pClassData == NULL) + if (pdev->dev_speed == USBD_SPEED_HIGH) { - return USBD_FAIL; + pdev->ep_out[AUDIO_OUT_EP & 0xFU].bInterval = AUDIO_HS_BINTERVAL; } - else + else /* LOW and FULL-speed endpoints */ { - haudio = (USBD_AUDIO_HandleTypeDef *) pdev->pClassData; - haudio->alt_setting = 0U; - haudio->offset = AUDIO_OFFSET_UNKNOWN; - haudio->wr_ptr = 0U; - haudio->rd_ptr = 0U; - haudio->rd_enable = 0U; - - /* Initialize the Audio output Hardware layer */ - if (((USBD_AUDIO_ItfTypeDef *)pdev->pUserData)->Init(USBD_AUDIO_FREQ, - AUDIO_DEFAULT_VOLUME, - 0U) != 0) - { - return USBD_FAIL; - } + pdev->ep_out[AUDIO_OUT_EP & 0xFU].bInterval = AUDIO_FS_BINTERVAL; + } + + /* Open EP OUT */ + (void)USBD_LL_OpenEP(pdev, AUDIO_OUT_EP, USBD_EP_TYPE_ISOC, AUDIO_OUT_PACKET); + pdev->ep_out[AUDIO_OUT_EP & 0xFU].is_used = 1U; + + haudio->alt_setting = 0U; + haudio->offset = AUDIO_OFFSET_UNKNOWN; + haudio->wr_ptr = 0U; + haudio->rd_ptr = 0U; + haudio->rd_enable = 0U; - /* Prepare Out endpoint to receive 1st packet */ - USBD_LL_PrepareReceive(pdev, AUDIO_OUT_EP, haudio->buffer, - AUDIO_OUT_PACKET); + /* Initialize the Audio output Hardware layer */ + if (((USBD_AUDIO_ItfTypeDef *)pdev->pUserData)->Init(USBD_AUDIO_FREQ, + AUDIO_DEFAULT_VOLUME, + 0U) != 0U) + { + return (uint8_t)USBD_FAIL; } - return USBD_OK; + /* Prepare Out endpoint to receive 1st packet */ + (void)USBD_LL_PrepareReceive(pdev, AUDIO_OUT_EP, haudio->buffer, + AUDIO_OUT_PACKET); + + return (uint8_t)USBD_OK; } /** @@ -376,22 +386,24 @@ static uint8_t USBD_AUDIO_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx) * @param cfgidx: Configuration index * @retval status */ -static uint8_t USBD_AUDIO_DeInit(USBD_HandleTypeDef *pdev, - uint8_t cfgidx) +static uint8_t USBD_AUDIO_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { + UNUSED(cfgidx); + /* Open EP OUT */ - USBD_LL_CloseEP(pdev, AUDIO_OUT_EP); + (void)USBD_LL_CloseEP(pdev, AUDIO_OUT_EP); pdev->ep_out[AUDIO_OUT_EP & 0xFU].is_used = 0U; + pdev->ep_out[AUDIO_OUT_EP & 0xFU].bInterval = 0U; /* DeInit physical Interface components */ if (pdev->pClassData != NULL) { ((USBD_AUDIO_ItfTypeDef *)pdev->pUserData)->DeInit(0U); - USBD_free(pdev->pClassData); + (void)USBD_free(pdev->pClassData); pdev->pClassData = NULL; } - return USBD_OK; + return (uint8_t)USBD_OK; } /** @@ -401,108 +413,111 @@ static uint8_t USBD_AUDIO_DeInit(USBD_HandleTypeDef *pdev, * @param req: usb requests * @retval status */ -static uint8_t USBD_AUDIO_Setup(USBD_HandleTypeDef *pdev, - USBD_SetupReqTypedef *req) +static uint8_t USBD_AUDIO_Setup(USBD_HandleTypeDef *pdev, + USBD_SetupReqTypedef *req) { USBD_AUDIO_HandleTypeDef *haudio; uint16_t len; uint8_t *pbuf; uint16_t status_info = 0U; - uint8_t ret = USBD_OK; + USBD_StatusTypeDef ret = USBD_OK; haudio = (USBD_AUDIO_HandleTypeDef *)pdev->pClassData; switch (req->bmRequest & USB_REQ_TYPE_MASK) { - case USB_REQ_TYPE_CLASS : - switch (req->bRequest) + case USB_REQ_TYPE_CLASS: + switch (req->bRequest) + { + case AUDIO_REQ_GET_CUR: + AUDIO_REQ_GetCurrent(pdev, req); + break; + + case AUDIO_REQ_SET_CUR: + AUDIO_REQ_SetCurrent(pdev, req); + break; + + default: + USBD_CtlError(pdev, req); + ret = USBD_FAIL; + break; + } + break; + + case USB_REQ_TYPE_STANDARD: + switch (req->bRequest) + { + case USB_REQ_GET_STATUS: + if (pdev->dev_state == USBD_STATE_CONFIGURED) + { + (void)USBD_CtlSendData(pdev, (uint8_t *)&status_info, 2U); + } + else + { + USBD_CtlError(pdev, req); + ret = USBD_FAIL; + } + break; + + case USB_REQ_GET_DESCRIPTOR: + if ((req->wValue >> 8) == AUDIO_DESCRIPTOR_TYPE) { - case AUDIO_REQ_GET_CUR: - AUDIO_REQ_GetCurrent(pdev, req); - break; + pbuf = USBD_AUDIO_CfgDesc + 18; + len = MIN(USB_AUDIO_DESC_SIZ, req->wLength); - case AUDIO_REQ_SET_CUR: - AUDIO_REQ_SetCurrent(pdev, req); - break; + (void)USBD_CtlSendData(pdev, pbuf, len); + } + break; - default: - USBD_CtlError(pdev, req); - ret = USBD_FAIL; - break; + case USB_REQ_GET_INTERFACE: + if (pdev->dev_state == USBD_STATE_CONFIGURED) + { + (void)USBD_CtlSendData(pdev, (uint8_t *)&haudio->alt_setting, 1U); + } + else + { + USBD_CtlError(pdev, req); + ret = USBD_FAIL; } break; - case USB_REQ_TYPE_STANDARD: - switch (req->bRequest) + case USB_REQ_SET_INTERFACE: + if (pdev->dev_state == USBD_STATE_CONFIGURED) { - case USB_REQ_GET_STATUS: - if (pdev->dev_state == USBD_STATE_CONFIGURED) - { - USBD_CtlSendData(pdev, (uint8_t *)(void *)&status_info, 2U); - } - else - { - USBD_CtlError(pdev, req); - ret = USBD_FAIL; - } - break; - - case USB_REQ_GET_DESCRIPTOR: - if ((req->wValue >> 8) == AUDIO_DESCRIPTOR_TYPE) - { - pbuf = USBD_AUDIO_CfgDesc + 18; - len = MIN(USB_AUDIO_DESC_SIZ, req->wLength); - - USBD_CtlSendData(pdev, pbuf, len); - } - break; - - case USB_REQ_GET_INTERFACE : - if (pdev->dev_state == USBD_STATE_CONFIGURED) - { - USBD_CtlSendData(pdev, (uint8_t *)(void *)&haudio->alt_setting, 1U); - } - else - { - USBD_CtlError(pdev, req); - ret = USBD_FAIL; - } - break; - - case USB_REQ_SET_INTERFACE : - if (pdev->dev_state == USBD_STATE_CONFIGURED) - { - if ((uint8_t)(req->wValue) <= USBD_MAX_NUM_INTERFACES) - { - haudio->alt_setting = (uint8_t)(req->wValue); - } - else - { - /* Call the error management function (command will be nacked */ - USBD_CtlError(pdev, req); - ret = USBD_FAIL; - } - } - else - { - USBD_CtlError(pdev, req); - ret = USBD_FAIL; - } - break; - - default: + if ((uint8_t)(req->wValue) <= USBD_MAX_NUM_INTERFACES) + { + haudio->alt_setting = (uint8_t)(req->wValue); + } + else + { + /* Call the error management function (command will be nacked */ USBD_CtlError(pdev, req); ret = USBD_FAIL; - break; + } + } + else + { + USBD_CtlError(pdev, req); + ret = USBD_FAIL; } break; + + case USB_REQ_CLEAR_FEATURE: + break; + default: USBD_CtlError(pdev, req); ret = USBD_FAIL; break; + } + break; + default: + USBD_CtlError(pdev, req); + ret = USBD_FAIL; + break; } - return ret; + return (uint8_t)ret; } @@ -513,9 +528,9 @@ static uint8_t USBD_AUDIO_Setup(USBD_HandleTypeDef *pdev, * @param length : pointer data length * @retval pointer to descriptor buffer */ -static uint8_t *USBD_AUDIO_GetCfgDesc(uint16_t *length) +static uint8_t *USBD_AUDIO_GetCfgDesc(uint16_t *length) { - *length = sizeof(USBD_AUDIO_CfgDesc); + *length = (uint16_t)sizeof(USBD_AUDIO_CfgDesc); return USBD_AUDIO_CfgDesc; } @@ -527,10 +542,13 @@ static uint8_t *USBD_AUDIO_GetCfgDesc(uint16_t *length) * @param epnum: endpoint index * @retval status */ -static uint8_t USBD_AUDIO_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum) +static uint8_t USBD_AUDIO_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum) { + UNUSED(pdev); + UNUSED(epnum); + /* Only OUT data are processed */ - return USBD_OK; + return (uint8_t)USBD_OK; } /** @@ -539,10 +557,10 @@ static uint8_t USBD_AUDIO_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum) * @param pdev: device instance * @retval status */ -static uint8_t USBD_AUDIO_EP0_RxReady(USBD_HandleTypeDef *pdev) +static uint8_t USBD_AUDIO_EP0_RxReady(USBD_HandleTypeDef *pdev) { - USBD_AUDIO_HandleTypeDef *haudio; - haudio = (USBD_AUDIO_HandleTypeDef *) pdev->pClassData; + USBD_AUDIO_HandleTypeDef *haudio; + haudio = (USBD_AUDIO_HandleTypeDef *)pdev->pClassData; if (haudio->control.cmd == AUDIO_REQ_SET_CUR) { @@ -556,7 +574,7 @@ static uint8_t USBD_AUDIO_EP0_RxReady(USBD_HandleTypeDef *pdev) } } - return USBD_OK; + return (uint8_t)USBD_OK; } /** * @brief USBD_AUDIO_EP0_TxReady @@ -564,10 +582,12 @@ static uint8_t USBD_AUDIO_EP0_RxReady(USBD_HandleTypeDef *pdev) * @param pdev: device instance * @retval status */ -static uint8_t USBD_AUDIO_EP0_TxReady(USBD_HandleTypeDef *pdev) +static uint8_t USBD_AUDIO_EP0_TxReady(USBD_HandleTypeDef *pdev) { + UNUSED(pdev); + /* Only OUT control data are processed */ - return USBD_OK; + return (uint8_t)USBD_OK; } /** * @brief USBD_AUDIO_SOF @@ -575,9 +595,11 @@ static uint8_t USBD_AUDIO_EP0_TxReady(USBD_HandleTypeDef *pdev) * @param pdev: device instance * @retval status */ -static uint8_t USBD_AUDIO_SOF(USBD_HandleTypeDef *pdev) +static uint8_t USBD_AUDIO_SOF(USBD_HandleTypeDef *pdev) { - return USBD_OK; + UNUSED(pdev); + + return (uint8_t)USBD_OK; } /** @@ -586,17 +608,23 @@ static uint8_t USBD_AUDIO_SOF(USBD_HandleTypeDef *pdev) * @param pdev: device instance * @retval status */ -void USBD_AUDIO_Sync(USBD_HandleTypeDef *pdev, AUDIO_OffsetTypeDef offset) +void USBD_AUDIO_Sync(USBD_HandleTypeDef *pdev, AUDIO_OffsetTypeDef offset) { - uint32_t cmd = 0U; - USBD_AUDIO_HandleTypeDef *haudio; - haudio = (USBD_AUDIO_HandleTypeDef *) pdev->pClassData; + USBD_AUDIO_HandleTypeDef *haudio; + uint32_t BufferSize = AUDIO_TOTAL_BUF_SIZE / 2U; + + if (pdev->pClassData == NULL) + { + return; + } - haudio->offset = offset; + haudio = (USBD_AUDIO_HandleTypeDef *)pdev->pClassData; + + haudio->offset = offset; if (haudio->rd_enable == 1U) { - haudio->rd_ptr += (uint16_t)(AUDIO_TOTAL_BUF_SIZE / 2U); + haudio->rd_ptr += (uint16_t)BufferSize; if (haudio->rd_ptr == AUDIO_TOTAL_BUF_SIZE) { @@ -609,13 +637,13 @@ void USBD_AUDIO_Sync(USBD_HandleTypeDef *pdev, AUDIO_OffsetTypeDef offset) { if ((haudio->rd_ptr - haudio->wr_ptr) < AUDIO_OUT_PACKET) { - cmd = AUDIO_TOTAL_BUF_SIZE / 2U + 4U; + BufferSize += 4U; } else { if ((haudio->rd_ptr - haudio->wr_ptr) > (AUDIO_TOTAL_BUF_SIZE - AUDIO_OUT_PACKET)) { - cmd = AUDIO_TOTAL_BUF_SIZE / 2U - 4U; + BufferSize -= 4U; } } } @@ -623,13 +651,13 @@ void USBD_AUDIO_Sync(USBD_HandleTypeDef *pdev, AUDIO_OffsetTypeDef offset) { if ((haudio->wr_ptr - haudio->rd_ptr) < AUDIO_OUT_PACKET) { - cmd = AUDIO_TOTAL_BUF_SIZE / 2U - 4U; + BufferSize -= 4U; } else { if ((haudio->wr_ptr - haudio->rd_ptr) > (AUDIO_TOTAL_BUF_SIZE - AUDIO_OUT_PACKET)) { - cmd = AUDIO_TOTAL_BUF_SIZE / 2U + 4U; + BufferSize += 4U; } } } @@ -637,8 +665,7 @@ void USBD_AUDIO_Sync(USBD_HandleTypeDef *pdev, AUDIO_OffsetTypeDef offset) if (haudio->offset == AUDIO_OFFSET_FULL) { ((USBD_AUDIO_ItfTypeDef *)pdev->pUserData)->AudioCmd(&haudio->buffer[0], - cmd, - AUDIO_CMD_PLAY); + BufferSize, AUDIO_CMD_PLAY); haudio->offset = AUDIO_OFFSET_NONE; } } @@ -650,9 +677,12 @@ void USBD_AUDIO_Sync(USBD_HandleTypeDef *pdev, AUDIO_OffsetTypeDef offset) * @param epnum: endpoint index * @retval status */ -static uint8_t USBD_AUDIO_IsoINIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum) +static uint8_t USBD_AUDIO_IsoINIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum) { - return USBD_OK; + UNUSED(pdev); + UNUSED(epnum); + + return (uint8_t)USBD_OK; } /** * @brief USBD_AUDIO_IsoOutIncomplete @@ -661,9 +691,12 @@ static uint8_t USBD_AUDIO_IsoINIncomplete(USBD_HandleTypeDef *pdev, uint8_t epn * @param epnum: endpoint index * @retval status */ -static uint8_t USBD_AUDIO_IsoOutIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum) +static uint8_t USBD_AUDIO_IsoOutIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum) { - return USBD_OK; + UNUSED(pdev); + UNUSED(epnum); + + return (uint8_t)USBD_OK; } /** * @brief USBD_AUDIO_DataOut @@ -672,16 +705,24 @@ static uint8_t USBD_AUDIO_IsoOutIncomplete(USBD_HandleTypeDef *pdev, uint8_t ep * @param epnum: endpoint index * @retval status */ -static uint8_t USBD_AUDIO_DataOut(USBD_HandleTypeDef *pdev, uint8_t epnum) +static uint8_t USBD_AUDIO_DataOut(USBD_HandleTypeDef *pdev, uint8_t epnum) { - USBD_AUDIO_HandleTypeDef *haudio; - haudio = (USBD_AUDIO_HandleTypeDef *) pdev->pClassData; + uint16_t PacketSize; + USBD_AUDIO_HandleTypeDef *haudio; + + haudio = (USBD_AUDIO_HandleTypeDef *)pdev->pClassData; if (epnum == AUDIO_OUT_EP) { - /* Increment the Buffer pointer or roll it back when all buffers are full */ + /* Get received data packet length */ + PacketSize = (uint16_t)USBD_LL_GetRxDataSize(pdev, epnum); - haudio->wr_ptr += AUDIO_OUT_PACKET; + /* Packet received Callback */ + ((USBD_AUDIO_ItfTypeDef *)pdev->pUserData)->PeriodicTC(&haudio->buffer[haudio->wr_ptr], + PacketSize, AUDIO_OUT_TC); + + /* Increment the Buffer pointer or roll it back when all buffers are full */ + haudio->wr_ptr += PacketSize; if (haudio->wr_ptr == AUDIO_TOTAL_BUF_SIZE) { @@ -706,11 +747,12 @@ static uint8_t USBD_AUDIO_DataOut(USBD_HandleTypeDef *pdev, uint8_t epnum) } /* Prepare Out endpoint to receive next audio packet */ - USBD_LL_PrepareReceive(pdev, AUDIO_OUT_EP, &haudio->buffer[haudio->wr_ptr], - AUDIO_OUT_PACKET); + (void)USBD_LL_PrepareReceive(pdev, AUDIO_OUT_EP, + &haudio->buffer[haudio->wr_ptr], + AUDIO_OUT_PACKET); } - return USBD_OK; + return (uint8_t)USBD_OK; } /** @@ -722,13 +764,13 @@ static uint8_t USBD_AUDIO_DataOut(USBD_HandleTypeDef *pdev, uint8_t epnum) */ static void AUDIO_REQ_GetCurrent(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { - USBD_AUDIO_HandleTypeDef *haudio; - haudio = (USBD_AUDIO_HandleTypeDef *) pdev->pClassData; + USBD_AUDIO_HandleTypeDef *haudio; + haudio = (USBD_AUDIO_HandleTypeDef *)pdev->pClassData; - memset(haudio->control.data, 0, 64U); + (void)USBD_memset(haudio->control.data, 0, 64U); /* Send the current mute state */ - USBD_CtlSendData(pdev, haudio->control.data, req->wLength); + (void)USBD_CtlSendData(pdev, haudio->control.data, req->wLength); } /** @@ -740,13 +782,13 @@ static void AUDIO_REQ_GetCurrent(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef */ static void AUDIO_REQ_SetCurrent(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { - USBD_AUDIO_HandleTypeDef *haudio; - haudio = (USBD_AUDIO_HandleTypeDef *) pdev->pClassData; + USBD_AUDIO_HandleTypeDef *haudio; + haudio = (USBD_AUDIO_HandleTypeDef *)pdev->pClassData; - if (req->wLength) + if (req->wLength != 0U) { /* Prepare the reception of the buffer over EP0 */ - USBD_CtlPrepareRx(pdev, haudio->control.data, req->wLength); + (void)USBD_CtlPrepareRx(pdev, haudio->control.data, req->wLength); haudio->control.cmd = AUDIO_REQ_SET_CUR; /* Set the request value */ haudio->control.len = (uint8_t)req->wLength; /* Set the request data length */ @@ -761,9 +803,9 @@ static void AUDIO_REQ_SetCurrent(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef * @param length : pointer data length * @retval pointer to descriptor buffer */ -static uint8_t *USBD_AUDIO_GetDeviceQualifierDesc(uint16_t *length) +static uint8_t *USBD_AUDIO_GetDeviceQualifierDesc(uint16_t *length) { - *length = sizeof(USBD_AUDIO_DeviceQualifierDesc); + *length = (uint16_t)sizeof(USBD_AUDIO_DeviceQualifierDesc); return USBD_AUDIO_DeviceQualifierDesc; } @@ -773,15 +815,17 @@ static uint8_t *USBD_AUDIO_GetDeviceQualifierDesc(uint16_t *length) * @param fops: Audio interface callback * @retval status */ -uint8_t USBD_AUDIO_RegisterInterface(USBD_HandleTypeDef *pdev, - USBD_AUDIO_ItfTypeDef *fops) +uint8_t USBD_AUDIO_RegisterInterface(USBD_HandleTypeDef *pdev, + USBD_AUDIO_ItfTypeDef *fops) { - if (fops != NULL) + if (fops == NULL) { - pdev->pUserData = fops; + return (uint8_t)USBD_FAIL; } - return USBD_OK; + pdev->pUserData = fops; + + return (uint8_t)USBD_OK; } /** * @} diff --git a/system/Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio_if_template.c b/system/Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio_if_template.c index 35515cc941..7c97c751ca 100644 --- a/system/Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio_if_template.c +++ b/system/Middlewares/ST/STM32_USB_Device_Library/Class/AUDIO/Src/usbd_audio_if_template.c @@ -70,7 +70,7 @@ static int8_t TEMPLATE_DeInit(uint32_t options); static int8_t TEMPLATE_AudioCmd(uint8_t *pbuf, uint32_t size, uint8_t cmd); static int8_t TEMPLATE_VolumeCtl(uint8_t vol); static int8_t TEMPLATE_MuteCtl(uint8_t cmd); -static int8_t TEMPLATE_PeriodicTC(uint8_t cmd); +static int8_t TEMPLATE_PeriodicTC(uint8_t *pbuf, uint32_t size, uint8_t cmd); static int8_t TEMPLATE_GetState(void); USBD_AUDIO_ItfTypeDef USBD_AUDIO_Template_fops = @@ -94,6 +94,10 @@ USBD_AUDIO_ItfTypeDef USBD_AUDIO_Template_fops = */ static int8_t TEMPLATE_Init(uint32_t AudioFreq, uint32_t Volume, uint32_t options) { + UNUSED(AudioFreq); + UNUSED(Volume); + UNUSED(options); + /* Add your initialization code here */ @@ -108,6 +112,8 @@ static int8_t TEMPLATE_Init(uint32_t AudioFreq, uint32_t Volume, uint32_t optio */ static int8_t TEMPLATE_DeInit(uint32_t options) { + UNUSED(options); + /* Add your deinitialization code here */ @@ -125,6 +131,10 @@ static int8_t TEMPLATE_DeInit(uint32_t options) */ static int8_t TEMPLATE_AudioCmd(uint8_t *pbuf, uint32_t size, uint8_t cmd) { + UNUSED(pbuf); + UNUSED(size); + UNUSED(cmd); + return (0); } @@ -135,6 +145,8 @@ static int8_t TEMPLATE_AudioCmd(uint8_t *pbuf, uint32_t size, uint8_t cmd) */ static int8_t TEMPLATE_VolumeCtl(uint8_t vol) { + UNUSED(vol); + return (0); } @@ -145,6 +157,8 @@ static int8_t TEMPLATE_VolumeCtl(uint8_t vol) */ static int8_t TEMPLATE_MuteCtl(uint8_t cmd) { + UNUSED(cmd); + return (0); } @@ -153,8 +167,12 @@ static int8_t TEMPLATE_MuteCtl(uint8_t cmd) * @param cmd * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL */ -static int8_t TEMPLATE_PeriodicTC(uint8_t cmd) +static int8_t TEMPLATE_PeriodicTC(uint8_t *pbuf, uint32_t size, uint8_t cmd) { + UNUSED(pbuf); + UNUSED(size); + UNUSED(cmd); + return (0); } diff --git a/system/Middlewares/ST/STM32_USB_Device_Library/Class/BillBoard/Inc/usbd_billboard.h b/system/Middlewares/ST/STM32_USB_Device_Library/Class/BillBoard/Inc/usbd_billboard.h new file mode 100644 index 0000000000..8bff7b3550 --- /dev/null +++ b/system/Middlewares/ST/STM32_USB_Device_Library/Class/BillBoard/Inc/usbd_billboard.h @@ -0,0 +1,163 @@ +/** + ****************************************************************************** + * @file usbd_billboard.h + * @author MCD Application Team + * @brief Header file for the usbd_billboard.c file. + ****************************************************************************** + * @attention + * + *

    © Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

    + * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USB_BB_H +#define __USB_BB_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_ioreq.h" +#include "usbd_desc.h" +/** @addtogroup STM32_USB_DEVICE_LIBRARY + * @{ + */ + +/** @defgroup USBD_BB + * @brief This file is the Header file for usbd_billboard.c + * @{ + */ + +/** @defgroup USBD_BB_Exported_Defines + * @{ + */ +#define USB_BB_CONFIG_DESC_SIZ 18U + +#ifndef USB_BB_MAX_NUM_ALT_MODE +#define USB_BB_MAX_NUM_ALT_MODE 0x2U +#endif /* USB_BB_MAX_NUM_ALT_MODE */ + +#ifndef USBD_BB_IF_STRING_INDEX +#define USBD_BB_IF_STRING_INDEX 0x10U +#endif /* USBD_BB_IF_STRING_INDEX */ + + +#define USBD_BILLBOARD_CAPABILITY 0x0DU +#define USBD_BILLBOARD_ALTMODE_CAPABILITY 0x0FU + +/** + * @} + */ + + +/** @defgroup USBD_CORE_Exported_TypesDefinitions + * @{ + */ +typedef struct _BB_DescHeader +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDevCapabilityType; +} +USBD_BB_DescHeader_t; + +typedef struct +{ + uint16_t wSVID; + uint8_t bAlternateMode; + uint8_t iAlternateModeString; +} USBD_BB_AltModeTypeDef; + +typedef struct +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDevCapabilityType; + uint8_t bIndex; + uint32_t dwAlternateModeVdo; +} USBD_BB_AltModeCapDescTypeDef; + +typedef struct +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDevCapabilityType; + uint8_t iAddtionalInfoURL; + uint8_t bNbrOfAltModes; + uint8_t bPreferredAltMode; + uint16_t VconnPwr; + uint8_t bmConfigured[32]; + uint16_t bcdVersion; + uint8_t bAdditionalFailureInfo; + uint8_t bReserved; + USBD_BB_AltModeTypeDef wSVID[USB_BB_MAX_NUM_ALT_MODE]; +} USBD_BosBBCapDescTypedef; + +typedef enum +{ + UNSPECIFIED_ERROR = 0, + CONFIGURATION_NOT_ATTEMPTED, + CONFIGURATION_UNSUCCESSFUL, + CONFIGURATION_SUCCESSFUL, +} BB_AltModeState; + +/** + * @} + */ + + + +/** @defgroup USBD_CORE_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup USBD_CORE_Exported_Variables + * @{ + */ + +extern USBD_ClassTypeDef USBD_BB; +#define USBD_BB_CLASS &USBD_BB +/** + * @} + */ + +/** @defgroup USB_CORE_Exported_Functions + * @{ + */ + +#if (USBD_CLASS_BOS_ENABLED == 1) +void *USBD_BB_GetCapDesc(USBD_HandleTypeDef *pdev, uint8_t *buf); +void *USBD_BB_GetAltModeDesc(USBD_HandleTypeDef *pdev, uint8_t *buf, uint8_t idx); +#endif + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_BB_H */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Middlewares/ST/STM32_USB_Device_Library/Class/BillBoard/Src/usbd_billboard.c b/system/Middlewares/ST/STM32_USB_Device_Library/Class/BillBoard/Src/usbd_billboard.c new file mode 100644 index 0000000000..b9e6d1906c --- /dev/null +++ b/system/Middlewares/ST/STM32_USB_Device_Library/Class/BillBoard/Src/usbd_billboard.c @@ -0,0 +1,496 @@ +/** + ****************************************************************************** + * @file usbd_billboard.c + * @author MCD Application Team + * @brief This file provides the high layer firmware functions to manage the + * following functionalities of the USB BillBoard Class: + * - Initialization and Configuration of high and low layer + * - Enumeration as BillBoard Device + * - Error management + * @verbatim + * + * =================================================================== + * BillBoard Class Description + * =================================================================== + * This module manages the BillBoard class V1.2.1 following the "Device Class Definition + * for BillBoard Devices (BB) Version R1.2.1 Sept 08, 2016". + * This driver implements the following aspects of the specification: + * - Device descriptor management + * - Configuration descriptor management + * - Enumeration as an USB BillBoard device + * - Enumeration & management of BillBoard device supported alternate modes + * + * @endverbatim + * + ****************************************************************************** + * @attention + * + *

    © Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

    + * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_billboard.h" +#include "usbd_ctlreq.h" + + +/** @addtogroup STM32_USB_DEVICE_LIBRARY + * @{ + */ + + +/** @defgroup USBD_BB + * @brief usbd core module + * @{ + */ + +/** @defgroup USBD_BB_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + + +/** @defgroup USBD_BB_Private_Defines + * @{ + */ + +/** + * @} + */ + + +/** @defgroup USBD_BB_Private_Macros + * @{ + */ +/** + * @} + */ + + +/** @defgroup USBD_BB_Private_FunctionPrototypes + * @{ + */ + +static uint8_t USBD_BB_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx); +static uint8_t USBD_BB_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx); +static uint8_t USBD_BB_Setup(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); +static uint8_t USBD_BB_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum); +static uint8_t USBD_BB_DataOut(USBD_HandleTypeDef *pdev, uint8_t epnum); +static uint8_t USBD_BB_EP0_RxReady(USBD_HandleTypeDef *pdev); + +static uint8_t *USBD_BB_GetCfgDesc(uint16_t *length); +static uint8_t *USBD_BB_GetDeviceQualifierDesc(uint16_t *length); +static uint8_t *USBD_BB_GetOtherSpeedCfgDesc(uint16_t *length); + +#if (USBD_CLASS_BOS_ENABLED == 1) +USBD_BB_DescHeader_t *USBD_BB_GetNextDesc(uint8_t *pbuf, uint16_t *ptr); +#endif + + + +/** + * @} + */ + +/** @defgroup USBD_BB_Private_Variables + * @{ + */ +USBD_ClassTypeDef USBD_BB = +{ + USBD_BB_Init, /* Init */ + USBD_BB_DeInit, /* DeInit */ + USBD_BB_Setup, /* Setup */ + NULL, /* EP0_TxSent */ + USBD_BB_EP0_RxReady, /* EP0_RxReady */ + USBD_BB_DataIn, /* DataIn */ + USBD_BB_DataOut, /* DataOut */ + NULL, /* SOF */ + NULL, + NULL, + USBD_BB_GetCfgDesc, + USBD_BB_GetCfgDesc, + USBD_BB_GetOtherSpeedCfgDesc, + USBD_BB_GetDeviceQualifierDesc, +#if (USBD_SUPPORT_USER_STRING_DESC == 1U) + NULL, +#endif +}; + +/* USB Standard Device Qualifier Descriptor */ +__ALIGN_BEGIN static uint8_t USBD_BB_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_DESC] __ALIGN_END = +{ + USB_LEN_DEV_QUALIFIER_DESC, /* bLength */ + USB_DESC_TYPE_DEVICE_QUALIFIER, /* bDescriptorType */ + 0x01, /* bcdUSB */ + 0x20, + 0x11, /* bDeviceClass */ + 0x00, /* bDeviceSubClass */ + 0x00, /* bDeviceProtocol */ + 0x40, /* bMaxPacketSize0 */ + 0x01, /* bNumConfigurations */ + 0x00, /* bReserved */ +}; + +/* USB device Configuration Descriptor */ +__ALIGN_BEGIN static uint8_t USBD_BB_CfgDesc[USB_BB_CONFIG_DESC_SIZ] __ALIGN_END = +{ + 0x09, /* bLength: Configuration Descriptor size */ + USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */ + USB_BB_CONFIG_DESC_SIZ, /* wTotalLength: Bytes returned */ + 0x00, + 0x01, /* bNumInterfaces: 1 interface */ + 0x01, /* bConfigurationValue: Configuration value */ + USBD_IDX_CONFIG_STR, /* iConfiguration: Index of string descriptor describing the configuration */ + 0xC0, /* bmAttributes: bus powered and Support Remote Wake-up */ + 0x00, /* MaxPower 100 mA: this current is used for detecting Vbus */ + /* 09 */ + + /************** Descriptor of BillBoard interface ****************/ + /* 09 */ + 0x09, /* bLength: Interface Descriptor size */ + USB_DESC_TYPE_INTERFACE, /* bDescriptorType: Interface descriptor type */ + 0x00, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x00, /* bNumEndpoints */ + 0x11, /* bInterfaceClass: billboard */ + 0x00, /* bInterfaceSubClass */ + 0x00, /* nInterfaceProtocol */ + USBD_BB_IF_STRING_INDEX, /* iInterface: Index of string descriptor */ +}; + +/* USB device Other Speed Configuration Descriptor */ +__ALIGN_BEGIN static uint8_t USBD_BB_OtherSpeedCfgDesc[USB_BB_CONFIG_DESC_SIZ] __ALIGN_END = +{ + 0x09, /* bLength: Configuation Descriptor size */ + USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION, + USB_BB_CONFIG_DESC_SIZ, + 0x00, + 0x01, /* bNumInterfaces: 1 interface */ + 0x01, /* bConfigurationValue: */ + USBD_IDX_CONFIG_STR, /* iConfiguration: */ + 0xC0, /* bmAttributes: */ + 0x00, /* MaxPower 100 mA */ + + /************** Descriptor of BillBoard interface ****************/ + /* 09 */ + 0x09, /* bLength: Interface Descriptor size */ + USB_DESC_TYPE_INTERFACE, /* bDescriptorType: Interface descriptor type */ + 0x00, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x00, /* bNumEndpoints*/ + 0x11, /* bInterfaceClass: billboard */ + 0x00, /* bInterfaceSubClass */ + 0x00, /* nInterfaceProtocol */ + USBD_BB_IF_STRING_INDEX, /* iInterface: Index of string descriptor */ +} ; + +/** + * @} + */ + +/** @defgroup USBD_BB_Private_Functions + * @{ + */ + +/** + * @brief USBD_BB_Init + * Initialize the BB interface + * @param pdev: device instance + * @param cfgidx: Configuration index + * @retval status + */ +static uint8_t USBD_BB_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx) +{ + /* Prevent unused argument compilation warning */ + UNUSED(pdev); + UNUSED(cfgidx); + + return (uint8_t)USBD_OK; +} + +/** + * @brief USBD_BB_Init + * DeInitialize the BB layer + * @param pdev: device instance + * @param cfgidx: Configuration index + * @retval status + */ +static uint8_t USBD_BB_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx) +{ + /* Prevent unused argument compilation warning */ + UNUSED(pdev); + UNUSED(cfgidx); + + return (uint8_t)USBD_OK; +} + +/** + * @brief USBD_BB_Setup + * Handle the BB specific requests + * @param pdev: instance + * @param req: usb requests + * @retval status + */ +static uint8_t USBD_BB_Setup(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) +{ + USBD_StatusTypeDef ret = USBD_OK; + uint16_t status_info = 0U; + uint16_t AltSetting = 0U; + + switch (req->bmRequest & USB_REQ_TYPE_MASK) + { + case USB_REQ_TYPE_CLASS: + break; + case USB_REQ_TYPE_STANDARD: + switch (req->bRequest) + { + case USB_REQ_GET_STATUS: + if (pdev->dev_state == USBD_STATE_CONFIGURED) + { + (void)USBD_CtlSendData(pdev, (uint8_t *)&status_info, 2U); + } + else + { + USBD_CtlError(pdev, req); + ret = USBD_FAIL; + } + break; + + case USB_REQ_GET_INTERFACE: + if (pdev->dev_state == USBD_STATE_CONFIGURED) + { + (void)USBD_CtlSendData(pdev, (uint8_t *)&AltSetting, 1U); + } + else + { + USBD_CtlError(pdev, req); + ret = USBD_FAIL; + } + break; + + case USB_REQ_SET_INTERFACE: + case USB_REQ_CLEAR_FEATURE: + break; + + default: + USBD_CtlError(pdev, req); + ret = USBD_FAIL; + break; + } + break; + + default: + USBD_CtlError(pdev, req); + ret = USBD_FAIL; + break; + } + + return (uint8_t)ret; +} + +/** + * @brief USBD_BB_DataIn + * Data sent on non-control IN endpoint + * @param pdev: device instance + * @param epnum: endpoint number + * @retval status + */ +static uint8_t USBD_BB_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum) +{ + /* Prevent unused argument compilation warning */ + UNUSED(pdev); + UNUSED(epnum); + + return (uint8_t)USBD_OK; +} + +/** + * @brief USBD_BB_DataOut + * Data received on non-control Out endpoint + * @param pdev: device instance + * @param epnum: endpoint number + * @retval status + */ +static uint8_t USBD_BB_DataOut(USBD_HandleTypeDef *pdev, uint8_t epnum) +{ + /* Prevent unused argument compilation warning */ + UNUSED(pdev); + UNUSED(epnum); + + return (uint8_t)USBD_OK; +} + +/** + * @brief USBD_BB_EP0_RxReady + * Handle EP0 Rx Ready event + * @param pdev: device instance + * @retval status + */ +static uint8_t USBD_BB_EP0_RxReady(USBD_HandleTypeDef *pdev) +{ + /* Prevent unused argument compilation warning */ + UNUSED(pdev); + + return (uint8_t)USBD_OK; +} + +/** + * @brief USBD_BB_GetCfgDesc + * return configuration descriptor + * @param speed : current device speed + * @param length : pointer data length + * @retval pointer to descriptor buffer + */ +static uint8_t *USBD_BB_GetCfgDesc(uint16_t *length) +{ + *length = (uint16_t)sizeof(USBD_BB_CfgDesc); + return USBD_BB_CfgDesc; +} + +/** + * @brief USBD_BB_GetOtherSpeedCfgDesc + * return other speed configuration descriptor + * @param length : pointer data length + * @retval pointer to descriptor buffer + */ +uint8_t *USBD_BB_GetOtherSpeedCfgDesc(uint16_t *length) +{ + *length = (uint16_t)sizeof(USBD_BB_OtherSpeedCfgDesc); + return USBD_BB_OtherSpeedCfgDesc; +} + +/** + * @brief DeviceQualifierDescriptor + * return Device Qualifier descriptor + * @param length : pointer data length + * @retval pointer to descriptor buffer + */ +static uint8_t *USBD_BB_GetDeviceQualifierDesc(uint16_t *length) +{ + *length = (uint16_t)sizeof(USBD_BB_DeviceQualifierDesc); + return USBD_BB_DeviceQualifierDesc; +} + + +#if (USBD_CLASS_BOS_ENABLED == 1U) +/** + * @brief USBD_BB_GetNextDesc + * This function return the next descriptor header + * @param buf: Buffer where the descriptor is available + * @param ptr: data pointer inside the descriptor + * @retval next header + */ +USBD_BB_DescHeader_t *USBD_BB_GetNextDesc(uint8_t *pbuf, uint16_t *ptr) +{ + USBD_BB_DescHeader_t *pnext = (USBD_BB_DescHeader_t *)pbuf; + + *ptr += pnext->bLength; + pnext = (USBD_BB_DescHeader_t *)(pbuf + pnext->bLength); + + return (pnext); +} + + +/** + * @brief USBD_BB_GetCapDesc + * This function return the Billboard Capability descriptor + * @param pdev: device instance + * @param pBosDesc: pointer to Bos descriptor + * @retval pointer to Billboard Capability descriptor + */ +void *USBD_BB_GetCapDesc(USBD_HandleTypeDef *pdev, uint8_t *pBosDesc) +{ + UNUSED(pdev); + + USBD_BB_DescHeader_t *pdesc = (USBD_BB_DescHeader_t *)pBosDesc; + USBD_BosDescTypedef *desc = (USBD_BosDescTypedef *)pBosDesc; + USBD_BosBBCapDescTypedef *pCapDesc = NULL; + uint16_t ptr; + + if (desc->wTotalLength > desc->bLength) + { + ptr = desc->bLength; + + while (ptr < desc->wTotalLength) + { + pdesc = USBD_BB_GetNextDesc((uint8_t *)pdesc, &ptr); + + if (pdesc->bDevCapabilityType == USBD_BILLBOARD_CAPABILITY) + { + pCapDesc = (USBD_BosBBCapDescTypedef *)pdesc; + break; + } + } + } + return (void *)pCapDesc; +} + + +/** + * @brief USBD_BB_GetAltModeDesc + * This function return the Billboard Alternate Mode descriptor + * @param pdev: device instance + * @param pBosDesc: pointer to Bos descriptor + * @param idx: Index of requested Alternate Mode descriptor + * @retval pointer to Alternate Mode descriptor + */ +void *USBD_BB_GetAltModeDesc(USBD_HandleTypeDef *pdev, uint8_t *pBosDesc, uint8_t idx) +{ + UNUSED(pdev); + + USBD_BB_DescHeader_t *pdesc = (USBD_BB_DescHeader_t *)pBosDesc; + USBD_BosDescTypedef *desc = (USBD_BosDescTypedef *)pBosDesc; + USBD_BB_AltModeCapDescTypeDef *pAltModDesc = NULL; + uint8_t cnt = 0U; + uint16_t ptr; + + if (desc->wTotalLength > desc->bLength) + { + ptr = desc->bLength; + + while (ptr < desc->wTotalLength) + { + pdesc = USBD_BB_GetNextDesc((uint8_t *)pdesc, &ptr); + + if (pdesc->bDevCapabilityType == USBD_BILLBOARD_ALTMODE_CAPABILITY) + { + if (cnt == idx) + { + pAltModDesc = (USBD_BB_AltModeCapDescTypeDef *)pdesc; + break; + } + else + { + cnt++; + } + } + } + } + return (void *)pAltModDesc; +} +#endif + +/** + * @} + */ + + +/** + * @} + */ + + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc/usbd_cdc.h b/system/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc/usbd_cdc.h index 121bdb5505..b484218e0f 100644 --- a/system/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc/usbd_cdc.h +++ b/system/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc/usbd_cdc.h @@ -46,11 +46,11 @@ extern "C" { #define CDC_CMD_EP 0x82U /* EP2 for CDC commands */ #ifndef CDC_HS_BINTERVAL -#define CDC_HS_BINTERVAL 0x10U +#define CDC_HS_BINTERVAL 0x10U #endif /* CDC_HS_BINTERVAL */ #ifndef CDC_FS_BINTERVAL -#define CDC_FS_BINTERVAL 0x10U +#define CDC_FS_BINTERVAL 0x10U #endif /* CDC_FS_BINTERVAL */ /* CDC Endpoints parameters: you can fine tune these values depending on the needed baudrates and performance. */ @@ -104,7 +104,7 @@ typedef struct _USBD_CDC_Itf int8_t (* DeInit)(void); int8_t (* Control)(uint8_t cmd, uint8_t *pbuf, uint16_t length); int8_t (* Receive)(uint8_t *Buf, uint32_t *Len); - + int8_t (* TransmitCplt)(uint8_t *Buf, uint32_t *Len, uint8_t epnum); } USBD_CDC_ItfTypeDef; @@ -120,8 +120,7 @@ typedef struct __IO uint32_t TxState; __IO uint32_t RxState; -} -USBD_CDC_HandleTypeDef; +} USBD_CDC_HandleTypeDef; @@ -137,8 +136,8 @@ USBD_CDC_HandleTypeDef; * @{ */ -extern USBD_ClassTypeDef USBD_CDC; -#define USBD_CDC_CLASS &USBD_CDC +extern USBD_ClassTypeDef USBD_CDC; +#define USBD_CDC_CLASS &USBD_CDC /** * @} */ @@ -146,19 +145,15 @@ extern USBD_ClassTypeDef USBD_CDC; /** @defgroup USB_CORE_Exported_Functions * @{ */ -uint8_t USBD_CDC_RegisterInterface(USBD_HandleTypeDef *pdev, - USBD_CDC_ItfTypeDef *fops); - -uint8_t USBD_CDC_SetTxBuffer(USBD_HandleTypeDef *pdev, - uint8_t *pbuff, - uint16_t length); - -uint8_t USBD_CDC_SetRxBuffer(USBD_HandleTypeDef *pdev, - uint8_t *pbuff); +uint8_t USBD_CDC_RegisterInterface(USBD_HandleTypeDef *pdev, + USBD_CDC_ItfTypeDef *fops); -uint8_t USBD_CDC_ReceivePacket(USBD_HandleTypeDef *pdev); +uint8_t USBD_CDC_SetTxBuffer(USBD_HandleTypeDef *pdev, uint8_t *pbuff, + uint32_t length); -uint8_t USBD_CDC_TransmitPacket(USBD_HandleTypeDef *pdev); +uint8_t USBD_CDC_SetRxBuffer(USBD_HandleTypeDef *pdev, uint8_t *pbuff); +uint8_t USBD_CDC_ReceivePacket(USBD_HandleTypeDef *pdev); +uint8_t USBD_CDC_TransmitPacket(USBD_HandleTypeDef *pdev); /** * @} */ diff --git a/system/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c b/system/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c index 8332b22c10..017e4cdc9e 100644 --- a/system/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c +++ b/system/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c @@ -99,33 +99,18 @@ EndBSPDependencies */ * @{ */ - -static uint8_t USBD_CDC_Init(USBD_HandleTypeDef *pdev, - uint8_t cfgidx); - -static uint8_t USBD_CDC_DeInit(USBD_HandleTypeDef *pdev, - uint8_t cfgidx); - -static uint8_t USBD_CDC_Setup(USBD_HandleTypeDef *pdev, - USBD_SetupReqTypedef *req); - -static uint8_t USBD_CDC_DataIn(USBD_HandleTypeDef *pdev, - uint8_t epnum); - -static uint8_t USBD_CDC_DataOut(USBD_HandleTypeDef *pdev, - uint8_t epnum); - -static uint8_t USBD_CDC_EP0_RxReady(USBD_HandleTypeDef *pdev); - -static uint8_t *USBD_CDC_GetFSCfgDesc(uint16_t *length); - -static uint8_t *USBD_CDC_GetHSCfgDesc(uint16_t *length); - -static uint8_t *USBD_CDC_GetOtherSpeedCfgDesc(uint16_t *length); - -static uint8_t *USBD_CDC_GetOtherSpeedCfgDesc(uint16_t *length); - -uint8_t *USBD_CDC_GetDeviceQualifierDescriptor(uint16_t *length); +static uint8_t USBD_CDC_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx); +static uint8_t USBD_CDC_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx); +static uint8_t USBD_CDC_Setup(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); +static uint8_t USBD_CDC_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum); +static uint8_t USBD_CDC_DataOut(USBD_HandleTypeDef *pdev, uint8_t epnum); +static uint8_t USBD_CDC_EP0_RxReady(USBD_HandleTypeDef *pdev); + +static uint8_t *USBD_CDC_GetFSCfgDesc(uint16_t *length); +static uint8_t *USBD_CDC_GetHSCfgDesc(uint16_t *length); +static uint8_t *USBD_CDC_GetOtherSpeedCfgDesc(uint16_t *length); +static uint8_t *USBD_CDC_GetOtherSpeedCfgDesc(uint16_t *length); +uint8_t *USBD_CDC_GetDeviceQualifierDescriptor(uint16_t *length); /* USB Standard Device Descriptor */ __ALIGN_BEGIN static uint8_t USBD_CDC_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_DESC] __ALIGN_END = @@ -171,286 +156,286 @@ USBD_ClassTypeDef USBD_CDC = }; /* USB CDC device Configuration Descriptor */ -__ALIGN_BEGIN uint8_t USBD_CDC_CfgHSDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END = +__ALIGN_BEGIN static uint8_t USBD_CDC_CfgHSDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END = { - /*Configuration Descriptor*/ - 0x09, /* bLength: Configuration Descriptor size */ - USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */ - USB_CDC_CONFIG_DESC_SIZ, /* wTotalLength:no of returned bytes */ + /* Configuration Descriptor */ + 0x09, /* bLength: Configuration Descriptor size */ + USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */ + USB_CDC_CONFIG_DESC_SIZ, /* wTotalLength:no of returned bytes */ 0x00, - 0x02, /* bNumInterfaces: 2 interface */ - 0x01, /* bConfigurationValue: Configuration value */ - 0x00, /* iConfiguration: Index of string descriptor describing the configuration */ - 0xC0, /* bmAttributes: self powered */ - 0x32, /* MaxPower 0 mA */ + 0x02, /* bNumInterfaces: 2 interface */ + 0x01, /* bConfigurationValue: Configuration value */ + 0x00, /* iConfiguration: Index of string descriptor describing the configuration */ + 0xC0, /* bmAttributes: self powered */ + 0x32, /* MaxPower 0 mA */ /*---------------------------------------------------------------------------*/ - /*Interface Descriptor */ - 0x09, /* bLength: Interface Descriptor size */ - USB_DESC_TYPE_INTERFACE, /* bDescriptorType: Interface */ - /* Interface descriptor type */ - 0x00, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x01, /* bNumEndpoints: One endpoints used */ - 0x02, /* bInterfaceClass: Communication Interface Class */ - 0x02, /* bInterfaceSubClass: Abstract Control Model */ - 0x01, /* bInterfaceProtocol: Common AT commands */ - 0x00, /* iInterface: */ - - /*Header Functional Descriptor*/ - 0x05, /* bLength: Endpoint Descriptor size */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x00, /* bDescriptorSubtype: Header Func Desc */ - 0x10, /* bcdCDC: spec release number */ + /* Interface Descriptor */ + 0x09, /* bLength: Interface Descriptor size */ + USB_DESC_TYPE_INTERFACE, /* bDescriptorType: Interface */ + /* Interface descriptor type */ + 0x00, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x01, /* bNumEndpoints: One endpoints used */ + 0x02, /* bInterfaceClass: Communication Interface Class */ + 0x02, /* bInterfaceSubClass: Abstract Control Model */ + 0x01, /* bInterfaceProtocol: Common AT commands */ + 0x00, /* iInterface: */ + + /* Header Functional Descriptor */ + 0x05, /* bLength: Endpoint Descriptor size */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x00, /* bDescriptorSubtype: Header Func Desc */ + 0x10, /* bcdCDC: spec release number */ 0x01, - /*Call Management Functional Descriptor*/ - 0x05, /* bFunctionLength */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x01, /* bDescriptorSubtype: Call Management Func Desc */ - 0x00, /* bmCapabilities: D0+D1 */ - 0x01, /* bDataInterface: 1 */ - - /*ACM Functional Descriptor*/ - 0x04, /* bFunctionLength */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x02, /* bDescriptorSubtype: Abstract Control Management desc */ - 0x02, /* bmCapabilities */ - - /*Union Functional Descriptor*/ - 0x05, /* bFunctionLength */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x06, /* bDescriptorSubtype: Union func desc */ - 0x00, /* bMasterInterface: Communication class interface */ - 0x01, /* bSlaveInterface0: Data Class Interface */ - - /*Endpoint 2 Descriptor*/ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ - CDC_CMD_EP, /* bEndpointAddress */ - 0x03, /* bmAttributes: Interrupt */ - LOBYTE(CDC_CMD_PACKET_SIZE), /* wMaxPacketSize: */ + /* Call Management Functional Descriptor */ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x01, /* bDescriptorSubtype: Call Management Func Desc */ + 0x00, /* bmCapabilities: D0+D1 */ + 0x01, /* bDataInterface: 1 */ + + /* ACM Functional Descriptor */ + 0x04, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x02, /* bDescriptorSubtype: Abstract Control Management desc */ + 0x02, /* bmCapabilities */ + + /* Union Functional Descriptor */ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x06, /* bDescriptorSubtype: Union func desc */ + 0x00, /* bMasterInterface: Communication class interface */ + 0x01, /* bSlaveInterface0: Data Class Interface */ + + /* Endpoint 2 Descriptor */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + CDC_CMD_EP, /* bEndpointAddress */ + 0x03, /* bmAttributes: Interrupt */ + LOBYTE(CDC_CMD_PACKET_SIZE), /* wMaxPacketSize: */ HIBYTE(CDC_CMD_PACKET_SIZE), CDC_HS_BINTERVAL, /* bInterval: */ /*---------------------------------------------------------------------------*/ - /*Data class interface descriptor*/ - 0x09, /* bLength: Endpoint Descriptor size */ - USB_DESC_TYPE_INTERFACE, /* bDescriptorType: */ - 0x01, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x02, /* bNumEndpoints: Two endpoints used */ - 0x0A, /* bInterfaceClass: CDC */ - 0x00, /* bInterfaceSubClass: */ - 0x00, /* bInterfaceProtocol: */ - 0x00, /* iInterface: */ - - /*Endpoint OUT Descriptor*/ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ - CDC_OUT_EP, /* bEndpointAddress */ - 0x02, /* bmAttributes: Bulk */ - LOBYTE(CDC_DATA_HS_MAX_PACKET_SIZE), /* wMaxPacketSize: */ + /* Data class interface descriptor */ + 0x09, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_INTERFACE, /* bDescriptorType: */ + 0x01, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x02, /* bNumEndpoints: Two endpoints used */ + 0x0A, /* bInterfaceClass: CDC */ + 0x00, /* bInterfaceSubClass: */ + 0x00, /* bInterfaceProtocol: */ + 0x00, /* iInterface: */ + + /* Endpoint OUT Descriptor */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + CDC_OUT_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + LOBYTE(CDC_DATA_HS_MAX_PACKET_SIZE), /* wMaxPacketSize: */ HIBYTE(CDC_DATA_HS_MAX_PACKET_SIZE), - 0x00, /* bInterval: ignore for Bulk transfer */ - - /*Endpoint IN Descriptor*/ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ - CDC_IN_EP, /* bEndpointAddress */ - 0x02, /* bmAttributes: Bulk */ - LOBYTE(CDC_DATA_HS_MAX_PACKET_SIZE), /* wMaxPacketSize: */ + 0x00, /* bInterval: ignore for Bulk transfer */ + + /* Endpoint IN Descriptor */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + CDC_IN_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + LOBYTE(CDC_DATA_HS_MAX_PACKET_SIZE), /* wMaxPacketSize: */ HIBYTE(CDC_DATA_HS_MAX_PACKET_SIZE), - 0x00 /* bInterval: ignore for Bulk transfer */ -} ; + 0x00 /* bInterval: ignore for Bulk transfer */ +}; /* USB CDC device Configuration Descriptor */ -__ALIGN_BEGIN uint8_t USBD_CDC_CfgFSDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END = +__ALIGN_BEGIN static uint8_t USBD_CDC_CfgFSDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END = { - /*Configuration Descriptor*/ - 0x09, /* bLength: Configuration Descriptor size */ - USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */ - USB_CDC_CONFIG_DESC_SIZ, /* wTotalLength:no of returned bytes */ + /* Configuration Descriptor */ + 0x09, /* bLength: Configuration Descriptor size */ + USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */ + USB_CDC_CONFIG_DESC_SIZ, /* wTotalLength:no of returned bytes */ 0x00, - 0x02, /* bNumInterfaces: 2 interface */ - 0x01, /* bConfigurationValue: Configuration value */ - 0x00, /* iConfiguration: Index of string descriptor describing the configuration */ - 0xC0, /* bmAttributes: self powered */ - 0x32, /* MaxPower 0 mA */ + 0x02, /* bNumInterfaces: 2 interface */ + 0x01, /* bConfigurationValue: Configuration value */ + 0x00, /* iConfiguration: Index of string descriptor describing the configuration */ + 0xC0, /* bmAttributes: self powered */ + 0x32, /* MaxPower 0 mA */ /*---------------------------------------------------------------------------*/ - /*Interface Descriptor */ - 0x09, /* bLength: Interface Descriptor size */ - USB_DESC_TYPE_INTERFACE, /* bDescriptorType: Interface */ + /* Interface Descriptor */ + 0x09, /* bLength: Interface Descriptor size */ + USB_DESC_TYPE_INTERFACE, /* bDescriptorType: Interface */ /* Interface descriptor type */ - 0x00, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x01, /* bNumEndpoints: One endpoints used */ - 0x02, /* bInterfaceClass: Communication Interface Class */ - 0x02, /* bInterfaceSubClass: Abstract Control Model */ - 0x01, /* bInterfaceProtocol: Common AT commands */ - 0x00, /* iInterface: */ - - /*Header Functional Descriptor*/ - 0x05, /* bLength: Endpoint Descriptor size */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x00, /* bDescriptorSubtype: Header Func Desc */ - 0x10, /* bcdCDC: spec release number */ + 0x00, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x01, /* bNumEndpoints: One endpoints used */ + 0x02, /* bInterfaceClass: Communication Interface Class */ + 0x02, /* bInterfaceSubClass: Abstract Control Model */ + 0x01, /* bInterfaceProtocol: Common AT commands */ + 0x00, /* iInterface: */ + + /* Header Functional Descriptor */ + 0x05, /* bLength: Endpoint Descriptor size */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x00, /* bDescriptorSubtype: Header Func Desc */ + 0x10, /* bcdCDC: spec release number */ 0x01, - /*Call Management Functional Descriptor*/ - 0x05, /* bFunctionLength */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x01, /* bDescriptorSubtype: Call Management Func Desc */ - 0x00, /* bmCapabilities: D0+D1 */ - 0x01, /* bDataInterface: 1 */ - - /*ACM Functional Descriptor*/ - 0x04, /* bFunctionLength */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x02, /* bDescriptorSubtype: Abstract Control Management desc */ - 0x02, /* bmCapabilities */ - - /*Union Functional Descriptor*/ - 0x05, /* bFunctionLength */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x06, /* bDescriptorSubtype: Union func desc */ - 0x00, /* bMasterInterface: Communication class interface */ - 0x01, /* bSlaveInterface0: Data Class Interface */ - - /*Endpoint 2 Descriptor*/ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ - CDC_CMD_EP, /* bEndpointAddress */ - 0x03, /* bmAttributes: Interrupt */ - LOBYTE(CDC_CMD_PACKET_SIZE), /* wMaxPacketSize: */ + /* Call Management Functional Descriptor */ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x01, /* bDescriptorSubtype: Call Management Func Desc */ + 0x00, /* bmCapabilities: D0+D1 */ + 0x01, /* bDataInterface: 1 */ + + /* ACM Functional Descriptor */ + 0x04, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x02, /* bDescriptorSubtype: Abstract Control Management desc */ + 0x02, /* bmCapabilities */ + + /* Union Functional Descriptor */ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x06, /* bDescriptorSubtype: Union func desc */ + 0x00, /* bMasterInterface: Communication class interface */ + 0x01, /* bSlaveInterface0: Data Class Interface */ + + /* Endpoint 2 Descriptor */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + CDC_CMD_EP, /* bEndpointAddress */ + 0x03, /* bmAttributes: Interrupt */ + LOBYTE(CDC_CMD_PACKET_SIZE), /* wMaxPacketSize: */ HIBYTE(CDC_CMD_PACKET_SIZE), CDC_FS_BINTERVAL, /* bInterval: */ /*---------------------------------------------------------------------------*/ - /*Data class interface descriptor*/ - 0x09, /* bLength: Endpoint Descriptor size */ - USB_DESC_TYPE_INTERFACE, /* bDescriptorType: */ - 0x01, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x02, /* bNumEndpoints: Two endpoints used */ - 0x0A, /* bInterfaceClass: CDC */ - 0x00, /* bInterfaceSubClass: */ - 0x00, /* bInterfaceProtocol: */ - 0x00, /* iInterface: */ - - /*Endpoint OUT Descriptor*/ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ - CDC_OUT_EP, /* bEndpointAddress */ - 0x02, /* bmAttributes: Bulk */ - LOBYTE(CDC_DATA_FS_MAX_PACKET_SIZE), /* wMaxPacketSize: */ + /* Data class interface descriptor */ + 0x09, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_INTERFACE, /* bDescriptorType: */ + 0x01, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x02, /* bNumEndpoints: Two endpoints used */ + 0x0A, /* bInterfaceClass: CDC */ + 0x00, /* bInterfaceSubClass: */ + 0x00, /* bInterfaceProtocol: */ + 0x00, /* iInterface: */ + + /* Endpoint OUT Descriptor */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + CDC_OUT_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + LOBYTE(CDC_DATA_FS_MAX_PACKET_SIZE), /* wMaxPacketSize: */ HIBYTE(CDC_DATA_FS_MAX_PACKET_SIZE), - 0x00, /* bInterval: ignore for Bulk transfer */ - - /*Endpoint IN Descriptor*/ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ - CDC_IN_EP, /* bEndpointAddress */ - 0x02, /* bmAttributes: Bulk */ - LOBYTE(CDC_DATA_FS_MAX_PACKET_SIZE), /* wMaxPacketSize: */ + 0x00, /* bInterval: ignore for Bulk transfer */ + + /* Endpoint IN Descriptor */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + CDC_IN_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + LOBYTE(CDC_DATA_FS_MAX_PACKET_SIZE), /* wMaxPacketSize: */ HIBYTE(CDC_DATA_FS_MAX_PACKET_SIZE), - 0x00 /* bInterval: ignore for Bulk transfer */ -} ; + 0x00 /* bInterval: ignore for Bulk transfer */ +}; -__ALIGN_BEGIN uint8_t USBD_CDC_OtherSpeedCfgDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END = +__ALIGN_BEGIN static uint8_t USBD_CDC_OtherSpeedCfgDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END = { - 0x09, /* bLength: Configuation Descriptor size */ + 0x09, /* bLength: Configuation Descriptor size */ USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION, USB_CDC_CONFIG_DESC_SIZ, 0x00, - 0x02, /* bNumInterfaces: 2 interfaces */ - 0x01, /* bConfigurationValue: */ - 0x04, /* iConfiguration: */ - 0xC0, /* bmAttributes: */ - 0x32, /* MaxPower 100 mA */ + 0x02, /* bNumInterfaces: 2 interfaces */ + 0x01, /* bConfigurationValue: */ + 0x04, /* iConfiguration: */ + 0xC0, /* bmAttributes: */ + 0x32, /* MaxPower 100 mA */ /*Interface Descriptor */ - 0x09, /* bLength: Interface Descriptor size */ - USB_DESC_TYPE_INTERFACE, /* bDescriptorType: Interface */ + 0x09, /* bLength: Interface Descriptor size */ + USB_DESC_TYPE_INTERFACE, /* bDescriptorType: Interface */ /* Interface descriptor type */ - 0x00, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x01, /* bNumEndpoints: One endpoints used */ - 0x02, /* bInterfaceClass: Communication Interface Class */ - 0x02, /* bInterfaceSubClass: Abstract Control Model */ - 0x01, /* bInterfaceProtocol: Common AT commands */ - 0x00, /* iInterface: */ - - /*Header Functional Descriptor*/ - 0x05, /* bLength: Endpoint Descriptor size */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x00, /* bDescriptorSubtype: Header Func Desc */ - 0x10, /* bcdCDC: spec release number */ + 0x00, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x01, /* bNumEndpoints: One endpoints used */ + 0x02, /* bInterfaceClass: Communication Interface Class */ + 0x02, /* bInterfaceSubClass: Abstract Control Model */ + 0x01, /* bInterfaceProtocol: Common AT commands */ + 0x00, /* iInterface: */ + + /* Header Functional Descriptor */ + 0x05, /* bLength: Endpoint Descriptor size */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x00, /* bDescriptorSubtype: Header Func Desc */ + 0x10, /* bcdCDC: spec release number */ 0x01, /*Call Management Functional Descriptor*/ - 0x05, /* bFunctionLength */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x01, /* bDescriptorSubtype: Call Management Func Desc */ - 0x00, /* bmCapabilities: D0+D1 */ - 0x01, /* bDataInterface: 1 */ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x01, /* bDescriptorSubtype: Call Management Func Desc */ + 0x00, /* bmCapabilities: D0+D1 */ + 0x01, /* bDataInterface: 1 */ /*ACM Functional Descriptor*/ - 0x04, /* bFunctionLength */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x02, /* bDescriptorSubtype: Abstract Control Management desc */ - 0x02, /* bmCapabilities */ + 0x04, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x02, /* bDescriptorSubtype: Abstract Control Management desc */ + 0x02, /* bmCapabilities */ /*Union Functional Descriptor*/ - 0x05, /* bFunctionLength */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x06, /* bDescriptorSubtype: Union func desc */ - 0x00, /* bMasterInterface: Communication class interface */ - 0x01, /* bSlaveInterface0: Data Class Interface */ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x06, /* bDescriptorSubtype: Union func desc */ + 0x00, /* bMasterInterface: Communication class interface */ + 0x01, /* bSlaveInterface0: Data Class Interface */ /*Endpoint 2 Descriptor*/ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ - CDC_CMD_EP, /* bEndpointAddress */ - 0x03, /* bmAttributes: Interrupt */ - LOBYTE(CDC_CMD_PACKET_SIZE), /* wMaxPacketSize: */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + CDC_CMD_EP, /* bEndpointAddress */ + 0x03, /* bmAttributes: Interrupt */ + LOBYTE(CDC_CMD_PACKET_SIZE), /* wMaxPacketSize: */ HIBYTE(CDC_CMD_PACKET_SIZE), CDC_FS_BINTERVAL, /* bInterval: */ /*---------------------------------------------------------------------------*/ /*Data class interface descriptor*/ - 0x09, /* bLength: Endpoint Descriptor size */ - USB_DESC_TYPE_INTERFACE, /* bDescriptorType: */ - 0x01, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x02, /* bNumEndpoints: Two endpoints used */ - 0x0A, /* bInterfaceClass: CDC */ - 0x00, /* bInterfaceSubClass: */ - 0x00, /* bInterfaceProtocol: */ - 0x00, /* iInterface: */ + 0x09, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_INTERFACE, /* bDescriptorType: */ + 0x01, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x02, /* bNumEndpoints: Two endpoints used */ + 0x0A, /* bInterfaceClass: CDC */ + 0x00, /* bInterfaceSubClass: */ + 0x00, /* bInterfaceProtocol: */ + 0x00, /* iInterface: */ /*Endpoint OUT Descriptor*/ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ - CDC_OUT_EP, /* bEndpointAddress */ - 0x02, /* bmAttributes: Bulk */ - 0x40, /* wMaxPacketSize: */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + CDC_OUT_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + 0x40, /* wMaxPacketSize: */ 0x00, - 0x00, /* bInterval: ignore for Bulk transfer */ + 0x00, /* bInterval: ignore for Bulk transfer */ /*Endpoint IN Descriptor*/ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ - CDC_IN_EP, /* bEndpointAddress */ - 0x02, /* bmAttributes: Bulk */ - 0x40, /* wMaxPacketSize: */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + CDC_IN_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + 0x40, /* wMaxPacketSize: */ 0x00, - 0x00 /* bInterval */ + 0x00 /* bInterval */ }; /** @@ -468,75 +453,81 @@ __ALIGN_BEGIN uint8_t USBD_CDC_OtherSpeedCfgDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIG * @param cfgidx: Configuration index * @retval status */ -static uint8_t USBD_CDC_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx) +static uint8_t USBD_CDC_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { - uint8_t ret = 0U; - USBD_CDC_HandleTypeDef *hcdc; + UNUSED(cfgidx); + USBD_CDC_HandleTypeDef *hcdc; + + hcdc = USBD_malloc(sizeof(USBD_CDC_HandleTypeDef)); + + if (hcdc == NULL) + { + pdev->pClassData = NULL; + return (uint8_t)USBD_EMEM; + } + + pdev->pClassData = (void *)hcdc; if (pdev->dev_speed == USBD_SPEED_HIGH) { /* Open EP IN */ - USBD_LL_OpenEP(pdev, CDC_IN_EP, USBD_EP_TYPE_BULK, - CDC_DATA_HS_IN_PACKET_SIZE); + (void)USBD_LL_OpenEP(pdev, CDC_IN_EP, USBD_EP_TYPE_BULK, + CDC_DATA_HS_IN_PACKET_SIZE); - pdev->ep_in[CDC_IN_EP & 0xFU].is_used = 1U; + pdev->ep_in[CDC_IN_EP & 0xFU].is_used = 1U; - /* Open EP OUT */ - USBD_LL_OpenEP(pdev, CDC_OUT_EP, USBD_EP_TYPE_BULK, - CDC_DATA_HS_OUT_PACKET_SIZE); + /* Open EP OUT */ + (void)USBD_LL_OpenEP(pdev, CDC_OUT_EP, USBD_EP_TYPE_BULK, + CDC_DATA_HS_OUT_PACKET_SIZE); - pdev->ep_out[CDC_OUT_EP & 0xFU].is_used = 1U; + pdev->ep_out[CDC_OUT_EP & 0xFU].is_used = 1U; + /* Set bInterval for CDC CMD Endpoint */ + pdev->ep_in[CDC_CMD_EP & 0xFU].bInterval = CDC_HS_BINTERVAL; } else { /* Open EP IN */ - USBD_LL_OpenEP(pdev, CDC_IN_EP, USBD_EP_TYPE_BULK, - CDC_DATA_FS_IN_PACKET_SIZE); + (void)USBD_LL_OpenEP(pdev, CDC_IN_EP, USBD_EP_TYPE_BULK, + CDC_DATA_FS_IN_PACKET_SIZE); + + pdev->ep_in[CDC_IN_EP & 0xFU].is_used = 1U; - pdev->ep_in[CDC_IN_EP & 0xFU].is_used = 1U; + /* Open EP OUT */ + (void)USBD_LL_OpenEP(pdev, CDC_OUT_EP, USBD_EP_TYPE_BULK, + CDC_DATA_FS_OUT_PACKET_SIZE); - /* Open EP OUT */ - USBD_LL_OpenEP(pdev, CDC_OUT_EP, USBD_EP_TYPE_BULK, - CDC_DATA_FS_OUT_PACKET_SIZE); + pdev->ep_out[CDC_OUT_EP & 0xFU].is_used = 1U; - pdev->ep_out[CDC_OUT_EP & 0xFU].is_used = 1U; + /* Set bInterval for CMD Endpoint */ + pdev->ep_in[CDC_CMD_EP & 0xFU].bInterval = CDC_FS_BINTERVAL; } + /* Open Command IN EP */ - USBD_LL_OpenEP(pdev, CDC_CMD_EP, USBD_EP_TYPE_INTR, CDC_CMD_PACKET_SIZE); + (void)USBD_LL_OpenEP(pdev, CDC_CMD_EP, USBD_EP_TYPE_INTR, CDC_CMD_PACKET_SIZE); pdev->ep_in[CDC_CMD_EP & 0xFU].is_used = 1U; - pdev->pClassData = USBD_malloc(sizeof(USBD_CDC_HandleTypeDef)); + /* Init physical Interface components */ + ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Init(); - if (pdev->pClassData == NULL) + /* Init Xfer states */ + hcdc->TxState = 0U; + hcdc->RxState = 0U; + + if (pdev->dev_speed == USBD_SPEED_HIGH) { - ret = 1U; + /* Prepare Out endpoint to receive next packet */ + (void)USBD_LL_PrepareReceive(pdev, CDC_OUT_EP, hcdc->RxBuffer, + CDC_DATA_HS_OUT_PACKET_SIZE); } else { - hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData; - - /* Init physical Interface components */ - ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Init(); - - /* Init Xfer states */ - hcdc->TxState = 0U; - hcdc->RxState = 0U; - - if (pdev->dev_speed == USBD_SPEED_HIGH) - { - /* Prepare Out endpoint to receive next packet */ - USBD_LL_PrepareReceive(pdev, CDC_OUT_EP, hcdc->RxBuffer, - CDC_DATA_HS_OUT_PACKET_SIZE); - } - else - { - /* Prepare Out endpoint to receive next packet */ - USBD_LL_PrepareReceive(pdev, CDC_OUT_EP, hcdc->RxBuffer, - CDC_DATA_FS_OUT_PACKET_SIZE); - } + /* Prepare Out endpoint to receive next packet */ + (void)USBD_LL_PrepareReceive(pdev, CDC_OUT_EP, hcdc->RxBuffer, + CDC_DATA_FS_OUT_PACKET_SIZE); } - return ret; + + return (uint8_t)USBD_OK; } /** @@ -546,27 +537,29 @@ static uint8_t USBD_CDC_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx) * @param cfgidx: Configuration index * @retval status */ -static uint8_t USBD_CDC_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx) +static uint8_t USBD_CDC_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { + UNUSED(cfgidx); uint8_t ret = 0U; /* Close EP IN */ - USBD_LL_CloseEP(pdev, CDC_IN_EP); + (void)USBD_LL_CloseEP(pdev, CDC_IN_EP); pdev->ep_in[CDC_IN_EP & 0xFU].is_used = 0U; /* Close EP OUT */ - USBD_LL_CloseEP(pdev, CDC_OUT_EP); + (void)USBD_LL_CloseEP(pdev, CDC_OUT_EP); pdev->ep_out[CDC_OUT_EP & 0xFU].is_used = 0U; /* Close Command IN EP */ - USBD_LL_CloseEP(pdev, CDC_CMD_EP); + (void)USBD_LL_CloseEP(pdev, CDC_CMD_EP); pdev->ep_in[CDC_CMD_EP & 0xFU].is_used = 0U; + pdev->ep_in[CDC_CMD_EP & 0xFU].bInterval = 0U; /* DeInit physical Interface components */ if (pdev->pClassData != NULL) { ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->DeInit(); - USBD_free(pdev->pClassData); + (void)USBD_free(pdev->pClassData); pdev->pClassData = NULL; } @@ -580,91 +573,94 @@ static uint8_t USBD_CDC_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx) * @param req: usb requests * @retval status */ -static uint8_t USBD_CDC_Setup(USBD_HandleTypeDef *pdev, - USBD_SetupReqTypedef *req) +static uint8_t USBD_CDC_Setup(USBD_HandleTypeDef *pdev, + USBD_SetupReqTypedef *req) { - USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData; + USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassData; uint8_t ifalt = 0U; uint16_t status_info = 0U; - uint8_t ret = USBD_OK; + USBD_StatusTypeDef ret = USBD_OK; switch (req->bmRequest & USB_REQ_TYPE_MASK) { - case USB_REQ_TYPE_CLASS : - if (req->wLength) + case USB_REQ_TYPE_CLASS: + if (req->wLength != 0U) + { + if ((req->bmRequest & 0x80U) != 0U) { - if (req->bmRequest & 0x80U) - { - ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest, - (uint8_t *)(void *)hcdc->data, - req->wLength); - - USBD_CtlSendData(pdev, (uint8_t *)(void *)hcdc->data, req->wLength); - } - else - { - hcdc->CmdOpCode = req->bRequest; - hcdc->CmdLength = (uint8_t)req->wLength; - - USBD_CtlPrepareRx(pdev, (uint8_t *)(void *)hcdc->data, req->wLength); - } + ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest, + (uint8_t *)hcdc->data, + req->wLength); + + (void)USBD_CtlSendData(pdev, (uint8_t *)hcdc->data, req->wLength); } else { - ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest, - (uint8_t *)(void *)req, 0U); + hcdc->CmdOpCode = req->bRequest; + hcdc->CmdLength = (uint8_t)req->wLength; + + (void)USBD_CtlPrepareRx(pdev, (uint8_t *)hcdc->data, req->wLength); + } + } + else + { + ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest, + (uint8_t *)req, 0U); + } + break; + + case USB_REQ_TYPE_STANDARD: + switch (req->bRequest) + { + case USB_REQ_GET_STATUS: + if (pdev->dev_state == USBD_STATE_CONFIGURED) + { + (void)USBD_CtlSendData(pdev, (uint8_t *)&status_info, 2U); + } + else + { + USBD_CtlError(pdev, req); + ret = USBD_FAIL; } break; - case USB_REQ_TYPE_STANDARD: - switch (req->bRequest) + case USB_REQ_GET_INTERFACE: + if (pdev->dev_state == USBD_STATE_CONFIGURED) { - case USB_REQ_GET_STATUS: - if (pdev->dev_state == USBD_STATE_CONFIGURED) - { - USBD_CtlSendData(pdev, (uint8_t *)(void *)&status_info, 2U); - } - else - { - USBD_CtlError(pdev, req); - ret = USBD_FAIL; - } - break; - - case USB_REQ_GET_INTERFACE: - if (pdev->dev_state == USBD_STATE_CONFIGURED) - { - USBD_CtlSendData(pdev, &ifalt, 1U); - } - else - { - USBD_CtlError(pdev, req); - ret = USBD_FAIL; - } - break; - - case USB_REQ_SET_INTERFACE: - if (pdev->dev_state != USBD_STATE_CONFIGURED) - { - USBD_CtlError(pdev, req); - ret = USBD_FAIL; - } - break; - - default: - USBD_CtlError(pdev, req); - ret = USBD_FAIL; - break; + (void)USBD_CtlSendData(pdev, &ifalt, 1U); + } + else + { + USBD_CtlError(pdev, req); + ret = USBD_FAIL; + } + break; + + case USB_REQ_SET_INTERFACE: + if (pdev->dev_state != USBD_STATE_CONFIGURED) + { + USBD_CtlError(pdev, req); + ret = USBD_FAIL; } break; + case USB_REQ_CLEAR_FEATURE: + break; + default: USBD_CtlError(pdev, req); ret = USBD_FAIL; break; + } + break; + + default: + USBD_CtlError(pdev, req); + ret = USBD_FAIL; + break; } - return ret; + return (uint8_t)ret; } /** @@ -674,31 +670,34 @@ static uint8_t USBD_CDC_Setup(USBD_HandleTypeDef *pdev, * @param epnum: endpoint number * @retval status */ -static uint8_t USBD_CDC_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum) +static uint8_t USBD_CDC_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum) { - USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassData; + USBD_CDC_HandleTypeDef *hcdc; PCD_HandleTypeDef *hpcd = pdev->pData; - if (pdev->pClassData != NULL) + if (pdev->pClassData == NULL) { - if ((pdev->ep_in[epnum].total_length > 0U) && ((pdev->ep_in[epnum].total_length % hpcd->IN_ep[epnum].maxpacket) == 0U)) - { - /* Update the packet total length */ - pdev->ep_in[epnum].total_length = 0U; + return (uint8_t)USBD_FAIL; + } - /* Send ZLP */ - USBD_LL_Transmit(pdev, epnum, NULL, 0U); - } - else - { - hcdc->TxState = 0U; - } - return USBD_OK; + hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassData; + + if ((pdev->ep_in[epnum].total_length > 0U) && + ((pdev->ep_in[epnum].total_length % hpcd->IN_ep[epnum].maxpacket) == 0U)) + { + /* Update the packet total length */ + pdev->ep_in[epnum].total_length = 0U; + + /* Send ZLP */ + (void)USBD_LL_Transmit(pdev, epnum, NULL, 0U); } else { - return USBD_FAIL; + hcdc->TxState = 0U; + ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->TransmitCplt(hcdc->TxBuffer, &hcdc->TxLength, epnum); } + + return (uint8_t)USBD_OK; } /** @@ -708,25 +707,24 @@ static uint8_t USBD_CDC_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum) * @param epnum: endpoint number * @retval status */ -static uint8_t USBD_CDC_DataOut(USBD_HandleTypeDef *pdev, uint8_t epnum) +static uint8_t USBD_CDC_DataOut(USBD_HandleTypeDef *pdev, uint8_t epnum) { - USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData; + USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassData; + + if (pdev->pClassData == NULL) + { + return (uint8_t)USBD_FAIL; + } /* Get the received data length */ hcdc->RxLength = USBD_LL_GetRxDataSize(pdev, epnum); /* USB data will be immediately processed, this allow next USB traffic being NAKed till the end of the application Xfer */ - if (pdev->pClassData != NULL) - { - ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Receive(hcdc->RxBuffer, &hcdc->RxLength); - return USBD_OK; - } - else - { - return USBD_FAIL; - } + ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Receive(hcdc->RxBuffer, &hcdc->RxLength); + + return (uint8_t)USBD_OK; } /** @@ -735,19 +733,20 @@ static uint8_t USBD_CDC_DataOut(USBD_HandleTypeDef *pdev, uint8_t epnum) * @param pdev: device instance * @retval status */ -static uint8_t USBD_CDC_EP0_RxReady(USBD_HandleTypeDef *pdev) +static uint8_t USBD_CDC_EP0_RxReady(USBD_HandleTypeDef *pdev) { - USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData; + USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassData; if ((pdev->pUserData != NULL) && (hcdc->CmdOpCode != 0xFFU)) { ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(hcdc->CmdOpCode, - (uint8_t *)(void *)hcdc->data, + (uint8_t *)hcdc->data, (uint16_t)hcdc->CmdLength); hcdc->CmdOpCode = 0xFFU; } - return USBD_OK; + + return (uint8_t)USBD_OK; } /** @@ -757,9 +756,10 @@ static uint8_t USBD_CDC_EP0_RxReady(USBD_HandleTypeDef *pdev) * @param length : pointer data length * @retval pointer to descriptor buffer */ -static uint8_t *USBD_CDC_GetFSCfgDesc(uint16_t *length) +static uint8_t *USBD_CDC_GetFSCfgDesc(uint16_t *length) { - *length = sizeof(USBD_CDC_CfgFSDesc); + *length = (uint16_t)sizeof(USBD_CDC_CfgFSDesc); + return USBD_CDC_CfgFSDesc; } @@ -770,9 +770,10 @@ static uint8_t *USBD_CDC_GetFSCfgDesc(uint16_t *length) * @param length : pointer data length * @retval pointer to descriptor buffer */ -static uint8_t *USBD_CDC_GetHSCfgDesc(uint16_t *length) +static uint8_t *USBD_CDC_GetHSCfgDesc(uint16_t *length) { - *length = sizeof(USBD_CDC_CfgHSDesc); + *length = (uint16_t)sizeof(USBD_CDC_CfgHSDesc); + return USBD_CDC_CfgHSDesc; } @@ -783,9 +784,10 @@ static uint8_t *USBD_CDC_GetHSCfgDesc(uint16_t *length) * @param length : pointer data length * @retval pointer to descriptor buffer */ -static uint8_t *USBD_CDC_GetOtherSpeedCfgDesc(uint16_t *length) +static uint8_t *USBD_CDC_GetOtherSpeedCfgDesc(uint16_t *length) { - *length = sizeof(USBD_CDC_OtherSpeedCfgDesc); + *length = (uint16_t)sizeof(USBD_CDC_OtherSpeedCfgDesc); + return USBD_CDC_OtherSpeedCfgDesc; } @@ -795,9 +797,10 @@ static uint8_t *USBD_CDC_GetOtherSpeedCfgDesc(uint16_t *length) * @param length : pointer data length * @retval pointer to descriptor buffer */ -uint8_t *USBD_CDC_GetDeviceQualifierDescriptor(uint16_t *length) +uint8_t *USBD_CDC_GetDeviceQualifierDescriptor(uint16_t *length) { - *length = sizeof(USBD_CDC_DeviceQualifierDesc); + *length = (uint16_t)sizeof(USBD_CDC_DeviceQualifierDesc); + return USBD_CDC_DeviceQualifierDesc; } @@ -807,18 +810,17 @@ uint8_t *USBD_CDC_GetDeviceQualifierDescriptor(uint16_t *length) * @param fops: CD Interface callback * @retval status */ -uint8_t USBD_CDC_RegisterInterface(USBD_HandleTypeDef *pdev, - USBD_CDC_ItfTypeDef *fops) +uint8_t USBD_CDC_RegisterInterface(USBD_HandleTypeDef *pdev, + USBD_CDC_ItfTypeDef *fops) { - uint8_t ret = USBD_FAIL; - - if (fops != NULL) + if (fops == NULL) { - pdev->pUserData = fops; - ret = USBD_OK; + return (uint8_t)USBD_FAIL; } - return ret; + pdev->pUserData = fops; + + return (uint8_t)USBD_OK; } /** @@ -827,16 +829,15 @@ uint8_t USBD_CDC_RegisterInterface(USBD_HandleTypeDef *pdev, * @param pbuff: Tx Buffer * @retval status */ -uint8_t USBD_CDC_SetTxBuffer(USBD_HandleTypeDef *pdev, - uint8_t *pbuff, - uint16_t length) +uint8_t USBD_CDC_SetTxBuffer(USBD_HandleTypeDef *pdev, + uint8_t *pbuff, uint32_t length) { - USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData; + USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassData; hcdc->TxBuffer = pbuff; hcdc->TxLength = length; - return USBD_OK; + return (uint8_t)USBD_OK; } @@ -846,14 +847,13 @@ uint8_t USBD_CDC_SetTxBuffer(USBD_HandleTypeDef *pdev, * @param pbuff: Rx Buffer * @retval status */ -uint8_t USBD_CDC_SetRxBuffer(USBD_HandleTypeDef *pdev, - uint8_t *pbuff) +uint8_t USBD_CDC_SetRxBuffer(USBD_HandleTypeDef *pdev, uint8_t *pbuff) { - USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData; + USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassData; hcdc->RxBuffer = pbuff; - return USBD_OK; + return (uint8_t)USBD_OK; } /** @@ -862,35 +862,31 @@ uint8_t USBD_CDC_SetRxBuffer(USBD_HandleTypeDef *pdev, * @param pdev: device instance * @retval status */ -uint8_t USBD_CDC_TransmitPacket(USBD_HandleTypeDef *pdev) +uint8_t USBD_CDC_TransmitPacket(USBD_HandleTypeDef *pdev) { - USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData; + USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassData; + USBD_StatusTypeDef ret = USBD_BUSY; - if (pdev->pClassData != NULL) + if (pdev->pClassData == NULL) { - if (hcdc->TxState == 0U) - { - /* Tx Transfer in progress */ - hcdc->TxState = 1U; + return (uint8_t)USBD_FAIL; + } - /* Update the packet total length */ - pdev->ep_in[CDC_IN_EP & 0xFU].total_length = hcdc->TxLength; + if (hcdc->TxState == 0U) + { + /* Tx Transfer in progress */ + hcdc->TxState = 1U; - /* Transmit next packet */ - USBD_LL_Transmit(pdev, CDC_IN_EP, hcdc->TxBuffer, - (uint16_t)hcdc->TxLength); + /* Update the packet total length */ + pdev->ep_in[CDC_IN_EP & 0xFU].total_length = hcdc->TxLength; - return USBD_OK; - } - else - { - return USBD_BUSY; - } - } - else - { - return USBD_FAIL; + /* Transmit next packet */ + (void)USBD_LL_Transmit(pdev, CDC_IN_EP, hcdc->TxBuffer, hcdc->TxLength); + + ret = USBD_OK; } + + return (uint8_t)ret; } @@ -900,35 +896,29 @@ uint8_t USBD_CDC_TransmitPacket(USBD_HandleTypeDef *pdev) * @param pdev: device instance * @retval status */ -uint8_t USBD_CDC_ReceivePacket(USBD_HandleTypeDef *pdev) +uint8_t USBD_CDC_ReceivePacket(USBD_HandleTypeDef *pdev) { - USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *) pdev->pClassData; + USBD_CDC_HandleTypeDef *hcdc = (USBD_CDC_HandleTypeDef *)pdev->pClassData; - /* Suspend or Resume USB Out process */ - if (pdev->pClassData != NULL) + if (pdev->pClassData == NULL) { - if (pdev->dev_speed == USBD_SPEED_HIGH) - { - /* Prepare Out endpoint to receive next packet */ - USBD_LL_PrepareReceive(pdev, - CDC_OUT_EP, - hcdc->RxBuffer, - CDC_DATA_HS_OUT_PACKET_SIZE); - } - else - { - /* Prepare Out endpoint to receive next packet */ - USBD_LL_PrepareReceive(pdev, - CDC_OUT_EP, - hcdc->RxBuffer, - CDC_DATA_FS_OUT_PACKET_SIZE); - } - return USBD_OK; + return (uint8_t)USBD_FAIL; + } + + if (pdev->dev_speed == USBD_SPEED_HIGH) + { + /* Prepare Out endpoint to receive next packet */ + (void)USBD_LL_PrepareReceive(pdev, CDC_OUT_EP, hcdc->RxBuffer, + CDC_DATA_HS_OUT_PACKET_SIZE); } else { - return USBD_FAIL; + /* Prepare Out endpoint to receive next packet */ + (void)USBD_LL_PrepareReceive(pdev, CDC_OUT_EP, hcdc->RxBuffer, + CDC_DATA_FS_OUT_PACKET_SIZE); } + + return (uint8_t)USBD_OK; } /** * @} diff --git a/system/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc_if_template.c b/system/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc_if_template.c index 9ebf8fb9a8..60748c39ff 100644 --- a/system/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc_if_template.c +++ b/system/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc_if_template.c @@ -68,13 +68,15 @@ static int8_t TEMPLATE_Init(void); static int8_t TEMPLATE_DeInit(void); static int8_t TEMPLATE_Control(uint8_t cmd, uint8_t *pbuf, uint16_t length); static int8_t TEMPLATE_Receive(uint8_t *pbuf, uint32_t *Len); +static int8_t TEMPLATE_TransmitCplt(uint8_t *pbuf, uint32_t *Len, uint8_t epnum); USBD_CDC_ItfTypeDef USBD_CDC_Template_fops = { TEMPLATE_Init, TEMPLATE_DeInit, TEMPLATE_Control, - TEMPLATE_Receive + TEMPLATE_Receive, + TEMPLATE_TransmitCplt }; USBD_CDC_LineCodingTypeDef linecoding = @@ -192,7 +194,7 @@ static int8_t TEMPLATE_Control(uint8_t cmd, uint8_t *pbuf, uint16_t length) * * @note * This function will issue a NAK packet on any OUT packet received on - * USB endpoint untill exiting this function. If you exit this function + * USB endpoint until exiting this function. If you exit this function * before transfer is complete on CDC interface (ie. using DMA controller) * it will result in receiving more data while previous ones are still * not sent. @@ -203,6 +205,29 @@ static int8_t TEMPLATE_Control(uint8_t cmd, uint8_t *pbuf, uint16_t length) */ static int8_t TEMPLATE_Receive(uint8_t *Buf, uint32_t *Len) { + UNUSED(Buf); + UNUSED(Len); + + return (0); +} + +/** + * @brief TEMPLATE_TransmitCplt + * Data transmited callback + * + * @note + * This function is IN transfer complete callback used to inform user that + * the submitted Data is successfully sent over USB. + * + * @param Buf: Buffer of data to be received + * @param Len: Number of data received (in bytes) + * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL + */ +static int8_t TEMPLATE_TransmitCplt(uint8_t *Buf, uint32_t *Len, uint8_t epnum) +{ + UNUSED(Buf); + UNUSED(Len); + UNUSED(epnum); return (0); } diff --git a/system/Middlewares/ST/STM32_USB_Device_Library/Class/CDC_ECM/Inc/usbd_cdc_ecm.h b/system/Middlewares/ST/STM32_USB_Device_Library/Class/CDC_ECM/Inc/usbd_cdc_ecm.h new file mode 100644 index 0000000000..f4bef2c718 --- /dev/null +++ b/system/Middlewares/ST/STM32_USB_Device_Library/Class/CDC_ECM/Inc/usbd_cdc_ecm.h @@ -0,0 +1,255 @@ +/** + ****************************************************************************** + * @file usbd_cdc_ecm.h + * @author MCD Application Team + * @brief header file for the usbd_cdc_ecm.c file. + ****************************************************************************** + * @attention + * + *

    © Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

    + * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USB_CDC_ECM_H +#define __USB_CDC_ECM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_ioreq.h" + +/** @addtogroup STM32_USB_DEVICE_LIBRARY + * @{ + */ + +/** @defgroup usbd_cdc_ecm + * @brief This file is the Header file for usbd_cdc_ecm.c + * @{ + */ + + +/** @defgroup usbd_cdc_ecm_Exported_Defines + * @{ + */ +/* Comment this define in order to disable the CDC ECM Notification pipe */ + + +#define CDC_ECM_IN_EP 0x81U /* EP1 for data IN */ +#define CDC_ECM_OUT_EP 0x01U /* EP1 for data OUT */ +#define CDC_ECM_CMD_EP 0x82U /* EP2 for CDC ECM commands */ + +#ifndef CDC_ECM_CMD_ITF_NBR +#define CDC_ECM_CMD_ITF_NBR 0x00U /* Command Interface Number 0 */ +#endif /* CDC_ECM_CMD_ITF_NBR */ + +#ifndef CDC_ECM_COM_ITF_NBR +#define CDC_ECM_COM_ITF_NBR 0x01U /* Communication Interface Number 0 */ +#endif /* CDC_ECM_CMD_ITF_NBR */ + +#ifndef CDC_ECM_HS_BINTERVAL +#define CDC_ECM_HS_BINTERVAL 0x10U +#endif /* CDC_ECM_HS_BINTERVAL */ + +#ifndef CDC_ECM_FS_BINTERVAL +#define CDC_ECM_FS_BINTERVAL 0x10U +#endif /* CDC_ECM_FS_BINTERVAL */ + +#ifndef USBD_SUPPORT_USER_STRING_DESC +#define USBD_SUPPORT_USER_STRING_DESC 1U +#endif /* USBD_SUPPORT_USER_STRING_DESC */ + +/* CDC_ECM Endpoints parameters: you can fine tune these values depending on the needed baudrates and performance. */ +#define CDC_ECM_DATA_HS_MAX_PACKET_SIZE 512U /* Endpoint IN & OUT Packet size */ +#define CDC_ECM_DATA_FS_MAX_PACKET_SIZE 64U /* Endpoint IN & OUT Packet size */ +#define CDC_ECM_CMD_PACKET_SIZE 16U /* Control Endpoint Packet size */ + +#define CDC_ECM_CONFIG_DESC_SIZ 79U + +#define CDC_ECM_DATA_HS_IN_PACKET_SIZE CDC_ECM_DATA_HS_MAX_PACKET_SIZE +#define CDC_ECM_DATA_HS_OUT_PACKET_SIZE CDC_ECM_DATA_HS_MAX_PACKET_SIZE + +#define CDC_ECM_DATA_FS_IN_PACKET_SIZE CDC_ECM_DATA_FS_MAX_PACKET_SIZE +#define CDC_ECM_DATA_FS_OUT_PACKET_SIZE CDC_ECM_DATA_FS_MAX_PACKET_SIZE + +/*---------------------------------------------------------------------*/ +/* CDC_ECM definitions */ +/*---------------------------------------------------------------------*/ +#define CDC_ECM_SEND_ENCAPSULATED_COMMAND 0x00U +#define CDC_ECM_GET_ENCAPSULATED_RESPONSE 0x01U +#define CDC_ECM_SET_ETH_MULTICAST_FILTERS 0x40U +#define CDC_ECM_SET_ETH_PWRM_PATTERN_FILTER 0x41U +#define CDC_ECM_GET_ETH_PWRM_PATTERN_FILTER 0x42U +#define CDC_ECM_SET_ETH_PACKET_FILTER 0x43U +#define CDC_ECM_GET_ETH_STATISTIC 0x44U + +#define CDC_ECM_NET_DISCONNECTED 0x00U +#define CDC_ECM_NET_CONNECTED 0x01U + + +/* Ethernet statistics definitions */ +#define CDC_ECM_XMIT_OK_VAL CDC_ECM_ETH_STATS_VAL_ENABLED +#define CDC_ECM_XMIT_OK 0x01U +#define CDC_ECM_RVC_OK 0x02U +#define CDC_ECM_XMIT_ERROR 0x04U +#define CDC_ECM_RCV_ERROR 0x08U +#define CDC_ECM_RCV_NO_BUFFER 0x10U +#define CDC_ECM_DIRECTED_BYTES_XMIT 0x20U +#define CDC_ECM_DIRECTED_FRAMES_XMIT 0x40U +#define CDC_ECM_MULTICAST_BYTES_XMIT 0x80U + +#define CDC_ECM_MULTICAST_FRAMES_XMIT 0x01U +#define CDC_ECM_BROADCAST_BYTES_XMIT 0x02U +#define CDC_ECM_BROADCAST_FRAMES_XMIT 0x04U +#define CDC_ECM_DIRECTED_BYTES_RCV 0x08U +#define CDC_ECM_DIRECTED_FRAMES_RCV 0x10U +#define CDC_ECM_MULTICAST_BYTES_RCV 0x20U +#define CDC_ECM_MULTICAST_FRAMES_RCV 0x40U +#define CDC_ECM_BROADCAST_BYTES_RCV 0x80U + +#define CDC_ECM_BROADCAST_FRAMES_RCV 0x01U +#define CDC_ECM_RCV_CRC_ERROR 0x02U +#define CDC_ECM_TRANSMIT_QUEUE_LENGTH 0x04U +#define CDC_ECM_RCV_ERROR_ALIGNMENT 0x08U +#define CDC_ECM_XMIT_ONE_COLLISION 0x10U +#define CDC_ECM_XMIT_MORE_COLLISIONS 0x20U +#define CDC_ECM_XMIT_DEFERRED 0x40U +#define CDC_ECM_XMIT_MAX_COLLISIONS 0x80U + +#define CDC_ECM_RCV_OVERRUN 0x40U +#define CDC_ECM_XMIT_UNDERRUN 0x40U +#define CDC_ECM_XMIT_HEARTBEAT_FAILURE 0x40U +#define CDC_ECM_XMIT_TIMES_CRS_LOST 0x40U +#define CDC_ECM_XMIT_LATE_COLLISIONS 0x40U + +#define CDC_ECM_ETH_STATS_RESERVED 0xE0U +#define CDC_ECM_BMREQUEST_TYPE_ECM 0xA1U + +/* MAC String index */ +#define CDC_ECM_MAC_STRING_INDEX 6U + +/** + * @} + */ + + +/** @defgroup USBD_CORE_Exported_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +typedef struct +{ + int8_t (* Init)(void); + int8_t (* DeInit)(void); + int8_t (* Control)(uint8_t cmd, uint8_t *pbuf, uint16_t length); + int8_t (* Receive)(uint8_t *Buf, uint32_t *Len); + int8_t (* TransmitCplt)(uint8_t *Buf, uint32_t *Len, uint8_t epnum); + int8_t (* Process)(USBD_HandleTypeDef *pdev); + const uint8_t *pStrDesc; +} USBD_CDC_ECM_ItfTypeDef; + +typedef struct +{ + uint8_t bmRequest; + uint8_t bRequest; + uint16_t wValue; + uint16_t wIndex; + uint16_t wLength; + uint8_t data[8]; +} USBD_CDC_ECM_NotifTypeDef; + +typedef struct +{ + uint32_t data[2000 / 4]; /* Force 32bits alignment */ + uint8_t CmdOpCode; + uint8_t CmdLength; + uint8_t Reserved1; /* Reserved Byte to force 4 bytes alignment of following fields */ + uint8_t Reserved2; /* Reserved Byte to force 4 bytes alignment of following fields */ + uint8_t *RxBuffer; + uint8_t *TxBuffer; + uint32_t RxLength; + uint32_t TxLength; + + __IO uint32_t TxState; + __IO uint32_t RxState; + + __IO uint32_t MaxPcktLen; + __IO uint32_t LinkStatus; + __IO uint32_t NotificationStatus; + USBD_CDC_ECM_NotifTypeDef Req; +} USBD_CDC_ECM_HandleTypeDef; + +typedef enum +{ + NETWORK_CONNECTION = 0x00, + RESPONSE_AVAILABLE = 0x01, + CONNECTION_SPEED_CHANGE = 0x2A +} USBD_CDC_ECM_NotifCodeTypeDef; + +/** @defgroup USBD_CORE_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup USBD_CORE_Exported_Variables + * @{ + */ + +extern USBD_ClassTypeDef USBD_CDC_ECM; +#define USBD_CDC_ECM_CLASS &USBD_CDC_ECM +/** + * @} + */ + +/** @defgroup USB_CORE_Exported_Functions + * @{ + */ +uint8_t USBD_CDC_ECM_RegisterInterface(USBD_HandleTypeDef *pdev, + USBD_CDC_ECM_ItfTypeDef *fops); + +uint8_t USBD_CDC_ECM_SetTxBuffer(USBD_HandleTypeDef *pdev, uint8_t *pbuff, + uint32_t length); + +uint8_t USBD_CDC_ECM_SetRxBuffer(USBD_HandleTypeDef *pdev, uint8_t *pbuff); + +uint8_t USBD_CDC_ECM_ReceivePacket(USBD_HandleTypeDef *pdev); + +uint8_t USBD_CDC_ECM_TransmitPacket(USBD_HandleTypeDef *pdev); + +uint8_t USBD_CDC_ECM_SendNotification(USBD_HandleTypeDef *pdev, + USBD_CDC_ECM_NotifCodeTypeDef Notif, + uint16_t bVal, uint8_t *pData); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_CDC_ECM_H */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Middlewares/ST/STM32_USB_Device_Library/Class/CDC_ECM/Inc/usbd_cdc_ecm_if_template.h b/system/Middlewares/ST/STM32_USB_Device_Library/Class/CDC_ECM/Inc/usbd_cdc_ecm_if_template.h new file mode 100644 index 0000000000..7ce8714dfb --- /dev/null +++ b/system/Middlewares/ST/STM32_USB_Device_Library/Class/CDC_ECM/Inc/usbd_cdc_ecm_if_template.h @@ -0,0 +1,82 @@ +/** + ****************************************************************************** + * @file Inc/usbd_cdc_ecm_if_template.h + * @author MCD Application Team + * @brief Header for usbd_cdc_ecm_if_template.c file. + ****************************************************************************** + * @attention + * + *

    © Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

    + * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USBD_CDC_ECM_IF_H +#define __USBD_CDC_ECM_IF_H + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_cdc_ecm.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* Ensure this MAC address value is same as MAC_ADDRx declared in STM32xxx_conf.h */ +#define CDC_ECM_MAC_STR_DESC (uint8_t *)"000202030000" +#define CDC_ECM_MAC_ADDR0 0x00U /* 01 */ +#define CDC_ECM_MAC_ADDR1 0x02U /* 02 */ +#define CDC_ECM_MAC_ADDR2 0x02U /* 03 */ +#define CDC_ECM_MAC_ADDR3 0x03U /* 00 */ +#define CDC_ECM_MAC_ADDR4 0x00U /* 00 */ +#define CDC_ECM_MAC_ADDR5 0x00U /* 00 */ + +/* Max Number of Trials waiting for Tx ready */ +#define CDC_ECM_MAX_TX_WAIT_TRIALS 1000000U + +#define CDC_ECM_ETH_STATS_BYTE0 0U +/*(uint8_t)(CDC_ECM_XMIT_OK_VAL | CDC_ECM_RVC_OK_VAL | CDC_ECM_XMIT_ERROR_VAL | \ + CDC_ECM_RCV_ERROR_VAL | CDC_ECM_RCV_NO_BUFFER_VAL | CDC_ECM_DIRECTED_BYTES_XMIT_VAL | \ + CDC_ECM_DIRECTED_FRAMES_XMIT_VAL | CDC_ECM_MULTICAST_BYTES_XMIT_VAL) */ + +#define CDC_ECM_ETH_STATS_BYTE1 0U +/*(uint8_t)(CDC_ECM_MULTICAST_FRAMES_XMIT_VAL | CDC_ECM_BROADCAST_BYTES_XMIT_VAL | \ + CDC_ECM_BROADCAST_FRAMES_XMIT_VAL | CDC_ECM_DIRECTED_BYTES_RCV_VAL | \ + CDC_ECM_DIRECTED_FRAMES_RCV_VAL | CDC_ECM_MULTICAST_BYTES_RCV_VAL | \ + CDC_ECM_MULTICAST_FRAMES_RCV_VAL | CDC_ECM_BROADCAST_BYTES_RCV_VAL) */ + +#define CDC_ECM_ETH_STATS_BYTE2 0U +/*(uint8_t)(CDC_ECM_BROADCAST_FRAMES_RCV_VAL | CDC_ECM_RCV_CRC_ERROR_VAL | \ + CDC_ECM_TRANSMIT_QUEUE_LENGTH_VAL | CDC_ECM_RCV_ERROR_ALIGNMENT_VAL | \ + CDC_ECM_XMIT_ONE_COLLISION_VAL | CDC_ECM_XMIT_MORE_COLLISIONS_VAL | \ + CDC_ECM_XMIT_DEFERRED_VAL | CDC_ECM_XMIT_MAX_COLLISIONS_VAL) */ + +#define CDC_ECM_ETH_STATS_BYTE3 0U +/*(uint8_t)(CDC_ECM_RCV_OVERRUN_VAL | CDC_ECM_XMIT_UNDERRUN_VAL | CDC_ECM_XMIT_HEARTBEAT_FAILURE_VAL | \ + CDC_ECM_XMIT_TIMES_CRS_LOST_VAL | CDC_ECM_XMIT_LATE_COLLISIONS_VAL | CDC_ECM_ETH_STATS_RESERVED) */ + +/* Ethernet Maximum Segment size, typically 1514 bytes */ +#define CDC_ECM_ETH_MAX_SEGSZE 1514U + +/* Number of Ethernet multicast filters */ +#define CDC_ECM_ETH_NBR_MACFILTERS 0U + +/* Number of wakeup power filters */ +#define CDC_ECM_ETH_NBR_PWRFILTERS 0U + + +#define CDC_ECM_CONNECT_SPEED_UPSTREAM 0x004C4B40U /* 5Mbps */ +#define CDC_ECM_CONNECT_SPEED_DOWNSTREAM 0x004C4B40U /* 5Mbps */ + +extern USBD_CDC_ECM_ItfTypeDef USBD_CDC_ECM_fops; + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +#endif /* __USBD_CDC_ECM_IF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Middlewares/ST/STM32_USB_Device_Library/Class/CDC_ECM/Src/usbd_cdc_ecm.c b/system/Middlewares/ST/STM32_USB_Device_Library/Class/CDC_ECM/Src/usbd_cdc_ecm.c new file mode 100644 index 0000000000..edc5d220d0 --- /dev/null +++ b/system/Middlewares/ST/STM32_USB_Device_Library/Class/CDC_ECM/Src/usbd_cdc_ecm.c @@ -0,0 +1,1091 @@ +/** + ****************************************************************************** + * @file usbd_cdc_ecm.c + * @author MCD Application Team + * @brief This file provides the high layer firmware functions to manage the + * following functionalities of the USB CDC_ECM Class: + * - Initialization and Configuration of high and low layer + * - Enumeration as CDC_ECM Device (and enumeration for each implemented memory interface) + * - OUT/IN data transfer + * - Command IN transfer (class requests management) + * - Error management + * + ****************************************************************************** + * @attention + * + *

    © Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

    + * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ + +/* BSPDependencies +- "stm32xxxxx_{eval}{discovery}{nucleo_144}.c" +- "stm32xxxxx_{eval}{discovery}_io.c" +EndBSPDependencies */ + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_cdc_ecm.h" +#include "usbd_ctlreq.h" + +#ifndef __USBD_CDC_ECM_IF_H +#include "usbd_cdc_ecm_if_template.h" +#endif + + +/** @addtogroup STM32_USB_DEVICE_LIBRARY + * @{ + */ + + +/** @defgroup USBD_CDC_ECM + * @brief usbd core module + * @{ + */ + +/** @defgroup USBD_CDC_ECM_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + + +/** @defgroup USBD_CDC_ECM_Private_Defines + * @{ + */ +/** + * @} + */ + +/** @defgroup USBD_CDC_ECM_Private_Macros + * @{ + */ + +/** + * @} + */ + + +/** @defgroup USBD_CDC_ECM_Private_FunctionPrototypes + * @{ + */ + +static uint8_t USBD_CDC_ECM_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx); +static uint8_t USBD_CDC_ECM_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx); +static uint8_t USBD_CDC_ECM_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum); +static uint8_t USBD_CDC_ECM_DataOut(USBD_HandleTypeDef *pdev, uint8_t epnum); +static uint8_t USBD_CDC_ECM_EP0_RxReady(USBD_HandleTypeDef *pdev); +static uint8_t USBD_CDC_ECM_Setup(USBD_HandleTypeDef *pdev, + USBD_SetupReqTypedef *req); + +static uint8_t *USBD_CDC_ECM_GetFSCfgDesc(uint16_t *length); +static uint8_t *USBD_CDC_ECM_GetHSCfgDesc(uint16_t *length); +static uint8_t *USBD_CDC_ECM_GetOtherSpeedCfgDesc(uint16_t *length); +static uint8_t *USBD_CDC_ECM_GetOtherSpeedCfgDesc(uint16_t *length); + +#if (USBD_SUPPORT_USER_STRING_DESC == 1U) +static uint8_t *USBD_CDC_ECM_USRStringDescriptor(USBD_HandleTypeDef *pdev, + uint8_t index, uint16_t *length); +#endif + +uint8_t *USBD_CDC_ECM_GetDeviceQualifierDescriptor(uint16_t *length); + +/* USB Standard Device Descriptor */ +__ALIGN_BEGIN static uint8_t USBD_CDC_ECM_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_DESC] __ALIGN_END = +{ + USB_LEN_DEV_QUALIFIER_DESC, + USB_DESC_TYPE_DEVICE_QUALIFIER, + 0x00, + 0x02, + 0x00, + 0x00, + 0x00, + 0x40, + 0x01, + 0x00, +}; + +static uint32_t ConnSpeedTab[2] = {CDC_ECM_CONNECT_SPEED_UPSTREAM, + CDC_ECM_CONNECT_SPEED_DOWNSTREAM}; + +/** + * @} + */ + +/** @defgroup USBD_CDC_ECM_Private_Variables + * @{ + */ + + +/* CDC_ECM interface class callbacks structure */ +USBD_ClassTypeDef USBD_CDC_ECM = +{ + USBD_CDC_ECM_Init, + USBD_CDC_ECM_DeInit, + USBD_CDC_ECM_Setup, + NULL, /* EP0_TxSent, */ + USBD_CDC_ECM_EP0_RxReady, + USBD_CDC_ECM_DataIn, + USBD_CDC_ECM_DataOut, + NULL, + NULL, + NULL, + USBD_CDC_ECM_GetHSCfgDesc, + USBD_CDC_ECM_GetFSCfgDesc, + USBD_CDC_ECM_GetOtherSpeedCfgDesc, + USBD_CDC_ECM_GetDeviceQualifierDescriptor, +#if (USBD_SUPPORT_USER_STRING_DESC == 1U) + USBD_CDC_ECM_USRStringDescriptor, +#endif +}; + +/* USB CDC_ECM device Configuration Descriptor */ +__ALIGN_BEGIN static uint8_t USBD_CDC_ECM_CfgHSDesc[] __ALIGN_END = +{ + /* Configuration Descriptor */ + 0x09, /* bLength: Configuration Descriptor size */ + USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */ + LOBYTE(CDC_ECM_CONFIG_DESC_SIZ), /* wTotalLength:no of returned bytes */ + HIBYTE(CDC_ECM_CONFIG_DESC_SIZ), + 0x02, /* bNumInterfaces: 2 interface */ + 0x01, /* bConfigurationValue: Configuration value */ + 0x00, /* iConfiguration: Index of string descriptor describing the configuration */ + 0xC0, /* bmAttributes: self powered */ + 0x32, /* MaxPower 0 mA */ + + /*---------------------------------------------------------------------------*/ + + /* IAD descriptor */ + 0x08, /* bLength */ + 0x0B, /* bDescriptorType */ + 0x00, /* bFirstInterface */ + 0x02, /* bInterfaceCount */ + 0x02, /* bFunctionClass (Wireless Controller) */ + 0x06, /* bFunctionSubClass */ + 0x00, /* bFunctionProtocol */ + 0x00, /* iFunction */ + + /* Interface Descriptor */ + 0x09, /* bLength: Interface Descriptor size */ + USB_DESC_TYPE_INTERFACE, /* bDescriptorType: Interface descriptor type */ + CDC_ECM_CMD_ITF_NBR, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x01, /* bNumEndpoints: One endpoint used */ + 0x02, /* bInterfaceClass: Communication Interface Class */ + 0x06, /* bInterfaceSubClass: Ethernet Control Model */ + 0x00, /* bInterfaceProtocol: No specific protocol required */ + 0x00, /* iInterface: */ + + /* Header Functional Descriptor */ + 0x05, /* bLength: Endpoint Descriptor size */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x00, /* bDescriptorSubtype: Header functional descriptor */ + 0x10, /* bcd CDC_ECM: spec release number: 1.10 */ + 0x01, + + /* CDC_ECM Functional Descriptor */ + 0x0D, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x0F, /* Ethernet Networking functional descriptor subtype */ + CDC_ECM_MAC_STRING_INDEX, /* Device's MAC string index */ + CDC_ECM_ETH_STATS_BYTE3, /* Ethernet statistics byte 3 (bitmap) */ + CDC_ECM_ETH_STATS_BYTE2, /* Ethernet statistics byte 2 (bitmap) */ + CDC_ECM_ETH_STATS_BYTE1, /* Ethernet statistics byte 1 (bitmap) */ + CDC_ECM_ETH_STATS_BYTE0, /* Ethernet statistics byte 0 (bitmap) */ + LOBYTE(CDC_ECM_ETH_MAX_SEGSZE), + HIBYTE(CDC_ECM_ETH_MAX_SEGSZE), /* wMaxSegmentSize: Ethernet Maximum Segment size, typically 1514 bytes */ + LOBYTE(CDC_ECM_ETH_NBR_MACFILTERS), + HIBYTE(CDC_ECM_ETH_NBR_MACFILTERS), /* wNumberMCFilters: the number of multicast filters */ + CDC_ECM_ETH_NBR_PWRFILTERS, /* bNumberPowerFilters: the number of wakeup power filters */ + + /* Union Functional Descriptor */ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x06, /* bDescriptorSubtype: Union functional descriptor */ + 0x00, /* bMasterInterface: Communication class interface */ + 0x01, /* bSlaveInterface0: Data Class Interface */ + + /* Communication Endpoint Descriptor */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + CDC_ECM_CMD_EP, /* bEndpointAddress */ + 0x03, /* bmAttributes: Interrupt */ + LOBYTE(CDC_ECM_CMD_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(CDC_ECM_CMD_PACKET_SIZE), + CDC_ECM_HS_BINTERVAL, /* bInterval */ + + /*----------------------*/ + + /* Data class interface descriptor */ + 0x09, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_INTERFACE, /* bDescriptorType: */ + CDC_ECM_COM_ITF_NBR, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x02, /* bNumEndpoints: Two endpoints used */ + 0x0A, /* bInterfaceClass: CDC */ + 0x00, /* bInterfaceSubClass: */ + 0x00, /* bInterfaceProtocol: */ + 0x00, /* iInterface: */ + + /* Endpoint OUT Descriptor */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + CDC_ECM_OUT_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + LOBYTE(CDC_ECM_DATA_HS_MAX_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(CDC_ECM_DATA_HS_MAX_PACKET_SIZE), + 0xFF, /* bInterval: ignore for Bulk transfer */ + + /* Endpoint IN Descriptor */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + CDC_ECM_IN_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + LOBYTE(CDC_ECM_DATA_HS_MAX_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(CDC_ECM_DATA_HS_MAX_PACKET_SIZE), + 0xFF /* bInterval: ignore for Bulk transfer */ +}; + + +/* USB CDC_ECM device Configuration Descriptor */ +__ALIGN_BEGIN static uint8_t USBD_CDC_ECM_CfgFSDesc[] __ALIGN_END = +{ + /* Configuration Descriptor */ + 0x09, /* bLength: Configuration Descriptor size */ + USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */ + LOBYTE(CDC_ECM_CONFIG_DESC_SIZ), /* wTotalLength: Total size of the Config descriptor */ + HIBYTE(CDC_ECM_CONFIG_DESC_SIZ), + 0x02, /* bNumInterfaces: 2 interface */ + 0x01, /* bConfigurationValue: Configuration value */ + 0x00, /* iConfiguration: Index of string descriptor describing the configuration */ + 0xC0, /* bmAttributes: self powered */ + 0x32, /* MaxPower 0 mA */ + + /*---------------------------------------------------------------------------*/ + /* IAD descriptor */ + 0x08, /* bLength */ + 0x0B, /* bDescriptorType */ + 0x00, /* bFirstInterface */ + 0x02, /* bInterfaceCount */ + 0x02, /* bFunctionClass (Wireless Controller) */ + 0x06, /* bFunctionSubClass */ + 0x00, /* bFunctionProtocol */ + 0x00, /* iFunction */ + + /* Interface Descriptor */ + 0x09, /* bLength: Interface Descriptor size */ + USB_DESC_TYPE_INTERFACE, /* bDescriptorType: Interface descriptor type */ + CDC_ECM_CMD_ITF_NBR, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x01, /* bNumEndpoints: One endpoint used */ + 0x02, /* bInterfaceClass: Communication Interface Class */ + 0x06, /* bInterfaceSubClass: Ethernet Control Model */ + 0x00, /* bInterfaceProtocol: No specific protocol required */ + 0x00, /* iInterface: */ + + /* Header Functional Descriptor */ + 0x05, /* bLength: Endpoint Descriptor size */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x00, /* bDescriptorSubtype: Header functional descriptor */ + 0x10, /* bcd CDC_ECM : spec release number: 1.20 */ + 0x01, + + /* Union Functional Descriptor */ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x06, /* bDescriptorSubtype: Union functional descriptor */ + CDC_ECM_CMD_ITF_NBR, /* bMasterInterface: Communication class interface */ + CDC_ECM_COM_ITF_NBR, /* bSlaveInterface0: Data Class Interface */ + + /* CDC_ECM Functional Descriptor */ + 0x0D, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x0F, /* Ethernet Networking functional descriptor subtype */ + CDC_ECM_MAC_STRING_INDEX, /* Device's MAC string index */ + CDC_ECM_ETH_STATS_BYTE3, /* Ethernet statistics byte 3 (bitmap) */ + CDC_ECM_ETH_STATS_BYTE2, /* Ethernet statistics byte 2 (bitmap) */ + CDC_ECM_ETH_STATS_BYTE1, /* Ethernet statistics byte 1 (bitmap) */ + CDC_ECM_ETH_STATS_BYTE0, /* Ethernet statistics byte 0 (bitmap) */ + LOBYTE(CDC_ECM_ETH_MAX_SEGSZE), + HIBYTE(CDC_ECM_ETH_MAX_SEGSZE), /* wMaxSegmentSize: Ethernet Maximum Segment size, typically 1514 bytes */ + LOBYTE(CDC_ECM_ETH_NBR_MACFILTERS), + HIBYTE(CDC_ECM_ETH_NBR_MACFILTERS), /* wNumberMCFilters: the number of multicast filters */ + CDC_ECM_ETH_NBR_PWRFILTERS, /* bNumberPowerFilters: the number of wakeup power filters */ + + + /* Communication Endpoint Descriptor */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + CDC_ECM_CMD_EP, /* bEndpointAddress */ + 0x03, /* bmAttributes: Interrupt */ + LOBYTE(CDC_ECM_CMD_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(CDC_ECM_CMD_PACKET_SIZE), + CDC_ECM_FS_BINTERVAL, /* bInterval */ + + /*----------------------*/ + + /* Data class interface descriptor */ + 0x09, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_INTERFACE, /* bDescriptorType: */ + CDC_ECM_COM_ITF_NBR, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x02, /* bNumEndpoints: Two endpoints used */ + 0x0A, /* bInterfaceClass: CDC_ECM */ + 0x00, /* bInterfaceSubClass: */ + 0x00, /* bInterfaceProtocol: */ + 0x00, /* iInterface: */ + + /* Endpoint OUT Descriptor */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + CDC_ECM_OUT_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + LOBYTE(CDC_ECM_DATA_FS_MAX_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(CDC_ECM_DATA_FS_MAX_PACKET_SIZE), + 0xFF, /* bInterval: ignore for Bulk transfer */ + + /* Endpoint IN Descriptor */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + CDC_ECM_IN_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + LOBYTE(CDC_ECM_DATA_FS_MAX_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(CDC_ECM_DATA_FS_MAX_PACKET_SIZE), + 0xFF /* bInterval: ignore for Bulk transfer */ +} ; + +__ALIGN_BEGIN static uint8_t USBD_CDC_ECM_OtherSpeedCfgDesc[] __ALIGN_END = +{ + /* Configuration Descriptor */ + 0x09, /* bLength: Configuration Descriptor size */ + USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */ + LOBYTE(CDC_ECM_CONFIG_DESC_SIZ), /* wTotalLength:no of returned bytes */ + HIBYTE(CDC_ECM_CONFIG_DESC_SIZ), + 0x02, /* bNumInterfaces: 2 interface */ + 0x01, /* bConfigurationValue: Configuration value */ + 0x04, /* iConfiguration: Index of string descriptor describing the configuration */ + 0xC0, /* bmAttributes: self powered */ + 0x32, /* MaxPower 0 mA */ + + /*--------------------------------------- ------------------------------------*/ + /* IAD descriptor */ + 0x08, /* bLength */ + 0x0B, /* bDescriptorType */ + 0x00, /* bFirstInterface */ + 0x02, /* bInterfaceCount */ + 0x02, /* bFunctionClass (Wireless Controller) */ + 0x06, /* bFunctionSubClass */ + 0x00, /* bFunctionProtocol */ + 0x00, /* iFunction */ + + /* Interface Descriptor */ + 0x09, /* bLength: Interface Descriptor size */ + USB_DESC_TYPE_INTERFACE, /* bDescriptorType: Interface descriptor type */ + 0x00, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x01, /* bNumEndpoints: One endpoint used */ + 0x02, /* bInterfaceClass: Communication Interface Class */ + 0x06, /* bInterfaceSubClass: Ethernet Control Model */ + 0x00, /* bInterfaceProtocol: No specific protocol required */ + 0x00, /* iInterface: */ + + /* Header Functional Descriptor */ + 0x05, /* bLength: Endpoint Descriptor size */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x00, /* bDescriptorSubtype: Header functional descriptor */ + 0x10, /* bcd CDC_ECM : spec release number: 1.20 */ + 0x01, + + /* CDC_ECM Functional Descriptor */ + 0x0D, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x0F, /* Ethernet Networking functional descriptor subtype */ + CDC_ECM_MAC_STRING_INDEX, /* Device's MAC string index */ + CDC_ECM_ETH_STATS_BYTE3, /* Ethernet statistics byte 3 (bitmap) */ + CDC_ECM_ETH_STATS_BYTE2, /* Ethernet statistics byte 2 (bitmap) */ + CDC_ECM_ETH_STATS_BYTE1, /* Ethernet statistics byte 1 (bitmap) */ + CDC_ECM_ETH_STATS_BYTE0, /* Ethernet statistics byte 0 (bitmap) */ + LOBYTE(CDC_ECM_ETH_MAX_SEGSZE), + HIBYTE(CDC_ECM_ETH_MAX_SEGSZE), /* wMaxSegmentSize: Ethernet Maximum Segment size, typically 1514 bytes */ + LOBYTE(CDC_ECM_ETH_NBR_MACFILTERS), + HIBYTE(CDC_ECM_ETH_NBR_MACFILTERS), /* wNumberMCFilters: the number of multicast filters */ + CDC_ECM_ETH_NBR_PWRFILTERS, /* bNumberPowerFilters: the number of wakeup power filters */ + + /* Union Functional Descriptor */ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x06, /* bDescriptorSubtype: Union functional descriptor */ + 0x00, /* bMasterInterface: Communication class interface */ + 0x01, /* bSlaveInterface0: Data Class Interface */ + + /* Communication Endpoint Descriptor */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + CDC_ECM_CMD_EP, /* bEndpointAddress */ + 0x03, /* bmAttributes: Interrupt */ + LOBYTE(CDC_ECM_CMD_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(CDC_ECM_CMD_PACKET_SIZE), + CDC_ECM_FS_BINTERVAL, /* bInterval */ + + /*----------------------*/ + + /* Data class interface descriptor */ + 0x09, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_INTERFACE, /* bDescriptorType: */ + 0x01, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x02, /* bNumEndpoints: Two endpoints used */ + 0x0A, /* bInterfaceClass: CDC */ + 0x00, /* bInterfaceSubClass: */ + 0x00, /* bInterfaceProtocol: */ + 0x00, /* iInterface: */ + + /* Endpoint OUT Descriptor */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + CDC_ECM_OUT_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + 0x40, /* wMaxPacketSize: */ + 0x00, + 0xFF, /* bInterval: ignore for Bulk transfer */ + + /* Endpoint IN Descriptor */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + CDC_ECM_IN_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + 0x40, /* wMaxPacketSize: */ + 0x00, + 0xFF /* bInterval: ignore for Bulk transfer */ +}; + +/** + * @} + */ + +/** @defgroup USBD_CDC_ECM_Private_Functions + * @{ + */ + +/** + * @brief USBD_CDC_ECM_Init + * Initialize the CDC_ECM interface + * @param pdev: device instance + * @param cfgidx: Configuration index + * @retval status + */ +static uint8_t USBD_CDC_ECM_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx) +{ + UNUSED(cfgidx); + + USBD_CDC_ECM_HandleTypeDef *hcdc; + + hcdc = USBD_malloc(sizeof(USBD_CDC_ECM_HandleTypeDef)); + + if (hcdc == NULL) + { + pdev->pClassData = NULL; + return (uint8_t)USBD_EMEM; + } + + pdev->pClassData = (void *)hcdc; + + if (pdev->dev_speed == USBD_SPEED_HIGH) + { + /* Open EP IN */ + (void)USBD_LL_OpenEP(pdev, CDC_ECM_IN_EP, USBD_EP_TYPE_BULK, + CDC_ECM_DATA_HS_IN_PACKET_SIZE); + + pdev->ep_in[CDC_ECM_IN_EP & 0xFU].is_used = 1U; + + /* Open EP OUT */ + (void)USBD_LL_OpenEP(pdev, CDC_ECM_OUT_EP, USBD_EP_TYPE_BULK, + CDC_ECM_DATA_HS_OUT_PACKET_SIZE); + + pdev->ep_out[CDC_ECM_OUT_EP & 0xFU].is_used = 1U; + + /* Set bInterval for CDC ECM CMD Endpoint */ + pdev->ep_in[CDC_ECM_CMD_EP & 0xFU].bInterval = CDC_ECM_HS_BINTERVAL; + } + else + { + /* Open EP IN */ + (void)USBD_LL_OpenEP(pdev, CDC_ECM_IN_EP, USBD_EP_TYPE_BULK, + CDC_ECM_DATA_FS_IN_PACKET_SIZE); + + pdev->ep_in[CDC_ECM_IN_EP & 0xFU].is_used = 1U; + + /* Open EP OUT */ + (void)USBD_LL_OpenEP(pdev, CDC_ECM_OUT_EP, USBD_EP_TYPE_BULK, + CDC_ECM_DATA_FS_OUT_PACKET_SIZE); + + pdev->ep_out[CDC_ECM_OUT_EP & 0xFU].is_used = 1U; + + /* Set bInterval for CDC ECM CMD Endpoint */ + pdev->ep_in[CDC_ECM_CMD_EP & 0xFU].bInterval = CDC_ECM_FS_BINTERVAL; + } + + /* Open Command IN EP */ + (void)USBD_LL_OpenEP(pdev, CDC_ECM_CMD_EP, USBD_EP_TYPE_INTR, CDC_ECM_CMD_PACKET_SIZE); + pdev->ep_in[CDC_ECM_CMD_EP & 0xFU].is_used = 1U; + + /* Init physical Interface components */ + ((USBD_CDC_ECM_ItfTypeDef *)pdev->pUserData)->Init(); + + /* Init Xfer states */ + hcdc->TxState = 0U; + hcdc->RxState = 0U; + hcdc->RxLength = 0U; + hcdc->TxLength = 0U; + hcdc->LinkStatus = 0U; + hcdc->NotificationStatus = 0U; + hcdc->MaxPcktLen = (pdev->dev_speed == USBD_SPEED_HIGH) ? CDC_ECM_DATA_HS_MAX_PACKET_SIZE : CDC_ECM_DATA_FS_MAX_PACKET_SIZE; + + /* Prepare Out endpoint to receive next packet */ + (void)USBD_LL_PrepareReceive(pdev, CDC_ECM_OUT_EP, hcdc->RxBuffer, hcdc->MaxPcktLen); + + return (uint8_t)USBD_OK; +} + +/** + * @brief USBD_CDC_ECM_DeInit + * DeInitialize the CDC_ECM layer + * @param pdev: device instance + * @param cfgidx: Configuration index + * @retval status + */ +static uint8_t USBD_CDC_ECM_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx) +{ + UNUSED(cfgidx); + + /* Close EP IN */ + (void)USBD_LL_CloseEP(pdev, CDC_ECM_IN_EP); + pdev->ep_in[CDC_ECM_IN_EP & 0xFU].is_used = 0U; + + /* Close EP OUT */ + (void)USBD_LL_CloseEP(pdev, CDC_ECM_OUT_EP); + pdev->ep_out[CDC_ECM_OUT_EP & 0xFU].is_used = 0U; + + /* Close Command IN EP */ + (void)USBD_LL_CloseEP(pdev, CDC_ECM_CMD_EP); + pdev->ep_in[CDC_ECM_CMD_EP & 0xFU].is_used = 0U; + pdev->ep_in[CDC_ECM_CMD_EP & 0xFU].bInterval = 0U; + + /* DeInit physical Interface components */ + if (pdev->pClassData != NULL) + { + ((USBD_CDC_ECM_ItfTypeDef *)pdev->pUserData)->DeInit(); + USBD_free(pdev->pClassData); + pdev->pClassData = NULL; + } + + return (uint8_t)USBD_OK; +} + +/** + * @brief USBD_CDC_ECM_Setup + * Handle the CDC_ECM specific requests + * @param pdev: instance + * @param req: usb requests + * @retval status + */ +static uint8_t USBD_CDC_ECM_Setup(USBD_HandleTypeDef *pdev, + USBD_SetupReqTypedef *req) +{ + USBD_CDC_ECM_HandleTypeDef *hcdc = (USBD_CDC_ECM_HandleTypeDef *) pdev->pClassData; + USBD_CDC_ECM_ItfTypeDef *EcmInterface = (USBD_CDC_ECM_ItfTypeDef *)pdev->pUserData; + USBD_StatusTypeDef ret = USBD_OK; + uint8_t ifalt = 0U; + uint16_t status_info = 0U; + + switch (req->bmRequest & USB_REQ_TYPE_MASK) + { + case USB_REQ_TYPE_CLASS : + if (req->wLength != 0U) + { + if ((req->bmRequest & 0x80U) != 0U) + { + EcmInterface->Control(req->bRequest, + (uint8_t *)hcdc->data, req->wLength); + + (void)USBD_CtlSendData(pdev, (uint8_t *)hcdc->data, req->wLength); + } + else + { + hcdc->CmdOpCode = req->bRequest; + hcdc->CmdLength = (uint8_t)req->wLength; + + (void)USBD_CtlPrepareRx(pdev, (uint8_t *)hcdc->data, req->wLength); + } + } + else + { + EcmInterface->Control(req->bRequest, (uint8_t *)req, 0U); + } + break; + + case USB_REQ_TYPE_STANDARD: + switch (req->bRequest) + { + case USB_REQ_GET_STATUS: + if (pdev->dev_state == USBD_STATE_CONFIGURED) + { + (void)USBD_CtlSendData(pdev, (uint8_t *)&status_info, 2U); + } + else + { + USBD_CtlError(pdev, req); + ret = USBD_FAIL; + } + break; + + case USB_REQ_GET_INTERFACE: + if (pdev->dev_state == USBD_STATE_CONFIGURED) + { + (void)USBD_CtlSendData(pdev, &ifalt, 1U); + } + else + { + USBD_CtlError(pdev, req); + ret = USBD_FAIL; + } + break; + + case USB_REQ_SET_INTERFACE: + if (pdev->dev_state != USBD_STATE_CONFIGURED) + { + USBD_CtlError(pdev, req); + ret = USBD_FAIL; + } + break; + + case USB_REQ_CLEAR_FEATURE: + break; + + default: + USBD_CtlError(pdev, req); + ret = USBD_FAIL; + break; + } + break; + + default: + USBD_CtlError(pdev, req); + ret = USBD_FAIL; + break; + } + + return (uint8_t)ret; +} + +/** + * @brief USBD_CDC_ECM_DataIn + * Data sent on non-control IN endpoint + * @param pdev: device instance + * @param epnum: endpoint number + * @retval status + */ +static uint8_t USBD_CDC_ECM_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum) +{ + USBD_CDC_ECM_HandleTypeDef *hcdc = (USBD_CDC_ECM_HandleTypeDef *)pdev->pClassData; + PCD_HandleTypeDef *hpcd = pdev->pData; + + if (pdev->pClassData == NULL) + { + return (uint8_t)USBD_FAIL; + } + + if (epnum == (CDC_ECM_IN_EP & 0x7FU)) + { + if ((pdev->ep_in[epnum].total_length > 0U) && + ((pdev->ep_in[epnum].total_length % hpcd->IN_ep[epnum].maxpacket) == 0U)) + { + /* Update the packet total length */ + pdev->ep_in[epnum].total_length = 0U; + + /* Send ZLP */ + (void)USBD_LL_Transmit(pdev, epnum, NULL, 0U); + } + else + { + hcdc->TxState = 0U; + ((USBD_CDC_ECM_ItfTypeDef *)pdev->pUserData)->TransmitCplt(hcdc->TxBuffer, &hcdc->TxLength, epnum); + } + } + else if (epnum == (CDC_ECM_CMD_EP & 0x7FU)) + { + if (hcdc->NotificationStatus != 0U) + { + (void)USBD_CDC_ECM_SendNotification(pdev, CONNECTION_SPEED_CHANGE, + 0U, (uint8_t *)ConnSpeedTab); + + hcdc->NotificationStatus = 0U; + } + } + else + { + return (uint8_t)USBD_FAIL; + } + + return (uint8_t)USBD_OK; +} + +/** + * @brief USBD_CDC_ECM_DataOut + * Data received on non-control Out endpoint + * @param pdev: device instance + * @param epnum: endpoint number + * @retval status + */ +static uint8_t USBD_CDC_ECM_DataOut(USBD_HandleTypeDef *pdev, uint8_t epnum) +{ + USBD_CDC_ECM_HandleTypeDef *hcdc = (USBD_CDC_ECM_HandleTypeDef *)pdev->pClassData; + uint32_t CurrPcktLen; + + if (pdev->pClassData == NULL) + { + return (uint8_t)USBD_FAIL; + } + + if (epnum == CDC_ECM_OUT_EP) + { + /* Get the received data length */ + CurrPcktLen = USBD_LL_GetRxDataSize(pdev, epnum); + + /* Increment the frame length */ + hcdc->RxLength += CurrPcktLen; + + /* If the buffer size is less than max packet size: it is the last packet in current frame */ + if ((CurrPcktLen < hcdc->MaxPcktLen) || (hcdc->RxLength >= CDC_ECM_ETH_MAX_SEGSZE)) + { + /* USB data will be immediately processed, this allow next USB traffic being + NACKed till the end of the application Xfer */ + + /* Process data by application (ie. copy to app buffer or notify user) + hcdc->RxLength must be reset to zero at the end of the call of this function */ + ((USBD_CDC_ECM_ItfTypeDef *)pdev->pUserData)->Receive(hcdc->RxBuffer, &hcdc->RxLength); + } + else + { + /* Prepare Out endpoint to receive next packet in current/new frame */ + (void)USBD_LL_PrepareReceive(pdev, CDC_ECM_OUT_EP, + (uint8_t *)(hcdc->RxBuffer + hcdc->RxLength), + hcdc->MaxPcktLen); + } + } + else + { + return (uint8_t)USBD_FAIL; + } + + return (uint8_t)USBD_OK; +} + +/** + * @brief USBD_CDC_ECM_EP0_RxReady + * Handle EP0 Rx Ready event + * @param pdev: device instance + * @retval status + */ +static uint8_t USBD_CDC_ECM_EP0_RxReady(USBD_HandleTypeDef *pdev) +{ + USBD_CDC_ECM_HandleTypeDef *hcdc = (USBD_CDC_ECM_HandleTypeDef *)pdev->pClassData; + + if ((pdev->pUserData != NULL) && (hcdc->CmdOpCode != 0xFFU)) + { + ((USBD_CDC_ECM_ItfTypeDef *)pdev->pUserData)->Control(hcdc->CmdOpCode, + (uint8_t *)hcdc->data, + (uint16_t)hcdc->CmdLength); + hcdc->CmdOpCode = 0xFFU; + + } + return (uint8_t)USBD_OK; +} + +/** + * @brief USBD_CDC_ECM_GetFSCfgDesc + * Return configuration descriptor + * @param speed : current device speed + * @param length : pointer data length + * @retval pointer to descriptor buffer + */ +static uint8_t *USBD_CDC_ECM_GetFSCfgDesc(uint16_t *length) +{ + *length = (uint16_t)sizeof(USBD_CDC_ECM_CfgFSDesc); + + return USBD_CDC_ECM_CfgFSDesc; +} + +/** + * @brief USBD_CDC_ECM_GetHSCfgDesc + * Return configuration descriptor + * @param speed : current device speed + * @param length : pointer data length + * @retval pointer to descriptor buffer + */ +static uint8_t *USBD_CDC_ECM_GetHSCfgDesc(uint16_t *length) +{ + *length = (uint16_t) sizeof(USBD_CDC_ECM_CfgHSDesc); + + return USBD_CDC_ECM_CfgHSDesc; +} + +/** + * @brief USBD_CDC_ECM_GetCfgDesc + * Return configuration descriptor + * @param speed : current device speed + * @param length : pointer data length + * @retval pointer to descriptor buffer + */ +static uint8_t *USBD_CDC_ECM_GetOtherSpeedCfgDesc(uint16_t *length) +{ + *length = (uint16_t)sizeof(USBD_CDC_ECM_OtherSpeedCfgDesc); + + return USBD_CDC_ECM_OtherSpeedCfgDesc; +} + +/** + * @brief DeviceQualifierDescriptor + * return Device Qualifier descriptor + * @param length : pointer data length + * @retval pointer to descriptor buffer + */ +uint8_t *USBD_CDC_ECM_GetDeviceQualifierDescriptor(uint16_t *length) +{ + *length = (uint16_t)sizeof(USBD_CDC_ECM_DeviceQualifierDesc); + + return USBD_CDC_ECM_DeviceQualifierDesc; +} + +/** + * @brief USBD_CDC_ECM_RegisterInterface + * @param pdev: device instance + * @param fops: CD Interface callback + * @retval status + */ +uint8_t USBD_CDC_ECM_RegisterInterface(USBD_HandleTypeDef *pdev, + USBD_CDC_ECM_ItfTypeDef *fops) +{ + if (fops == NULL) + { + return (uint8_t)USBD_FAIL; + } + + pdev->pUserData = fops; + + return (uint8_t)USBD_OK; +} + + +/** + * @brief USBD_CDC_ECM_USRStringDescriptor + * Manages the transfer of user string descriptors. + * @param speed : current device speed + * @param index: descriptor index + * @param length : pointer data length + * @retval pointer to the descriptor table or NULL if the descriptor is not supported. + */ +#if (USBD_SUPPORT_USER_STRING_DESC == 1U) +static uint8_t *USBD_CDC_ECM_USRStringDescriptor(USBD_HandleTypeDef *pdev, uint8_t index, uint16_t *length) +{ + static uint8_t USBD_StrDesc[255]; + + /* Check if the requested string interface is supported */ + if (index == CDC_ECM_MAC_STRING_INDEX) + { + USBD_GetString((uint8_t *)((USBD_CDC_ECM_ItfTypeDef *)pdev->pUserData)->pStrDesc, USBD_StrDesc, length); + return USBD_StrDesc; + } + /* Not supported Interface Descriptor index */ + else + { + return NULL; + } +} +#endif + +/** + * @brief USBD_CDC_ECM_SetTxBuffer + * @param pdev: device instance + * @param pbuff: Tx Buffer + * @retval status + */ +uint8_t USBD_CDC_ECM_SetTxBuffer(USBD_HandleTypeDef *pdev, uint8_t *pbuff, uint32_t length) +{ + USBD_CDC_ECM_HandleTypeDef *hcdc = (USBD_CDC_ECM_HandleTypeDef *)pdev->pClassData; + + hcdc->TxBuffer = pbuff; + hcdc->TxLength = length; + + return (uint8_t)USBD_OK; +} + + +/** + * @brief USBD_CDC_ECM_SetRxBuffer + * @param pdev: device instance + * @param pbuff: Rx Buffer + * @retval status + */ +uint8_t USBD_CDC_ECM_SetRxBuffer(USBD_HandleTypeDef *pdev, uint8_t *pbuff) +{ + USBD_CDC_ECM_HandleTypeDef *hcdc = (USBD_CDC_ECM_HandleTypeDef *)pdev->pClassData; + + hcdc->RxBuffer = pbuff; + + return (uint8_t)USBD_OK; +} + +/** + * @brief USBD_CDC_ECM_TransmitPacket + * Transmit packet on IN endpoint + * @param pdev: device instance + * @retval status + */ +uint8_t USBD_CDC_ECM_TransmitPacket(USBD_HandleTypeDef *pdev) +{ + USBD_CDC_ECM_HandleTypeDef *hcdc = (USBD_CDC_ECM_HandleTypeDef *)pdev->pClassData; + USBD_StatusTypeDef ret = USBD_BUSY; + + if (pdev->pClassData == NULL) + { + return (uint8_t)USBD_FAIL; + } + + if (hcdc->TxState == 0U) + { + /* Tx Transfer in progress */ + hcdc->TxState = 1U; + + /* Update the packet total length */ + pdev->ep_in[CDC_ECM_IN_EP & 0xFU].total_length = hcdc->TxLength; + + /* Transmit next packet */ + (void)USBD_LL_Transmit(pdev, CDC_ECM_IN_EP, hcdc->TxBuffer, hcdc->TxLength); + + ret = USBD_OK; + } + + return (uint8_t)ret; +} + + +/** + * @brief USBD_CDC_ECM_ReceivePacket + * prepare OUT Endpoint for reception + * @param pdev: device instance + * @retval status + */ +uint8_t USBD_CDC_ECM_ReceivePacket(USBD_HandleTypeDef *pdev) +{ + USBD_CDC_ECM_HandleTypeDef *hcdc = (USBD_CDC_ECM_HandleTypeDef *)pdev->pClassData; + + if (pdev->pClassData == NULL) + { + return (uint8_t)USBD_FAIL; + } + + /* Prepare Out endpoint to receive next packet */ + (void)USBD_LL_PrepareReceive(pdev, CDC_ECM_OUT_EP,hcdc->RxBuffer, hcdc->MaxPcktLen); + + return (uint8_t)USBD_OK; +} + +/** + * @brief USBD_CDC_ECM_SendNotification + * Transmit Notification packet on CMD IN interrupt endpoint + * @param pdev: device instance + * Notif: value of the notification type (from CDC_ECM_Notification_TypeDef enumeration list) + * bVal: value of the notification switch (ie. 0x00 or 0x01 for Network Connection notification) + * pData: pointer to data buffer (ie. upstream and downstream connection speed values) + * @retval status + */ +uint8_t USBD_CDC_ECM_SendNotification(USBD_HandleTypeDef *pdev, + USBD_CDC_ECM_NotifCodeTypeDef Notif, + uint16_t bVal, uint8_t *pData) +{ + uint32_t Idx; + uint32_t ReqSize = 0U; + USBD_CDC_ECM_HandleTypeDef *hcdc = (USBD_CDC_ECM_HandleTypeDef *)pdev->pClassData; + USBD_StatusTypeDef ret = USBD_OK; + + /* Initialize the request fields */ + (hcdc->Req).bmRequest = CDC_ECM_BMREQUEST_TYPE_ECM; + (hcdc->Req).bRequest = (uint8_t)Notif; + + switch (Notif) + { + case NETWORK_CONNECTION: + (hcdc->Req).wValue = bVal; + (hcdc->Req).wIndex = CDC_ECM_CMD_ITF_NBR; + (hcdc->Req).wLength = 0U; + + for (Idx = 0U; Idx < 8U; Idx++) + { + (hcdc->Req).data[Idx] = 0U; + } + ReqSize = 8U; + break; + + case RESPONSE_AVAILABLE: + (hcdc->Req).wValue = 0U; + (hcdc->Req).wIndex = CDC_ECM_CMD_ITF_NBR; + (hcdc->Req).wLength = 0U; + for (Idx = 0U; Idx < 8U; Idx++) + { + (hcdc->Req).data[Idx] = 0U; + } + ReqSize = 8U; + break; + + case CONNECTION_SPEED_CHANGE: + (hcdc->Req).wValue = 0U; + (hcdc->Req).wIndex = CDC_ECM_CMD_ITF_NBR; + (hcdc->Req).wLength = 0x0008U; + ReqSize = 16U; + + /* Check pointer to data buffer */ + if (pData != NULL) + { + for (Idx = 0U; Idx < 8U; Idx++) + { + (hcdc->Req).data[Idx] = pData[Idx]; + } + } + break; + + default: + ret = USBD_FAIL; + break; + } + + /* Transmit notification packet */ + if (ReqSize != 0U) + { + (void)USBD_LL_Transmit(pdev, CDC_ECM_CMD_EP, (uint8_t *)&(hcdc->Req), ReqSize); + } + + return (uint8_t)ret; +} + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Middlewares/ST/STM32_USB_Device_Library/Class/CDC_ECM/Src/usbd_cdc_ecm_if_template.c b/system/Middlewares/ST/STM32_USB_Device_Library/Class/CDC_ECM/Src/usbd_cdc_ecm_if_template.c new file mode 100644 index 0000000000..9b96de8b4e --- /dev/null +++ b/system/Middlewares/ST/STM32_USB_Device_Library/Class/CDC_ECM/Src/usbd_cdc_ecm_if_template.c @@ -0,0 +1,247 @@ +/** + ****************************************************************************** + * @file Src/usbd_cdc_ecm_if_template.c + * @author MCD Application Team + * @brief Source file for USBD CDC_ECM interface + ****************************************************************************** + * @attention + * + *

    © Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

    + * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ + +#include "main.h" +/* + + Include here LwIP files if used + +*/ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +#if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 +#endif +__ALIGN_BEGIN static uint8_t UserRxBuffer[CDC_ECM_ETH_MAX_SEGSZE + 100]__ALIGN_END; /* Received Data over USB are stored in this buffer */ + +#if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 +#endif +__ALIGN_BEGIN static uint8_t UserTxBuffer[CDC_ECM_ETH_MAX_SEGSZE + 100]__ALIGN_END; /* Received Data over CDC_ECM (CDC_ECM interface) are stored in this buffer */ + +static uint8_t CDC_ECMInitialized = 0U; + +/* USB handler declaration */ +extern USBD_HandleTypeDef USBD_Device; + +/* Private function prototypes -----------------------------------------------*/ +static int8_t CDC_ECM_Itf_Init(void); +static int8_t CDC_ECM_Itf_DeInit(void); +static int8_t CDC_ECM_Itf_Control(uint8_t cmd, uint8_t *pbuf, uint16_t length); +static int8_t CDC_ECM_Itf_Receive(uint8_t *pbuf, uint32_t *Len); +static int8_t CDC_ECM_Itf_TransmitCplt(uint8_t *pbuf, uint32_t *Len, uint8_t epnum); +static int8_t CDC_ECM_Itf_Process(USBD_HandleTypeDef *pdev); + +USBD_CDC_ECM_ItfTypeDef USBD_CDC_ECM_fops = +{ + CDC_ECM_Itf_Init, + CDC_ECM_Itf_DeInit, + CDC_ECM_Itf_Control, + CDC_ECM_Itf_Receive, + CDC_ECM_Itf_TransmitCplt, + CDC_ECM_Itf_Process, + (uint8_t *)CDC_ECM_MAC_STR_DESC, +}; + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief CDC_ECM_Itf_Init + * Initializes the CDC_ECM media low layer + * @param None + * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL + */ +static int8_t CDC_ECM_Itf_Init(void) +{ + if (CDC_ECMInitialized == 0U) + { + /* + Initialize the TCP/IP stack here + */ + + CDC_ECMInitialized = 1U; + } + + /* Set Application Buffers */ + (void)USBD_CDC_ECM_SetTxBuffer(&USBD_Device, UserTxBuffer, 0U); + (void)USBD_CDC_ECM_SetRxBuffer(&USBD_Device, UserRxBuffer); + + return (0); +} + +/** + * @brief CDC_ECM_Itf_DeInit + * DeInitializes the CDC_ECM media low layer + * @param None + * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL + */ +static int8_t CDC_ECM_Itf_DeInit(void) +{ + USBD_CDC_ECM_HandleTypeDef *hcdc_cdc_ecm = (USBD_CDC_ECM_HandleTypeDef *)(USBD_Device.pClassData); + + /* Notify application layer that link is down */ + hcdc_cdc_ecm->LinkStatus = 0U; + + return (0); +} + +/** + * @brief CDC_ECM_Itf_Control + * Manage the CDC_ECM class requests + * @param Cmd: Command code + * @param Buf: Buffer containing command data (request parameters) + * @param Len: Number of data to be sent (in bytes) + * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL + */ +static int8_t CDC_ECM_Itf_Control(uint8_t cmd, uint8_t *pbuf, uint16_t length) +{ + USBD_CDC_ECM_HandleTypeDef *hcdc_cdc_ecm = (USBD_CDC_ECM_HandleTypeDef *)(USBD_Device.pClassData); + + switch (cmd) + { + case CDC_ECM_SEND_ENCAPSULATED_COMMAND: + /* Add your code here */ + break; + + case CDC_ECM_GET_ENCAPSULATED_RESPONSE: + /* Add your code here */ + break; + + case CDC_ECM_SET_ETH_MULTICAST_FILTERS: + /* Add your code here */ + break; + + case CDC_ECM_SET_ETH_PWRM_PATTERN_FILTER: + /* Add your code here */ + break; + + case CDC_ECM_GET_ETH_PWRM_PATTERN_FILTER: + /* Add your code here */ + break; + + case CDC_ECM_SET_ETH_PACKET_FILTER: + /* Check if this is the first time we enter */ + if (hcdc_cdc_ecm->LinkStatus == 0U) + { + /* + Setup the Link up at TCP/IP level + */ + hcdc_cdc_ecm->LinkStatus = 1U; + + /* Modification for MacOS which doesn't send SetInterface before receiving INs */ + if (hcdc_cdc_ecm->NotificationStatus == 0U) + { + /* Send notification: NETWORK_CONNECTION Event */ + (void)USBD_CDC_ECM_SendNotification(&USBD_Device, NETWORK_CONNECTION, + CDC_ECM_NET_CONNECTED, NULL); + + /* Prepare for sending Connection Speed Change notification */ + hcdc_cdc_ecm->NotificationStatus = 1U; + } + } + /* Add your code here */ + break; + + case CDC_ECM_GET_ETH_STATISTIC: + /* Add your code here */ + break; + + default: + break; + } + UNUSED(length); + UNUSED(pbuf); + + return (0); +} + +/** + * @brief CDC_ECM_Itf_Receive + * Data received over USB OUT endpoint are sent over CDC_ECM interface + * through this function. + * @param Buf: Buffer of data to be transmitted + * @param Len: Number of data received (in bytes) + * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL + */ +static int8_t CDC_ECM_Itf_Receive(uint8_t *Buf, uint32_t *Len) +{ + /* Get the CDC_ECM handler pointer */ + USBD_CDC_ECM_HandleTypeDef *hcdc_cdc_ecm = (USBD_CDC_ECM_HandleTypeDef *)(USBD_Device.pClassData); + + /* Call Eth buffer processing */ + hcdc_cdc_ecm->RxState = 1U; + + UNUSED(Len); + UNUSED(Buf); + + return (0); +} + +/** + * @brief CDC_ECM_Itf_TransmitCplt + * Data transmited callback + * + * @note + * This function is IN transfer complete callback used to inform user that + * the submitted Data is successfully sent over USB. + * + * @param Buf: Buffer of data to be received + * @param Len: Number of data received (in bytes) + * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL + */ +static int8_t CDC_ECM_Itf_TransmitCplt(uint8_t *Buf, uint32_t *Len, uint8_t epnum) +{ + UNUSED(Buf); + UNUSED(Len); + UNUSED(epnum); + + return (0); +} + +/** + * @brief CDC_ECM_Itf_Process + * Data received over USB OUT endpoint are sent over CDC_ECM interface + * through this function. + * @param pdef: pointer to the USB Device Handle + * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL + */ +static int8_t CDC_ECM_Itf_Process(USBD_HandleTypeDef *pdev) +{ + /* Get the CDC_ECM handler pointer */ + USBD_CDC_ECM_HandleTypeDef *hcdc_cdc_ecm = (USBD_CDC_ECM_HandleTypeDef *)(pdev->pClassData); + + if ((hcdc_cdc_ecm != NULL) && (hcdc_cdc_ecm->LinkStatus != 0U)) + { + /* + Read a received packet from the Ethernet buffers and send it + to the lwIP for handling + Call here the TCP/IP background tasks. + */ + } + + return (0); +} + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Middlewares/ST/STM32_USB_Device_Library/Class/CDC_RNDIS/Inc/usbd_cdc_rndis.h b/system/Middlewares/ST/STM32_USB_Device_Library/Class/CDC_RNDIS/Inc/usbd_cdc_rndis.h new file mode 100644 index 0000000000..ef76894400 --- /dev/null +++ b/system/Middlewares/ST/STM32_USB_Device_Library/Class/CDC_RNDIS/Inc/usbd_cdc_rndis.h @@ -0,0 +1,529 @@ +/** + ****************************************************************************** + * @file usbd_cdc_rndis.h + * @author MCD Application Team + * @brief header file for the usbd_cdc_rndis.c file. + ****************************************************************************** + * @attention + * + *

    © Copyright (c) 2015 STMicroelectronics. + * All rights reserved.

    + * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USB_CDC_RNDIS_H +#define __USB_CDC_RNDIS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_ioreq.h" + +/** @addtogroup STM32_USB_DEVICE_LIBRARY + * @{ + */ + +/** @defgroup usbd_cdc_rndis + * @brief This file is the Header file for usbd_cdc_rndis.c + * @{ + */ + + +/** @defgroup usbd_cdc_rndis_Exported_Defines + * @{ + */ + +#define CDC_RNDIS_IN_EP 0x81U /* EP1 for data IN */ +#define CDC_RNDIS_OUT_EP 0x01U /* EP1 for data OUT */ +#define CDC_RNDIS_CMD_EP 0x82U /* EP2 for CDC_RNDIS commands */ + +#ifndef CDC_RNDIS_CMD_ITF_NBR +#define CDC_RNDIS_CMD_ITF_NBR 0x00U /* Command Interface Number 0 */ +#endif /* CDC_RNDIS_CMD_ITF_NBR */ + +#ifndef CDC_RNDIS_COM_ITF_NBR +#define CDC_RNDIS_COM_ITF_NBR 0x01U /* Communication Interface Number 0 */ +#endif /* CDC_RNDIS_CMD_ITF_NBR */ + +#ifndef CDC_RNDIS_HS_BINTERVAL +#define CDC_RNDIS_HS_BINTERVAL 0x10U +#endif /* CDC_RNDIS_HS_BINTERVAL */ + +#ifndef CDC_RNDIS_FS_BINTERVAL +#define CDC_RNDIS_FS_BINTERVAL 0x10U +#endif /* CDC_RNDIS_FS_BINTERVAL */ + + +/* CDC_RNDIS Endpoints parameters: you can fine tune these values + depending on the needed baudrates and performance. */ +#define CDC_RNDIS_DATA_HS_MAX_PACKET_SIZE 512U /* Endpoint IN & OUT Packet size */ +#define CDC_RNDIS_DATA_FS_MAX_PACKET_SIZE 64U /* Endpoint IN & OUT Packet size */ +#define CDC_RNDIS_CMD_PACKET_SIZE 16U /* Control Endpoint Packet size */ + +#define CDC_RNDIS_CONFIG_DESC_SIZ 75U +#define CDC_RNDIS_DATA_HS_IN_PACKET_SIZE CDC_RNDIS_DATA_HS_MAX_PACKET_SIZE +#define CDC_RNDIS_DATA_HS_OUT_PACKET_SIZE CDC_RNDIS_DATA_HS_MAX_PACKET_SIZE + +#define CDC_RNDIS_DATA_FS_IN_PACKET_SIZE CDC_RNDIS_DATA_FS_MAX_PACKET_SIZE +#define CDC_RNDIS_DATA_FS_OUT_PACKET_SIZE CDC_RNDIS_DATA_FS_MAX_PACKET_SIZE + +/*---------------------------------------------------------------------*/ +/* CDC_RNDIS definitions */ +/*---------------------------------------------------------------------*/ + +/** Implemented CDC_RNDIS Version Major */ +#define CDC_RNDIS_VERSION_MAJOR 0x01U + +/* Implemented CDC_RNDIS Version Minor */ +#define CDC_RNDIS_VERSION_MINOR 0x00U + +/* Maximum size in bytes of a CDC_RNDIS control message + which can be sent or received */ +#define CDC_RNDIS_MESSAGE_BUFFER_SIZE 128U + +/* Maximum size in bytes of an Ethernet frame + according to the Ethernet standard */ +#define CDC_RNDIS_ETH_FRAME_SIZE_MAX 1536U + +/* Maximum size allocated for buffer + inside Query messages structures */ +#define CDC_RNDIS_MAX_INFO_BUFF_SZ 200U +#define CDC_RNDIS_MAX_DATA_SZE 2000U + +/* Notification request value for a CDC_RNDIS + Response Available notification */ +#define CDC_RNDIS_NOTIFICATION_RESP_AVAILABLE 0x00000001UL + + +#define CDC_RNDIS_PACKET_MSG_ID 0x00000001UL +#define CDC_RNDIS_INITIALIZE_MSG_ID 0x00000002UL +#define CDC_RNDIS_HALT_MSG_ID 0x00000003UL +#define CDC_RNDIS_QUERY_MSG_ID 0x00000004UL +#define CDC_RNDIS_SET_MSG_ID 0x00000005UL +#define CDC_RNDIS_RESET_MSG_ID 0x00000006UL +#define CDC_RNDIS_INDICATE_STATUS_MSG_ID 0x00000007UL +#define CDC_RNDIS_KEEPALIVE_MSG_ID 0x00000008UL + +#define CDC_RNDIS_INITIALIZE_CMPLT_ID 0x80000002UL +#define CDC_RNDIS_QUERY_CMPLT_ID 0x80000004UL +#define CDC_RNDIS_SET_CMPLT_ID 0x80000005UL +#define CDC_RNDIS_RESET_CMPLT_ID 0x80000006UL +#define CDC_RNDIS_KEEPALIVE_CMPLT_ID 0x80000008UL + +#define CDC_RNDIS_STATUS_SUCCESS 0x00000000UL +#define CDC_RNDIS_STATUS_FAILURE 0xC0000001UL +#define CDC_RNDIS_STATUS_INVALID_DATA 0xC0010015UL +#define CDC_RNDIS_STATUS_NOT_SUPPORTED 0xC00000BBUL +#define CDC_RNDIS_STATUS_MEDIA_CONNECT 0x4001000BUL +#define CDC_RNDIS_STATUS_MEDIA_DISCONNECT 0x4001000CUL +/** Media state */ +#define CDC_RNDIS_MEDIA_STATE_CONNECTED 0x00000000UL +#define CDC_RNDIS_MEDIA_STATE_DISCONNECTED 0x00000001UL + +/** Media types */ +#define CDC_RNDIS_MEDIUM_802_3 0x00000000UL + +#define CDC_RNDIS_DF_CONNECTIONLESS 0x00000001UL +#define CDC_RNDIS_DF_CONNECTION_ORIENTED 0x00000002UL + +/** Hardware status of the underlying NIC */ +#define CDC_RNDIS_HW_STS_READY 0x00000000UL +#define CDC_RNDIS_HW_STS_INITIALIZING 0x00000001UL +#define CDC_RNDIS_HW_STS_RESET 0x00000002UL +#define CDC_RNDIS_HW_STS_CLOSING 0x00000003UL +#define CDC_RNDIS_HW_STS_NOT_READY 0x00000004UL + +/** Packet filter */ +#define CDC_RNDIS_PACKET_DIRECTED 0x00000001UL +#define CDC_RNDIS_PACKET_MULTICAST 0x00000002UL +#define CDC_RNDIS_PACKET_ALL_MULTICAST 0x00000004UL +#define CDC_RNDIS_PACKET_BROADCAST 0x00000008UL +#define CDC_RNDIS_PACKET_SOURCE_ROUTING 0x00000010UL +#define CDC_RNDIS_PACKET_PROMISCUOUS 0x00000020UL +#define CDC_RNDIS_PACKET_SMT 0x00000040UL +#define CDC_RNDIS_PACKET_ALL_LOCAL 0x00000080UL +#define CDC_RNDIS_PACKET_GROUP 0x00001000UL +#define CDC_RNDIS_PACKET_ALL_FUNCTIONAL 0x00002000UL +#define CDC_RNDIS_PACKET_FUNCTIONAL 0x00004000UL +#define CDC_RNDIS_PACKET_MAC_FRAME 0x00008000UL + +#define OID_GEN_SUPPORTED_LIST 0x00010101UL +#define OID_GEN_HARDWARE_STATUS 0x00010102UL +#define OID_GEN_MEDIA_SUPPORTED 0x00010103UL +#define OID_GEN_MEDIA_IN_USE 0x00010104UL +#define OID_GEN_MAXIMUM_FRAME_SIZE 0x00010106UL +#define OID_GEN_MAXIMUM_TOTAL_SIZE 0x00010111UL +#define OID_GEN_LINK_SPEED 0x00010107UL +#define OID_GEN_TRANSMIT_BLOCK_SIZE 0x0001010AUL +#define OID_GEN_RECEIVE_BLOCK_SIZE 0x0001010BUL +#define OID_GEN_VENDOR_ID 0x0001010CUL +#define OID_GEN_VENDOR_DESCRIPTION 0x0001010DUL +#define OID_GEN_CURRENT_PACKET_FILTER 0x0001010EUL +#define OID_GEN_MEDIA_CONNECT_STATUS 0x00010114UL +#define OID_GEN_MAXIMUM_SEND_PACKETS 0x00010115UL +#define OID_GEN_PHYSICAL_MEDIUM 0x00010202UL +#define OID_GEN_XMIT_OK 0x00020101UL +#define OID_GEN_RCV_OK 0x00020102UL +#define OID_GEN_XMIT_ERROR 0x00020103UL +#define OID_GEN_RCV_ERROR 0x00020104UL +#define OID_GEN_RCV_NO_BUFFER 0x00020105UL +#define OID_GEN_CDC_RNDIS_CONFIG_PARAMETER 0x0001021BUL +#define OID_802_3_PERMANENT_ADDRESS 0x01010101UL +#define OID_802_3_CURRENT_ADDRESS 0x01010102UL +#define OID_802_3_MULTICAST_LIST 0x01010103UL +#define OID_802_3_MAXIMUM_LIST_SIZE 0x01010104UL +#define OID_802_3_RCV_ERROR_ALIGNMENT 0x01020101UL +#define OID_802_3_XMIT_ONE_COLLISION 0x01020102UL +#define OID_802_3_XMIT_MORE_COLLISIONS 0x01020103UL + + +#define CDC_RNDIS_SEND_ENCAPSULATED_COMMAND 0x00U +#define CDC_RNDIS_GET_ENCAPSULATED_RESPONSE 0x01U + +#define CDC_RNDIS_NET_DISCONNECTED 0x00U +#define CDC_RNDIS_NET_CONNECTED 0x01U + +#define CDC_RNDIS_BMREQUEST_TYPE_RNDIS 0xA1U +#define CDC_RNDIS_PCKTMSG_DATAOFFSET_OFFSET 8U + +/* MAC String index */ +#define CDC_RNDIS_MAC_STRING_INDEX 6U + +/** + * @} + */ + + +/** @defgroup USBD_CORE_Exported_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +typedef struct _USBD_CDC_RNDIS_Itf +{ + int8_t (* Init)(void); + int8_t (* DeInit)(void); + int8_t (* Control)(uint8_t cmd, uint8_t *pbuf, uint16_t length); + int8_t (* Receive)(uint8_t *Buf, uint32_t *Len); + int8_t (* TransmitCplt)(uint8_t *Buf, uint32_t *Len, uint8_t epnum); + int8_t (* Process)(USBD_HandleTypeDef *pdev); + uint8_t *pStrDesc; +} USBD_CDC_RNDIS_ItfTypeDef; + +/* CDC_RNDIS State values */ +typedef enum +{ + CDC_RNDIS_STATE_UNINITIALIZED = 0, + CDC_RNDIS_STATE_BUS_INITIALIZED = 1, + CDC_RNDIS_STATE_INITIALIZED = 2, + CDC_RNDIS_STATE_DATA_INITIALIZED = 3 +} USBD_CDC_RNDIS_StateTypeDef; + +typedef struct +{ + uint8_t bmRequest; + uint8_t bRequest; + uint16_t wValue; + uint16_t wIndex; + uint16_t wLength; + uint8_t data[8]; +} USBD_CDC_RNDIS_NotifTypeDef; + +typedef struct +{ + uint32_t data[2000 / 4]; /* Force 32bits alignment */ + uint8_t CmdOpCode; + uint8_t CmdLength; + uint8_t ResponseRdy; /* Indicates if the Device Response to an CDC_RNDIS msg is ready */ + uint8_t Reserved1; /* Reserved Byte to force 4 bytes alignment of following fields */ + uint8_t *RxBuffer; + uint8_t *TxBuffer; + uint32_t RxLength; + uint32_t TxLength; + + USBD_CDC_RNDIS_NotifTypeDef Req; + USBD_CDC_RNDIS_StateTypeDef State; + + __IO uint32_t TxState; + __IO uint32_t RxState; + + __IO uint32_t MaxPcktLen; + __IO uint32_t LinkStatus; + __IO uint32_t NotificationStatus; + __IO uint32_t PacketFilter; +} USBD_CDC_RNDIS_HandleTypeDef; + + +typedef enum +{ + NETWORK_CONNECTION = 0x00, + RESPONSE_AVAILABLE = 0x01, + CONNECTION_SPEED_CHANGE = 0x2A +} USBD_CDC_RNDIS_NotifCodeTypeDef; + + +/* Messages Sent by the Host ---------------------*/ + +/* Type define for a CDC_RNDIS Initialize command message */ +typedef struct +{ + uint32_t MsgType; + uint32_t MsgLength; + uint32_t ReqId; + uint32_t MajorVersion; + uint32_t MinorVersion; + uint32_t MaxTransferSize; +} USBD_CDC_RNDIS_InitMsgTypeDef; + +/* Type define for a CDC_RNDIS Halt Message */ +typedef struct +{ + uint32_t MsgType; + uint32_t MsgLength; + uint32_t ReqId; +} USBD_CDC_RNDIS_HaltMsgTypeDef; + +/* Type define for a CDC_RNDIS Query command message */ +typedef struct +{ + uint32_t MsgType; + uint32_t MsgLength; + uint32_t RequestId; + uint32_t Oid; + uint32_t InfoBufLength; + uint32_t InfoBufOffset; + uint32_t DeviceVcHandle; + uint32_t InfoBuf[CDC_RNDIS_MAX_INFO_BUFF_SZ]; +} USBD_CDC_RNDIS_QueryMsgTypeDef; + +/* Type define for a CDC_RNDIS Set command message */ +typedef struct +{ + uint32_t MsgType; + uint32_t MsgLength; + uint32_t ReqId; + uint32_t Oid; + uint32_t InfoBufLength; + uint32_t InfoBufOffset; + uint32_t DeviceVcHandle; + uint32_t InfoBuf[CDC_RNDIS_MAX_INFO_BUFF_SZ]; +} USBD_CDC_RNDIS_SetMsgTypeDef; + +/* Type define for a CDC_RNDIS Reset message */ +typedef struct +{ + uint32_t MsgType; + uint32_t MsgLength; + uint32_t Reserved; +} USBD_CDC_RNDIS_ResetMsgTypeDef; + +/* Type define for a CDC_RNDIS Keepalive command message */ +typedef struct +{ + uint32_t MsgType; + uint32_t MsgLength; + uint32_t ReqId; +} USBD_CDC_RNDIS_KpAliveMsgTypeDef; + + +/* Messages Sent by the Device ---------------------*/ + +/* Type define for a CDC_RNDIS Initialize complete response message */ +typedef struct +{ + uint32_t MsgType; + uint32_t MsgLength; + uint32_t ReqId; + uint32_t Status; + uint32_t MajorVersion; + uint32_t MinorVersion; + uint32_t DeviceFlags; + uint32_t Medium; + uint32_t MaxPacketsPerTransfer; + uint32_t MaxTransferSize; + uint32_t PacketAlignmentFactor; + uint32_t AFListOffset; + uint32_t AFListSize; +} USBD_CDC_RNDIS_InitCpltMsgTypeDef; + +/* Type define for a CDC_RNDIS Query complete response message */ +typedef struct +{ + uint32_t MsgType; + uint32_t MsgLength; + uint32_t ReqId; + uint32_t Status; + uint32_t InfoBufLength; + uint32_t InfoBufOffset; + uint32_t InfoBuf[CDC_RNDIS_MAX_INFO_BUFF_SZ]; +} USBD_CDC_RNDIS_QueryCpltMsgTypeDef; + +/* Type define for a CDC_RNDIS Set complete response message */ +typedef struct +{ + uint32_t MsgType; + uint32_t MsgLength; + uint32_t ReqId; + uint32_t Status; +} USBD_CDC_RNDIS_SetCpltMsgTypeDef; + +/* Type define for a CDC_RNDIS Reset complete message */ +typedef struct +{ + uint32_t MsgType; + uint32_t MsgLength; + uint32_t Status; + uint32_t AddrReset; +} USBD_CDC_RNDIS_ResetCpltMsgTypeDef; + +/* Type define for CDC_RNDIS struct to indicate a change + in the status of the device */ +typedef struct +{ + uint32_t MsgType; + uint32_t MsgLength; + uint32_t Status; + uint32_t StsBufLength; + uint32_t StsBufOffset; +} USBD_CDC_RNDIS_StsChangeMsgTypeDef; + +/* Type define for a CDC_RNDIS Keepalive complete message */ +typedef struct +{ + uint32_t MsgType; + uint32_t MsgLength; + uint32_t ReqId; + uint32_t Status; +} USBD_CDC_RNDIS_KpAliveCpltMsgTypeDef; + + +/* Messages Sent by both Host and Device ---------------------*/ + +/* Type define for a CDC_RNDIS packet message, used to encapsulate + Ethernet packets sent to and from the adapter */ +typedef struct +{ + uint32_t MsgType; + uint32_t MsgLength; + uint32_t DataOffset; + uint32_t DataLength; + uint32_t OOBDataOffset; + uint32_t OOBDataLength; + uint32_t NumOOBDataElements; + uint32_t PerPacketInfoOffset; + uint32_t PerPacketInfoLength; + uint32_t VcHandle; + uint32_t Reserved; +} USBD_CDC_RNDIS_PacketMsgTypeDef; + +/* Miscellaneous types used for parsing ---------------------*/ + +/* The common part for all CDC_RNDIS messages Complete response */ +typedef struct +{ + uint32_t MsgType; + uint32_t MsgLength; + uint32_t ReqId; + uint32_t Status; +} USBD_CDC_RNDIS_CommonCpltMsgTypeDef; + +/* Type define for a single parameter structure */ +typedef struct +{ + uint32_t ParamNameOffset; + uint32_t ParamNameLength; + uint32_t ParamType; + uint32_t ParamValueOffset; + uint32_t ParamValueLength; +} USBD_CDC_RNDIS_ParamStructTypeDef; + + +/* Type define of a single CDC_RNDIS OOB data record */ +typedef struct +{ + uint32_t Size; + uint32_t Type; + uint32_t ClassInfoType; + uint32_t OOBData[sizeof(uint32_t)]; +} USBD_CDC_RNDIS_OOBPacketTypeDef; + +/* Type define for notification structure */ +typedef struct +{ + uint32_t notification; + uint32_t reserved; +} USBD_CDC_RNDIS_NotifStructTypeDef; + +/* This structure will be used to store the type, the size and ID for any + received message from the control endpoint */ +typedef struct +{ + uint32_t MsgType; + uint32_t MsgLength; +} USBD_CDC_RNDIS_CtrlMsgTypeDef; + + +/** @defgroup USBD_CORE_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup USBD_CORE_Exported_Variables + * @{ + */ + +extern USBD_ClassTypeDef USBD_CDC_RNDIS; +#define USBD_CDC_RNDIS_CLASS &USBD_CDC_RNDIS +/** + * @} + */ + +/** @defgroup USB_CORE_Exported_Functions + * @{ + */ +uint8_t USBD_CDC_RNDIS_SetRxBuffer(USBD_HandleTypeDef *pdev, uint8_t *pbuff); +uint8_t USBD_CDC_RNDIS_ReceivePacket(USBD_HandleTypeDef *pdev); +uint8_t USBD_CDC_RNDIS_TransmitPacket(USBD_HandleTypeDef *pdev); + +uint8_t USBD_CDC_RNDIS_RegisterInterface(USBD_HandleTypeDef *pdev, + USBD_CDC_RNDIS_ItfTypeDef *fops); + +uint8_t USBD_CDC_RNDIS_SetTxBuffer(USBD_HandleTypeDef *pdev, + uint8_t *pbuff, uint32_t length); + +uint8_t USBD_CDC_RNDIS_SendNotification(USBD_HandleTypeDef *pdev, + USBD_CDC_RNDIS_NotifCodeTypeDef Notif, + uint16_t bVal, uint8_t *pData); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_CDC_RNDIS_H */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Middlewares/ST/STM32_USB_Device_Library/Class/CDC_RNDIS/Inc/usbd_cdc_rndis_if_template.h b/system/Middlewares/ST/STM32_USB_Device_Library/Class/CDC_RNDIS/Inc/usbd_cdc_rndis_if_template.h new file mode 100644 index 0000000000..3cf0271654 --- /dev/null +++ b/system/Middlewares/ST/STM32_USB_Device_Library/Class/CDC_RNDIS/Inc/usbd_cdc_rndis_if_template.h @@ -0,0 +1,60 @@ +/** + ****************************************************************************** + * @file usbd_cdc_rndis_if_template.h + * @author MCD Application Team + * @brief Header for usbd_cdc_rndis_if.c file. + ****************************************************************************** + * @attention + * + *

    © Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

    + * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USBD_CDC_RNDIS_IF_H +#define __USBD_CDC_RNDIS_IF_H + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_cdc_rndis.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* Ensure this MAC address value is same as MAC_ADDRx declared in STM32xxx_conf.h */ +#define CDC_RNDIS_MAC_STR_DESC (uint8_t *)"000202030000" +#define CDC_RNDIS_MAC_ADDR0 0x00U /* 01 */ +#define CDC_RNDIS_MAC_ADDR1 0x02U /* 02 */ +#define CDC_RNDIS_MAC_ADDR2 0x02U /* 03 */ +#define CDC_RNDIS_MAC_ADDR3 0x03U /* 00 */ +#define CDC_RNDIS_MAC_ADDR4 0x00U /* 00 */ +#define CDC_RNDIS_MAC_ADDR5 0x00U /* 00 */ + +#define USBD_CDC_RNDIS_VENDOR_DESC "STMicroelectronics" +#define USBD_CDC_RNDIS_LINK_SPEED 100000U /* 10Mbps */ +#define USBD_CDC_RNDIS_VID 0x0483U + +/* Max Number of Trials waiting for Tx ready */ +#define CDC_RNDIS_MAX_TX_WAIT_TRIALS 1000000U + +/* Ethernet Maximum Segment size, typically 1514 bytes */ +#define CDC_RNDIS_ETH_MAX_SEGSZE 1514U + +#define CDC_RNDIS_CONNECT_SPEED_UPSTREAM 0x1E000000U +#define CDC_RNDIS_CONNECT_SPEED_DOWNSTREAM 0x1E000000U + + +extern USBD_CDC_RNDIS_ItfTypeDef USBD_CDC_RNDIS_fops; + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +#endif /* __USBD_CDC_RNDIS_IF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Middlewares/ST/STM32_USB_Device_Library/Class/CDC_RNDIS/Src/usbd_cdc_rndis.c b/system/Middlewares/ST/STM32_USB_Device_Library/Class/CDC_RNDIS/Src/usbd_cdc_rndis.c new file mode 100644 index 0000000000..946ed5018c --- /dev/null +++ b/system/Middlewares/ST/STM32_USB_Device_Library/Class/CDC_RNDIS/Src/usbd_cdc_rndis.c @@ -0,0 +1,1698 @@ +/** + ****************************************************************************** + * @file usbd_cdc_rndis.c + * @author MCD Application Team + * @brief This file provides the high layer firmware functions to manage the + * following functionalities of the USB CDC_RNDIS Class: + * - Initialization and Configuration of high and low layer + * - Enumeration as CDC_RNDIS Device (and enumeration for each implemented memory interface) + * - OUT/IN data transfer + * - Command IN transfer (class requests management) + * - Error management + * + * @verbatim + * + * =================================================================== + * CDC_RNDIS Class Driver Description + * =================================================================== + * This driver manages the "Universal Serial Bus Class Definitions for Communications Devices + * Revision 1.2 November 16, 2007" and the sub-protocol specification of "Universal Serial Bus + * Communications Class Subclass Specification for PSTN Devices Revision 1.2 February 9, 2007" + * This driver implements the following aspects of the specification: + * - Device descriptor management + * - Configuration descriptor management + * - Enumeration as CDC device with 2 data endpoints (IN and OUT) and 1 command endpoint (IN) + * - Requests management (as described in section 6.2 in specification) + * - Abstract Control Model compliant + * - Union Functional collection (using 1 IN endpoint for control) + * - Data interface class + * + * These aspects may be enriched or modified for a specific user application. + * + * This driver doesn't implement the following aspects of the specification + * (but it is possible to manage these features with some modifications on this driver): + * - Any class-specific aspect relative to communication classes should be managed by user application. + * - All communication classes other than PSTN are not managed + * + * @endverbatim + * + ****************************************************************************** + * @attention + * + *

    © Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

    + * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "usbd_cdc_rndis.h" +#include "usbd_ctlreq.h" + +#ifndef __USBD_CDC_RNDIS_IF_H +#include "usbd_cdc_rndis_if_template.h" +#endif +/** @addtogroup STM32_USB_DEVICE_LIBRARY + * @{ + */ + + +/** @defgroup USBD_CDC_RNDIS + * @brief usbd core module + * @{ + */ + +/** @defgroup USBD_CDC_RNDIS_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + + +/** @defgroup USBD_CDC_RNDIS_Private_Defines + * @{ + */ +/** + * @} + */ + + +/** @defgroup USBD_CDC_RNDIS_Private_Macros + * @{ + */ + +/** + * @} + */ + + +/** @defgroup USBD_CDC_RNDIS_Private_FunctionPrototypes + * @{ + */ + +static uint8_t USBD_CDC_RNDIS_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx); +static uint8_t USBD_CDC_RNDIS_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx); + +static uint8_t USBD_CDC_RNDIS_Setup(USBD_HandleTypeDef *pdev, + USBD_SetupReqTypedef *req); + +static uint8_t USBD_CDC_RNDIS_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum); +static uint8_t USBD_CDC_RNDIS_DataOut(USBD_HandleTypeDef *pdev, uint8_t epnum); +static uint8_t USBD_CDC_RNDIS_EP0_RxReady(USBD_HandleTypeDef *pdev); +static uint8_t *USBD_CDC_RNDIS_GetFSCfgDesc(uint16_t *length); +static uint8_t *USBD_CDC_RNDIS_GetHSCfgDesc(uint16_t *length); +static uint8_t *USBD_CDC_RNDIS_GetOtherSpeedCfgDesc(uint16_t *length); +static uint8_t *USBD_CDC_RNDIS_GetOtherSpeedCfgDesc(uint16_t *length); + +#if (USBD_SUPPORT_USER_STRING_DESC == 1U) +static uint8_t *USBD_CDC_RNDIS_USRStringDescriptor(USBD_HandleTypeDef *pdev, uint8_t index, uint16_t *length); +#endif + +uint8_t *USBD_CDC_RNDIS_GetDeviceQualifierDescriptor(uint16_t *length); + + +/* CDC_RNDIS Internal messages parsing and construction functions */ +static uint8_t USBD_CDC_RNDIS_MsgParsing(USBD_HandleTypeDef *pdev, uint8_t *RxBuff); +static uint8_t USBD_CDC_RNDIS_ProcessInitMsg(USBD_HandleTypeDef *pdev, USBD_CDC_RNDIS_InitMsgTypeDef *Msg); +static uint8_t USBD_CDC_RNDIS_ProcessHaltMsg(USBD_HandleTypeDef *pdev, USBD_CDC_RNDIS_HaltMsgTypeDef *Msg); +static uint8_t USBD_CDC_RNDIS_ProcessKeepAliveMsg(USBD_HandleTypeDef *pdev, USBD_CDC_RNDIS_KpAliveMsgTypeDef *Msg); +static uint8_t USBD_CDC_RNDIS_ProcessQueryMsg(USBD_HandleTypeDef *pdev, USBD_CDC_RNDIS_QueryMsgTypeDef *Msg); +static uint8_t USBD_CDC_RNDIS_ProcessSetMsg(USBD_HandleTypeDef *pdev, USBD_CDC_RNDIS_SetMsgTypeDef *Msg); +static uint8_t USBD_CDC_RNDIS_ProcessResetMsg(USBD_HandleTypeDef *pdev, USBD_CDC_RNDIS_ResetMsgTypeDef *Msg); +static uint8_t USBD_CDC_RNDIS_ProcessPacketMsg(USBD_HandleTypeDef *pdev, USBD_CDC_RNDIS_PacketMsgTypeDef *Msg); +static uint8_t USBD_CDC_RNDIS_ProcessUnsupportedMsg(USBD_HandleTypeDef *pdev, USBD_CDC_RNDIS_CtrlMsgTypeDef *Msg); + +/* USB Standard Device Descriptor */ +__ALIGN_BEGIN static uint8_t USBD_CDC_RNDIS_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_DESC] __ALIGN_END = +{ + USB_LEN_DEV_QUALIFIER_DESC, + USB_DESC_TYPE_DEVICE_QUALIFIER, + 0x00, + 0x02, + 0x00, + 0x00, + 0x00, + 0x40, + 0x01, + 0x00, +}; + +static uint8_t MAC_StrDesc[6] = {CDC_RNDIS_MAC_ADDR0, CDC_RNDIS_MAC_ADDR1, CDC_RNDIS_MAC_ADDR2, + CDC_RNDIS_MAC_ADDR3, CDC_RNDIS_MAC_ADDR4, CDC_RNDIS_MAC_ADDR5}; + +static uint32_t ConnSpeedTab[2] = {CDC_RNDIS_CONNECT_SPEED_UPSTREAM, + CDC_RNDIS_CONNECT_SPEED_DOWNSTREAM}; + +static uint8_t EmptyResponse = 0x00U; + +/** + * @} + */ + +/** @defgroup USBD_CDC_RNDIS_Private_Variables + * @{ + */ + + +/* CDC_RNDIS interface class callbacks structure */ +USBD_ClassTypeDef USBD_CDC_RNDIS = +{ + USBD_CDC_RNDIS_Init, + USBD_CDC_RNDIS_DeInit, + USBD_CDC_RNDIS_Setup, + NULL, /* EP0_TxSent, */ + USBD_CDC_RNDIS_EP0_RxReady, + USBD_CDC_RNDIS_DataIn, + USBD_CDC_RNDIS_DataOut, + NULL, + NULL, + NULL, + USBD_CDC_RNDIS_GetHSCfgDesc, + USBD_CDC_RNDIS_GetFSCfgDesc, + USBD_CDC_RNDIS_GetOtherSpeedCfgDesc, + USBD_CDC_RNDIS_GetDeviceQualifierDescriptor, +#if (USBD_SUPPORT_USER_STRING_DESC == 1U) + USBD_CDC_RNDIS_USRStringDescriptor, +#endif +}; + +/* USB CDC_RNDIS device Configuration Descriptor */ +__ALIGN_BEGIN static uint8_t USBD_CDC_RNDIS_CfgHSDesc[] __ALIGN_END = +{ + /* Configuration Descriptor */ + 0x09, /* bLength: Configuration Descriptor size */ + USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */ + LOBYTE(CDC_RNDIS_CONFIG_DESC_SIZ), /* wTotalLength: Total size of the Config descriptor */ + HIBYTE(CDC_RNDIS_CONFIG_DESC_SIZ), + 0x02, /* bNumInterfaces: 2 interface */ + 0x01, /* bConfigurationValue: Configuration value */ + 0x00, /* iConfiguration: Index of string descriptor describing the configuration */ + 0xC0, /* bmAttributes: self powered */ + 0x32, /* MaxPower 0 mA */ + + /*---------------------------------------------------------------------------*/ + /* IAD descriptor */ + 0x08, /* bLength */ + 0x0B, /* bDescriptorType */ + 0x00, /* bFirstInterface */ + 0x02, /* bInterfaceCount */ + 0xE0, /* bFunctionClass (Wireless Controller) */ + 0x01, /* bFunctionSubClass */ + 0x03, /* bFunctionProtocol */ + 0x00, /* iFunction */ + + /*---------------------------------------------------------------------------*/ + /* Interface Descriptor */ + 0x09, /* bLength: Interface Descriptor size */ + USB_DESC_TYPE_INTERFACE, /* bDescriptorType: Interface descriptor type */ + CDC_RNDIS_CMD_ITF_NBR, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x01, /* bNumEndpoints: One endpoint used */ + 0x02, /* bInterfaceClass: Communication Interface Class */ + 0x02, /* bInterfaceSubClass:Abstract Control Model */ + 0xFF, /* bInterfaceProtocol: Common AT commands */ + 0x00, /* iInterface: */ + + /* Header Functional Descriptor */ + 0x05, /* bLength: Endpoint Descriptor size */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x00, /* bDescriptorSubtype: Header functional descriptor */ + 0x10, /* bcdCDC: spec release number: 1.20 */ + 0x01, + + /* Call Management Functional Descriptor */ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x01, /* bDescriptorSubtype: Call Management Func Desc */ + 0x00, /* bmCapabilities: D0+D1 */ + CDC_RNDIS_COM_ITF_NBR, /* bDataInterface: 1 */ + + /* ACM Functional Descriptor */ + 0x04, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x02, /* bDescriptorSubtype: Abstract Control Management desc */ + 0x00, /* bmCapabilities */ + + /* Union Functional Descriptor */ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x06, /* bDescriptorSubtype: Union functional descriptor */ + CDC_RNDIS_CMD_ITF_NBR, /* bMasterInterface: Communication class interface */ + CDC_RNDIS_COM_ITF_NBR, /* bSlaveInterface0: Data Class Interface */ + + /* Notification Endpoint Descriptor */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + CDC_RNDIS_CMD_EP, /* bEndpointAddress */ + 0x03, /* bmAttributes: Interrupt */ + LOBYTE(CDC_RNDIS_CMD_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(CDC_RNDIS_CMD_PACKET_SIZE), + CDC_RNDIS_HS_BINTERVAL, /* bInterval */ + + /*---------------------------------------------------------------------------*/ + /* Data class interface descriptor */ + 0x09, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_INTERFACE, /* bDescriptorType: */ + CDC_RNDIS_COM_ITF_NBR, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x02, /* bNumEndpoints: Two endpoints used */ + 0x0A, /* bInterfaceClass: CDC */ + 0x00, /* bInterfaceSubClass: */ + 0x00, /* bInterfaceProtocol: */ + 0x00, /* iInterface: */ + + /* Endpoint OUT Descriptor */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + CDC_RNDIS_OUT_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + LOBYTE(CDC_RNDIS_DATA_HS_MAX_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(CDC_RNDIS_DATA_HS_MAX_PACKET_SIZE), + 0xFF, /* bInterval: ignore for Bulk transfer */ + + /* Endpoint IN Descriptor */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + CDC_RNDIS_IN_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + LOBYTE(CDC_RNDIS_DATA_HS_MAX_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(CDC_RNDIS_DATA_HS_MAX_PACKET_SIZE), + 0xFF /* bInterval: ignore for Bulk transfer */ +}; + + +/* USB CDC device Configuration Descriptor */ +__ALIGN_BEGIN static uint8_t USBD_CDC_RNDIS_CfgFSDesc[] __ALIGN_END = +{ + /* Configuration Descriptor */ + 0x09, /* bLength: Configuration Descriptor size */ + USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */ + LOBYTE(CDC_RNDIS_CONFIG_DESC_SIZ), /* wTotalLength: Total size of the Config descriptor */ + HIBYTE(CDC_RNDIS_CONFIG_DESC_SIZ), + 0x02, /* bNumInterfaces: 2 interface */ + 0x01, /* bConfigurationValue: Configuration value */ + 0x00, /* iConfiguration: Index of string descriptor describing the configuration */ + 0xC0, /* bmAttributes: self powered */ + 0x32, /* MaxPower 0 mA */ + + /*---------------------------------------------------------------------------*/ + /* IAD descriptor */ + 0x08, /* bLength */ + 0x0B, /* bDescriptorType */ + 0x00, /* bFirstInterface */ + 0x02, /* bInterfaceCount */ + 0xE0, /* bFunctionClass (Wireless Controller) */ + 0x01, /* bFunctionSubClass */ + 0x03, /* bFunctionProtocol */ + 0x00, /* iFunction */ + + /*---------------------------------------------------------------------------*/ + /* Interface Descriptor */ + 0x09, /* bLength: Interface Descriptor size */ + USB_DESC_TYPE_INTERFACE, /* bDescriptorType: Interface descriptor type */ + CDC_RNDIS_CMD_ITF_NBR, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x01, /* bNumEndpoints: One endpoint used */ + 0x02, /* bInterfaceClass: Communication Interface Class */ + 0x02, /* bInterfaceSubClass:Abstract Control Model */ + 0xFF, /* bInterfaceProtocol: Common AT commands */ + 0x00, /* iInterface: */ + + /* Header Functional Descriptor */ + 0x05, /* bLength: Endpoint Descriptor size */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x00, /* bDescriptorSubtype: Header functional descriptor */ + 0x10, /* bcdCDC: spec release number: 1.20 */ + 0x01, + + /* Call Management Functional Descriptor */ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x01, /* bDescriptorSubtype: Call Management Func Desc */ + 0x00, /* bmCapabilities: D0+D1 */ + CDC_RNDIS_COM_ITF_NBR, /* bDataInterface: 1 */ + + /* ACM Functional Descriptor */ + 0x04, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x02, /* bDescriptorSubtype: Abstract Control Management desc */ + 0x00, /* bmCapabilities */ + + /* Union Functional Descriptor */ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x06, /* bDescriptorSubtype: Union functional descriptor */ + CDC_RNDIS_CMD_ITF_NBR, /* bMasterInterface: Communication class interface */ + CDC_RNDIS_COM_ITF_NBR, /* bSlaveInterface0: Data Class Interface */ + + /* Notification Endpoint Descriptor */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + CDC_RNDIS_CMD_EP, /* bEndpointAddress */ + 0x03, /* bmAttributes: Interrupt */ + LOBYTE(CDC_RNDIS_CMD_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(CDC_RNDIS_CMD_PACKET_SIZE), + CDC_RNDIS_FS_BINTERVAL, /* bInterval */ + + /*---------------------------------------------------------------------------*/ + /* Data class interface descriptor */ + 0x09, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_INTERFACE, /* bDescriptorType: */ + CDC_RNDIS_COM_ITF_NBR, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x02, /* bNumEndpoints: Two endpoints used */ + 0x0A, /* bInterfaceClass: CDC */ + 0x00, /* bInterfaceSubClass: */ + 0x00, /* bInterfaceProtocol: */ + 0x00, /* iInterface: */ + + /* Endpoint OUT Descriptor */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + CDC_RNDIS_OUT_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + LOBYTE(CDC_RNDIS_DATA_FS_MAX_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(CDC_RNDIS_DATA_FS_MAX_PACKET_SIZE), + 0xFF, /* bInterval: ignore for Bulk transfer */ + + /* Endpoint IN Descriptor */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + CDC_RNDIS_IN_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + LOBYTE(CDC_RNDIS_DATA_FS_MAX_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(CDC_RNDIS_DATA_FS_MAX_PACKET_SIZE), + 0xFF /* bInterval: ignore for Bulk transfer */ +} ; + +__ALIGN_BEGIN static uint8_t USBD_CDC_RNDIS_OtherSpeedCfgDesc[] __ALIGN_END = +{ + /* Configuration Descriptor */ + 0x09, /* bLength: Configuration Descriptor size */ + USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */ + LOBYTE(CDC_RNDIS_CONFIG_DESC_SIZ), /* wTotalLength:no of returned bytes */ + HIBYTE(CDC_RNDIS_CONFIG_DESC_SIZ), + 0x02, /* bNumInterfaces: 2 interface */ + 0x01, /* bConfigurationValue: Configuration value */ + 0x04, /* iConfiguration: Index of string descriptor describing the configuration */ + 0xC0, /* bmAttributes: self powered */ + 0x32, /* MaxPower 0 mA */ + + /*---------------------------------------------------------------------------*/ + /* IAD descriptor */ + 0x08, /* bLength */ + 0x0B, /* bDescriptorType */ + 0x00, /* bFirstInterface */ + 0x02, /* bInterfaceCount */ + 0xE0, /* bFunctionClass (Wireless Controller) */ + 0x01, /* bFunctionSubClass */ + 0x03, /* bFunctionProtocol */ + 0x00, /* iFunction */ + + /*---------------------------------------------------------------------------*/ + /* Interface Descriptor */ + 0x09, /* bLength: Interface Descriptor size */ + USB_DESC_TYPE_INTERFACE, /* bDescriptorType: Interface descriptor type */ + CDC_RNDIS_CMD_ITF_NBR, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x01, /* bNumEndpoints: One endpoint used */ + 0x02, /* bInterfaceClass: Communication Interface Class */ + 0x02, /* bInterfaceSubClass:Abstract Control Model */ + 0xFF, /* bInterfaceProtocol: Common AT commands */ + 0x00, /* iInterface: */ + + /* Header Functional Descriptor */ + 0x05, /* bLength: Endpoint Descriptor size */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x00, /* bDescriptorSubtype: Header functional descriptor */ + 0x10, /* bcdCDC: spec release number: 1.20 */ + 0x01, + + /* Call Management Functional Descriptor */ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x01, /* bDescriptorSubtype: Call Management Func Desc */ + 0x00, /* bmCapabilities: D0+D1 */ + CDC_RNDIS_COM_ITF_NBR, /* bDataInterface: 1 */ + + /* ACM Functional Descriptor */ + 0x04, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x02, /* bDescriptorSubtype: Abstract Control Management desc */ + 0x00, /* bmCapabilities */ + + /* Union Functional Descriptor */ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x06, /* bDescriptorSubtype: Union functional descriptor */ + CDC_RNDIS_CMD_ITF_NBR, /* bMasterInterface: Communication class interface */ + CDC_RNDIS_COM_ITF_NBR, /* bSlaveInterface0: Data Class Interface */ + + /* Communication Endpoint Descriptor */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + CDC_RNDIS_CMD_EP, /* bEndpointAddress */ + 0x03, /* bmAttributes: Interrupt */ + LOBYTE(CDC_RNDIS_CMD_PACKET_SIZE), /* wMaxPacketSize: */ + HIBYTE(CDC_RNDIS_CMD_PACKET_SIZE), + CDC_RNDIS_FS_BINTERVAL, /* bInterval */ + + /*---------------------------------------------------------------------------*/ + /* Data class interface descriptor */ + 0x09, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_INTERFACE, /* bDescriptorType: */ + CDC_RNDIS_COM_ITF_NBR, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x02, /* bNumEndpoints: Two endpoints used */ + 0x0A, /* bInterfaceClass: CDC */ + 0x00, /* bInterfaceSubClass: */ + 0x00, /* bInterfaceProtocol: */ + 0x00, /* iInterface: */ + + /* Endpoint OUT Descriptor */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + CDC_RNDIS_OUT_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + 0x40, /* wMaxPacketSize: */ + 0x00, + 0xFF, /* bInterval: ignore for Bulk transfer */ + + /* Endpoint IN Descriptor */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */ + CDC_RNDIS_IN_EP, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + 0x40, /* wMaxPacketSize: */ + 0x00, + 0xFF /* bInterval: ignore for Bulk transfer */ +}; + + +static const uint32_t CDC_RNDIS_SupportedOIDs[] = +{ + OID_GEN_SUPPORTED_LIST, + OID_GEN_HARDWARE_STATUS, + OID_GEN_MEDIA_SUPPORTED, + OID_GEN_MEDIA_IN_USE, + OID_GEN_MAXIMUM_FRAME_SIZE, + OID_GEN_LINK_SPEED, + OID_GEN_TRANSMIT_BLOCK_SIZE, + OID_GEN_RECEIVE_BLOCK_SIZE, + OID_GEN_VENDOR_ID, + OID_GEN_VENDOR_DESCRIPTION, + OID_GEN_CURRENT_PACKET_FILTER, + OID_GEN_MAXIMUM_TOTAL_SIZE, + OID_GEN_MEDIA_CONNECT_STATUS, + OID_GEN_MAXIMUM_SEND_PACKETS, + OID_802_3_PERMANENT_ADDRESS, + OID_802_3_CURRENT_ADDRESS, + OID_802_3_MULTICAST_LIST, + OID_802_3_MAXIMUM_LIST_SIZE, + OID_802_3_RCV_ERROR_ALIGNMENT, + OID_802_3_XMIT_ONE_COLLISION, + OID_802_3_XMIT_MORE_COLLISIONS, +}; + +/** + * @} + */ + +/** @defgroup USBD_CDC_RNDIS_Private_Functions + * @{ + */ + +/** + * @brief USBD_CDC_RNDIS_Init + * Initialize the CDC CDC_RNDIS interface + * @param pdev: device instance + * @param cfgidx: Configuration index + * @retval status + */ +static uint8_t USBD_CDC_RNDIS_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx) +{ + UNUSED(cfgidx); + USBD_CDC_RNDIS_HandleTypeDef *hcdc; + + hcdc = USBD_malloc(sizeof(USBD_CDC_RNDIS_HandleTypeDef)); + + if (hcdc == NULL) + { + pdev->pClassData = NULL; + return (uint8_t)USBD_EMEM; + } + + pdev->pClassData = (void *)hcdc; + + if (pdev->dev_speed == USBD_SPEED_HIGH) + { + /* Open EP IN */ + (void)USBD_LL_OpenEP(pdev, CDC_RNDIS_IN_EP, USBD_EP_TYPE_BULK, + CDC_RNDIS_DATA_HS_IN_PACKET_SIZE); + + pdev->ep_in[CDC_RNDIS_IN_EP & 0xFU].is_used = 1U; + + /* Open EP OUT */ + (void)USBD_LL_OpenEP(pdev, CDC_RNDIS_OUT_EP, USBD_EP_TYPE_BULK, + CDC_RNDIS_DATA_HS_OUT_PACKET_SIZE); + + pdev->ep_out[CDC_RNDIS_OUT_EP & 0xFU].is_used = 1U; + + /* Set bInterval for CDC RNDIS CMD Endpoint */ + pdev->ep_in[CDC_RNDIS_CMD_EP & 0xFU].bInterval = CDC_RNDIS_HS_BINTERVAL; + } + else + { + /* Open EP IN */ + (void)USBD_LL_OpenEP(pdev, CDC_RNDIS_IN_EP, USBD_EP_TYPE_BULK, + CDC_RNDIS_DATA_FS_IN_PACKET_SIZE); + + pdev->ep_in[CDC_RNDIS_IN_EP & 0xFU].is_used = 1U; + + /* Open EP OUT */ + (void)USBD_LL_OpenEP(pdev, CDC_RNDIS_OUT_EP, USBD_EP_TYPE_BULK, + CDC_RNDIS_DATA_FS_OUT_PACKET_SIZE); + + pdev->ep_out[CDC_RNDIS_OUT_EP & 0xFU].is_used = 1U; + + /* Set bInterval for CDC RNDIS CMD Endpoint */ + pdev->ep_in[CDC_RNDIS_CMD_EP & 0xFU].bInterval = CDC_RNDIS_FS_BINTERVAL; + } + + /* Open Command IN EP */ + (void)USBD_LL_OpenEP(pdev, CDC_RNDIS_CMD_EP, USBD_EP_TYPE_INTR, CDC_RNDIS_CMD_PACKET_SIZE); + pdev->ep_in[CDC_RNDIS_CMD_EP & 0xFU].is_used = 1U; + + /* Init physical Interface components */ + ((USBD_CDC_RNDIS_ItfTypeDef *)pdev->pUserData)->Init(); + + /* Init the CDC_RNDIS state */ + hcdc->State = CDC_RNDIS_STATE_BUS_INITIALIZED; + + /* Init Xfer states */ + hcdc->TxState = 0U; + hcdc->RxState = 0U; + hcdc->RxLength = 0U; + hcdc->TxLength = 0U; + hcdc->LinkStatus = 0U; + hcdc->NotificationStatus = 0U; + hcdc->MaxPcktLen = (pdev->dev_speed == USBD_SPEED_HIGH) ? CDC_RNDIS_DATA_HS_MAX_PACKET_SIZE : CDC_RNDIS_DATA_FS_MAX_PACKET_SIZE; + + /* Prepare Out endpoint to receive next packet */ + (void)USBD_LL_PrepareReceive(pdev, CDC_RNDIS_OUT_EP, + hcdc->RxBuffer, hcdc->MaxPcktLen); + + return (uint8_t)USBD_OK; +} + +/** + * @brief USBD_CDC_RNDIS_DeInit + * DeInitialize the CDC layer + * @param pdev: device instance + * @param cfgidx: Configuration index + * @retval status + */ +static uint8_t USBD_CDC_RNDIS_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx) +{ + UNUSED(cfgidx); + + /* Close EP IN */ + (void)USBD_LL_CloseEP(pdev, CDC_RNDIS_IN_EP); + pdev->ep_in[CDC_RNDIS_IN_EP & 0xFU].is_used = 0U; + + /* Close EP OUT */ + (void)USBD_LL_CloseEP(pdev, CDC_RNDIS_OUT_EP); + pdev->ep_out[CDC_RNDIS_OUT_EP & 0xFU].is_used = 0U; + + /* Close Command IN EP */ + (void)USBD_LL_CloseEP(pdev, CDC_RNDIS_CMD_EP); + pdev->ep_in[CDC_RNDIS_CMD_EP & 0xFU].is_used = 0U; + pdev->ep_in[CDC_RNDIS_CMD_EP & 0xFU].bInterval = 0U; + + /* DeInit physical Interface components */ + if (pdev->pClassData != NULL) + { + ((USBD_CDC_RNDIS_ItfTypeDef *)pdev->pUserData)->DeInit(); + USBD_free(pdev->pClassData); + pdev->pClassData = NULL; + } + + return (uint8_t)USBD_OK; +} + +/** + * @brief USBD_CDC_RNDIS_Setup + * Handle the CDC specific requests + * @param pdev: instance + * @param req: usb requests + * @retval status + */ +static uint8_t USBD_CDC_RNDIS_Setup(USBD_HandleTypeDef *pdev, + USBD_SetupReqTypedef *req) +{ + USBD_CDC_RNDIS_HandleTypeDef *hcdc = (USBD_CDC_RNDIS_HandleTypeDef *)pdev->pClassData; + USBD_CDC_RNDIS_CtrlMsgTypeDef *Msg = (USBD_CDC_RNDIS_CtrlMsgTypeDef *)hcdc->data; + uint8_t ifalt = 0U; + uint16_t status_info = 0U; + USBD_StatusTypeDef ret = USBD_OK; + + switch (req->bmRequest & USB_REQ_TYPE_MASK) + { + case USB_REQ_TYPE_CLASS : + if (req->wLength != 0U) + { + /* Control Request Data from Device to Host, send data prepared by device */ + if ((req->bmRequest & 0x80U) != 0U) + { + /* Update opcode and length */ + hcdc->CmdOpCode = req->bRequest; + hcdc->CmdLength = (uint8_t)req->wLength; + + if (hcdc->CmdOpCode == CDC_RNDIS_GET_ENCAPSULATED_RESPONSE) + { + /* Data of Response Message has already been prepared by USBD_CDC_RNDIS_MsgParsing. + Just check that length is corresponding to right expected value */ + if (req->wLength != Msg->MsgLength) + { + } + } + + /* Allow application layer to pre-process data or add own processing before sending response */ + ((USBD_CDC_RNDIS_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest, + (uint8_t *)hcdc->data, + req->wLength); + /* Check if Response is ready */ + if (hcdc->ResponseRdy != 0U) + { + /* Clear Response Ready flag */ + hcdc->ResponseRdy = 0U; + + /* Send data on control endpoint */ + (void)USBD_CtlSendData(pdev, (uint8_t *)hcdc->data, Msg->MsgLength); + } + else + { + /* CDC_RNDIS Specification says: If for some reason the device receives a GET ENCAPSULATED RESPONSE + and is unable to respond with a valid data on the Control endpoint, + then it should return a one-byte packet set to 0x00, rather than + stalling the Control endpoint */ + (void)USBD_CtlSendData(pdev, &EmptyResponse, 1U); + } + } + /* Control Request Data from Host to Device: Prepare reception of control data stage */ + else + { + hcdc->CmdOpCode = req->bRequest; + hcdc->CmdLength = (uint8_t)req->wLength; + + (void)USBD_CtlPrepareRx(pdev, (uint8_t *)hcdc->data, req->wLength); + } + } + /* No Data control request: there is no such request for CDC_RNDIS protocol, + so let application layer manage this case */ + else + { + ((USBD_CDC_RNDIS_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest, + (uint8_t *)req, 0U); + } + break; + + case USB_REQ_TYPE_STANDARD: + switch (req->bRequest) + { + case USB_REQ_GET_STATUS: + if (pdev->dev_state == USBD_STATE_CONFIGURED) + { + (void)USBD_CtlSendData(pdev, (uint8_t *)&status_info, 2U); + } + else + { + USBD_CtlError(pdev, req); + ret = USBD_FAIL; + } + break; + + case USB_REQ_GET_INTERFACE: + if (pdev->dev_state == USBD_STATE_CONFIGURED) + { + (void)USBD_CtlSendData(pdev, &ifalt, 1U); + } + else + { + USBD_CtlError(pdev, req); + ret = USBD_FAIL; + } + break; + + case USB_REQ_SET_INTERFACE: + if (pdev->dev_state != USBD_STATE_CONFIGURED) + { + USBD_CtlError(pdev, req); + ret = USBD_FAIL; + } + break; + + case USB_REQ_CLEAR_FEATURE: + break; + + default: + USBD_CtlError(pdev, req); + ret = USBD_FAIL; + break; + } + break; + + default: + USBD_CtlError(pdev, req); + ret = USBD_FAIL; + break; + } + + return (uint8_t)ret; +} + +/** + * @brief USBD_CDC_RNDIS_DataIn + * Data sent on non-control IN endpoint + * @param pdev: device instance + * @param epnum: endpoint number + * @retval status + */ +static uint8_t USBD_CDC_RNDIS_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum) +{ + USBD_CDC_RNDIS_HandleTypeDef *hcdc; + PCD_HandleTypeDef *hpcd = pdev->pData; + + if (pdev->pClassData == NULL) + { + return (uint8_t)USBD_FAIL; + } + + hcdc = (USBD_CDC_RNDIS_HandleTypeDef *)pdev->pClassData; + + if (epnum == (CDC_RNDIS_IN_EP & 0x7FU)) + { + if ((pdev->ep_in[epnum & 0xFU].total_length > 0U) && + ((pdev->ep_in[epnum & 0xFU].total_length % hpcd->IN_ep[epnum & 0xFU].maxpacket) == 0U)) + { + /* Update the packet total length */ + pdev->ep_in[epnum & 0xFU].total_length = 0U; + + /* Send ZLP */ + (void)USBD_LL_Transmit(pdev, epnum, NULL, 0U); + } + else + { + hcdc->TxState = 0U; + ((USBD_CDC_RNDIS_ItfTypeDef *)pdev->pUserData)->TransmitCplt(hcdc->TxBuffer, &hcdc->TxLength, epnum); + } + } + else if (epnum == (CDC_RNDIS_CMD_EP & 0x7FU)) + { + if (hcdc->NotificationStatus != 0U) + { + (void)USBD_CDC_RNDIS_SendNotification(pdev, CONNECTION_SPEED_CHANGE, + 0U, (uint8_t *)ConnSpeedTab); + + hcdc->NotificationStatus = 0U; + } + } + else + { + return (uint8_t)USBD_FAIL; + } + + return (uint8_t)USBD_OK; +} + +/** + * @brief USBD_CDC_RNDIS_DataOut + * Data received on non-control Out endpoint + * @param pdev: device instance + * @param epnum: endpoint number + * @retval status + */ +static uint8_t USBD_CDC_RNDIS_DataOut(USBD_HandleTypeDef *pdev, uint8_t epnum) +{ + USBD_CDC_RNDIS_HandleTypeDef *hcdc; + uint32_t CurrPcktLen; + + if (pdev->pClassData == NULL) + { + return (uint8_t)USBD_FAIL; + } + + hcdc = (USBD_CDC_RNDIS_HandleTypeDef *)pdev->pClassData; + + if (epnum == CDC_RNDIS_OUT_EP) + { + /* Get the received data length */ + CurrPcktLen = USBD_LL_GetRxDataSize(pdev, epnum); + + /* Increment the frame length */ + hcdc->RxLength += CurrPcktLen; + + /* If the buffer size is less than max packet size: it is the last packet in current frame */ + if ((CurrPcktLen < hcdc->MaxPcktLen) || + (hcdc->RxLength >= (CDC_RNDIS_ETH_MAX_SEGSZE + sizeof(USBD_CDC_RNDIS_PacketMsgTypeDef)))) + { + /* USB data will be immediately processed, this allow next USB traffic being + NACKed till the end of the application Xfer */ + + /* Call data packet message parsing and processing function */ + (void)USBD_CDC_RNDIS_ProcessPacketMsg(pdev, (USBD_CDC_RNDIS_PacketMsgTypeDef *)hcdc->RxBuffer); + } + else + { + /* Prepare Out endpoint to receive next packet in current/new frame */ + (void)USBD_LL_PrepareReceive(pdev, CDC_RNDIS_OUT_EP, + (uint8_t *)(hcdc->RxBuffer + hcdc->RxLength), + hcdc->MaxPcktLen); + } + } + else + { + return (uint8_t)USBD_FAIL; + } + + return (uint8_t)USBD_OK; +} + +/** + * @brief USBD_CDC_RNDIS_EP0_RxReady + * Handle EP0 Rx Ready event + * @param pdev: device instance + * @retval status + */ +static uint8_t USBD_CDC_RNDIS_EP0_RxReady(USBD_HandleTypeDef *pdev) +{ + USBD_CDC_RNDIS_HandleTypeDef *hcdc = (USBD_CDC_RNDIS_HandleTypeDef *)pdev->pClassData; + + if ((pdev->pUserData != NULL) && (hcdc->CmdOpCode != 0xFFU)) + { + /* Check if the received command is SendEncapsulated command */ + if (hcdc->CmdOpCode == CDC_RNDIS_SEND_ENCAPSULATED_COMMAND) + { + /* Process Received CDC_RNDIS Control Message */ + (void)USBD_CDC_RNDIS_MsgParsing(pdev, (uint8_t *)(hcdc->data)); + + /* Reset the command opcode for next processing */ + hcdc->CmdOpCode = 0xFFU; + } + else + { + /* Reset the command opcode for next processing */ + hcdc->CmdOpCode = 0xFFU; + + /* Ignore the command and return fail */ + return (uint8_t)USBD_FAIL; + } + } + + return (uint8_t)USBD_OK; +} + +/** + * @brief USBD_CDC_RNDIS_GetFSCfgDesc + * Return configuration descriptor + * @param speed : current device speed + * @param length : pointer data length + * @retval pointer to descriptor buffer + */ +static uint8_t *USBD_CDC_RNDIS_GetFSCfgDesc(uint16_t *length) +{ + *length = (uint16_t)(sizeof(USBD_CDC_RNDIS_CfgFSDesc)); + + return USBD_CDC_RNDIS_CfgFSDesc; +} + +/** + * @brief USBD_CDC_RNDIS_GetHSCfgDesc + * Return configuration descriptor + * @param speed : current device speed + * @param length : pointer data length + * @retval pointer to descriptor buffer + */ +static uint8_t *USBD_CDC_RNDIS_GetHSCfgDesc(uint16_t *length) +{ + *length = (uint16_t)(sizeof(USBD_CDC_RNDIS_CfgHSDesc)); + + return USBD_CDC_RNDIS_CfgHSDesc; +} + +/** + * @brief USBD_CDC_RNDIS_GetOtherSpeedCfgDesc + * Return configuration descriptor + * @param speed : current device speed + * @param length : pointer data length + * @retval pointer to descriptor buffer + */ +static uint8_t *USBD_CDC_RNDIS_GetOtherSpeedCfgDesc(uint16_t *length) +{ + *length = (uint16_t)(sizeof(USBD_CDC_RNDIS_OtherSpeedCfgDesc)); + + return USBD_CDC_RNDIS_OtherSpeedCfgDesc; +} + +/** + * @brief DeviceQualifierDescriptor + * return Device Qualifier descriptor + * @param length : pointer data length + * @retval pointer to descriptor buffer + */ +uint8_t *USBD_CDC_RNDIS_GetDeviceQualifierDescriptor(uint16_t *length) +{ + *length = (uint16_t)(sizeof(USBD_CDC_RNDIS_DeviceQualifierDesc)); + + return USBD_CDC_RNDIS_DeviceQualifierDesc; +} + +/** + * @brief USBD_CDC_RNDIS_RegisterInterface + * @param pdev: device instance + * @param fops: CD Interface callback + * @retval status + */ +uint8_t USBD_CDC_RNDIS_RegisterInterface(USBD_HandleTypeDef *pdev, + USBD_CDC_RNDIS_ItfTypeDef *fops) +{ + if (fops == NULL) + { + return (uint8_t)USBD_FAIL; + } + + pdev->pUserData = fops; + + return (uint8_t)USBD_OK; +} + + +/** + * @brief USBD_CDC_RNDIS_USRStringDescriptor + * Manages the transfer of user string descriptors. + * @param speed : current device speed + * @param index: descriptor index + * @param length : pointer data length + * @retval pointer to the descriptor table or NULL if the descriptor is not supported. + */ +#if (USBD_SUPPORT_USER_STRING_DESC == 1U) +static uint8_t *USBD_CDC_RNDIS_USRStringDescriptor(USBD_HandleTypeDef *pdev, uint8_t index, uint16_t *length) +{ + static uint8_t USBD_StrDesc[255]; + + /* Check if the requested string interface is supported */ + if (index == CDC_RNDIS_MAC_STRING_INDEX) + { + USBD_GetString((uint8_t *)((USBD_CDC_RNDIS_ItfTypeDef *)pdev->pUserData)->pStrDesc, USBD_StrDesc, length); + return USBD_StrDesc; + } + /* Not supported Interface Descriptor index */ + else + { + return NULL; + } +} +#endif /* USBD_SUPPORT_USER_STRING_DESC */ + +/** + * @brief USBD_CDC_RNDIS_SetTxBuffer + * @param pdev: device instance + * @param pbuff: Tx Buffer + * @retval status + */ +uint8_t USBD_CDC_RNDIS_SetTxBuffer(USBD_HandleTypeDef *pdev, uint8_t *pbuff, uint32_t length) +{ + USBD_CDC_RNDIS_HandleTypeDef *hcdc = (USBD_CDC_RNDIS_HandleTypeDef *)pdev->pClassData; + + hcdc->TxBuffer = pbuff; + hcdc->TxLength = length; + + return (uint8_t)USBD_OK; +} + + +/** + * @brief USBD_CDC_RNDIS_SetRxBuffer + * @param pdev: device instance + * @param pbuff: Rx Buffer + * @retval status + */ +uint8_t USBD_CDC_RNDIS_SetRxBuffer(USBD_HandleTypeDef *pdev, uint8_t *pbuff) +{ + USBD_CDC_RNDIS_HandleTypeDef *hcdc = (USBD_CDC_RNDIS_HandleTypeDef *)pdev->pClassData; + + hcdc->RxBuffer = pbuff; + + return (uint8_t)USBD_OK; +} + + +/** + * @brief USBD_CDC_RNDIS_TransmitPacket + * Transmit packet on IN endpoint + * @param pdev: device instance + * @retval status + */ +uint8_t USBD_CDC_RNDIS_TransmitPacket(USBD_HandleTypeDef *pdev) +{ + USBD_CDC_RNDIS_HandleTypeDef *hcdc; + USBD_CDC_RNDIS_PacketMsgTypeDef *PacketMsg; + USBD_StatusTypeDef ret = USBD_BUSY; + + if (pdev->pClassData == NULL) + { + return (uint8_t)USBD_FAIL; + } + + hcdc = (USBD_CDC_RNDIS_HandleTypeDef *)pdev->pClassData; + PacketMsg = (USBD_CDC_RNDIS_PacketMsgTypeDef *)hcdc->TxBuffer; + + if (hcdc->TxState == 0U) + { + /* Tx Transfer in progress */ + hcdc->TxState = 1U; + + /* Format the packet information */ + PacketMsg->MsgType = CDC_RNDIS_PACKET_MSG_ID; + PacketMsg->MsgLength = hcdc->TxLength; + PacketMsg->DataOffset = sizeof(USBD_CDC_RNDIS_PacketMsgTypeDef) - CDC_RNDIS_PCKTMSG_DATAOFFSET_OFFSET; + PacketMsg->DataLength = hcdc->TxLength - sizeof(USBD_CDC_RNDIS_PacketMsgTypeDef); + PacketMsg->OOBDataOffset = 0U; + PacketMsg->OOBDataLength = 0U; + PacketMsg->NumOOBDataElements = 0U; + PacketMsg->PerPacketInfoOffset = 0U; + PacketMsg->PerPacketInfoLength = 0U; + PacketMsg->VcHandle = 0U; + PacketMsg->Reserved = 0U; + + /* Update the packet total length */ + pdev->ep_in[CDC_RNDIS_IN_EP & 0xFU].total_length = hcdc->TxLength; + + /* Transmit next packet */ + (void)USBD_LL_Transmit(pdev, CDC_RNDIS_IN_EP, hcdc->TxBuffer, hcdc->TxLength); + + ret = USBD_OK; + } + + return (uint8_t)ret; +} + + +/** + * @brief USBD_CDC_RNDIS_ReceivePacket + * prepare OUT Endpoint for reception + * @param pdev: device instance + * @retval status + */ +uint8_t USBD_CDC_RNDIS_ReceivePacket(USBD_HandleTypeDef *pdev) +{ + USBD_CDC_RNDIS_HandleTypeDef *hcdc; + + if (pdev->pClassData == NULL) + { + return (uint8_t)USBD_FAIL; + } + + hcdc = (USBD_CDC_RNDIS_HandleTypeDef *)pdev->pClassData; + + /* Prepare Out endpoint to receive next packet */ + (void)USBD_LL_PrepareReceive(pdev, CDC_RNDIS_OUT_EP, + hcdc->RxBuffer, hcdc->MaxPcktLen); + + return (uint8_t)USBD_OK; +} + + +/** + * @brief USBD_CDC_RNDIS_SendNotification + * Transmit Notification packet on CMD IN interrupt endpoint + * @param pdev: device instance + * Notif: value of the notification type (from CDC_RNDIS_Notification_TypeDef enumeration list) + * bVal: value of the notification switch (ie. 0x00 or 0x01 for Network Connection notification) + * pData: pointer to data buffer (ie. upstream and downstream connection speed values) + * @retval status + */ +uint8_t USBD_CDC_RNDIS_SendNotification(USBD_HandleTypeDef *pdev, + USBD_CDC_RNDIS_NotifCodeTypeDef Notif, + uint16_t bVal, uint8_t *pData) +{ + uint32_t Idx; + uint16_t ReqSize = 0U; + USBD_CDC_RNDIS_HandleTypeDef *hcdc = (USBD_CDC_RNDIS_HandleTypeDef *)pdev->pClassData; + USBD_StatusTypeDef ret = USBD_OK; + + UNUSED(bVal); + UNUSED(pData); + + /* Initialize the request fields */ + (hcdc->Req).bmRequest = CDC_RNDIS_BMREQUEST_TYPE_RNDIS; + (hcdc->Req).bRequest = (uint8_t)Notif; + + switch (Notif) + { + case RESPONSE_AVAILABLE: + (hcdc->Req).wValue = 0U; + (hcdc->Req).wIndex = CDC_RNDIS_CMD_ITF_NBR; + (hcdc->Req).wLength = 0U; + for (Idx = 0U; Idx < 8U; Idx++) + { + (hcdc->Req).data[Idx] = 0U; + } + ReqSize = 8U; + break; + + default: + ret = USBD_FAIL; + break; + } + + /* Transmit notification packet */ + if (ReqSize != 0U) + { + (void)USBD_LL_Transmit(pdev, CDC_RNDIS_CMD_EP, (uint8_t *)&(hcdc->Req), ReqSize); + } + + return (uint8_t)ret; +} + + +/* ----------------------------- CDC_RNDIS Messages processing functions ----------------------- */ +/** + * @brief USBD_CDC_RNDIS_MsgParsing + * Parse received message and process it depending on its nature. + * @param pdev: USB Device Handle pointer + * @param RxBuff: Pointer to the message data extracted from SendEncapsulated command + * @retval status + */ +static uint8_t USBD_CDC_RNDIS_MsgParsing(USBD_HandleTypeDef *pdev, uint8_t *RxBuff) +{ + USBD_CDC_RNDIS_CtrlMsgTypeDef *Msg = (USBD_CDC_RNDIS_CtrlMsgTypeDef *)RxBuff; + static uint8_t ret = (uint8_t)USBD_OK; + + /* Check message type */ + switch (Msg->MsgType) + { + /* CDC_RNDIS Initialize message */ + case CDC_RNDIS_INITIALIZE_MSG_ID: + ret = USBD_CDC_RNDIS_ProcessInitMsg(pdev, (USBD_CDC_RNDIS_InitMsgTypeDef *)Msg); + break; + + /* CDC_RNDIS Halt message */ + case CDC_RNDIS_HALT_MSG_ID: + ret = USBD_CDC_RNDIS_ProcessHaltMsg(pdev, (USBD_CDC_RNDIS_HaltMsgTypeDef *)Msg); + break; + + /* CDC_RNDIS Query message */ + case CDC_RNDIS_QUERY_MSG_ID: + ret = USBD_CDC_RNDIS_ProcessQueryMsg(pdev, (USBD_CDC_RNDIS_QueryMsgTypeDef *)Msg); + break; + + /* CDC_RNDIS Set message */ + case CDC_RNDIS_SET_MSG_ID: + ret = USBD_CDC_RNDIS_ProcessSetMsg(pdev, (USBD_CDC_RNDIS_SetMsgTypeDef *)Msg); + break; + + /* CDC_RNDIS Reset message */ + case CDC_RNDIS_RESET_MSG_ID: + ret = USBD_CDC_RNDIS_ProcessResetMsg(pdev, (USBD_CDC_RNDIS_ResetMsgTypeDef *)Msg); + break; + + /* CDC_RNDIS Keep-Alive message */ + case CDC_RNDIS_KEEPALIVE_MSG_ID: + ret = USBD_CDC_RNDIS_ProcessKeepAliveMsg(pdev, (USBD_CDC_RNDIS_KpAliveMsgTypeDef *)Msg); + break; + + /* CDC_RNDIS unsupported message */ + default: + ret = USBD_CDC_RNDIS_ProcessUnsupportedMsg(pdev, (USBD_CDC_RNDIS_CtrlMsgTypeDef *)Msg); + break; + } + + return ret; +} + + +/** + * @brief USBD_CDC_RNDIS_ProcessInitMsg + * Parse, extract data and check correctness of CDC_RNDIS INIT_MSG command. + * @param pdev: USB Device Handle pointer + * @param Msg: Pointer to the message data extracted from SendEncapsulated command + * @retval status + */ +static uint8_t USBD_CDC_RNDIS_ProcessInitMsg(USBD_HandleTypeDef *pdev, + USBD_CDC_RNDIS_InitMsgTypeDef *Msg) +{ + /* Get the CDC_RNDIS handle pointer */ + USBD_CDC_RNDIS_HandleTypeDef *hcdc = (USBD_CDC_RNDIS_HandleTypeDef *)pdev->pClassData; + + /* Get and format the Msg input */ + USBD_CDC_RNDIS_InitMsgTypeDef *InitMessage = (USBD_CDC_RNDIS_InitMsgTypeDef *)Msg; + + /* Use same Msg input buffer as response buffer */ + USBD_CDC_RNDIS_InitCpltMsgTypeDef *InitResponse = (USBD_CDC_RNDIS_InitCpltMsgTypeDef *)Msg; + + /* Store the Message Request ID */ + uint32_t ReqId = InitMessage->ReqId; + + /* Check correctness of the message (MsgType already checked by entry to this function) */ + if ((InitMessage->MsgLength != sizeof(USBD_CDC_RNDIS_InitMsgTypeDef)) || \ + (InitMessage->MajorVersion < CDC_RNDIS_VERSION_MAJOR)) + { + InitResponse->Status = CDC_RNDIS_STATUS_FAILURE; + } + else + { + InitResponse->Status = CDC_RNDIS_STATUS_SUCCESS; + } + + /* Setup the response buffer content */ + InitResponse->MsgType = CDC_RNDIS_INITIALIZE_CMPLT_ID; + InitResponse->MsgLength = sizeof(USBD_CDC_RNDIS_InitCpltMsgTypeDef); + InitResponse->ReqId = ReqId; + InitResponse->MajorVersion = CDC_RNDIS_VERSION_MAJOR; + InitResponse->MinorVersion = CDC_RNDIS_VERSION_MINOR; + InitResponse->DeviceFlags = CDC_RNDIS_DF_CONNECTIONLESS; + InitResponse->Medium = CDC_RNDIS_MEDIUM_802_3; + InitResponse->MaxPacketsPerTransfer = 1U; + InitResponse->MaxTransferSize = (sizeof(USBD_CDC_RNDIS_PacketMsgTypeDef) + CDC_RNDIS_ETH_FRAME_SIZE_MAX); + InitResponse->PacketAlignmentFactor = 2U; /* Not needed as single packet by transfer set */ + InitResponse->AFListOffset = 0U; /* Reserved for connection-oriented devices. Set value to zero. */ + InitResponse->AFListSize = 0U; /* Reserved for connection-oriented devices. Set value to zero. */ + + /* Set CDC_RNDIS state to INITIALIZED */ + hcdc->State = CDC_RNDIS_STATE_INITIALIZED; + + /* Set Response Ready field in order to send response during next control request */ + hcdc->ResponseRdy = 1U; + + /* Send Notification on Interrupt EP to inform Host that response is ready */ + (void)USBD_CDC_RNDIS_SendNotification(pdev, RESPONSE_AVAILABLE, 0U, NULL); + + return (uint8_t)USBD_OK; +} + + +/** + * @brief USBD_CDC_RNDIS_ProcessHaltMsg + * Parse, extract data and check correctness of CDC_RNDIS Halt command. + * @param pdev: USB Device Handle pointer + * @param Msg: Pointer to the message data extracted from SendEncapsulated command + * @retval status + */ +static uint8_t USBD_CDC_RNDIS_ProcessHaltMsg(USBD_HandleTypeDef *pdev, + USBD_CDC_RNDIS_HaltMsgTypeDef *Msg) +{ + /* Get the CDC_RNDIS handle pointer */ + USBD_CDC_RNDIS_HandleTypeDef *hcdc = (USBD_CDC_RNDIS_HandleTypeDef *)pdev->pClassData; + + /* Set CDC_RNDIS state to INITIALIZED */ + hcdc->State = CDC_RNDIS_STATE_UNINITIALIZED; + + /* No response required for this message, so no notification (RESPNSE_AVAILABLE) is sent */ + + UNUSED(Msg); + + return (uint8_t)USBD_OK; +} + + +/** + * @brief USBD_CDC_RNDIS_ProcessKeepAliveMsg + * Parse, extract data and check correctness of CDC_RNDIS KeepAlive command. + * @param pdev: USB Device Handle pointer + * @param Msg: Pointer to the message data extracted from SendEncapsulated command + * @retval status + */ +static uint8_t USBD_CDC_RNDIS_ProcessKeepAliveMsg(USBD_HandleTypeDef *pdev, + USBD_CDC_RNDIS_KpAliveMsgTypeDef *Msg) +{ + /* Get the CDC_RNDIS handle pointer */ + USBD_CDC_RNDIS_HandleTypeDef *hcdc = (USBD_CDC_RNDIS_HandleTypeDef *)pdev->pClassData; + + /* Use same Msg input buffer as response buffer */ + USBD_CDC_RNDIS_KpAliveCpltMsgTypeDef *InitResponse = (USBD_CDC_RNDIS_KpAliveCpltMsgTypeDef *)Msg; + + /* Store the Message Request ID */ + uint32_t ReqId = Msg->ReqId; + + /* Check correctness of the message (MsgType already checked by entry to this function) */ + if (Msg->MsgLength != sizeof(USBD_CDC_RNDIS_KpAliveMsgTypeDef)) + { + InitResponse->Status = CDC_RNDIS_STATUS_FAILURE; + } + else + { + InitResponse->Status = CDC_RNDIS_STATUS_SUCCESS; + } + + /* Setup the response buffer content */ + InitResponse->MsgType = CDC_RNDIS_KEEPALIVE_CMPLT_ID; + InitResponse->MsgLength = sizeof(USBD_CDC_RNDIS_KpAliveCpltMsgTypeDef); + InitResponse->ReqId = ReqId; + InitResponse->Status = CDC_RNDIS_STATUS_SUCCESS; + + /* Set Response Ready field in order to send response during next control request */ + hcdc->ResponseRdy = 1U; + + /* Send Notification on Interrupt EP to inform Host that response is ready */ + (void)USBD_CDC_RNDIS_SendNotification(pdev, RESPONSE_AVAILABLE, 0U, NULL); + + return (uint8_t)USBD_OK; +} + + +/** + * @brief USBD_CDC_RNDIS_ProcessQueryMsg + * Parse, extract data and check correctness of CDC_RNDIS Query command. + * @param pdev: USB Device Handle pointer + * @param Msg: Pointer to the message data extracted from SendEncapsulated command + * @retval status + */ +static uint8_t USBD_CDC_RNDIS_ProcessQueryMsg(USBD_HandleTypeDef *pdev, + USBD_CDC_RNDIS_QueryMsgTypeDef *Msg) +{ + /* Get the CDC_RNDIS handle pointer */ + USBD_CDC_RNDIS_HandleTypeDef *hcdc = (USBD_CDC_RNDIS_HandleTypeDef *)pdev->pClassData; + + /* Use same Msg input buffer as response buffer */ + USBD_CDC_RNDIS_QueryCpltMsgTypeDef *QueryResponse = (USBD_CDC_RNDIS_QueryCpltMsgTypeDef *)Msg; + + /* Store the Message Request ID */ + uint32_t ReqId = Msg->RequestId; + + /* Process the OID depending on its code */ + switch (Msg->Oid) + { + case OID_GEN_SUPPORTED_LIST: + QueryResponse->InfoBufLength = sizeof(CDC_RNDIS_SupportedOIDs); + (void)USBD_memcpy(QueryResponse->InfoBuf, CDC_RNDIS_SupportedOIDs, + sizeof(CDC_RNDIS_SupportedOIDs)); + + QueryResponse->Status = CDC_RNDIS_STATUS_SUCCESS; + break; + + case OID_GEN_HARDWARE_STATUS: + QueryResponse->InfoBufLength = sizeof(uint32_t); + QueryResponse->InfoBuf[0] = CDC_RNDIS_HW_STS_READY; + QueryResponse->Status = CDC_RNDIS_STATUS_SUCCESS; + break; + + case OID_GEN_MEDIA_SUPPORTED: + case OID_GEN_MEDIA_IN_USE: + QueryResponse->InfoBufLength = sizeof(uint32_t); + QueryResponse->InfoBuf[0] = CDC_RNDIS_MEDIUM_802_3; + QueryResponse->Status = CDC_RNDIS_STATUS_SUCCESS; + break; + + case OID_GEN_VENDOR_ID: + QueryResponse->InfoBufLength = sizeof(uint32_t); + QueryResponse->InfoBuf[0] = USBD_CDC_RNDIS_VID; + QueryResponse->Status = CDC_RNDIS_STATUS_SUCCESS; + break; + + case OID_GEN_MAXIMUM_FRAME_SIZE: + case OID_GEN_TRANSMIT_BLOCK_SIZE: + case OID_GEN_RECEIVE_BLOCK_SIZE: + QueryResponse->InfoBufLength = sizeof(uint32_t); + QueryResponse->InfoBuf[0] = CDC_RNDIS_ETH_FRAME_SIZE_MAX; + QueryResponse->Status = CDC_RNDIS_STATUS_SUCCESS; + break; + + case OID_GEN_VENDOR_DESCRIPTION: + QueryResponse->InfoBufLength = (strlen(USBD_CDC_RNDIS_VENDOR_DESC) + 1U); + (void)USBD_memcpy(QueryResponse->InfoBuf, USBD_CDC_RNDIS_VENDOR_DESC, + strlen(USBD_CDC_RNDIS_VENDOR_DESC)); + + QueryResponse->Status = CDC_RNDIS_STATUS_SUCCESS; + break; + + case OID_GEN_MEDIA_CONNECT_STATUS: + QueryResponse->InfoBufLength = sizeof(uint32_t); + QueryResponse->InfoBuf[0] = CDC_RNDIS_MEDIA_STATE_CONNECTED; + QueryResponse->Status = CDC_RNDIS_STATUS_SUCCESS; + break; + + case OID_GEN_MAXIMUM_SEND_PACKETS: + QueryResponse->InfoBufLength = sizeof(uint32_t); + QueryResponse->InfoBuf[0] = 1U; + QueryResponse->Status = CDC_RNDIS_STATUS_SUCCESS; + break; + + case OID_GEN_LINK_SPEED: + QueryResponse->InfoBufLength = sizeof(uint32_t); + QueryResponse->InfoBuf[0] = USBD_CDC_RNDIS_LINK_SPEED; + QueryResponse->Status = CDC_RNDIS_STATUS_SUCCESS; + break; + + case OID_802_3_PERMANENT_ADDRESS: + case OID_802_3_CURRENT_ADDRESS: + QueryResponse->InfoBufLength = 6U; + (void)USBD_memcpy(QueryResponse->InfoBuf, MAC_StrDesc, 6); + QueryResponse->Status = CDC_RNDIS_STATUS_SUCCESS; + break; + + case OID_802_3_MAXIMUM_LIST_SIZE: + QueryResponse->InfoBufLength = sizeof(uint32_t); + QueryResponse->InfoBuf[0] = 1U; /* Only one multicast address supported */ + QueryResponse->Status = CDC_RNDIS_STATUS_SUCCESS; + break; + + case OID_GEN_CURRENT_PACKET_FILTER: + QueryResponse->InfoBufLength = sizeof(uint32_t); + QueryResponse->InfoBuf[0] = 0xFFFFFFU; /* USBD_CDC_RNDIS_DEVICE.packetFilter; */ + QueryResponse->Status = CDC_RNDIS_STATUS_SUCCESS; + break; + + case OID_802_3_RCV_ERROR_ALIGNMENT: + case OID_802_3_XMIT_ONE_COLLISION: + case OID_802_3_XMIT_MORE_COLLISIONS: + QueryResponse->InfoBufLength = sizeof(uint32_t); + QueryResponse->InfoBuf[0] = 0U; /* Unused OIDs, return zero */ + QueryResponse->Status = CDC_RNDIS_STATUS_SUCCESS; + break; + + case OID_GEN_MAXIMUM_TOTAL_SIZE: + QueryResponse->InfoBufLength = sizeof(uint32_t); + /* Indicate maximum overall buffer (Ethernet frame and CDC_RNDIS header) the adapter can handle */ + QueryResponse->InfoBuf[0] = (CDC_RNDIS_MESSAGE_BUFFER_SIZE + CDC_RNDIS_ETH_FRAME_SIZE_MAX); + QueryResponse->Status = CDC_RNDIS_STATUS_SUCCESS; + break; + + default: + /* Unknown or unsupported OID */ + QueryResponse->InfoBufLength = 0U; + QueryResponse->Status = CDC_RNDIS_STATUS_FAILURE; + break; + } + + /* Setup the response buffer content */ + QueryResponse->MsgType = CDC_RNDIS_QUERY_CMPLT_ID; + QueryResponse->MsgLength = QueryResponse->InfoBufLength + 24U; + QueryResponse->ReqId = ReqId; + QueryResponse->InfoBufOffset = 16U; + + /* Set Response Ready field in order to send response during next control request */ + hcdc->ResponseRdy = 1U; + + /* Send Notification on Interrupt EP to inform Host that response is ready */ + (void)USBD_CDC_RNDIS_SendNotification(pdev, RESPONSE_AVAILABLE, 0U, NULL); + + return(uint8_t)USBD_OK; +} + + +/** + * @brief USBD_CDC_RNDIS_ProcessSetMsg + * Parse, extract data and check correctness of CDC_RNDIS Set Message command. + * @param pdev: USB Device Handle pointer + * @param Msg: Pointer to the message data extracted from SendEncapsulated command + * @retval status + */ +static uint8_t USBD_CDC_RNDIS_ProcessSetMsg(USBD_HandleTypeDef *pdev, + USBD_CDC_RNDIS_SetMsgTypeDef *Msg) +{ + /* Get the CDC_RNDIS handle pointer */ + USBD_CDC_RNDIS_HandleTypeDef *hcdc = (USBD_CDC_RNDIS_HandleTypeDef *)pdev->pClassData; + + /* Get and format the Msg input */ + USBD_CDC_RNDIS_SetMsgTypeDef *SetMessage = (USBD_CDC_RNDIS_SetMsgTypeDef *)Msg; + + /* Use same Msg input buffer as response buffer */ + USBD_CDC_RNDIS_SetCpltMsgTypeDef *SetResponse = (USBD_CDC_RNDIS_SetCpltMsgTypeDef *)Msg; + + /* Store the Message Request ID */ + uint32_t ReqId = SetMessage->ReqId; + + switch (SetMessage->Oid) + { + case OID_GEN_CURRENT_PACKET_FILTER: + /* Setup the packet filter value */ + hcdc->PacketFilter = SetMessage->InfoBuf[0]; + SetResponse->Status = CDC_RNDIS_STATUS_SUCCESS; + break; + + case OID_802_3_MULTICAST_LIST: + /* List of multicast addresses on a miniport adapter */ + SetResponse->Status = CDC_RNDIS_STATUS_SUCCESS; + break; + + default: + /* Report an error */ + SetResponse->Status = CDC_RNDIS_STATUS_FAILURE; + break; + } + + /* Prepare response buffer */ + SetResponse->MsgType = CDC_RNDIS_SET_CMPLT_ID; + SetResponse->MsgLength = sizeof(USBD_CDC_RNDIS_SetCpltMsgTypeDef); + SetResponse->ReqId = ReqId; + + /* Set Response Ready field in order to send response during next control request */ + hcdc->ResponseRdy = 1U; + + /* Send Notification on Interrupt EP to inform Host that response is ready */ + (void)USBD_CDC_RNDIS_SendNotification(pdev, RESPONSE_AVAILABLE, 0U, NULL); + + return (uint8_t)USBD_OK; +} + + +/** + * @brief USBD_CDC_RNDIS_ProcessResetMsg + * Parse, extract data and check correctness of CDC_RNDIS Set Message command. + * @param pdev: USB Device Handle pointer + * @param Msg: Pointer to the message data extracted from SendEncapsulated command + * @retval status + */ +static uint8_t USBD_CDC_RNDIS_ProcessResetMsg(USBD_HandleTypeDef *pdev, + USBD_CDC_RNDIS_ResetMsgTypeDef *Msg) +{ + /* Get and format the Msg input */ + USBD_CDC_RNDIS_ResetMsgTypeDef *ResetMessage = (USBD_CDC_RNDIS_ResetMsgTypeDef *)Msg; + /* Get the CDC_RNDIS handle pointer */ + USBD_CDC_RNDIS_HandleTypeDef *hcdc = (USBD_CDC_RNDIS_HandleTypeDef *)pdev->pClassData; + /* Use same Msg input buffer as response buffer */ + USBD_CDC_RNDIS_ResetCpltMsgTypeDef *ResetResponse = (USBD_CDC_RNDIS_ResetCpltMsgTypeDef *)Msg; + + if ((ResetMessage->MsgLength != sizeof(USBD_CDC_RNDIS_ResetMsgTypeDef)) || \ + (ResetMessage->Reserved != 0U)) + { + ResetResponse->Status = CDC_RNDIS_STATUS_FAILURE; + } + else + { + ResetResponse->Status = CDC_RNDIS_STATUS_SUCCESS; + } + + /* Prepare response buffer */ + ResetResponse->MsgType = CDC_RNDIS_RESET_CMPLT_ID; + ResetResponse->MsgLength = sizeof(USBD_CDC_RNDIS_ResetCpltMsgTypeDef); + ResetResponse->AddrReset = 0U; + + /* Set CDC_RNDIS state to INITIALIZED */ + hcdc->State = CDC_RNDIS_STATE_BUS_INITIALIZED; + hcdc->LinkStatus = 0U; + + /* Set Response Ready field in order to send response during next control request */ + hcdc->ResponseRdy = 1U; + + /* Send Notification on Interrupt EP to inform Host that response is ready */ + (void)USBD_CDC_RNDIS_SendNotification(pdev, RESPONSE_AVAILABLE, 0U, NULL); + + return (uint8_t)USBD_OK; +} + + +/** + * @brief USBD_CDC_RNDIS_ProcessPacketMsg + * Parse, extract data and check correctness of CDC_RNDIS Data Packet. + * @param pdev: USB Device Handle pointer + * @param Msg: Pointer to the message data extracted from Packet + * @retval status + */ +static uint8_t USBD_CDC_RNDIS_ProcessPacketMsg(USBD_HandleTypeDef *pdev, + USBD_CDC_RNDIS_PacketMsgTypeDef *Msg) +{ + uint32_t tmp1, tmp2; + + /* Get the CDC_RNDIS handle pointer */ + USBD_CDC_RNDIS_HandleTypeDef *hcdc = (USBD_CDC_RNDIS_HandleTypeDef *)pdev->pClassData; + + /* Get and format the Msg input */ + USBD_CDC_RNDIS_PacketMsgTypeDef *PacketMsg = (USBD_CDC_RNDIS_PacketMsgTypeDef *)Msg; + + /* Check correctness of the message */ + if ((PacketMsg->MsgType != CDC_RNDIS_PACKET_MSG_ID)) + { + return (uint8_t)USBD_FAIL; + } + + /* Point to the payload and udpate the message length */ + + /* Use temporary storage variables to comply with MISRA-C 2012 rule of (+) operand allowed types */ + tmp1 = (uint32_t)PacketMsg; + tmp2 = (uint32_t)(PacketMsg->DataOffset); + hcdc->RxBuffer = (uint8_t *)(tmp1 + tmp2 + CDC_RNDIS_PCKTMSG_DATAOFFSET_OFFSET); + hcdc->RxLength = PacketMsg->DataLength; + + /* Process data by application */ + ((USBD_CDC_RNDIS_ItfTypeDef *)pdev->pUserData)->Receive(hcdc->RxBuffer, &hcdc->RxLength); + + return (uint8_t)USBD_OK; +} + + +/** +* @brief USBD_CDC_RNDIS_ProcessUnsupportedMsg +* Parse, extract data and check correctness of CDC_RNDIS KeepAlive command. +* @param pdev: USB Device Handle pointer +* @param Msg: Pointer to the message data extracted from SendEncapsulated command +* @retval status +*/ +static uint8_t USBD_CDC_RNDIS_ProcessUnsupportedMsg(USBD_HandleTypeDef *pdev, + USBD_CDC_RNDIS_CtrlMsgTypeDef *Msg) +{ + /* Get the CDC_RNDIS handle pointer */ + USBD_CDC_RNDIS_HandleTypeDef *hcdc = (USBD_CDC_RNDIS_HandleTypeDef *)pdev->pClassData; + + /* Use same Msg input buffer as response buffer */ + USBD_CDC_RNDIS_StsChangeMsgTypeDef *Response = (USBD_CDC_RNDIS_StsChangeMsgTypeDef *)Msg; + + /* Setup the response buffer content */ + Response->MsgType = CDC_RNDIS_INDICATE_STATUS_MSG_ID; + Response->MsgLength = sizeof(USBD_CDC_RNDIS_StsChangeMsgTypeDef); + Response->Status = CDC_RNDIS_STATUS_NOT_SUPPORTED; + Response->StsBufLength = 0U; + Response->StsBufOffset = 20U; + + /* Set Response Ready field in order to send response during next control request */ + hcdc->ResponseRdy = 1U; + + /* Send Notification on Interrupt EP to inform Host that response is ready */ + (void)USBD_CDC_RNDIS_SendNotification(pdev, RESPONSE_AVAILABLE, 0U, NULL); + + UNUSED(Msg); + + return (uint8_t)USBD_OK; +} + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Middlewares/ST/STM32_USB_Device_Library/Class/CDC_RNDIS/Src/usbd_cdc_rndis_if_template.c b/system/Middlewares/ST/STM32_USB_Device_Library/Class/CDC_RNDIS/Src/usbd_cdc_rndis_if_template.c new file mode 100644 index 0000000000..9408d43bb4 --- /dev/null +++ b/system/Middlewares/ST/STM32_USB_Device_Library/Class/CDC_RNDIS/Src/usbd_cdc_rndis_if_template.c @@ -0,0 +1,233 @@ +/** + ****************************************************************************** + * @file usbd_cdc_rndis_if_template.c + * @author MCD Application Team + * @brief Source file for USBD CDC_RNDIS interface template + ****************************************************************************** + * @attention + * + *

    © Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

    + * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ + +/* Include TCP/IP stack header files */ +/* +#include "lwip/opt.h" +#include "lwip/init.h" +#include "lwip/dhcp.h" +#include "lwip/netif.h" +#include "lwip/timeouts.h" +#include "netif/etharp.h" +#include "http_cgi_ssi.h" +#include "ethernetif.h" +*/ + +#include "main.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +#if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 +#endif +__ALIGN_BEGIN uint8_t UserRxBuffer[CDC_RNDIS_ETH_MAX_SEGSZE + 100] __ALIGN_END; /* Received Data over USB are stored in this buffer */ + +#if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 +#endif +__ALIGN_BEGIN static uint8_t UserTxBuffer[CDC_RNDIS_ETH_MAX_SEGSZE + 100] __ALIGN_END; /* Received Data over CDC_RNDIS (CDC_RNDIS interface) are stored in this buffer */ + +static uint8_t CDC_RNDISInitialized = 0U; + +/* USB handler declaration */ +extern USBD_HandleTypeDef USBD_Device; + + +/* Private function prototypes -----------------------------------------------*/ +static int8_t CDC_RNDIS_Itf_Init(void); +static int8_t CDC_RNDIS_Itf_DeInit(void); +static int8_t CDC_RNDIS_Itf_Control(uint8_t cmd, uint8_t *pbuf, uint16_t length); +static int8_t CDC_RNDIS_Itf_Receive(uint8_t *pbuf, uint32_t *Len); +static int8_t CDC_RNDIS_Itf_TransmitCplt(uint8_t *pbuf, uint32_t *Len, uint8_t epnum); +static int8_t CDC_RNDIS_Itf_Process(USBD_HandleTypeDef *pdev); + +USBD_CDC_RNDIS_ItfTypeDef USBD_CDC_RNDIS_fops = +{ + CDC_RNDIS_Itf_Init, + CDC_RNDIS_Itf_DeInit, + CDC_RNDIS_Itf_Control, + CDC_RNDIS_Itf_Receive, + CDC_RNDIS_Itf_TransmitCplt, + CDC_RNDIS_Itf_Process, + (uint8_t *)CDC_RNDIS_MAC_STR_DESC, +}; + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief CDC_RNDIS_Itf_Init + * Initializes the CDC_RNDIS media low layer + * @param None + * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL + */ +static int8_t CDC_RNDIS_Itf_Init(void) +{ + if (CDC_RNDISInitialized == 0U) + { + /* + Initialize the LwIP stack + Add your code here + + */ + + CDC_RNDISInitialized = 1U; + } + + /* Set Application Buffers */ + (void)USBD_CDC_RNDIS_SetTxBuffer(&USBD_Device, UserTxBuffer, 0U); + (void)USBD_CDC_RNDIS_SetRxBuffer(&USBD_Device, UserRxBuffer); + + return (0); +} + +/** + * @brief CDC_RNDIS_Itf_DeInit + * DeInitializes the CDC_RNDIS media low layer + * @param None + * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL + */ +static int8_t CDC_RNDIS_Itf_DeInit(void) +{ + USBD_CDC_RNDIS_HandleTypeDef *hcdc_cdc_rndis = (USBD_CDC_RNDIS_HandleTypeDef *)(USBD_Device.pClassData); + + /* + Add your code here + */ + + /* Notify application layer that link is down */ + hcdc_cdc_rndis->LinkStatus = 0U; + + return (0); +} + +/** + * @brief CDC_RNDIS_Itf_Control + * Manage the CDC_RNDIS class requests + * @param Cmd: Command code + * @param Buf: Buffer containing command data (request parameters) + * @param Len: Number of data to be sent (in bytes) + * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL + */ +static int8_t CDC_RNDIS_Itf_Control(uint8_t cmd, uint8_t *pbuf, uint16_t length) +{ + USBD_CDC_RNDIS_HandleTypeDef *hcdc_cdc_rndis = (USBD_CDC_RNDIS_HandleTypeDef *)(USBD_Device.pClassData); + + switch (cmd) + { + case CDC_RNDIS_SEND_ENCAPSULATED_COMMAND: + /* Add your code here */ + break; + + case CDC_RNDIS_GET_ENCAPSULATED_RESPONSE: + /* Check if this is the first time we enter */ + if (hcdc_cdc_rndis->LinkStatus == 0U) + { + /* Setup the Link up at TCP/IP stack level */ + hcdc_cdc_rndis->LinkStatus = 1U; + /* + Add your code here + */ + } + /* Add your code here */ + break; + + default: + /* Add your code here */ + break; + } + + UNUSED(length); + UNUSED(pbuf); + + return (0); +} + +/** + * @brief CDC_RNDIS_Itf_Receive + * Data received over USB OUT endpoint are sent over CDC_RNDIS interface + * through this function. + * @param Buf: Buffer of data to be transmitted + * @param Len: Number of data received (in bytes) + * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL + */ +static int8_t CDC_RNDIS_Itf_Receive(uint8_t *Buf, uint32_t *Len) +{ + /* Get the CDC_RNDIS handler pointer */ + USBD_CDC_RNDIS_HandleTypeDef *hcdc_cdc_rndis = (USBD_CDC_RNDIS_HandleTypeDef *)(USBD_Device.pClassData); + + /* Call Eth buffer processing */ + hcdc_cdc_rndis->RxState = 1U; + + UNUSED(Buf); + UNUSED(Len); + + return (0); +} + +/** + * @brief CDC_RNDIS_Itf_TransmitCplt + * Data transmited callback + * + * @note + * This function is IN transfer complete callback used to inform user that + * the submitted Data is successfully sent over USB. + * + * @param Buf: Buffer of data to be received + * @param Len: Number of data received (in bytes) + * @param epnum: EP number + * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL + */ +static int8_t CDC_RNDIS_Itf_TransmitCplt(uint8_t *Buf, uint32_t *Len, uint8_t epnum) +{ + UNUSED(Buf); + UNUSED(Len); + UNUSED(epnum); + + return (0); +} + +/** + * @brief CDC_RNDIS_Itf_Process + * Data received over USB OUT endpoint are sent over CDC_RNDIS interface + * through this function. + * @param pdef: pointer to the USB Device Handle + * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL + */ +static int8_t CDC_RNDIS_Itf_Process(USBD_HandleTypeDef *pdev) +{ + /* Get the CDC_RNDIS handler pointer */ + USBD_CDC_RNDIS_HandleTypeDef *hcdc_cdc_rndis = (USBD_CDC_RNDIS_HandleTypeDef *)(pdev->pClassData); + + if ((hcdc_cdc_rndis != NULL) && (hcdc_cdc_rndis->LinkStatus != 0U)) + { + /* + Add your code here + Read a received packet from the Ethernet buffers and send it + to the lwIP for handling + */ + } + + return (0); +} + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Middlewares/ST/STM32_USB_Device_Library/Class/CustomHID/Inc/usbd_customhid.h b/system/Middlewares/ST/STM32_USB_Device_Library/Class/CustomHID/Inc/usbd_customhid.h index d461c01a33..a1dcd7ca7b 100644 --- a/system/Middlewares/ST/STM32_USB_Device_Library/Class/CustomHID/Inc/usbd_customhid.h +++ b/system/Middlewares/ST/STM32_USB_Device_Library/Class/CustomHID/Inc/usbd_customhid.h @@ -41,41 +41,42 @@ extern "C" { /** @defgroup USBD_CUSTOM_HID_Exported_Defines * @{ */ -#define CUSTOM_HID_EPIN_ADDR 0x81U -#define CUSTOM_HID_EPIN_SIZE 0x02U +#define CUSTOM_HID_EPIN_ADDR 0x81U +#define CUSTOM_HID_EPIN_SIZE 0x02U -#define CUSTOM_HID_EPOUT_ADDR 0x01U -#define CUSTOM_HID_EPOUT_SIZE 0x02U +#define CUSTOM_HID_EPOUT_ADDR 0x01U +#define CUSTOM_HID_EPOUT_SIZE 0x02U -#define USB_CUSTOM_HID_CONFIG_DESC_SIZ 41U -#define USB_CUSTOM_HID_DESC_SIZ 9U +#define USB_CUSTOM_HID_CONFIG_DESC_SIZ 41U +#define USB_CUSTOM_HID_DESC_SIZ 9U #ifndef CUSTOM_HID_HS_BINTERVAL -#define CUSTOM_HID_HS_BINTERVAL 0x05U +#define CUSTOM_HID_HS_BINTERVAL 0x05U #endif /* CUSTOM_HID_HS_BINTERVAL */ #ifndef CUSTOM_HID_FS_BINTERVAL -#define CUSTOM_HID_FS_BINTERVAL 0x05U +#define CUSTOM_HID_FS_BINTERVAL 0x05U #endif /* CUSTOM_HID_FS_BINTERVAL */ #ifndef USBD_CUSTOMHID_OUTREPORT_BUF_SIZE -#define USBD_CUSTOMHID_OUTREPORT_BUF_SIZE 0x02U +#define USBD_CUSTOMHID_OUTREPORT_BUF_SIZE 0x02U #endif /* USBD_CUSTOMHID_OUTREPORT_BUF_SIZE */ + #ifndef USBD_CUSTOM_HID_REPORT_DESC_SIZE -#define USBD_CUSTOM_HID_REPORT_DESC_SIZE 163U +#define USBD_CUSTOM_HID_REPORT_DESC_SIZE 163U #endif /* USBD_CUSTOM_HID_REPORT_DESC_SIZE */ -#define CUSTOM_HID_DESCRIPTOR_TYPE 0x21U -#define CUSTOM_HID_REPORT_DESC 0x22U +#define CUSTOM_HID_DESCRIPTOR_TYPE 0x21U +#define CUSTOM_HID_REPORT_DESC 0x22U -#define CUSTOM_HID_REQ_SET_PROTOCOL 0x0BU -#define CUSTOM_HID_REQ_GET_PROTOCOL 0x03U +#define CUSTOM_HID_REQ_SET_PROTOCOL 0x0BU +#define CUSTOM_HID_REQ_GET_PROTOCOL 0x03U -#define CUSTOM_HID_REQ_SET_IDLE 0x0AU -#define CUSTOM_HID_REQ_GET_IDLE 0x02U +#define CUSTOM_HID_REQ_SET_IDLE 0x0AU +#define CUSTOM_HID_REQ_GET_IDLE 0x02U -#define CUSTOM_HID_REQ_SET_REPORT 0x09U -#define CUSTOM_HID_REQ_GET_REPORT 0x01U +#define CUSTOM_HID_REQ_SET_REPORT 0x09U +#define CUSTOM_HID_REQ_GET_REPORT 0x01U /** * @} */ @@ -88,12 +89,11 @@ typedef enum { CUSTOM_HID_IDLE = 0U, CUSTOM_HID_BUSY, -} -CUSTOM_HID_StateTypeDef; +} CUSTOM_HID_StateTypeDef; typedef struct _USBD_CUSTOM_HID_Itf { - uint8_t *pReport; + uint8_t *pReport; int8_t (* Init)(void); int8_t (* DeInit)(void); int8_t (* OutEvent)(uint8_t event_idx, uint8_t state); @@ -102,14 +102,13 @@ typedef struct _USBD_CUSTOM_HID_Itf typedef struct { - uint8_t Report_buf[USBD_CUSTOMHID_OUTREPORT_BUF_SIZE]; - uint32_t Protocol; - uint32_t IdleState; - uint32_t AltSetting; - uint32_t IsReportAvailable; - CUSTOM_HID_StateTypeDef state; -} -USBD_CUSTOM_HID_HandleTypeDef; + uint8_t Report_buf[USBD_CUSTOMHID_OUTREPORT_BUF_SIZE]; + uint32_t Protocol; + uint32_t IdleState; + uint32_t AltSetting; + uint32_t IsReportAvailable; + CUSTOM_HID_StateTypeDef state; +} USBD_CUSTOM_HID_HandleTypeDef; /** * @} */ @@ -128,8 +127,8 @@ USBD_CUSTOM_HID_HandleTypeDef; * @{ */ -extern USBD_ClassTypeDef USBD_CUSTOM_HID; -#define USBD_CUSTOM_HID_CLASS &USBD_CUSTOM_HID +extern USBD_ClassTypeDef USBD_CUSTOM_HID; +#define USBD_CUSTOM_HID_CLASS &USBD_CUSTOM_HID /** * @} */ @@ -138,13 +137,12 @@ extern USBD_ClassTypeDef USBD_CUSTOM_HID; * @{ */ uint8_t USBD_CUSTOM_HID_SendReport(USBD_HandleTypeDef *pdev, - uint8_t *report, - uint16_t len); - + uint8_t *report, uint16_t len); +uint8_t USBD_CUSTOM_HID_ReceivePacket(USBD_HandleTypeDef *pdev); -uint8_t USBD_CUSTOM_HID_RegisterInterface(USBD_HandleTypeDef *pdev, - USBD_CUSTOM_HID_ItfTypeDef *fops); +uint8_t USBD_CUSTOM_HID_RegisterInterface(USBD_HandleTypeDef *pdev, + USBD_CUSTOM_HID_ItfTypeDef *fops); /** * @} diff --git a/system/Middlewares/ST/STM32_USB_Device_Library/Class/CustomHID/Src/usbd_customhid.c b/system/Middlewares/ST/STM32_USB_Device_Library/Class/CustomHID/Src/usbd_customhid.c index 8998070c0a..268027407f 100644 --- a/system/Middlewares/ST/STM32_USB_Device_Library/Class/CustomHID/Src/usbd_customhid.c +++ b/system/Middlewares/ST/STM32_USB_Device_Library/Class/CustomHID/Src/usbd_customhid.c @@ -84,28 +84,19 @@ EndBSPDependencies */ * @{ */ +static uint8_t USBD_CUSTOM_HID_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx); +static uint8_t USBD_CUSTOM_HID_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx); +static uint8_t USBD_CUSTOM_HID_Setup(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); -static uint8_t USBD_CUSTOM_HID_Init(USBD_HandleTypeDef *pdev, - uint8_t cfgidx); +static uint8_t USBD_CUSTOM_HID_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum); +static uint8_t USBD_CUSTOM_HID_DataOut(USBD_HandleTypeDef *pdev, uint8_t epnum); +static uint8_t USBD_CUSTOM_HID_EP0_RxReady(USBD_HandleTypeDef *pdev); -static uint8_t USBD_CUSTOM_HID_DeInit(USBD_HandleTypeDef *pdev, - uint8_t cfgidx); +static uint8_t *USBD_CUSTOM_HID_GetFSCfgDesc(uint16_t *length); +static uint8_t *USBD_CUSTOM_HID_GetHSCfgDesc(uint16_t *length); +static uint8_t *USBD_CUSTOM_HID_GetOtherSpeedCfgDesc(uint16_t *length); +static uint8_t *USBD_CUSTOM_HID_GetDeviceQualifierDesc(uint16_t *length); -static uint8_t USBD_CUSTOM_HID_Setup(USBD_HandleTypeDef *pdev, - USBD_SetupReqTypedef *req); - -static uint8_t *USBD_CUSTOM_HID_GetFSCfgDesc(uint16_t *length); - -static uint8_t *USBD_CUSTOM_HID_GetHSCfgDesc(uint16_t *length); - -static uint8_t *USBD_CUSTOM_HID_GetOtherSpeedCfgDesc(uint16_t *length); - -static uint8_t *USBD_CUSTOM_HID_GetDeviceQualifierDesc(uint16_t *length); - -static uint8_t USBD_CUSTOM_HID_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum); - -static uint8_t USBD_CUSTOM_HID_DataOut(USBD_HandleTypeDef *pdev, uint8_t epnum); -static uint8_t USBD_CUSTOM_HID_EP0_RxReady(USBD_HandleTypeDef *pdev); /** * @} */ @@ -135,177 +126,174 @@ USBD_ClassTypeDef USBD_CUSTOM_HID = /* USB CUSTOM_HID device FS Configuration Descriptor */ __ALIGN_BEGIN static uint8_t USBD_CUSTOM_HID_CfgFSDesc[USB_CUSTOM_HID_CONFIG_DESC_SIZ] __ALIGN_END = { - 0x09, /* bLength: Configuration Descriptor size */ - USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */ + 0x09, /* bLength: Configuration Descriptor size */ + USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */ USB_CUSTOM_HID_CONFIG_DESC_SIZ, - /* wTotalLength: Bytes returned */ + /* wTotalLength: Bytes returned */ 0x00, - 0x01, /*bNumInterfaces: 1 interface*/ - 0x01, /*bConfigurationValue: Configuration value*/ - 0x00, /*iConfiguration: Index of string descriptor describing - the configuration*/ - 0xC0, /*bmAttributes: bus powered */ - 0x32, /*MaxPower 100 mA: this current is used for detecting Vbus*/ + 0x01, /* bNumInterfaces: 1 interface */ + 0x01, /* bConfigurationValue: Configuration value */ + 0x00, /* iConfiguration: Index of string descriptor describing the configuration */ + 0xC0, /* bmAttributes: bus powered */ + 0x32, /* MaxPower 100 mA: this current is used for detecting Vbus */ /************** Descriptor of CUSTOM HID interface ****************/ /* 09 */ - 0x09, /*bLength: Interface Descriptor size*/ - USB_DESC_TYPE_INTERFACE,/*bDescriptorType: Interface descriptor type*/ - 0x00, /*bInterfaceNumber: Number of Interface*/ - 0x00, /*bAlternateSetting: Alternate setting*/ - 0x02, /*bNumEndpoints*/ - 0x03, /*bInterfaceClass: CUSTOM_HID*/ - 0x00, /*bInterfaceSubClass : 1=BOOT, 0=no boot*/ - 0x00, /*nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse*/ - 0, /*iInterface: Index of string descriptor*/ + 0x09, /* bLength: Interface Descriptor size*/ + USB_DESC_TYPE_INTERFACE, /* bDescriptorType: Interface descriptor type */ + 0x00, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x02, /* bNumEndpoints*/ + 0x03, /* bInterfaceClass: CUSTOM_HID */ + 0x00, /* bInterfaceSubClass : 1=BOOT, 0=no boot */ + 0x00, /* nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse */ + 0x00, /* iInterface: Index of string descriptor */ /******************** Descriptor of CUSTOM_HID *************************/ /* 18 */ - 0x09, /*bLength: CUSTOM_HID Descriptor size*/ - CUSTOM_HID_DESCRIPTOR_TYPE, /*bDescriptorType: CUSTOM_HID*/ - 0x11, /*bCUSTOM_HIDUSTOM_HID: CUSTOM_HID Class Spec release number*/ + 0x09, /* bLength: CUSTOM_HID Descriptor size */ + CUSTOM_HID_DESCRIPTOR_TYPE, /* bDescriptorType: CUSTOM_HID */ + 0x11, /* bCUSTOM_HIDUSTOM_HID: CUSTOM_HID Class Spec release number */ 0x01, - 0x00, /*bCountryCode: Hardware target country*/ - 0x01, /*bNumDescriptors: Number of CUSTOM_HID class descriptors to follow*/ - 0x22, /*bDescriptorType*/ - USBD_CUSTOM_HID_REPORT_DESC_SIZE,/*wItemLength: Total length of Report descriptor*/ + 0x00, /* bCountryCode: Hardware target country */ + 0x01, /* bNumDescriptors: Number of CUSTOM_HID class descriptors to follow */ + 0x22, /* bDescriptorType */ + USBD_CUSTOM_HID_REPORT_DESC_SIZE, /* wItemLength: Total length of Report descriptor */ 0x00, /******************** Descriptor of Custom HID endpoints ********************/ /* 27 */ - 0x07, /*bLength: Endpoint Descriptor size*/ - USB_DESC_TYPE_ENDPOINT, /*bDescriptorType:*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: */ - CUSTOM_HID_EPIN_ADDR, /*bEndpointAddress: Endpoint Address (IN)*/ - 0x03, /*bmAttributes: Interrupt endpoint*/ - CUSTOM_HID_EPIN_SIZE, /*wMaxPacketSize: 2 Byte max */ + CUSTOM_HID_EPIN_ADDR, /* bEndpointAddress: Endpoint Address (IN) */ + 0x03, /* bmAttributes: Interrupt endpoint */ + CUSTOM_HID_EPIN_SIZE, /* wMaxPacketSize: 2 Byte max */ 0x00, - CUSTOM_HID_FS_BINTERVAL, /*bInterval: Polling Interval */ + CUSTOM_HID_FS_BINTERVAL, /* bInterval: Polling Interval */ /* 34 */ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: */ - CUSTOM_HID_EPOUT_ADDR, /*bEndpointAddress: Endpoint Address (OUT)*/ - 0x03, /* bmAttributes: Interrupt endpoint */ - CUSTOM_HID_EPOUT_SIZE, /* wMaxPacketSize: 2 Bytes max */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: */ + CUSTOM_HID_EPOUT_ADDR, /* bEndpointAddress: Endpoint Address (OUT) */ + 0x03, /* bmAttributes: Interrupt endpoint */ + CUSTOM_HID_EPOUT_SIZE, /* wMaxPacketSize: 2 Bytes max */ 0x00, - CUSTOM_HID_FS_BINTERVAL, /* bInterval: Polling Interval */ + CUSTOM_HID_FS_BINTERVAL, /* bInterval: Polling Interval */ /* 41 */ }; /* USB CUSTOM_HID device HS Configuration Descriptor */ __ALIGN_BEGIN static uint8_t USBD_CUSTOM_HID_CfgHSDesc[USB_CUSTOM_HID_CONFIG_DESC_SIZ] __ALIGN_END = { - 0x09, /* bLength: Configuration Descriptor size */ - USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */ + 0x09, /* bLength: Configuration Descriptor size */ + USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */ USB_CUSTOM_HID_CONFIG_DESC_SIZ, - /* wTotalLength: Bytes returned */ + /* wTotalLength: Bytes returned */ 0x00, - 0x01, /*bNumInterfaces: 1 interface*/ - 0x01, /*bConfigurationValue: Configuration value*/ - 0x00, /*iConfiguration: Index of string descriptor describing - the configuration*/ - 0xC0, /*bmAttributes: bus powered */ - 0x32, /*MaxPower 100 mA: this current is used for detecting Vbus*/ + 0x01, /* bNumInterfaces: 1 interface */ + 0x01, /* bConfigurationValue: Configuration value */ + 0x00, /* iConfiguration: Index of string descriptor describing the configuration */ + 0xC0, /* bmAttributes: bus powered */ + 0x32, /* MaxPower 100 mA: this current is used for detecting Vbus */ /************** Descriptor of CUSTOM HID interface ****************/ /* 09 */ - 0x09, /*bLength: Interface Descriptor size*/ - USB_DESC_TYPE_INTERFACE,/*bDescriptorType: Interface descriptor type*/ - 0x00, /*bInterfaceNumber: Number of Interface*/ - 0x00, /*bAlternateSetting: Alternate setting*/ - 0x02, /*bNumEndpoints*/ - 0x03, /*bInterfaceClass: CUSTOM_HID*/ - 0x00, /*bInterfaceSubClass : 1=BOOT, 0=no boot*/ - 0x00, /*nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse*/ - 0, /*iInterface: Index of string descriptor*/ + 0x09, /* bLength: Interface Descriptor size */ + USB_DESC_TYPE_INTERFACE, /* bDescriptorType: Interface descriptor type */ + 0x00, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x02, /* bNumEndpoints */ + 0x03, /* bInterfaceClass: CUSTOM_HID */ + 0x00, /* bInterfaceSubClass : 1=BOOT, 0=no boot */ + 0x00, /* nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse */ + 0, /* iInterface: Index of string descriptor */ /******************** Descriptor of CUSTOM_HID *************************/ /* 18 */ - 0x09, /*bLength: CUSTOM_HID Descriptor size*/ - CUSTOM_HID_DESCRIPTOR_TYPE, /*bDescriptorType: CUSTOM_HID*/ - 0x11, /*bCUSTOM_HIDUSTOM_HID: CUSTOM_HID Class Spec release number*/ + 0x09, /* bLength: CUSTOM_HID Descriptor size */ + CUSTOM_HID_DESCRIPTOR_TYPE, /* bDescriptorType: CUSTOM_HID */ + 0x11, /* bCUSTOM_HIDUSTOM_HID: CUSTOM_HID Class Spec release number */ 0x01, - 0x00, /*bCountryCode: Hardware target country*/ - 0x01, /*bNumDescriptors: Number of CUSTOM_HID class descriptors to follow*/ - 0x22, /*bDescriptorType*/ - USBD_CUSTOM_HID_REPORT_DESC_SIZE,/*wItemLength: Total length of Report descriptor*/ + 0x00, /* bCountryCode: Hardware target country */ + 0x01, /* bNumDescriptors: Number of CUSTOM_HID class descriptors to follow */ + 0x22, /* bDescriptorType */ + USBD_CUSTOM_HID_REPORT_DESC_SIZE, /* wItemLength: Total length of Report descriptor */ 0x00, /******************** Descriptor of Custom HID endpoints ********************/ /* 27 */ - 0x07, /*bLength: Endpoint Descriptor size*/ - USB_DESC_TYPE_ENDPOINT, /*bDescriptorType:*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: */ - CUSTOM_HID_EPIN_ADDR, /*bEndpointAddress: Endpoint Address (IN)*/ - 0x03, /*bmAttributes: Interrupt endpoint*/ - CUSTOM_HID_EPIN_SIZE, /*wMaxPacketSize: 2 Byte max */ + CUSTOM_HID_EPIN_ADDR, /* bEndpointAddress: Endpoint Address (IN) */ + 0x03, /* bmAttributes: Interrupt endpoint */ + CUSTOM_HID_EPIN_SIZE, /* wMaxPacketSize: 2 Byte max */ 0x00, - CUSTOM_HID_HS_BINTERVAL, /*bInterval: Polling Interval */ + CUSTOM_HID_HS_BINTERVAL, /* bInterval: Polling Interval */ /* 34 */ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: */ - CUSTOM_HID_EPOUT_ADDR, /*bEndpointAddress: Endpoint Address (OUT)*/ - 0x03, /* bmAttributes: Interrupt endpoint */ - CUSTOM_HID_EPOUT_SIZE, /* wMaxPacketSize: 2 Bytes max */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: */ + CUSTOM_HID_EPOUT_ADDR, /* bEndpointAddress: Endpoint Address (OUT) */ + 0x03, /* bmAttributes: Interrupt endpoint */ + CUSTOM_HID_EPOUT_SIZE, /* wMaxPacketSize: 2 Bytes max */ 0x00, - CUSTOM_HID_HS_BINTERVAL, /* bInterval: Polling Interval */ + CUSTOM_HID_HS_BINTERVAL, /* bInterval: Polling Interval */ /* 41 */ }; /* USB CUSTOM_HID device Other Speed Configuration Descriptor */ __ALIGN_BEGIN static uint8_t USBD_CUSTOM_HID_OtherSpeedCfgDesc[USB_CUSTOM_HID_CONFIG_DESC_SIZ] __ALIGN_END = { - 0x09, /* bLength: Configuration Descriptor size */ - USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */ + 0x09, /* bLength: Configuration Descriptor size */ + USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */ USB_CUSTOM_HID_CONFIG_DESC_SIZ, - /* wTotalLength: Bytes returned */ + /* wTotalLength: Bytes returned */ 0x00, - 0x01, /*bNumInterfaces: 1 interface*/ - 0x01, /*bConfigurationValue: Configuration value*/ - 0x00, /*iConfiguration: Index of string descriptor describing - the configuration*/ - 0xC0, /*bmAttributes: bus powered */ - 0x32, /*MaxPower 100 mA: this current is used for detecting Vbus*/ + 0x01, /* bNumInterfaces: 1 interface */ + 0x01, /* bConfigurationValue: Configuration value */ + 0x00, /* iConfiguration: Index of string descriptor describing the configuration */ + 0xC0, /* bmAttributes: bus powered */ + 0x32, /* MaxPower 100 mA: this current is used for detecting Vbus */ /************** Descriptor of CUSTOM HID interface ****************/ /* 09 */ - 0x09, /*bLength: Interface Descriptor size*/ - USB_DESC_TYPE_INTERFACE,/*bDescriptorType: Interface descriptor type*/ - 0x00, /*bInterfaceNumber: Number of Interface*/ - 0x00, /*bAlternateSetting: Alternate setting*/ - 0x02, /*bNumEndpoints*/ - 0x03, /*bInterfaceClass: CUSTOM_HID*/ - 0x00, /*bInterfaceSubClass : 1=BOOT, 0=no boot*/ - 0x00, /*nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse*/ - 0, /*iInterface: Index of string descriptor*/ + 0x09, /* bLength: Interface Descriptor size */ + USB_DESC_TYPE_INTERFACE, /* bDescriptorType: Interface descriptor type */ + 0x00, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x02, /* bNumEndpoints */ + 0x03, /* bInterfaceClass: CUSTOM_HID */ + 0x00, /* bInterfaceSubClass : 1=BOOT, 0=no boot */ + 0x00, /* nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse */ + 0, /* iInterface: Index of string descriptor */ /******************** Descriptor of CUSTOM_HID *************************/ /* 18 */ - 0x09, /*bLength: CUSTOM_HID Descriptor size*/ - CUSTOM_HID_DESCRIPTOR_TYPE, /*bDescriptorType: CUSTOM_HID*/ - 0x11, /*bCUSTOM_HIDUSTOM_HID: CUSTOM_HID Class Spec release number*/ + 0x09, /* bLength: CUSTOM_HID Descriptor size */ + CUSTOM_HID_DESCRIPTOR_TYPE, /* bDescriptorType: CUSTOM_HID */ + 0x11, /* bCUSTOM_HIDUSTOM_HID: CUSTOM_HID Class Spec release number */ 0x01, - 0x00, /*bCountryCode: Hardware target country*/ - 0x01, /*bNumDescriptors: Number of CUSTOM_HID class descriptors to follow*/ - 0x22, /*bDescriptorType*/ - USBD_CUSTOM_HID_REPORT_DESC_SIZE,/*wItemLength: Total length of Report descriptor*/ + 0x00, /* bCountryCode: Hardware target country */ + 0x01, /* bNumDescriptors: Number of CUSTOM_HID class descriptors to follow */ + 0x22, /* bDescriptorType */ + USBD_CUSTOM_HID_REPORT_DESC_SIZE, /* wItemLength: Total length of Report descriptor */ 0x00, /******************** Descriptor of Custom HID endpoints ********************/ /* 27 */ - 0x07, /*bLength: Endpoint Descriptor size*/ - USB_DESC_TYPE_ENDPOINT, /*bDescriptorType:*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: */ - CUSTOM_HID_EPIN_ADDR, /*bEndpointAddress: Endpoint Address (IN)*/ - 0x03, /*bmAttributes: Interrupt endpoint*/ - CUSTOM_HID_EPIN_SIZE, /*wMaxPacketSize: 2 Byte max */ + CUSTOM_HID_EPIN_ADDR, /* bEndpointAddress: Endpoint Address (IN) */ + 0x03, /* bmAttributes: Interrupt endpoint */ + CUSTOM_HID_EPIN_SIZE, /* wMaxPacketSize: 2 Byte max */ 0x00, - CUSTOM_HID_FS_BINTERVAL, /*bInterval: Polling Interval */ + CUSTOM_HID_FS_BINTERVAL, /* bInterval: Polling Interval */ /* 34 */ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: */ - CUSTOM_HID_EPOUT_ADDR, /*bEndpointAddress: Endpoint Address (OUT)*/ - 0x03, /* bmAttributes: Interrupt endpoint */ - CUSTOM_HID_EPOUT_SIZE, /* wMaxPacketSize: 2 Bytes max */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: */ + CUSTOM_HID_EPOUT_ADDR, /* bEndpointAddress: Endpoint Address (OUT) */ + 0x03, /* bmAttributes: Interrupt endpoint */ + CUSTOM_HID_EPOUT_SIZE, /* wMaxPacketSize: 2 Bytes max */ 0x00, - CUSTOM_HID_FS_BINTERVAL, /* bInterval: Polling Interval */ + CUSTOM_HID_FS_BINTERVAL, /* bInterval: Polling Interval */ /* 41 */ }; @@ -313,14 +301,14 @@ __ALIGN_BEGIN static uint8_t USBD_CUSTOM_HID_OtherSpeedCfgDesc[USB_CUSTOM_HID_CO __ALIGN_BEGIN static uint8_t USBD_CUSTOM_HID_Desc[USB_CUSTOM_HID_DESC_SIZ] __ALIGN_END = { /* 18 */ - 0x09, /*bLength: CUSTOM_HID Descriptor size*/ - CUSTOM_HID_DESCRIPTOR_TYPE, /*bDescriptorType: CUSTOM_HID*/ - 0x11, /*bCUSTOM_HIDUSTOM_HID: CUSTOM_HID Class Spec release number*/ + 0x09, /* bLength: CUSTOM_HID Descriptor size */ + CUSTOM_HID_DESCRIPTOR_TYPE, /* bDescriptorType: CUSTOM_HID */ + 0x11, /* bCUSTOM_HIDUSTOM_HID: CUSTOM_HID Class Spec release number */ 0x01, - 0x00, /*bCountryCode: Hardware target country*/ - 0x01, /*bNumDescriptors: Number of CUSTOM_HID class descriptors to follow*/ - 0x22, /*bDescriptorType*/ - USBD_CUSTOM_HID_REPORT_DESC_SIZE,/*wItemLength: Total length of Report descriptor*/ + 0x00, /* bCountryCode: Hardware target country */ + 0x01, /* bNumDescriptors: Number of CUSTOM_HID class descriptors to follow */ + 0x22, /* bDescriptorType */ + USBD_CUSTOM_HID_REPORT_DESC_SIZE, /* wItemLength: Total length of Report descriptor */ 0x00, }; @@ -354,43 +342,53 @@ __ALIGN_BEGIN static uint8_t USBD_CUSTOM_HID_DeviceQualifierDesc[USB_LEN_DEV_QUA * @param cfgidx: Configuration index * @retval status */ -static uint8_t USBD_CUSTOM_HID_Init(USBD_HandleTypeDef *pdev, - uint8_t cfgidx) +static uint8_t USBD_CUSTOM_HID_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { - uint8_t ret = 0U; - USBD_CUSTOM_HID_HandleTypeDef *hhid; + UNUSED(cfgidx); + USBD_CUSTOM_HID_HandleTypeDef *hhid; + + hhid = USBD_malloc(sizeof(USBD_CUSTOM_HID_HandleTypeDef)); + + if (hhid == NULL) + { + pdev->pClassData = NULL; + return (uint8_t)USBD_EMEM; + } + + pdev->pClassData = (void *)hhid; + + if (pdev->dev_speed == USBD_SPEED_HIGH) + { + pdev->ep_in[CUSTOM_HID_EPIN_ADDR & 0xFU].bInterval = CUSTOM_HID_HS_BINTERVAL; + pdev->ep_out[CUSTOM_HID_EPOUT_ADDR & 0xFU].bInterval = CUSTOM_HID_HS_BINTERVAL; + } + else /* LOW and FULL-speed endpoints */ + { + pdev->ep_in[CUSTOM_HID_EPIN_ADDR & 0xFU].bInterval = CUSTOM_HID_FS_BINTERVAL; + pdev->ep_out[CUSTOM_HID_EPOUT_ADDR & 0xFU].bInterval = CUSTOM_HID_FS_BINTERVAL; + } /* Open EP IN */ - USBD_LL_OpenEP(pdev, CUSTOM_HID_EPIN_ADDR, USBD_EP_TYPE_INTR, - CUSTOM_HID_EPIN_SIZE); + (void)USBD_LL_OpenEP(pdev, CUSTOM_HID_EPIN_ADDR, USBD_EP_TYPE_INTR, + CUSTOM_HID_EPIN_SIZE); pdev->ep_in[CUSTOM_HID_EPIN_ADDR & 0xFU].is_used = 1U; /* Open EP OUT */ - USBD_LL_OpenEP(pdev, CUSTOM_HID_EPOUT_ADDR, USBD_EP_TYPE_INTR, - CUSTOM_HID_EPOUT_SIZE); + (void)USBD_LL_OpenEP(pdev, CUSTOM_HID_EPOUT_ADDR, USBD_EP_TYPE_INTR, + CUSTOM_HID_EPOUT_SIZE); pdev->ep_out[CUSTOM_HID_EPOUT_ADDR & 0xFU].is_used = 1U; - pdev->pClassData = USBD_malloc(sizeof(USBD_CUSTOM_HID_HandleTypeDef)); - - if (pdev->pClassData == NULL) - { - ret = 1U; - } - else - { - hhid = (USBD_CUSTOM_HID_HandleTypeDef *) pdev->pClassData; + hhid->state = CUSTOM_HID_IDLE; - hhid->state = CUSTOM_HID_IDLE; - ((USBD_CUSTOM_HID_ItfTypeDef *)pdev->pUserData)->Init(); + ((USBD_CUSTOM_HID_ItfTypeDef *)pdev->pUserData)->Init(); - /* Prepare Out endpoint to receive 1st packet */ - USBD_LL_PrepareReceive(pdev, CUSTOM_HID_EPOUT_ADDR, hhid->Report_buf, - USBD_CUSTOMHID_OUTREPORT_BUF_SIZE); - } + /* Prepare Out endpoint to receive 1st packet */ + (void)USBD_LL_PrepareReceive(pdev, CUSTOM_HID_EPOUT_ADDR, hhid->Report_buf, + USBD_CUSTOMHID_OUTREPORT_BUF_SIZE); - return ret; + return (uint8_t)USBD_OK; } /** @@ -400,16 +398,19 @@ static uint8_t USBD_CUSTOM_HID_Init(USBD_HandleTypeDef *pdev, * @param cfgidx: Configuration index * @retval status */ -static uint8_t USBD_CUSTOM_HID_DeInit(USBD_HandleTypeDef *pdev, - uint8_t cfgidx) +static uint8_t USBD_CUSTOM_HID_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { + UNUSED(cfgidx); + /* Close CUSTOM_HID EP IN */ - USBD_LL_CloseEP(pdev, CUSTOM_HID_EPIN_ADDR); + (void)USBD_LL_CloseEP(pdev, CUSTOM_HID_EPIN_ADDR); pdev->ep_in[CUSTOM_HID_EPIN_ADDR & 0xFU].is_used = 0U; + pdev->ep_in[CUSTOM_HID_EPIN_ADDR & 0xFU].bInterval = 0U; /* Close CUSTOM_HID EP OUT */ - USBD_LL_CloseEP(pdev, CUSTOM_HID_EPOUT_ADDR); + (void)USBD_LL_CloseEP(pdev, CUSTOM_HID_EPOUT_ADDR); pdev->ep_out[CUSTOM_HID_EPOUT_ADDR & 0xFU].is_used = 0U; + pdev->ep_out[CUSTOM_HID_EPOUT_ADDR & 0xFU].bInterval = 0U; /* FRee allocated memory */ if (pdev->pClassData != NULL) @@ -418,7 +419,8 @@ static uint8_t USBD_CUSTOM_HID_DeInit(USBD_HandleTypeDef *pdev, USBD_free(pdev->pClassData); pdev->pClassData = NULL; } - return USBD_OK; + + return (uint8_t)USBD_OK; } /** @@ -428,118 +430,121 @@ static uint8_t USBD_CUSTOM_HID_DeInit(USBD_HandleTypeDef *pdev, * @param req: usb requests * @retval status */ -static uint8_t USBD_CUSTOM_HID_Setup(USBD_HandleTypeDef *pdev, - USBD_SetupReqTypedef *req) +static uint8_t USBD_CUSTOM_HID_Setup(USBD_HandleTypeDef *pdev, + USBD_SetupReqTypedef *req) { USBD_CUSTOM_HID_HandleTypeDef *hhid = (USBD_CUSTOM_HID_HandleTypeDef *)pdev->pClassData; uint16_t len = 0U; uint8_t *pbuf = NULL; uint16_t status_info = 0U; - uint8_t ret = USBD_OK; + USBD_StatusTypeDef ret = USBD_OK; switch (req->bmRequest & USB_REQ_TYPE_MASK) { - case USB_REQ_TYPE_CLASS : - switch (req->bRequest) + case USB_REQ_TYPE_CLASS: + switch (req->bRequest) + { + case CUSTOM_HID_REQ_SET_PROTOCOL: + hhid->Protocol = (uint8_t)(req->wValue); + break; + + case CUSTOM_HID_REQ_GET_PROTOCOL: + (void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->Protocol, 1U); + break; + + case CUSTOM_HID_REQ_SET_IDLE: + hhid->IdleState = (uint8_t)(req->wValue >> 8); + break; + + case CUSTOM_HID_REQ_GET_IDLE: + (void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->IdleState, 1U); + break; + + case CUSTOM_HID_REQ_SET_REPORT: + hhid->IsReportAvailable = 1U; + (void)USBD_CtlPrepareRx(pdev, hhid->Report_buf, req->wLength); + break; + + default: + USBD_CtlError(pdev, req); + ret = USBD_FAIL; + break; + } + break; + + case USB_REQ_TYPE_STANDARD: + switch (req->bRequest) + { + case USB_REQ_GET_STATUS: + if (pdev->dev_state == USBD_STATE_CONFIGURED) + { + (void)USBD_CtlSendData(pdev, (uint8_t *)&status_info, 2U); + } + else + { + USBD_CtlError(pdev, req); + ret = USBD_FAIL; + } + break; + + case USB_REQ_GET_DESCRIPTOR: + if ((req->wValue >> 8) == CUSTOM_HID_REPORT_DESC) + { + len = MIN(USBD_CUSTOM_HID_REPORT_DESC_SIZE, req->wLength); + pbuf = ((USBD_CUSTOM_HID_ItfTypeDef *)pdev->pUserData)->pReport; + } + else + { + if ((req->wValue >> 8) == CUSTOM_HID_DESCRIPTOR_TYPE) + { + pbuf = USBD_CUSTOM_HID_Desc; + len = MIN(USB_CUSTOM_HID_DESC_SIZ, req->wLength); + } + } + + (void)USBD_CtlSendData(pdev, pbuf, len); + break; + + case USB_REQ_GET_INTERFACE: + if (pdev->dev_state == USBD_STATE_CONFIGURED) + { + (void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->AltSetting, 1U); + } + else { - case CUSTOM_HID_REQ_SET_PROTOCOL: - hhid->Protocol = (uint8_t)(req->wValue); - break; - - case CUSTOM_HID_REQ_GET_PROTOCOL: - USBD_CtlSendData(pdev, (uint8_t *)(void *)&hhid->Protocol, 1U); - break; - - case CUSTOM_HID_REQ_SET_IDLE: - hhid->IdleState = (uint8_t)(req->wValue >> 8); - break; - - case CUSTOM_HID_REQ_GET_IDLE: - USBD_CtlSendData(pdev, (uint8_t *)(void *)&hhid->IdleState, 1U); - break; - - case CUSTOM_HID_REQ_SET_REPORT: - hhid->IsReportAvailable = 1U; - USBD_CtlPrepareRx(pdev, hhid->Report_buf, req->wLength); - break; - - default: - USBD_CtlError(pdev, req); - ret = USBD_FAIL; - break; + USBD_CtlError(pdev, req); + ret = USBD_FAIL; } break; - case USB_REQ_TYPE_STANDARD: - switch (req->bRequest) + case USB_REQ_SET_INTERFACE: + if (pdev->dev_state == USBD_STATE_CONFIGURED) + { + hhid->AltSetting = (uint8_t)(req->wValue); + } + else { - case USB_REQ_GET_STATUS: - if (pdev->dev_state == USBD_STATE_CONFIGURED) - { - USBD_CtlSendData(pdev, (uint8_t *)(void *)&status_info, 2U); - } - else - { - USBD_CtlError(pdev, req); - ret = USBD_FAIL; - } - break; - - case USB_REQ_GET_DESCRIPTOR: - if (req->wValue >> 8 == CUSTOM_HID_REPORT_DESC) - { - len = MIN(USBD_CUSTOM_HID_REPORT_DESC_SIZE, req->wLength); - pbuf = ((USBD_CUSTOM_HID_ItfTypeDef *)pdev->pUserData)->pReport; - } - else - { - if (req->wValue >> 8 == CUSTOM_HID_DESCRIPTOR_TYPE) - { - pbuf = USBD_CUSTOM_HID_Desc; - len = MIN(USB_CUSTOM_HID_DESC_SIZ, req->wLength); - } - } - - USBD_CtlSendData(pdev, pbuf, len); - break; - - case USB_REQ_GET_INTERFACE : - if (pdev->dev_state == USBD_STATE_CONFIGURED) - { - USBD_CtlSendData(pdev, (uint8_t *)(void *)&hhid->AltSetting, 1U); - } - else - { - USBD_CtlError(pdev, req); - ret = USBD_FAIL; - } - break; - - case USB_REQ_SET_INTERFACE : - if (pdev->dev_state == USBD_STATE_CONFIGURED) - { - hhid->AltSetting = (uint8_t)(req->wValue); - } - else - { - USBD_CtlError(pdev, req); - ret = USBD_FAIL; - } - break; - - default: - USBD_CtlError(pdev, req); - ret = USBD_FAIL; - break; + USBD_CtlError(pdev, req); + ret = USBD_FAIL; } break; + case USB_REQ_CLEAR_FEATURE: + break; + default: USBD_CtlError(pdev, req); ret = USBD_FAIL; break; + } + break; + + default: + USBD_CtlError(pdev, req); + ret = USBD_FAIL; + break; } - return ret; + return (uint8_t)ret; } /** @@ -549,25 +554,31 @@ static uint8_t USBD_CUSTOM_HID_Setup(USBD_HandleTypeDef *pdev, * @param buff: pointer to report * @retval status */ -uint8_t USBD_CUSTOM_HID_SendReport(USBD_HandleTypeDef *pdev, - uint8_t *report, - uint16_t len) +uint8_t USBD_CUSTOM_HID_SendReport(USBD_HandleTypeDef *pdev, + uint8_t *report, uint16_t len) { - USBD_CUSTOM_HID_HandleTypeDef *hhid = (USBD_CUSTOM_HID_HandleTypeDef *)pdev->pClassData; + USBD_CUSTOM_HID_HandleTypeDef *hhid; + + if (pdev->pClassData == NULL) + { + return (uint8_t)USBD_FAIL; + } + + hhid = (USBD_CUSTOM_HID_HandleTypeDef*)pdev->pClassData; if (pdev->dev_state == USBD_STATE_CONFIGURED) { if (hhid->state == CUSTOM_HID_IDLE) { hhid->state = CUSTOM_HID_BUSY; - USBD_LL_Transmit(pdev, CUSTOM_HID_EPIN_ADDR, report, len); + (void)USBD_LL_Transmit(pdev, CUSTOM_HID_EPIN_ADDR, report, len); } else { - return USBD_BUSY; + return (uint8_t)USBD_BUSY; } } - return USBD_OK; + return (uint8_t)USBD_OK; } /** @@ -577,9 +588,10 @@ uint8_t USBD_CUSTOM_HID_SendReport(USBD_HandleTypeDef *pdev, * @param length : pointer data length * @retval pointer to descriptor buffer */ -static uint8_t *USBD_CUSTOM_HID_GetFSCfgDesc(uint16_t *length) +static uint8_t *USBD_CUSTOM_HID_GetFSCfgDesc(uint16_t *length) { - *length = sizeof(USBD_CUSTOM_HID_CfgFSDesc); + *length = (uint16_t)sizeof(USBD_CUSTOM_HID_CfgFSDesc); + return USBD_CUSTOM_HID_CfgFSDesc; } @@ -590,9 +602,10 @@ static uint8_t *USBD_CUSTOM_HID_GetFSCfgDesc(uint16_t *length) * @param length : pointer data length * @retval pointer to descriptor buffer */ -static uint8_t *USBD_CUSTOM_HID_GetHSCfgDesc(uint16_t *length) +static uint8_t *USBD_CUSTOM_HID_GetHSCfgDesc(uint16_t *length) { - *length = sizeof(USBD_CUSTOM_HID_CfgHSDesc); + *length = (uint16_t)sizeof(USBD_CUSTOM_HID_CfgHSDesc); + return USBD_CUSTOM_HID_CfgHSDesc; } @@ -603,9 +616,10 @@ static uint8_t *USBD_CUSTOM_HID_GetHSCfgDesc(uint16_t *length) * @param length : pointer data length * @retval pointer to descriptor buffer */ -static uint8_t *USBD_CUSTOM_HID_GetOtherSpeedCfgDesc(uint16_t *length) +static uint8_t *USBD_CUSTOM_HID_GetOtherSpeedCfgDesc(uint16_t *length) { - *length = sizeof(USBD_CUSTOM_HID_OtherSpeedCfgDesc); + *length = (uint16_t)sizeof(USBD_CUSTOM_HID_OtherSpeedCfgDesc); + return USBD_CUSTOM_HID_OtherSpeedCfgDesc; } @@ -616,14 +630,15 @@ static uint8_t *USBD_CUSTOM_HID_GetOtherSpeedCfgDesc(uint16_t *length) * @param epnum: endpoint index * @retval status */ -static uint8_t USBD_CUSTOM_HID_DataIn(USBD_HandleTypeDef *pdev, - uint8_t epnum) +static uint8_t USBD_CUSTOM_HID_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum) { + UNUSED(epnum); + /* Ensure that the FIFO is empty before a new transfer, this condition could be caused by a new transfer before the end of the previous transfer */ ((USBD_CUSTOM_HID_HandleTypeDef *)pdev->pClassData)->state = CUSTOM_HID_IDLE; - return USBD_OK; + return (uint8_t)USBD_OK; } /** @@ -633,21 +648,52 @@ static uint8_t USBD_CUSTOM_HID_DataIn(USBD_HandleTypeDef *pdev, * @param epnum: endpoint index * @retval status */ -static uint8_t USBD_CUSTOM_HID_DataOut(USBD_HandleTypeDef *pdev, - uint8_t epnum) +static uint8_t USBD_CUSTOM_HID_DataOut(USBD_HandleTypeDef *pdev, uint8_t epnum) { + UNUSED(epnum); + USBD_CUSTOM_HID_HandleTypeDef *hhid; + + if (pdev->pClassData == NULL) + { + return (uint8_t)USBD_FAIL; + } - USBD_CUSTOM_HID_HandleTypeDef *hhid = (USBD_CUSTOM_HID_HandleTypeDef *)pdev->pClassData; + hhid = (USBD_CUSTOM_HID_HandleTypeDef*)pdev->pClassData; + /* USB data will be immediately processed, this allow next USB traffic being + NAKed till the end of the application processing */ ((USBD_CUSTOM_HID_ItfTypeDef *)pdev->pUserData)->OutEvent(hhid->Report_buf[0], hhid->Report_buf[1]); - USBD_LL_PrepareReceive(pdev, CUSTOM_HID_EPOUT_ADDR, hhid->Report_buf, - USBD_CUSTOMHID_OUTREPORT_BUF_SIZE); + return (uint8_t)USBD_OK; +} + + +/** + * @brief USBD_CUSTOM_HID_ReceivePacket + * prepare OUT Endpoint for reception + * @param pdev: device instance + * @retval status + */ +uint8_t USBD_CUSTOM_HID_ReceivePacket(USBD_HandleTypeDef *pdev) +{ + USBD_CUSTOM_HID_HandleTypeDef *hhid; + + if (pdev->pClassData == NULL) + { + return (uint8_t)USBD_FAIL; + } + + hhid = (USBD_CUSTOM_HID_HandleTypeDef*)pdev->pClassData; - return USBD_OK; + /* Resume USB Out process */ + (void)USBD_LL_PrepareReceive(pdev, CUSTOM_HID_EPOUT_ADDR, hhid->Report_buf, + USBD_CUSTOMHID_OUTREPORT_BUF_SIZE); + + return (uint8_t)USBD_OK; } + /** * @brief USBD_CUSTOM_HID_EP0_RxReady * Handles control request data. @@ -656,7 +702,7 @@ static uint8_t USBD_CUSTOM_HID_DataOut(USBD_HandleTypeDef *pdev, */ static uint8_t USBD_CUSTOM_HID_EP0_RxReady(USBD_HandleTypeDef *pdev) { - USBD_CUSTOM_HID_HandleTypeDef *hhid = (USBD_CUSTOM_HID_HandleTypeDef *)pdev->pClassData; + USBD_CUSTOM_HID_HandleTypeDef *hhid = (USBD_CUSTOM_HID_HandleTypeDef *)pdev->pClassData; if (hhid->IsReportAvailable == 1U) { @@ -665,7 +711,7 @@ static uint8_t USBD_CUSTOM_HID_EP0_RxReady(USBD_HandleTypeDef *pdev) hhid->IsReportAvailable = 0U; } - return USBD_OK; + return (uint8_t)USBD_OK; } /** @@ -674,9 +720,10 @@ static uint8_t USBD_CUSTOM_HID_EP0_RxReady(USBD_HandleTypeDef *pdev) * @param length : pointer data length * @retval pointer to descriptor buffer */ -static uint8_t *USBD_CUSTOM_HID_GetDeviceQualifierDesc(uint16_t *length) +static uint8_t *USBD_CUSTOM_HID_GetDeviceQualifierDesc(uint16_t *length) { - *length = sizeof(USBD_CUSTOM_HID_DeviceQualifierDesc); + *length = (uint16_t)sizeof(USBD_CUSTOM_HID_DeviceQualifierDesc); + return USBD_CUSTOM_HID_DeviceQualifierDesc; } @@ -686,18 +733,17 @@ static uint8_t *USBD_CUSTOM_HID_GetDeviceQualifierDesc(uint16_t *length) * @param fops: CUSTOMHID Interface callback * @retval status */ -uint8_t USBD_CUSTOM_HID_RegisterInterface(USBD_HandleTypeDef *pdev, - USBD_CUSTOM_HID_ItfTypeDef *fops) +uint8_t USBD_CUSTOM_HID_RegisterInterface(USBD_HandleTypeDef *pdev, + USBD_CUSTOM_HID_ItfTypeDef *fops) { - uint8_t ret = USBD_FAIL; - - if (fops != NULL) + if (fops == NULL) { - pdev->pUserData = fops; - ret = USBD_OK; + return (uint8_t)USBD_FAIL; } - return ret; + pdev->pUserData = fops; + + return (uint8_t)USBD_OK; } /** * @} diff --git a/system/Middlewares/ST/STM32_USB_Device_Library/Class/CustomHID/Src/usbd_customhid_if_template.c b/system/Middlewares/ST/STM32_USB_Device_Library/Class/CustomHID/Src/usbd_customhid_if_template.c index 9f1fbf2e66..1fb6edd16d 100644 --- a/system/Middlewares/ST/STM32_USB_Device_Library/Class/CustomHID/Src/usbd_customhid_if_template.c +++ b/system/Middlewares/ST/STM32_USB_Device_Library/Class/CustomHID/Src/usbd_customhid_if_template.c @@ -53,7 +53,6 @@ USBD_CUSTOM_HID_ItfTypeDef USBD_CustomHID_template_fops = */ static int8_t TEMPLATE_CUSTOM_HID_Init(void) { - return (0); } @@ -81,6 +80,11 @@ static int8_t TEMPLATE_CUSTOM_HID_DeInit(void) */ static int8_t TEMPLATE_CUSTOM_HID_OutEvent(uint8_t event_idx, uint8_t state) { + UNUSED(event_idx); + UNUSED(state); + + /* Start next USB packet transfer once data processing is completed */ + USBD_CUSTOM_HID_ReceivePacket(&USBD_Device); return (0); } diff --git a/system/Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Inc/usbd_dfu.h b/system/Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Inc/usbd_dfu.h index 7b4035f988..307c96d931 100644 --- a/system/Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Inc/usbd_dfu.h +++ b/system/Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Inc/usbd_dfu.h @@ -115,7 +115,7 @@ extern "C" { /* Other defines */ /**************************************************/ /* Bit Detach capable = bit 3 in bmAttributes field */ -#define DFU_DETACH_MASK (uint8_t)(1 << 4) +#define DFU_DETACH_MASK (1U << 4) #define DFU_STATUS_DEPTH 6U typedef enum @@ -133,7 +133,7 @@ typedef void (*pFunction)(void); /********** Descriptor of DFU interface 0 Alternate setting n ****************/ -#define USBD_DFU_IF_DESC(n) 0x09, /* bLength: Interface Descriptor size */ \ +#define USBD_DFU_IF_DESC(n) 0x09, /* bLength: Interface Descriptor size */ \ USB_DESC_TYPE_INTERFACE, /* bDescriptorType */ \ 0x00, /* bInterfaceNumber: Number of Interface */ \ (n), /* bAlternateSetting: Alternate setting */ \ @@ -162,20 +162,19 @@ typedef struct union { uint32_t d32[USBD_DFU_XFER_SIZE / 4U]; - uint8_t d8[USBD_DFU_XFER_SIZE]; + uint8_t d8[USBD_DFU_XFER_SIZE]; } buffer; - uint32_t wblock_num; - uint32_t wlength; - uint32_t data_ptr; - uint32_t alt_setting; + uint32_t wblock_num; + uint32_t wlength; + uint32_t data_ptr; + uint32_t alt_setting; - uint8_t dev_status[DFU_STATUS_DEPTH]; - uint8_t ReservedForAlign[2]; - uint8_t dev_state; - uint8_t manif_state; -} -USBD_DFU_HandleTypeDef; + uint8_t dev_status[DFU_STATUS_DEPTH]; + uint8_t ReservedForAlign[2]; + uint8_t dev_state; + uint8_t manif_state; +} USBD_DFU_HandleTypeDef; typedef struct { @@ -186,8 +185,7 @@ typedef struct uint16_t (* Write)(uint8_t *src, uint8_t *dest, uint32_t Len); uint8_t *(* Read)(uint8_t *src, uint8_t *dest, uint32_t Len); uint16_t (* GetStatus)(uint32_t Add, uint8_t cmd, uint8_t *buff); -} -USBD_DFU_MediaTypeDef; +} USBD_DFU_MediaTypeDef; /** * @} */ @@ -206,8 +204,8 @@ USBD_DFU_MediaTypeDef; * @{ */ -extern USBD_ClassTypeDef USBD_DFU; -#define USBD_DFU_CLASS &USBD_DFU +extern USBD_ClassTypeDef USBD_DFU; +#define USBD_DFU_CLASS &USBD_DFU /** * @} */ @@ -215,8 +213,8 @@ extern USBD_ClassTypeDef USBD_DFU; /** @defgroup USB_CORE_Exported_Functions * @{ */ -uint8_t USBD_DFU_RegisterMedia(USBD_HandleTypeDef *pdev, - USBD_DFU_MediaTypeDef *fops); +uint8_t USBD_DFU_RegisterMedia(USBD_HandleTypeDef *pdev, + USBD_DFU_MediaTypeDef *fops); /** * @} */ diff --git a/system/Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c b/system/Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c index dc85d61760..d179650b1a 100644 --- a/system/Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c +++ b/system/Middlewares/ST/STM32_USB_Device_Library/Class/DFU/Src/usbd_dfu.c @@ -93,61 +93,34 @@ EndBSPDependencies */ */ - - /** @defgroup USBD_DFU_Private_FunctionPrototypes * @{ */ +static uint8_t USBD_DFU_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx); +static uint8_t USBD_DFU_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx); +static uint8_t USBD_DFU_Setup(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); +static uint8_t USBD_DFU_EP0_RxReady(USBD_HandleTypeDef *pdev); +static uint8_t USBD_DFU_EP0_TxReady(USBD_HandleTypeDef *pdev); +static uint8_t USBD_DFU_SOF(USBD_HandleTypeDef *pdev); -static uint8_t USBD_DFU_Init(USBD_HandleTypeDef *pdev, - uint8_t cfgidx); - -static uint8_t USBD_DFU_DeInit(USBD_HandleTypeDef *pdev, - uint8_t cfgidx); - -static uint8_t USBD_DFU_Setup(USBD_HandleTypeDef *pdev, - USBD_SetupReqTypedef *req); - -static uint8_t *USBD_DFU_GetCfgDesc(uint16_t *length); - -static uint8_t *USBD_DFU_GetDeviceQualifierDesc(uint16_t *length); - -static uint8_t USBD_DFU_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum); - -static uint8_t USBD_DFU_DataOut(USBD_HandleTypeDef *pdev, uint8_t epnum); - -static uint8_t USBD_DFU_EP0_RxReady(USBD_HandleTypeDef *pdev); - -static uint8_t USBD_DFU_EP0_TxReady(USBD_HandleTypeDef *pdev); - -static uint8_t USBD_DFU_SOF(USBD_HandleTypeDef *pdev); - -static uint8_t USBD_DFU_IsoINIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum); - -static uint8_t USBD_DFU_IsoOutIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum); +static uint8_t *USBD_DFU_GetCfgDesc(uint16_t *length); +static uint8_t *USBD_DFU_GetDeviceQualifierDesc(uint16_t *length); #if (USBD_SUPPORT_USER_STRING_DESC == 1U) -static uint8_t *USBD_DFU_GetUsrStringDesc(USBD_HandleTypeDef *pdev, uint8_t index, uint16_t *length); +static uint8_t *USBD_DFU_GetUsrStringDesc(USBD_HandleTypeDef *pdev, + uint8_t index, uint16_t *length); #endif static void DFU_Detach(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); - static void DFU_Download(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); - static void DFU_Upload(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); - static void DFU_GetStatus(USBD_HandleTypeDef *pdev); - static void DFU_ClearStatus(USBD_HandleTypeDef *pdev); - static void DFU_GetState(USBD_HandleTypeDef *pdev); - static void DFU_Abort(USBD_HandleTypeDef *pdev); - static void DFU_Leave(USBD_HandleTypeDef *pdev); - /** * @} */ @@ -156,18 +129,18 @@ static void DFU_Leave(USBD_HandleTypeDef *pdev); * @{ */ -USBD_ClassTypeDef USBD_DFU = +USBD_ClassTypeDef USBD_DFU = { USBD_DFU_Init, USBD_DFU_DeInit, USBD_DFU_Setup, USBD_DFU_EP0_TxReady, USBD_DFU_EP0_RxReady, - USBD_DFU_DataIn, - USBD_DFU_DataOut, + NULL, + NULL, USBD_DFU_SOF, - USBD_DFU_IsoINIncomplete, - USBD_DFU_IsoOutIncomplete, + NULL, + NULL, USBD_DFU_GetCfgDesc, USBD_DFU_GetCfgDesc, USBD_DFU_GetCfgDesc, @@ -180,20 +153,20 @@ USBD_ClassTypeDef USBD_DFU = /* USB DFU device Configuration Descriptor */ __ALIGN_BEGIN static uint8_t USBD_DFU_CfgDesc[USB_DFU_CONFIG_DESC_SIZ] __ALIGN_END = { - 0x09, /* bLength: Configuation Descriptor size */ - USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */ + 0x09, /* bLength: Configuation Descriptor size */ + USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */ USB_DFU_CONFIG_DESC_SIZ, - /* wTotalLength: Bytes returned */ + /* wTotalLength: Bytes returned */ 0x00, - 0x01, /*bNumInterfaces: 1 interface*/ - 0x01, /*bConfigurationValue: Configuration value*/ - 0x02, /*iConfiguration: Index of string descriptor describing the configuration*/ - 0xC0, /*bmAttributes: bus powered and Supprts Remote Wakeup */ - 0x32, /*MaxPower 100 mA: this current is used for detecting Vbus*/ + 0x01, /* bNumInterfaces: 1 interface */ + 0x01, /* bConfigurationValue: Configuration value */ + 0x02, /* iConfiguration: Index of string descriptor describing the configuration */ + 0xC0, /* bmAttributes: bus powered and Supprts Remote Wakeup */ + 0x32, /* MaxPower 100 mA: this current is used for detecting Vbus */ /* 09 */ /********** Descriptor of DFU interface 0 Alternate setting 0 **************/ - USBD_DFU_IF_DESC(0U), /* This interface is mandatory for all devices */ + USBD_DFU_IF_DESC(0U), /* This interface is mandatory for all devices */ #if (USBD_DFU_MAX_ITF_NUM > 1U) /********** Descriptor of DFU interface 0 Alternate setting 1 **************/ @@ -225,21 +198,21 @@ __ALIGN_BEGIN static uint8_t USBD_DFU_CfgDesc[USB_DFU_CONFIG_DESC_SIZ] __ALIGN_E #endif /* (USBD_DFU_MAX_ITF_NUM > 6) */ /******************** DFU Functional Descriptor********************/ - 0x09, /*blength = 9 Bytes*/ - DFU_DESCRIPTOR_TYPE, /* DFU Functional Descriptor*/ - 0x0B, /*bmAttribute - bitCanDnload = 1 (bit 0) - bitCanUpload = 1 (bit 1) - bitManifestationTolerant = 0 (bit 2) - bitWillDetach = 1 (bit 3) - Reserved (bit4-6) - bitAcceleratedST = 0 (bit 7)*/ - 0xFF, /*DetachTimeOut= 255 ms*/ + 0x09, /* blength = 9 Bytes */ + DFU_DESCRIPTOR_TYPE, /* DFU Functional Descriptor */ + 0x0B, /* bmAttribute: + bitCanDnload = 1 (bit 0) + bitCanUpload = 1 (bit 1) + bitManifestationTolerant = 0 (bit 2) + bitWillDetach = 1 (bit 3) + Reserved (bit4-6) + bitAcceleratedST = 0 (bit 7) */ + 0xFF, /* DetachTimeOut= 255 ms*/ 0x00, - /*WARNING: In DMA mode the multiple MPS packets feature is still not supported + /* WARNING: In DMA mode the multiple MPS packets feature is still not supported ==> In this case, when using DMA USBD_DFU_XFER_SIZE should be set to 64 in usbd_conf.h */ - TRANSFER_SIZE_BYTES(USBD_DFU_XFER_SIZE), /* TransferSize = 1024 Byte*/ - 0x1A, /* bcdDFUVersion*/ + TRANSFER_SIZE_BYTES(USBD_DFU_XFER_SIZE), /* TransferSize = 1024 Byte */ + 0x1A, /* bcdDFUVersion */ 0x01 /***********************************************************/ /* 9*/ @@ -275,44 +248,45 @@ __ALIGN_BEGIN static uint8_t USBD_DFU_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_ * @param cfgidx: Configuration index * @retval status */ -static uint8_t USBD_DFU_Init(USBD_HandleTypeDef *pdev, - uint8_t cfgidx) +static uint8_t USBD_DFU_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { - USBD_DFU_HandleTypeDef *hdfu; + UNUSED(cfgidx); + + USBD_DFU_HandleTypeDef *hdfu; /* Allocate Audio structure */ - pdev->pClassData = USBD_malloc(sizeof(USBD_DFU_HandleTypeDef)); + hdfu = USBD_malloc(sizeof(USBD_DFU_HandleTypeDef)); - if (pdev->pClassData == NULL) + if (hdfu == NULL) { - return USBD_FAIL; + pdev->pClassData = NULL; + return (uint8_t)USBD_EMEM; } - else - { - hdfu = (USBD_DFU_HandleTypeDef *) pdev->pClassData; - hdfu->alt_setting = 0U; - hdfu->data_ptr = USBD_DFU_APP_DEFAULT_ADD; - hdfu->wblock_num = 0U; - hdfu->wlength = 0U; + pdev->pClassData = (void *)hdfu; - hdfu->manif_state = DFU_MANIFEST_COMPLETE; - hdfu->dev_state = DFU_STATE_IDLE; + hdfu->alt_setting = 0U; + hdfu->data_ptr = USBD_DFU_APP_DEFAULT_ADD; + hdfu->wblock_num = 0U; + hdfu->wlength = 0U; - hdfu->dev_status[0] = DFU_ERROR_NONE; - hdfu->dev_status[1] = 0U; - hdfu->dev_status[2] = 0U; - hdfu->dev_status[3] = 0U; - hdfu->dev_status[4] = DFU_STATE_IDLE; - hdfu->dev_status[5] = 0U; + hdfu->manif_state = DFU_MANIFEST_COMPLETE; + hdfu->dev_state = DFU_STATE_IDLE; - /* Initialize Hardware layer */ - if (((USBD_DFU_MediaTypeDef *)pdev->pUserData)->Init() != USBD_OK) - { - return USBD_FAIL; - } + hdfu->dev_status[0] = DFU_ERROR_NONE; + hdfu->dev_status[1] = 0U; + hdfu->dev_status[2] = 0U; + hdfu->dev_status[3] = 0U; + hdfu->dev_status[4] = DFU_STATE_IDLE; + hdfu->dev_status[5] = 0U; + + /* Initialize Hardware layer */ + if (((USBD_DFU_MediaTypeDef *)pdev->pUserData)->Init() != USBD_OK) + { + return (uint8_t)USBD_FAIL; } - return USBD_OK; + + return (uint8_t)USBD_OK; } /** @@ -322,12 +296,17 @@ static uint8_t USBD_DFU_Init(USBD_HandleTypeDef *pdev, * @param cfgidx: Configuration index * @retval status */ -static uint8_t USBD_DFU_DeInit(USBD_HandleTypeDef *pdev, - uint8_t cfgidx) +static uint8_t USBD_DFU_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { - USBD_DFU_HandleTypeDef *hdfu; - hdfu = (USBD_DFU_HandleTypeDef *) pdev->pClassData; + UNUSED(cfgidx); + USBD_DFU_HandleTypeDef *hdfu; + if (pdev->pClassData == NULL) + { + return (uint8_t)USBD_EMEM; + } + + hdfu = (USBD_DFU_HandleTypeDef *)pdev->pClassData; hdfu->wblock_num = 0U; hdfu->wlength = 0U; @@ -335,16 +314,12 @@ static uint8_t USBD_DFU_DeInit(USBD_HandleTypeDef *pdev, hdfu->dev_status[0] = DFU_ERROR_NONE; hdfu->dev_status[4] = DFU_STATE_IDLE; - /* DeInit physical Interface components */ - if (pdev->pClassData != NULL) - { - /* De-Initialize Hardware layer */ - ((USBD_DFU_MediaTypeDef *)pdev->pUserData)->DeInit(); - USBD_free(pdev->pClassData); - pdev->pClassData = NULL; - } + /* DeInit physical Interface components and Hardware Layer */ + ((USBD_DFU_MediaTypeDef *)pdev->pUserData)->DeInit(); + USBD_free(pdev->pClassData); + pdev->pClassData = NULL; - return USBD_OK; + return (uint8_t)USBD_OK; } /** @@ -354,129 +329,129 @@ static uint8_t USBD_DFU_DeInit(USBD_HandleTypeDef *pdev, * @param req: usb requests * @retval status */ -static uint8_t USBD_DFU_Setup(USBD_HandleTypeDef *pdev, - USBD_SetupReqTypedef *req) +static uint8_t USBD_DFU_Setup(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { - USBD_DFU_HandleTypeDef *hdfu; - uint8_t *pbuf = 0U; + USBD_DFU_HandleTypeDef *hdfu = (USBD_DFU_HandleTypeDef *)pdev->pClassData; + USBD_StatusTypeDef ret = USBD_OK; + uint8_t *pbuf = NULL; uint16_t len = 0U; uint16_t status_info = 0U; - uint8_t ret = USBD_OK; - - hdfu = (USBD_DFU_HandleTypeDef *) pdev->pClassData; switch (req->bmRequest & USB_REQ_TYPE_MASK) { - case USB_REQ_TYPE_CLASS: - switch (req->bRequest) - { - case DFU_DNLOAD: - DFU_Download(pdev, req); - break; + case USB_REQ_TYPE_CLASS: + switch (req->bRequest) + { + case DFU_DNLOAD: + DFU_Download(pdev, req); + break; + + case DFU_UPLOAD: + DFU_Upload(pdev, req); + break; - case DFU_UPLOAD: - DFU_Upload(pdev, req); - break; + case DFU_GETSTATUS: + DFU_GetStatus(pdev); + break; - case DFU_GETSTATUS: - DFU_GetStatus(pdev); - break; + case DFU_CLRSTATUS: + DFU_ClearStatus(pdev); + break; - case DFU_CLRSTATUS: - DFU_ClearStatus(pdev); - break; + case DFU_GETSTATE: + DFU_GetState(pdev); + break; - case DFU_GETSTATE: - DFU_GetState(pdev); - break; + case DFU_ABORT: + DFU_Abort(pdev); + break; - case DFU_ABORT: - DFU_Abort(pdev); - break; + case DFU_DETACH: + DFU_Detach(pdev, req); + break; - case DFU_DETACH: - DFU_Detach(pdev, req); - break; + default: + USBD_CtlError(pdev, req); + ret = USBD_FAIL; + break; + } + break; - default: - USBD_CtlError(pdev, req); - ret = USBD_FAIL; - break; + case USB_REQ_TYPE_STANDARD: + switch (req->bRequest) + { + case USB_REQ_GET_STATUS: + if (pdev->dev_state == USBD_STATE_CONFIGURED) + { + (void)USBD_CtlSendData(pdev, (uint8_t *)&status_info, 2U); + } + else + { + USBD_CtlError(pdev, req); + ret = USBD_FAIL; } break; - case USB_REQ_TYPE_STANDARD: - switch (req->bRequest) + case USB_REQ_GET_DESCRIPTOR: + if ((req->wValue >> 8) == DFU_DESCRIPTOR_TYPE) { - case USB_REQ_GET_STATUS: - if (pdev->dev_state == USBD_STATE_CONFIGURED) - { - USBD_CtlSendData(pdev, (uint8_t *)(void *)&status_info, 2U); - } - else - { - USBD_CtlError(pdev, req); - ret = USBD_FAIL; - } - break; - - case USB_REQ_GET_DESCRIPTOR: - if ((req->wValue >> 8) == DFU_DESCRIPTOR_TYPE) - { - pbuf = USBD_DFU_CfgDesc + (9U * (USBD_DFU_MAX_ITF_NUM + 1U)); - len = MIN(USB_DFU_DESC_SIZ, req->wLength); - } - - USBD_CtlSendData(pdev, pbuf, len); - break; + pbuf = USBD_DFU_CfgDesc + (9U * (USBD_DFU_MAX_ITF_NUM + 1U)); + len = MIN(USB_DFU_DESC_SIZ, req->wLength); + } - case USB_REQ_GET_INTERFACE: - if (pdev->dev_state == USBD_STATE_CONFIGURED) - { - USBD_CtlSendData(pdev, (uint8_t *)(void *)&hdfu->alt_setting, 1U); - } - else - { - USBD_CtlError(pdev, req); - ret = USBD_FAIL; - } - break; + (void)USBD_CtlSendData(pdev, pbuf, len); + break; - case USB_REQ_SET_INTERFACE: - if ((uint8_t)(req->wValue) < USBD_DFU_MAX_ITF_NUM) - { - if (pdev->dev_state == USBD_STATE_CONFIGURED) - { - hdfu->alt_setting = (uint8_t)(req->wValue); - } - else - { - USBD_CtlError(pdev, req); - ret = USBD_FAIL; - } - } - else - { - /* Call the error management function (command will be nacked */ - USBD_CtlError(pdev, req); - ret = USBD_FAIL; - } - break; + case USB_REQ_GET_INTERFACE: + if (pdev->dev_state == USBD_STATE_CONFIGURED) + { + (void)USBD_CtlSendData(pdev, (uint8_t *)hdfu->alt_setting, 1U); + } + else + { + USBD_CtlError(pdev, req); + ret = USBD_FAIL; + } + break; - default: + case USB_REQ_SET_INTERFACE: + if ((uint8_t)(req->wValue) < USBD_DFU_MAX_ITF_NUM) + { + if (pdev->dev_state == USBD_STATE_CONFIGURED) + { + hdfu->alt_setting = (uint8_t)(req->wValue); + } + else + { USBD_CtlError(pdev, req); ret = USBD_FAIL; - break; + } + } + else + { + /* Call the error management function (command will be nacked */ + USBD_CtlError(pdev, req); + ret = USBD_FAIL; } break; + case USB_REQ_CLEAR_FEATURE: + break; + default: USBD_CtlError(pdev, req); ret = USBD_FAIL; break; + } + break; + + default: + USBD_CtlError(pdev, req); + ret = USBD_FAIL; + break; } - return ret; + return (uint8_t)ret; } @@ -487,25 +462,13 @@ static uint8_t USBD_DFU_Setup(USBD_HandleTypeDef *pdev, * @param length : pointer data length * @retval pointer to descriptor buffer */ -static uint8_t *USBD_DFU_GetCfgDesc(uint16_t *length) +static uint8_t *USBD_DFU_GetCfgDesc(uint16_t *length) { - *length = sizeof(USBD_DFU_CfgDesc); + *length = (uint16_t)sizeof(USBD_DFU_CfgDesc); + return USBD_DFU_CfgDesc; } -/** - * @brief USBD_DFU_DataIn - * handle data IN Stage - * @param pdev: device instance - * @param epnum: endpoint index - * @retval status - */ -static uint8_t USBD_DFU_DataIn(USBD_HandleTypeDef *pdev, - uint8_t epnum) -{ - - return USBD_OK; -} /** * @brief USBD_DFU_EP0_RxReady @@ -513,10 +476,11 @@ static uint8_t USBD_DFU_DataIn(USBD_HandleTypeDef *pdev, * @param pdev: device instance * @retval status */ -static uint8_t USBD_DFU_EP0_RxReady(USBD_HandleTypeDef *pdev) +static uint8_t USBD_DFU_EP0_RxReady(USBD_HandleTypeDef *pdev) { + UNUSED(pdev); - return USBD_OK; + return (uint8_t)USBD_OK; } /** * @brief USBD_DFU_EP0_TxReady @@ -526,38 +490,47 @@ static uint8_t USBD_DFU_EP0_RxReady(USBD_HandleTypeDef *pdev) */ static uint8_t USBD_DFU_EP0_TxReady(USBD_HandleTypeDef *pdev) { + USBD_SetupReqTypedef req; uint32_t addr; - USBD_SetupReqTypedef req; - USBD_DFU_HandleTypeDef *hdfu; - - hdfu = (USBD_DFU_HandleTypeDef *) pdev->pClassData; + USBD_DFU_HandleTypeDef *hdfu = (USBD_DFU_HandleTypeDef *)pdev->pClassData; + USBD_DFU_MediaTypeDef *DfuInterface = (USBD_DFU_MediaTypeDef *)pdev->pUserData; if (hdfu->dev_state == DFU_STATE_DNLOAD_BUSY) { /* Decode the Special Command*/ if (hdfu->wblock_num == 0U) { - if ((hdfu->buffer.d8[0] == DFU_CMD_GETCOMMANDS) && (hdfu->wlength == 1U)) + if(hdfu->wlength == 1U) { - - } - else if ((hdfu->buffer.d8[0] == DFU_CMD_SETADDRESSPOINTER) && (hdfu->wlength == 5U)) - { - hdfu->data_ptr = hdfu->buffer.d8[1]; - hdfu->data_ptr += (uint32_t)hdfu->buffer.d8[2] << 8; - hdfu->data_ptr += (uint32_t)hdfu->buffer.d8[3] << 16; - hdfu->data_ptr += (uint32_t)hdfu->buffer.d8[4] << 24; + if (hdfu->buffer.d8[0] == DFU_CMD_GETCOMMANDS) + { + /* nothink to do */ + } } - else if ((hdfu->buffer.d8[0] == DFU_CMD_ERASE) && (hdfu->wlength == 5U)) + else if (hdfu->wlength == 5U) { - hdfu->data_ptr = hdfu->buffer.d8[1]; - hdfu->data_ptr += (uint32_t)hdfu->buffer.d8[2] << 8; - hdfu->data_ptr += (uint32_t)hdfu->buffer.d8[3] << 16; - hdfu->data_ptr += (uint32_t)hdfu->buffer.d8[4] << 24; + if (hdfu->buffer.d8[0] == DFU_CMD_SETADDRESSPOINTER) + { + hdfu->data_ptr = hdfu->buffer.d8[1]; + hdfu->data_ptr += (uint32_t)hdfu->buffer.d8[2] << 8; + hdfu->data_ptr += (uint32_t)hdfu->buffer.d8[3] << 16; + hdfu->data_ptr += (uint32_t)hdfu->buffer.d8[4] << 24; + } + else if (hdfu->buffer.d8[0] == DFU_CMD_ERASE) + { + hdfu->data_ptr = hdfu->buffer.d8[1]; + hdfu->data_ptr += (uint32_t)hdfu->buffer.d8[2] << 8; + hdfu->data_ptr += (uint32_t)hdfu->buffer.d8[3] << 16; + hdfu->data_ptr += (uint32_t)hdfu->buffer.d8[4] << 24; - if (((USBD_DFU_MediaTypeDef *)pdev->pUserData)->Erase(hdfu->data_ptr) != USBD_OK) + if (DfuInterface->Erase(hdfu->data_ptr) != USBD_OK) + { + return (uint8_t)USBD_FAIL; + } + } + else { - return USBD_FAIL; + /* .. */ } } else @@ -580,10 +553,9 @@ static uint8_t USBD_DFU_EP0_TxReady(USBD_HandleTypeDef *pdev) addr = ((hdfu->wblock_num - 2U) * USBD_DFU_XFER_SIZE) + hdfu->data_ptr; /* Preform the write operation */ - if (((USBD_DFU_MediaTypeDef *)pdev->pUserData)->Write(hdfu->buffer.d8, - (uint8_t *)addr, hdfu->wlength) != USBD_OK) + if (DfuInterface->Write(hdfu->buffer.d8, (uint8_t *)addr, hdfu->wlength) != USBD_OK) { - return USBD_FAIL; + return (uint8_t)USBD_FAIL; } } } @@ -599,18 +571,18 @@ static uint8_t USBD_DFU_EP0_TxReady(USBD_HandleTypeDef *pdev) hdfu->dev_status[2] = 0U; hdfu->dev_status[3] = 0U; hdfu->dev_status[4] = hdfu->dev_state; - return USBD_OK; + } + else if (hdfu->dev_state == DFU_STATE_MANIFEST)/* Manifestation in progress */ + { + /* Start leaving DFU mode */ + DFU_Leave(pdev); } else { - if (hdfu->dev_state == DFU_STATE_MANIFEST)/* Manifestation in progress */ - { - /* Start leaving DFU mode */ - DFU_Leave(pdev); - } + /* .. */ } - return USBD_OK; + return (uint8_t)USBD_OK; } /** * @brief USBD_DFU_SOF @@ -618,48 +590,13 @@ static uint8_t USBD_DFU_EP0_TxReady(USBD_HandleTypeDef *pdev) * @param pdev: device instance * @retval status */ -static uint8_t USBD_DFU_SOF(USBD_HandleTypeDef *pdev) +static uint8_t USBD_DFU_SOF(USBD_HandleTypeDef *pdev) { + UNUSED(pdev); - return USBD_OK; + return (uint8_t)USBD_OK; } -/** - * @brief USBD_DFU_IsoINIncomplete - * handle data ISO IN Incomplete event - * @param pdev: device instance - * @param epnum: endpoint index - * @retval status - */ -static uint8_t USBD_DFU_IsoINIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum) -{ - - return USBD_OK; -} -/** - * @brief USBD_DFU_IsoOutIncomplete - * handle data ISO OUT Incomplete event - * @param pdev: device instance - * @param epnum: endpoint index - * @retval status - */ -static uint8_t USBD_DFU_IsoOutIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum) -{ - - return USBD_OK; -} -/** - * @brief USBD_DFU_DataOut - * handle data OUT Stage - * @param pdev: device instance - * @param epnum: endpoint index - * @retval status - */ -static uint8_t USBD_DFU_DataOut(USBD_HandleTypeDef *pdev, - uint8_t epnum) -{ - return USBD_OK; -} /** * @brief DeviceQualifierDescriptor @@ -667,9 +604,10 @@ static uint8_t USBD_DFU_DataOut(USBD_HandleTypeDef *pdev, * @param length : pointer data length * @retval pointer to descriptor buffer */ -static uint8_t *USBD_DFU_GetDeviceQualifierDesc(uint16_t *length) +static uint8_t *USBD_DFU_GetDeviceQualifierDesc(uint16_t *length) { - *length = sizeof(USBD_DFU_DeviceQualifierDesc); + *length = (uint16_t)sizeof(USBD_DFU_DeviceQualifierDesc); + return USBD_DFU_DeviceQualifierDesc; } @@ -685,15 +623,17 @@ static uint8_t *USBD_DFU_GetDeviceQualifierDesc(uint16_t *length) static uint8_t *USBD_DFU_GetUsrStringDesc(USBD_HandleTypeDef *pdev, uint8_t index, uint16_t *length) { static uint8_t USBD_StrDesc[255]; + USBD_DFU_MediaTypeDef *DfuInterface = (USBD_DFU_MediaTypeDef *)pdev->pUserData; + /* Check if the requested string interface is supported */ if (index <= (USBD_IDX_INTERFACE_STR + USBD_DFU_MAX_ITF_NUM)) { - USBD_GetString((uint8_t *)((USBD_DFU_MediaTypeDef *)pdev->pUserData)->pStrDesc, USBD_StrDesc, length); + USBD_GetString((uint8_t *)DfuInterface->pStrDesc, USBD_StrDesc, length); return USBD_StrDesc; } - /* Not supported Interface Descriptor index */ else { + /* Not supported Interface Descriptor index */ return NULL; } } @@ -704,14 +644,17 @@ static uint8_t *USBD_DFU_GetUsrStringDesc(USBD_HandleTypeDef *pdev, uint8_t inde * @param fops: storage callback * @retval status */ -uint8_t USBD_DFU_RegisterMedia(USBD_HandleTypeDef *pdev, - USBD_DFU_MediaTypeDef *fops) +uint8_t USBD_DFU_RegisterMedia(USBD_HandleTypeDef *pdev, + USBD_DFU_MediaTypeDef *fops) { - if (fops != NULL) + if (fops == NULL) { - pdev->pUserData = fops; + return (uint8_t)USBD_FAIL; } - return 0U; + + pdev->pUserData = fops; + + return (uint8_t)USBD_OK; } /****************************************************************************** @@ -726,13 +669,13 @@ uint8_t USBD_DFU_RegisterMedia(USBD_HandleTypeDef *pdev, */ static void DFU_Detach(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { - USBD_DFU_HandleTypeDef *hdfu; + USBD_DFU_HandleTypeDef *hdfu = (USBD_DFU_HandleTypeDef *)pdev->pClassData; - hdfu = (USBD_DFU_HandleTypeDef *) pdev->pClassData; - - if (hdfu->dev_state == DFU_STATE_IDLE || hdfu->dev_state == DFU_STATE_DNLOAD_SYNC - || hdfu->dev_state == DFU_STATE_DNLOAD_IDLE || hdfu->dev_state == DFU_STATE_MANIFEST_SYNC - || hdfu->dev_state == DFU_STATE_UPLOAD_IDLE) + if ((hdfu->dev_state == DFU_STATE_IDLE) || + (hdfu->dev_state == DFU_STATE_DNLOAD_SYNC) || + (hdfu->dev_state == DFU_STATE_DNLOAD_IDLE) || + (hdfu->dev_state == DFU_STATE_MANIFEST_SYNC) || + (hdfu->dev_state == DFU_STATE_UPLOAD_IDLE)) { /* Update the state machine */ hdfu->dev_state = DFU_STATE_IDLE; @@ -747,11 +690,11 @@ static void DFU_Detach(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) } /* Check the detach capability in the DFU functional descriptor */ - if ((USBD_DFU_CfgDesc[12U + (9U * USBD_DFU_MAX_ITF_NUM)]) & DFU_DETACH_MASK) + if (((USBD_DFU_CfgDesc[12U + (9U * USBD_DFU_MAX_ITF_NUM)]) & DFU_DETACH_MASK) != 0U) { /* Perform an Attach-Detach operation on USB bus */ - USBD_Stop(pdev); - USBD_Start(pdev); + (void)USBD_Stop(pdev); + (void)USBD_Start(pdev); } else { @@ -769,9 +712,7 @@ static void DFU_Detach(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) */ static void DFU_Download(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { - USBD_DFU_HandleTypeDef *hdfu; - - hdfu = (USBD_DFU_HandleTypeDef *) pdev->pClassData; + USBD_DFU_HandleTypeDef *hdfu = (USBD_DFU_HandleTypeDef *)pdev->pClassData; /* Data setup request */ if (req->wLength > 0U) @@ -787,8 +728,7 @@ static void DFU_Download(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) hdfu->dev_status[4] = hdfu->dev_state; /* Prepare the reception of the buffer over EP0 */ - USBD_CtlPrepareRx(pdev, (uint8_t *)hdfu->buffer.d8, - (uint16_t)hdfu->wlength); + (void)USBD_CtlPrepareRx(pdev, (uint8_t *)hdfu->buffer.d8, hdfu->wlength); } /* Unsupported state */ else @@ -801,7 +741,7 @@ static void DFU_Download(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) else { /* End of DNLOAD operation*/ - if (hdfu->dev_state == DFU_STATE_DNLOAD_IDLE || hdfu->dev_state == DFU_STATE_IDLE) + if ((hdfu->dev_state == DFU_STATE_DNLOAD_IDLE) || (hdfu->dev_state == DFU_STATE_IDLE)) { hdfu->manif_state = DFU_MANIFEST_IN_PROGRESS; hdfu->dev_state = DFU_STATE_MANIFEST_SYNC; @@ -827,12 +767,10 @@ static void DFU_Download(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) */ static void DFU_Upload(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { - USBD_DFU_HandleTypeDef *hdfu; - - hdfu = (USBD_DFU_HandleTypeDef *) pdev->pClassData; - - uint8_t *phaddr = NULL; - uint32_t addr = 0U; + USBD_DFU_HandleTypeDef *hdfu = (USBD_DFU_HandleTypeDef *)pdev->pClassData; + USBD_DFU_MediaTypeDef *DfuInterface = (USBD_DFU_MediaTypeDef *)pdev->pUserData; + uint8_t *phaddr; + uint32_t addr; /* Data setup request */ if (req->wLength > 0U) @@ -860,7 +798,7 @@ static void DFU_Upload(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) hdfu->buffer.d8[2] = DFU_CMD_ERASE; /* Send the status data over EP0 */ - USBD_CtlSendData(pdev, (uint8_t *)(&(hdfu->buffer.d8[0])), 3U); + (void)USBD_CtlSendData(pdev, (uint8_t *)(&(hdfu->buffer.d8[0])), 3U); } else if (hdfu->wblock_num > 1U) { @@ -871,13 +809,13 @@ static void DFU_Upload(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) hdfu->dev_status[3] = 0U; hdfu->dev_status[4] = hdfu->dev_state; - addr = ((hdfu->wblock_num - 2U) * USBD_DFU_XFER_SIZE) + hdfu->data_ptr; /* Change is Accelerated*/ + addr = ((hdfu->wblock_num - 2U) * USBD_DFU_XFER_SIZE) + hdfu->data_ptr; /* Return the physical address where data are stored */ - phaddr = ((USBD_DFU_MediaTypeDef *)pdev->pUserData)->Read((uint8_t *)addr, hdfu->buffer.d8, hdfu->wlength); + phaddr = DfuInterface->Read((uint8_t *)addr, hdfu->buffer.d8, hdfu->wlength); /* Send the status data over EP0 */ - USBD_CtlSendData(pdev, phaddr, (uint16_t)hdfu->wlength); + (void)USBD_CtlSendData(pdev, phaddr, hdfu->wlength); } else /* unsupported hdfu->wblock_num */ { @@ -897,6 +835,7 @@ static void DFU_Upload(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { hdfu->wlength = 0U; hdfu->wblock_num = 0U; + /* Call the error management function (command will be nacked */ USBD_CtlError(pdev, req); } @@ -921,73 +860,72 @@ static void DFU_Upload(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) */ static void DFU_GetStatus(USBD_HandleTypeDef *pdev) { - USBD_DFU_HandleTypeDef *hdfu; - - hdfu = (USBD_DFU_HandleTypeDef *) pdev->pClassData; + USBD_DFU_HandleTypeDef *hdfu = (USBD_DFU_HandleTypeDef *)pdev->pClassData; + USBD_DFU_MediaTypeDef *DfuInterface = (USBD_DFU_MediaTypeDef *)pdev->pUserData; switch (hdfu->dev_state) { - case DFU_STATE_DNLOAD_SYNC: - if (hdfu->wlength != 0U) - { - hdfu->dev_state = DFU_STATE_DNLOAD_BUSY; + case DFU_STATE_DNLOAD_SYNC: + if (hdfu->wlength != 0U) + { + hdfu->dev_state = DFU_STATE_DNLOAD_BUSY; - hdfu->dev_status[1] = 0U; - hdfu->dev_status[2] = 0U; - hdfu->dev_status[3] = 0U; - hdfu->dev_status[4] = hdfu->dev_state; + hdfu->dev_status[1] = 0U; + hdfu->dev_status[2] = 0U; + hdfu->dev_status[3] = 0U; + hdfu->dev_status[4] = hdfu->dev_state; - if ((hdfu->wblock_num == 0U) && (hdfu->buffer.d8[0] == DFU_CMD_ERASE)) - { - ((USBD_DFU_MediaTypeDef *)pdev->pUserData)->GetStatus(hdfu->data_ptr, DFU_MEDIA_ERASE, hdfu->dev_status); - } - else - { - ((USBD_DFU_MediaTypeDef *)pdev->pUserData)->GetStatus(hdfu->data_ptr, DFU_MEDIA_PROGRAM, hdfu->dev_status); - } + if ((hdfu->wblock_num == 0U) && (hdfu->buffer.d8[0] == DFU_CMD_ERASE)) + { + DfuInterface->GetStatus(hdfu->data_ptr, DFU_MEDIA_ERASE, hdfu->dev_status); } - else /* (hdfu->wlength==0)*/ + else { - hdfu->dev_state = DFU_STATE_DNLOAD_IDLE; - - hdfu->dev_status[1] = 0U; - hdfu->dev_status[2] = 0U; - hdfu->dev_status[3] = 0U; - hdfu->dev_status[4] = hdfu->dev_state; + DfuInterface->GetStatus(hdfu->data_ptr, DFU_MEDIA_PROGRAM, hdfu->dev_status); } - break; + } + else /* (hdfu->wlength==0)*/ + { + hdfu->dev_state = DFU_STATE_DNLOAD_IDLE; + + hdfu->dev_status[1] = 0U; + hdfu->dev_status[2] = 0U; + hdfu->dev_status[3] = 0U; + hdfu->dev_status[4] = hdfu->dev_state; + } + break; - case DFU_STATE_MANIFEST_SYNC : - if (hdfu->manif_state == DFU_MANIFEST_IN_PROGRESS) + case DFU_STATE_MANIFEST_SYNC: + if (hdfu->manif_state == DFU_MANIFEST_IN_PROGRESS) + { + hdfu->dev_state = DFU_STATE_MANIFEST; + + hdfu->dev_status[1] = 1U; /*bwPollTimeout = 1ms*/ + hdfu->dev_status[2] = 0U; + hdfu->dev_status[3] = 0U; + hdfu->dev_status[4] = hdfu->dev_state; + } + else + { + if ((hdfu->manif_state == DFU_MANIFEST_COMPLETE) && + (((USBD_DFU_CfgDesc[(11U + (9U * USBD_DFU_MAX_ITF_NUM))]) & 0x04U) != 0U)) { - hdfu->dev_state = DFU_STATE_MANIFEST; + hdfu->dev_state = DFU_STATE_IDLE; - hdfu->dev_status[1] = 1U; /*bwPollTimeout = 1ms*/ + hdfu->dev_status[1] = 0U; hdfu->dev_status[2] = 0U; hdfu->dev_status[3] = 0U; hdfu->dev_status[4] = hdfu->dev_state; } - else - { - if ((hdfu->manif_state == DFU_MANIFEST_COMPLETE) && - ((USBD_DFU_CfgDesc[(11U + (9U * USBD_DFU_MAX_ITF_NUM))]) & 0x04U)) - { - hdfu->dev_state = DFU_STATE_IDLE; - - hdfu->dev_status[1] = 0U; - hdfu->dev_status[2] = 0U; - hdfu->dev_status[3] = 0U; - hdfu->dev_status[4] = hdfu->dev_state; - } - } - break; + } + break; - default : - break; + default: + break; } /* Send the status data over EP0 */ - USBD_CtlSendData(pdev, (uint8_t *)(&(hdfu->dev_status[0])), 6U); + (void)USBD_CtlSendData(pdev, (uint8_t *)(&(hdfu->dev_status[0])), 6U); } /** @@ -998,30 +936,28 @@ static void DFU_GetStatus(USBD_HandleTypeDef *pdev) */ static void DFU_ClearStatus(USBD_HandleTypeDef *pdev) { - USBD_DFU_HandleTypeDef *hdfu; - - hdfu = (USBD_DFU_HandleTypeDef *) pdev->pClassData; + USBD_DFU_HandleTypeDef *hdfu = (USBD_DFU_HandleTypeDef *)pdev->pClassData; if (hdfu->dev_state == DFU_STATE_ERROR) { hdfu->dev_state = DFU_STATE_IDLE; - hdfu->dev_status[0] = DFU_ERROR_NONE;/*bStatus*/ + hdfu->dev_status[0] = DFU_ERROR_NONE; /*bStatus*/ hdfu->dev_status[1] = 0U; hdfu->dev_status[2] = 0U; hdfu->dev_status[3] = 0U; /*bwPollTimeout=0ms*/ - hdfu->dev_status[4] = hdfu->dev_state;/*bState*/ - hdfu->dev_status[5] = 0U;/*iString*/ + hdfu->dev_status[4] = hdfu->dev_state; /*bState*/ + hdfu->dev_status[5] = 0U; /*iString*/ } else { /*State Error*/ hdfu->dev_state = DFU_STATE_ERROR; - hdfu->dev_status[0] = DFU_ERROR_UNKNOWN;/*bStatus*/ + hdfu->dev_status[0] = DFU_ERROR_UNKNOWN; /*bStatus*/ hdfu->dev_status[1] = 0U; hdfu->dev_status[2] = 0U; hdfu->dev_status[3] = 0U; /*bwPollTimeout=0ms*/ - hdfu->dev_status[4] = hdfu->dev_state;/*bState*/ - hdfu->dev_status[5] = 0U;/*iString*/ + hdfu->dev_status[4] = hdfu->dev_state; /*bState*/ + hdfu->dev_status[5] = 0U; /*iString*/ } } @@ -1033,12 +969,10 @@ static void DFU_ClearStatus(USBD_HandleTypeDef *pdev) */ static void DFU_GetState(USBD_HandleTypeDef *pdev) { - USBD_DFU_HandleTypeDef *hdfu; - - hdfu = (USBD_DFU_HandleTypeDef *) pdev->pClassData; + USBD_DFU_HandleTypeDef *hdfu = (USBD_DFU_HandleTypeDef *)pdev->pClassData; /* Return the current state of the DFU interface */ - USBD_CtlSendData(pdev, &hdfu->dev_state, 1U); + (void)USBD_CtlSendData(pdev, &hdfu->dev_state, 1U); } /** @@ -1049,13 +983,14 @@ static void DFU_GetState(USBD_HandleTypeDef *pdev) */ static void DFU_Abort(USBD_HandleTypeDef *pdev) { - USBD_DFU_HandleTypeDef *hdfu; + USBD_DFU_HandleTypeDef *hdfu = (USBD_DFU_HandleTypeDef *)pdev->pClassData; - hdfu = (USBD_DFU_HandleTypeDef *) pdev->pClassData; - if (hdfu->dev_state == DFU_STATE_IDLE || hdfu->dev_state == DFU_STATE_DNLOAD_SYNC - || hdfu->dev_state == DFU_STATE_DNLOAD_IDLE || hdfu->dev_state == DFU_STATE_MANIFEST_SYNC - || hdfu->dev_state == DFU_STATE_UPLOAD_IDLE) + if ((hdfu->dev_state == DFU_STATE_IDLE) || + (hdfu->dev_state == DFU_STATE_DNLOAD_SYNC) || + (hdfu->dev_state == DFU_STATE_DNLOAD_IDLE) || + (hdfu->dev_state == DFU_STATE_MANIFEST_SYNC) || + (hdfu->dev_state == DFU_STATE_UPLOAD_IDLE)) { hdfu->dev_state = DFU_STATE_IDLE; hdfu->dev_status[0] = DFU_ERROR_NONE; @@ -1078,13 +1013,11 @@ static void DFU_Abort(USBD_HandleTypeDef *pdev) */ static void DFU_Leave(USBD_HandleTypeDef *pdev) { - USBD_DFU_HandleTypeDef *hdfu; - - hdfu = (USBD_DFU_HandleTypeDef *) pdev->pClassData; + USBD_DFU_HandleTypeDef *hdfu = (USBD_DFU_HandleTypeDef *)pdev->pClassData; hdfu->manif_state = DFU_MANIFEST_COMPLETE; - if ((USBD_DFU_CfgDesc[(11U + (9U * USBD_DFU_MAX_ITF_NUM))]) & 0x04U) + if (((USBD_DFU_CfgDesc[(11U + (9U * USBD_DFU_MAX_ITF_NUM))]) & 0x04U) != 0U) { hdfu->dev_state = DFU_STATE_MANIFEST_SYNC; @@ -1104,10 +1037,7 @@ static void DFU_Leave(USBD_HandleTypeDef *pdev) hdfu->dev_status[4] = hdfu->dev_state; /* Disconnect the USB device */ - USBD_Stop(pdev); - - /* DeInitilialize the MAL(Media Access Layer) */ - ((USBD_DFU_MediaTypeDef *)pdev->pUserData)->DeInit(); + (void)USBD_Stop(pdev); /* Generate system reset to allow jumping to the user code */ NVIC_SystemReset(); diff --git a/system/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Inc/usbd_hid.h b/system/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Inc/usbd_hid.h index 3b533c0083..40ed7291af 100644 --- a/system/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Inc/usbd_hid.h +++ b/system/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Inc/usbd_hid.h @@ -41,32 +41,32 @@ extern "C" { /** @defgroup USBD_HID_Exported_Defines * @{ */ -#define HID_EPIN_ADDR 0x81U -#define HID_EPIN_SIZE 0x04U +#define HID_EPIN_ADDR 0x81U +#define HID_EPIN_SIZE 0x04U -#define USB_HID_CONFIG_DESC_SIZ 34U -#define USB_HID_DESC_SIZ 9U -#define HID_MOUSE_REPORT_DESC_SIZE 74U +#define USB_HID_CONFIG_DESC_SIZ 34U +#define USB_HID_DESC_SIZ 9U +#define HID_MOUSE_REPORT_DESC_SIZE 74U -#define HID_DESCRIPTOR_TYPE 0x21U -#define HID_REPORT_DESC 0x22U +#define HID_DESCRIPTOR_TYPE 0x21U +#define HID_REPORT_DESC 0x22U #ifndef HID_HS_BINTERVAL -#define HID_HS_BINTERVAL 0x07U +#define HID_HS_BINTERVAL 0x07U #endif /* HID_HS_BINTERVAL */ #ifndef HID_FS_BINTERVAL -#define HID_FS_BINTERVAL 0x0AU +#define HID_FS_BINTERVAL 0x0AU #endif /* HID_FS_BINTERVAL */ -#define HID_REQ_SET_PROTOCOL 0x0BU -#define HID_REQ_GET_PROTOCOL 0x03U +#define HID_REQ_SET_PROTOCOL 0x0BU +#define HID_REQ_GET_PROTOCOL 0x03U -#define HID_REQ_SET_IDLE 0x0AU -#define HID_REQ_GET_IDLE 0x02U +#define HID_REQ_SET_IDLE 0x0AU +#define HID_REQ_GET_IDLE 0x02U -#define HID_REQ_SET_REPORT 0x09U -#define HID_REQ_GET_REPORT 0x01U +#define HID_REQ_SET_REPORT 0x09U +#define HID_REQ_GET_REPORT 0x01U /** * @} */ @@ -79,18 +79,16 @@ typedef enum { HID_IDLE = 0, HID_BUSY, -} -HID_StateTypeDef; +} HID_StateTypeDef; typedef struct { - uint32_t Protocol; - uint32_t IdleState; - uint32_t AltSetting; - HID_StateTypeDef state; -} -USBD_HID_HandleTypeDef; + uint32_t Protocol; + uint32_t IdleState; + uint32_t AltSetting; + HID_StateTypeDef state; +} USBD_HID_HandleTypeDef; /** * @} */ @@ -109,8 +107,8 @@ USBD_HID_HandleTypeDef; * @{ */ -extern USBD_ClassTypeDef USBD_HID; -#define USBD_HID_CLASS &USBD_HID +extern USBD_ClassTypeDef USBD_HID; +#define USBD_HID_CLASS &USBD_HID /** * @} */ @@ -118,10 +116,7 @@ extern USBD_ClassTypeDef USBD_HID; /** @defgroup USB_CORE_Exported_Functions * @{ */ -uint8_t USBD_HID_SendReport(USBD_HandleTypeDef *pdev, - uint8_t *report, - uint16_t len); - +uint8_t USBD_HID_SendReport(USBD_HandleTypeDef *pdev, uint8_t *report,uint16_t len); uint32_t USBD_HID_GetPollingInterval(USBD_HandleTypeDef *pdev); /** diff --git a/system/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c b/system/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c index d9b4223513..c73dacebe9 100644 --- a/system/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c +++ b/system/Middlewares/ST/STM32_USB_Device_Library/Class/HID/Src/usbd_hid.c @@ -83,31 +83,20 @@ EndBSPDependencies */ */ - - /** @defgroup USBD_HID_Private_FunctionPrototypes * @{ */ +static uint8_t USBD_HID_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx); +static uint8_t USBD_HID_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx); +static uint8_t USBD_HID_Setup(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); +static uint8_t USBD_HID_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum); -static uint8_t USBD_HID_Init(USBD_HandleTypeDef *pdev, - uint8_t cfgidx); - -static uint8_t USBD_HID_DeInit(USBD_HandleTypeDef *pdev, - uint8_t cfgidx); - -static uint8_t USBD_HID_Setup(USBD_HandleTypeDef *pdev, - USBD_SetupReqTypedef *req); - -static uint8_t *USBD_HID_GetFSCfgDesc(uint16_t *length); +static uint8_t *USBD_HID_GetFSCfgDesc(uint16_t *length); +static uint8_t *USBD_HID_GetHSCfgDesc(uint16_t *length); +static uint8_t *USBD_HID_GetOtherSpeedCfgDesc(uint16_t *length); +static uint8_t *USBD_HID_GetDeviceQualifierDesc(uint16_t *length); -static uint8_t *USBD_HID_GetHSCfgDesc(uint16_t *length); - -static uint8_t *USBD_HID_GetOtherSpeedCfgDesc(uint16_t *length); - -static uint8_t *USBD_HID_GetDeviceQualifierDesc(uint16_t *length); - -static uint8_t USBD_HID_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum); /** * @} */ @@ -116,16 +105,15 @@ static uint8_t USBD_HID_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum); * @{ */ -USBD_ClassTypeDef USBD_HID = -{ +USBD_ClassTypeDef USBD_HID = { USBD_HID_Init, USBD_HID_DeInit, USBD_HID_Setup, - NULL, /*EP0_TxSent*/ - NULL, /*EP0_RxReady*/ - USBD_HID_DataIn, /*DataIn*/ - NULL, /*DataOut*/ - NULL, /*SOF */ + NULL, /* EP0_TxSent */ + NULL, /* EP0_RxReady */ + USBD_HID_DataIn, /* DataIn */ + NULL, /* DataOut */ + NULL, /* SOF */ NULL, NULL, USBD_HID_GetHSCfgDesc, @@ -135,174 +123,166 @@ USBD_ClassTypeDef USBD_HID = }; /* USB HID device FS Configuration Descriptor */ -__ALIGN_BEGIN static uint8_t USBD_HID_CfgFSDesc[USB_HID_CONFIG_DESC_SIZ] __ALIGN_END = -{ - 0x09, /* bLength: Configuration Descriptor size */ - USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */ +__ALIGN_BEGIN static uint8_t USBD_HID_CfgFSDesc[USB_HID_CONFIG_DESC_SIZ] __ALIGN_END = { + 0x09, /* bLength: Configuration Descriptor size */ + USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */ USB_HID_CONFIG_DESC_SIZ, - /* wTotalLength: Bytes returned */ + /* wTotalLength: Bytes returned */ 0x00, - 0x01, /*bNumInterfaces: 1 interface*/ - 0x01, /*bConfigurationValue: Configuration value*/ - 0x00, /*iConfiguration: Index of string descriptor describing - the configuration*/ - 0xE0, /*bmAttributes: bus powered and Support Remote Wake-up */ - 0x32, /*MaxPower 100 mA: this current is used for detecting Vbus*/ + 0x01, /* bNumInterfaces: 1 interface */ + 0x01, /* bConfigurationValue: Configuration value */ + 0x00, /* iConfiguration: Index of string descriptor describing the configuration */ + 0xE0, /* bmAttributes: bus powered and Support Remote Wake-up */ + 0x32, /* MaxPower 100 mA: this current is used for detecting Vbus */ /************** Descriptor of Joystick Mouse interface ****************/ /* 09 */ - 0x09, /*bLength: Interface Descriptor size*/ - USB_DESC_TYPE_INTERFACE,/*bDescriptorType: Interface descriptor type*/ - 0x00, /*bInterfaceNumber: Number of Interface*/ - 0x00, /*bAlternateSetting: Alternate setting*/ - 0x01, /*bNumEndpoints*/ - 0x03, /*bInterfaceClass: HID*/ - 0x01, /*bInterfaceSubClass : 1=BOOT, 0=no boot*/ - 0x02, /*nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse*/ - 0, /*iInterface: Index of string descriptor*/ + 0x09, /* bLength: Interface Descriptor size */ + USB_DESC_TYPE_INTERFACE, /* bDescriptorType: Interface descriptor type */ + 0x00, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x01, /* bNumEndpoints */ + 0x03, /* bInterfaceClass: HID */ + 0x01, /* bInterfaceSubClass : 1=BOOT, 0=no boot */ + 0x02, /* nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse */ + 0, /* iInterface: Index of string descriptor */ /******************** Descriptor of Joystick Mouse HID ********************/ /* 18 */ - 0x09, /*bLength: HID Descriptor size*/ - HID_DESCRIPTOR_TYPE, /*bDescriptorType: HID*/ - 0x11, /*bcdHID: HID Class Spec release number*/ + 0x09, /* bLength: HID Descriptor size */ + HID_DESCRIPTOR_TYPE, /* bDescriptorType: HID */ + 0x11, /* bcdHID: HID Class Spec release number */ 0x01, - 0x00, /*bCountryCode: Hardware target country*/ - 0x01, /*bNumDescriptors: Number of HID class descriptors to follow*/ - 0x22, /*bDescriptorType*/ - HID_MOUSE_REPORT_DESC_SIZE,/*wItemLength: Total length of Report descriptor*/ + 0x00, /* bCountryCode: Hardware target country */ + 0x01, /* bNumDescriptors: Number of HID class descriptors to follow */ + 0x22, /* bDescriptorType */ + HID_MOUSE_REPORT_DESC_SIZE, /* wItemLength: Total length of Report descriptor */ 0x00, /******************** Descriptor of Mouse endpoint ********************/ /* 27 */ - 0x07, /*bLength: Endpoint Descriptor size*/ - USB_DESC_TYPE_ENDPOINT, /*bDescriptorType:*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType:*/ - HID_EPIN_ADDR, /*bEndpointAddress: Endpoint Address (IN)*/ - 0x03, /*bmAttributes: Interrupt endpoint*/ - HID_EPIN_SIZE, /*wMaxPacketSize: 4 Byte max */ + HID_EPIN_ADDR, /* bEndpointAddress: Endpoint Address (IN) */ + 0x03, /* bmAttributes: Interrupt endpoint */ + HID_EPIN_SIZE, /* wMaxPacketSize: 4 Byte max */ 0x00, - HID_FS_BINTERVAL, /*bInterval: Polling Interval */ + HID_FS_BINTERVAL, /* bInterval: Polling Interval */ /* 34 */ }; /* USB HID device HS Configuration Descriptor */ -__ALIGN_BEGIN static uint8_t USBD_HID_CfgHSDesc[USB_HID_CONFIG_DESC_SIZ] __ALIGN_END = -{ - 0x09, /* bLength: Configuration Descriptor size */ - USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */ +__ALIGN_BEGIN static uint8_t USBD_HID_CfgHSDesc[USB_HID_CONFIG_DESC_SIZ] __ALIGN_END = { + 0x09, /* bLength: Configuration Descriptor size */ + USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */ USB_HID_CONFIG_DESC_SIZ, - /* wTotalLength: Bytes returned */ + /* wTotalLength: Bytes returned */ 0x00, - 0x01, /*bNumInterfaces: 1 interface*/ - 0x01, /*bConfigurationValue: Configuration value*/ - 0x00, /*iConfiguration: Index of string descriptor describing - the configuration*/ - 0xE0, /*bmAttributes: bus powered and Support Remote Wake-up */ - 0x32, /*MaxPower 100 mA: this current is used for detecting Vbus*/ + 0x01, /* bNumInterfaces: 1 interface */ + 0x01, /* bConfigurationValue: Configuration value */ + 0x00, /* iConfiguration: Index of string descriptor describing the configuration */ + 0xE0, /* bmAttributes: bus powered and Support Remote Wake-up */ + 0x32, /* MaxPower 100 mA: this current is used for detecting Vbus */ /************** Descriptor of Joystick Mouse interface ****************/ /* 09 */ - 0x09, /*bLength: Interface Descriptor size*/ - USB_DESC_TYPE_INTERFACE,/*bDescriptorType: Interface descriptor type*/ - 0x00, /*bInterfaceNumber: Number of Interface*/ - 0x00, /*bAlternateSetting: Alternate setting*/ - 0x01, /*bNumEndpoints*/ - 0x03, /*bInterfaceClass: HID*/ - 0x01, /*bInterfaceSubClass : 1=BOOT, 0=no boot*/ - 0x02, /*nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse*/ - 0, /*iInterface: Index of string descriptor*/ + 0x09, /* bLength: Interface Descriptor size */ + USB_DESC_TYPE_INTERFACE, /* bDescriptorType: Interface descriptor type */ + 0x00, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x01, /* bNumEndpoints */ + 0x03, /* bInterfaceClass: HID */ + 0x01, /* bInterfaceSubClass : 1=BOOT, 0=no boot */ + 0x02, /* nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse */ + 0, /* iInterface: Index of string descriptor */ /******************** Descriptor of Joystick Mouse HID ********************/ /* 18 */ - 0x09, /*bLength: HID Descriptor size*/ - HID_DESCRIPTOR_TYPE, /*bDescriptorType: HID*/ - 0x11, /*bcdHID: HID Class Spec release number*/ + 0x09, /* bLength: HID Descriptor size */ + HID_DESCRIPTOR_TYPE, /* bDescriptorType: HID */ + 0x11, /* bcdHID: HID Class Spec release number */ 0x01, - 0x00, /*bCountryCode: Hardware target country*/ - 0x01, /*bNumDescriptors: Number of HID class descriptors to follow*/ - 0x22, /*bDescriptorType*/ - HID_MOUSE_REPORT_DESC_SIZE,/*wItemLength: Total length of Report descriptor*/ + 0x00, /* bCountryCode: Hardware target country */ + 0x01, /* bNumDescriptors: Number of HID class descriptors to follow */ + 0x22, /* bDescriptorType */ + HID_MOUSE_REPORT_DESC_SIZE, /* wItemLength: Total length of Report descriptor */ 0x00, /******************** Descriptor of Mouse endpoint ********************/ /* 27 */ - 0x07, /*bLength: Endpoint Descriptor size*/ - USB_DESC_TYPE_ENDPOINT, /*bDescriptorType:*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: */ - HID_EPIN_ADDR, /*bEndpointAddress: Endpoint Address (IN)*/ - 0x03, /*bmAttributes: Interrupt endpoint*/ - HID_EPIN_SIZE, /*wMaxPacketSize: 4 Byte max */ + HID_EPIN_ADDR, /* bEndpointAddress: Endpoint Address (IN) */ + 0x03, /* bmAttributes: Interrupt endpoint */ + HID_EPIN_SIZE, /* wMaxPacketSize: 4 Byte max */ 0x00, - HID_HS_BINTERVAL, /*bInterval: Polling Interval */ + HID_HS_BINTERVAL, /* bInterval: Polling Interval */ /* 34 */ }; /* USB HID device Other Speed Configuration Descriptor */ -__ALIGN_BEGIN static uint8_t USBD_HID_OtherSpeedCfgDesc[USB_HID_CONFIG_DESC_SIZ] __ALIGN_END = -{ - 0x09, /* bLength: Configuration Descriptor size */ - USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */ +__ALIGN_BEGIN static uint8_t USBD_HID_OtherSpeedCfgDesc[USB_HID_CONFIG_DESC_SIZ] __ALIGN_END = { + 0x09, /* bLength: Configuration Descriptor size */ + USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */ USB_HID_CONFIG_DESC_SIZ, - /* wTotalLength: Bytes returned */ + /* wTotalLength: Bytes returned */ 0x00, - 0x01, /*bNumInterfaces: 1 interface*/ - 0x01, /*bConfigurationValue: Configuration value*/ - 0x00, /*iConfiguration: Index of string descriptor describing - the configuration*/ - 0xE0, /*bmAttributes: bus powered and Support Remote Wake-up */ - 0x32, /*MaxPower 100 mA: this current is used for detecting Vbus*/ + 0x01, /* bNumInterfaces: 1 interface */ + 0x01, /* bConfigurationValue: Configuration value */ + 0x00, /* iConfiguration: Index of string descriptor describing the configuration */ + 0xE0, /* bmAttributes: bus powered and Support Remote Wake-up */ + 0x32, /* MaxPower 100 mA: this current is used for detecting Vbus */ /************** Descriptor of Joystick Mouse interface ****************/ /* 09 */ - 0x09, /*bLength: Interface Descriptor size*/ - USB_DESC_TYPE_INTERFACE,/*bDescriptorType: Interface descriptor type*/ - 0x00, /*bInterfaceNumber: Number of Interface*/ - 0x00, /*bAlternateSetting: Alternate setting*/ - 0x01, /*bNumEndpoints*/ - 0x03, /*bInterfaceClass: HID*/ - 0x01, /*bInterfaceSubClass : 1=BOOT, 0=no boot*/ - 0x02, /*nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse*/ - 0, /*iInterface: Index of string descriptor*/ + 0x09, /* bLength: Interface Descriptor size */ + USB_DESC_TYPE_INTERFACE, /* bDescriptorType: Interface descriptor type */ + 0x00, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x01, /* bNumEndpoints */ + 0x03, /* bInterfaceClass: HID */ + 0x01, /* bInterfaceSubClass : 1=BOOT, 0=no boot */ + 0x02, /* nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse */ + 0, /* iInterface: Index of string descriptor */ /******************** Descriptor of Joystick Mouse HID ********************/ /* 18 */ - 0x09, /*bLength: HID Descriptor size*/ - HID_DESCRIPTOR_TYPE, /*bDescriptorType: HID*/ - 0x11, /*bcdHID: HID Class Spec release number*/ + 0x09, /* bLength: HID Descriptor size */ + HID_DESCRIPTOR_TYPE, /* bDescriptorType: HID */ + 0x11, /* bcdHID: HID Class Spec release number */ 0x01, - 0x00, /*bCountryCode: Hardware target country*/ - 0x01, /*bNumDescriptors: Number of HID class descriptors to follow*/ - 0x22, /*bDescriptorType*/ - HID_MOUSE_REPORT_DESC_SIZE,/*wItemLength: Total length of Report descriptor*/ + 0x00, /* bCountryCode: Hardware target country */ + 0x01, /* bNumDescriptors: Number of HID class descriptors to follow */ + 0x22, /* bDescriptorType */ + HID_MOUSE_REPORT_DESC_SIZE, /* wItemLength: Total length of Report descriptor */ 0x00, /******************** Descriptor of Mouse endpoint ********************/ /* 27 */ - 0x07, /*bLength: Endpoint Descriptor size*/ - USB_DESC_TYPE_ENDPOINT, /*bDescriptorType:*/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESC_TYPE_ENDPOINT, /* bDescriptorType: */ - HID_EPIN_ADDR, /*bEndpointAddress: Endpoint Address (IN)*/ - 0x03, /*bmAttributes: Interrupt endpoint*/ - HID_EPIN_SIZE, /*wMaxPacketSize: 4 Byte max */ + HID_EPIN_ADDR, /* bEndpointAddress: Endpoint Address (IN) */ + 0x03, /* bmAttributes: Interrupt endpoint */ + HID_EPIN_SIZE, /* wMaxPacketSize: 4 Byte max */ 0x00, - HID_FS_BINTERVAL, /*bInterval: Polling Interval */ + HID_FS_BINTERVAL, /* bInterval: Polling Interval */ /* 34 */ }; /* USB HID device Configuration Descriptor */ -__ALIGN_BEGIN static uint8_t USBD_HID_Desc[USB_HID_DESC_SIZ] __ALIGN_END = -{ +__ALIGN_BEGIN static uint8_t USBD_HID_Desc[USB_HID_DESC_SIZ] __ALIGN_END = { /* 18 */ - 0x09, /*bLength: HID Descriptor size*/ - HID_DESCRIPTOR_TYPE, /*bDescriptorType: HID*/ - 0x11, /*bcdHID: HID Class Spec release number*/ + 0x09, /* bLength: HID Descriptor size */ + HID_DESCRIPTOR_TYPE, /* bDescriptorType: HID */ + 0x11, /* bcdHID: HID Class Spec release number */ 0x01, - 0x00, /*bCountryCode: Hardware target country*/ - 0x01, /*bNumDescriptors: Number of HID class descriptors to follow*/ - 0x22, /*bDescriptorType*/ - HID_MOUSE_REPORT_DESC_SIZE,/*wItemLength: Total length of Report descriptor*/ + 0x00, /* bCountryCode: Hardware target country */ + 0x01, /* bNumDescriptors: Number of HID class descriptors to follow */ + 0x22, /* bDescriptorType */ + HID_MOUSE_REPORT_DESC_SIZE, /* wItemLength: Total length of Report descriptor */ 0x00, }; /* USB Standard Device Descriptor */ -__ALIGN_BEGIN static uint8_t USBD_HID_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_DESC] __ALIGN_END = -{ +__ALIGN_BEGIN static uint8_t USBD_HID_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_DESC] __ALIGN_END = { USB_LEN_DEV_QUALIFIER_DESC, USB_DESC_TYPE_DEVICE_QUALIFIER, 0x00, @@ -315,8 +295,7 @@ __ALIGN_BEGIN static uint8_t USBD_HID_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_ 0x00, }; -__ALIGN_BEGIN static uint8_t HID_MOUSE_ReportDesc[HID_MOUSE_REPORT_DESC_SIZE] __ALIGN_END = -{ +__ALIGN_BEGIN static uint8_t HID_MOUSE_ReportDesc[HID_MOUSE_REPORT_DESC_SIZE] __ALIGN_END = { 0x05, 0x01, 0x09, 0x02, 0xA1, 0x01, @@ -380,46 +359,64 @@ __ALIGN_BEGIN static uint8_t HID_MOUSE_ReportDesc[HID_MOUSE_REPORT_DESC_SIZE] _ * @param cfgidx: Configuration index * @retval status */ -static uint8_t USBD_HID_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx) +static uint8_t USBD_HID_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { - /* Open EP IN */ - USBD_LL_OpenEP(pdev, HID_EPIN_ADDR, USBD_EP_TYPE_INTR, HID_EPIN_SIZE); - pdev->ep_in[HID_EPIN_ADDR & 0xFU].is_used = 1U; + UNUSED(cfgidx); + + USBD_HID_HandleTypeDef *hhid; - pdev->pClassData = USBD_malloc(sizeof(USBD_HID_HandleTypeDef)); + hhid = USBD_malloc(sizeof(USBD_HID_HandleTypeDef)); - if (pdev->pClassData == NULL) + if (hhid == NULL) { - return USBD_FAIL; + pdev->pClassData = NULL; + return (uint8_t)USBD_EMEM; } - ((USBD_HID_HandleTypeDef *)pdev->pClassData)->state = HID_IDLE; + pdev->pClassData = (void *)hhid; - return USBD_OK; + if (pdev->dev_speed == USBD_SPEED_HIGH) + { + pdev->ep_in[HID_EPIN_ADDR & 0xFU].bInterval = HID_HS_BINTERVAL; + } + else /* LOW and FULL-speed endpoints */ + { + pdev->ep_in[HID_EPIN_ADDR & 0xFU].bInterval = HID_FS_BINTERVAL; + } + + /* Open EP IN */ + (void)USBD_LL_OpenEP(pdev, HID_EPIN_ADDR, USBD_EP_TYPE_INTR, HID_EPIN_SIZE); + pdev->ep_in[HID_EPIN_ADDR & 0xFU].is_used = 1U; + + hhid->state = HID_IDLE; + + return (uint8_t)USBD_OK; } /** - * @brief USBD_HID_Init + * @brief USBD_HID_DeInit * DeInitialize the HID layer * @param pdev: device instance * @param cfgidx: Configuration index * @retval status */ -static uint8_t USBD_HID_DeInit(USBD_HandleTypeDef *pdev, - uint8_t cfgidx) +static uint8_t USBD_HID_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { + UNUSED(cfgidx); + /* Close HID EPs */ - USBD_LL_CloseEP(pdev, HID_EPIN_ADDR); + (void)USBD_LL_CloseEP(pdev, HID_EPIN_ADDR); pdev->ep_in[HID_EPIN_ADDR & 0xFU].is_used = 0U; + pdev->ep_in[HID_EPIN_ADDR & 0xFU].bInterval = 0U; /* FRee allocated memory */ if (pdev->pClassData != NULL) { - USBD_free(pdev->pClassData); + (void)USBD_free(pdev->pClassData); pdev->pClassData = NULL; } - return USBD_OK; + return (uint8_t)USBD_OK; } /** @@ -429,115 +426,117 @@ static uint8_t USBD_HID_DeInit(USBD_HandleTypeDef *pdev, * @param req: usb requests * @retval status */ -static uint8_t USBD_HID_Setup(USBD_HandleTypeDef *pdev, - USBD_SetupReqTypedef *req) +static uint8_t USBD_HID_Setup(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { - USBD_HID_HandleTypeDef *hhid = (USBD_HID_HandleTypeDef *) pdev->pClassData; - uint16_t len = 0U; - uint8_t *pbuf = NULL; - uint16_t status_info = 0U; + USBD_HID_HandleTypeDef *hhid = (USBD_HID_HandleTypeDef *)pdev->pClassData; USBD_StatusTypeDef ret = USBD_OK; + uint16_t len; + uint8_t *pbuf; + uint16_t status_info = 0U; switch (req->bmRequest & USB_REQ_TYPE_MASK) { - case USB_REQ_TYPE_CLASS : - switch (req->bRequest) + case USB_REQ_TYPE_CLASS : + switch (req->bRequest) + { + case HID_REQ_SET_PROTOCOL: + hhid->Protocol = (uint8_t)(req->wValue); + break; + + case HID_REQ_GET_PROTOCOL: + (void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->Protocol, 1U); + break; + + case HID_REQ_SET_IDLE: + hhid->IdleState = (uint8_t)(req->wValue >> 8); + break; + + case HID_REQ_GET_IDLE: + (void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->IdleState, 1U); + break; + + default: + USBD_CtlError(pdev, req); + ret = USBD_FAIL; + break; + } + break; + case USB_REQ_TYPE_STANDARD: + switch (req->bRequest) + { + case USB_REQ_GET_STATUS: + if (pdev->dev_state == USBD_STATE_CONFIGURED) + { + (void)USBD_CtlSendData(pdev, (uint8_t *)&status_info, 2U); + } + else { - case HID_REQ_SET_PROTOCOL: - hhid->Protocol = (uint8_t)(req->wValue); - break; - - case HID_REQ_GET_PROTOCOL: - USBD_CtlSendData(pdev, (uint8_t *)(void *)&hhid->Protocol, 1U); - break; - - case HID_REQ_SET_IDLE: - hhid->IdleState = (uint8_t)(req->wValue >> 8); - break; - - case HID_REQ_GET_IDLE: - USBD_CtlSendData(pdev, (uint8_t *)(void *)&hhid->IdleState, 1U); - break; - - default: - USBD_CtlError(pdev, req); - ret = USBD_FAIL; - break; + USBD_CtlError(pdev, req); + ret = USBD_FAIL; } break; - case USB_REQ_TYPE_STANDARD: - switch (req->bRequest) + + case USB_REQ_GET_DESCRIPTOR: + if ((req->wValue >> 8) == HID_REPORT_DESC) + { + len = MIN(HID_MOUSE_REPORT_DESC_SIZE, req->wLength); + pbuf = HID_MOUSE_ReportDesc; + } + else if ((req->wValue >> 8) == HID_DESCRIPTOR_TYPE) + { + pbuf = USBD_HID_Desc; + len = MIN(USB_HID_DESC_SIZ, req->wLength); + } + else { - case USB_REQ_GET_STATUS: - if (pdev->dev_state == USBD_STATE_CONFIGURED) - { - USBD_CtlSendData(pdev, (uint8_t *)(void *)&status_info, 2U); - } - else - { - USBD_CtlError(pdev, req); - ret = USBD_FAIL; - } - break; - - case USB_REQ_GET_DESCRIPTOR: - if (req->wValue >> 8 == HID_REPORT_DESC) - { - len = MIN(HID_MOUSE_REPORT_DESC_SIZE, req->wLength); - pbuf = HID_MOUSE_ReportDesc; - } - else if (req->wValue >> 8 == HID_DESCRIPTOR_TYPE) - { - pbuf = USBD_HID_Desc; - len = MIN(USB_HID_DESC_SIZ, req->wLength); - } - else - { - USBD_CtlError(pdev, req); - ret = USBD_FAIL; - break; - } - USBD_CtlSendData(pdev, pbuf, len); - break; - - case USB_REQ_GET_INTERFACE : - if (pdev->dev_state == USBD_STATE_CONFIGURED) - { - USBD_CtlSendData(pdev, (uint8_t *)(void *)&hhid->AltSetting, 1U); - } - else - { - USBD_CtlError(pdev, req); - ret = USBD_FAIL; - } - break; - - case USB_REQ_SET_INTERFACE : - if (pdev->dev_state == USBD_STATE_CONFIGURED) - { - hhid->AltSetting = (uint8_t)(req->wValue); - } - else - { - USBD_CtlError(pdev, req); - ret = USBD_FAIL; - } - break; - - default: - USBD_CtlError(pdev, req); - ret = USBD_FAIL; - break; + USBD_CtlError(pdev, req); + ret = USBD_FAIL; + break; } + (void)USBD_CtlSendData(pdev, pbuf, len); + break; + + case USB_REQ_GET_INTERFACE : + if (pdev->dev_state == USBD_STATE_CONFIGURED) + { + (void)USBD_CtlSendData(pdev, (uint8_t *)&hhid->AltSetting, 1U); + } + else + { + USBD_CtlError(pdev, req); + ret = USBD_FAIL; + } + break; + + case USB_REQ_SET_INTERFACE: + if (pdev->dev_state == USBD_STATE_CONFIGURED) + { + hhid->AltSetting = (uint8_t)(req->wValue); + } + else + { + USBD_CtlError(pdev, req); + ret = USBD_FAIL; + } + break; + + case USB_REQ_CLEAR_FEATURE: break; default: USBD_CtlError(pdev, req); ret = USBD_FAIL; break; + } + break; + + default: + USBD_CtlError(pdev, req); + ret = USBD_FAIL; + break; } - return ret; + return (uint8_t)ret; } /** @@ -547,24 +546,20 @@ static uint8_t USBD_HID_Setup(USBD_HandleTypeDef *pdev, * @param buff: pointer to report * @retval status */ -uint8_t USBD_HID_SendReport(USBD_HandleTypeDef *pdev, - uint8_t *report, - uint16_t len) +uint8_t USBD_HID_SendReport(USBD_HandleTypeDef *pdev, uint8_t *report, uint16_t len) { - USBD_HID_HandleTypeDef *hhid = (USBD_HID_HandleTypeDef *)pdev->pClassData; + USBD_HID_HandleTypeDef *hhid = (USBD_HID_HandleTypeDef *)pdev->pClassData; if (pdev->dev_state == USBD_STATE_CONFIGURED) { if (hhid->state == HID_IDLE) { hhid->state = HID_BUSY; - USBD_LL_Transmit(pdev, - HID_EPIN_ADDR, - report, - len); + (void)USBD_LL_Transmit(pdev, HID_EPIN_ADDR, report, len); } } - return USBD_OK; + + return (uint8_t)USBD_OK; } /** @@ -575,7 +570,7 @@ uint8_t USBD_HID_SendReport(USBD_HandleTypeDef *pdev, */ uint32_t USBD_HID_GetPollingInterval(USBD_HandleTypeDef *pdev) { - uint32_t polling_interval = 0U; + uint32_t polling_interval; /* HIGH-speed endpoints */ if (pdev->dev_speed == USBD_SPEED_HIGH) @@ -602,9 +597,10 @@ uint32_t USBD_HID_GetPollingInterval(USBD_HandleTypeDef *pdev) * @param length : pointer data length * @retval pointer to descriptor buffer */ -static uint8_t *USBD_HID_GetFSCfgDesc(uint16_t *length) +static uint8_t *USBD_HID_GetFSCfgDesc(uint16_t *length) { - *length = sizeof(USBD_HID_CfgFSDesc); + *length = (uint16_t)sizeof(USBD_HID_CfgFSDesc); + return USBD_HID_CfgFSDesc; } @@ -615,9 +611,10 @@ static uint8_t *USBD_HID_GetFSCfgDesc(uint16_t *length) * @param length : pointer data length * @retval pointer to descriptor buffer */ -static uint8_t *USBD_HID_GetHSCfgDesc(uint16_t *length) +static uint8_t *USBD_HID_GetHSCfgDesc(uint16_t *length) { - *length = sizeof(USBD_HID_CfgHSDesc); + *length = (uint16_t)sizeof(USBD_HID_CfgHSDesc); + return USBD_HID_CfgHSDesc; } @@ -628,9 +625,10 @@ static uint8_t *USBD_HID_GetHSCfgDesc(uint16_t *length) * @param length : pointer data length * @retval pointer to descriptor buffer */ -static uint8_t *USBD_HID_GetOtherSpeedCfgDesc(uint16_t *length) +static uint8_t *USBD_HID_GetOtherSpeedCfgDesc(uint16_t *length) { - *length = sizeof(USBD_HID_OtherSpeedCfgDesc); + *length = (uint16_t)sizeof(USBD_HID_OtherSpeedCfgDesc); + return USBD_HID_OtherSpeedCfgDesc; } @@ -641,14 +639,14 @@ static uint8_t *USBD_HID_GetOtherSpeedCfgDesc(uint16_t *length) * @param epnum: endpoint index * @retval status */ -static uint8_t USBD_HID_DataIn(USBD_HandleTypeDef *pdev, - uint8_t epnum) +static uint8_t USBD_HID_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum) { - + UNUSED(epnum); /* Ensure that the FIFO is empty before a new transfer, this condition could be caused by a new transfer before the end of the previous transfer */ ((USBD_HID_HandleTypeDef *)pdev->pClassData)->state = HID_IDLE; - return USBD_OK; + + return (uint8_t)USBD_OK; } @@ -658,9 +656,10 @@ static uint8_t USBD_HID_DataIn(USBD_HandleTypeDef *pdev, * @param length : pointer data length * @retval pointer to descriptor buffer */ -static uint8_t *USBD_HID_GetDeviceQualifierDesc(uint16_t *length) +static uint8_t *USBD_HID_GetDeviceQualifierDesc(uint16_t *length) { - *length = sizeof(USBD_HID_DeviceQualifierDesc); + *length = (uint16_t)sizeof(USBD_HID_DeviceQualifierDesc); + return USBD_HID_DeviceQualifierDesc; } diff --git a/system/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Inc/usbd_msc.h b/system/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Inc/usbd_msc.h index 932bbba8c3..a0bbab9065 100644 --- a/system/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Inc/usbd_msc.h +++ b/system/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Inc/usbd_msc.h @@ -86,7 +86,7 @@ typedef struct uint32_t interface; uint8_t bot_state; uint8_t bot_status; - uint16_t bot_data_length; + uint32_t bot_data_length; uint8_t bot_data[MSC_MEDIA_PACKET]; USBD_MSC_BOT_CBWTypeDef cbw; USBD_MSC_BOT_CSWTypeDef csw; @@ -94,6 +94,7 @@ typedef struct USBD_SCSI_SenseTypeDef scsi_sense [SENSE_LIST_DEEPTH]; uint8_t scsi_sense_head; uint8_t scsi_sense_tail; + uint8_t scsi_medium_state; uint16_t scsi_blk_size; uint32_t scsi_blk_nbr; diff --git a/system/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Inc/usbd_msc_data.h b/system/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Inc/usbd_msc_data.h index 79dafbd67f..26838de02e 100644 --- a/system/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Inc/usbd_msc_data.h +++ b/system/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Inc/usbd_msc_data.h @@ -40,10 +40,11 @@ extern "C" { /** @defgroup USB_INFO_Exported_Defines * @{ */ -#define MODE_SENSE6_LEN 8U -#define MODE_SENSE10_LEN 8U -#define LENGTH_INQUIRY_PAGE00 7U -#define LENGTH_FORMAT_CAPACITIES 20U +#define MODE_SENSE6_LEN 0x17U +#define MODE_SENSE10_LEN 0x1BU +#define LENGTH_INQUIRY_PAGE00 0x06U +#define LENGTH_INQUIRY_PAGE80 0x08U +#define LENGTH_FORMAT_CAPACITIES 0x14U /** * @} @@ -70,9 +71,10 @@ extern "C" { /** @defgroup USBD_INFO_Exported_Variables * @{ */ -extern const uint8_t MSC_Page00_Inquiry_Data[]; -extern const uint8_t MSC_Mode_Sense6_data[]; -extern const uint8_t MSC_Mode_Sense10_data[] ; +extern uint8_t MSC_Page00_Inquiry_Data[LENGTH_INQUIRY_PAGE00]; +extern uint8_t MSC_Page80_Inquiry_Data[LENGTH_INQUIRY_PAGE80]; +extern uint8_t MSC_Mode_Sense6_data[MODE_SENSE6_LEN]; +extern uint8_t MSC_Mode_Sense10_data[MODE_SENSE10_LEN]; /** * @} diff --git a/system/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Inc/usbd_msc_scsi.h b/system/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Inc/usbd_msc_scsi.h index 1629d786c3..b32ded0f6c 100644 --- a/system/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Inc/usbd_msc_scsi.h +++ b/system/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Inc/usbd_msc_scsi.h @@ -103,20 +103,13 @@ extern "C" { #define READ_FORMAT_CAPACITY_DATA_LEN 0x0CU #define READ_CAPACITY10_DATA_LEN 0x08U -#define MODE_SENSE10_DATA_LEN 0x08U -#define MODE_SENSE6_DATA_LEN 0x04U #define REQUEST_SENSE_DATA_LEN 0x12U #define STANDARD_INQUIRY_DATA_LEN 0x24U #define BLKVFY 0x04U -extern uint8_t Page00_Inquiry_Data[]; -extern uint8_t Standard_Inquiry_Data[]; -extern uint8_t Standard_Inquiry_Data2[]; -extern uint8_t Mode_Sense6_data[]; -extern uint8_t Mode_Sense10_data[]; -extern uint8_t Scsi_Sense_Data[]; -extern uint8_t ReadCapacity10_Data[]; -extern uint8_t ReadFormatCapacity_Data []; +#define SCSI_MEDIUM_UNLOCKED 0x00U +#define SCSI_MEDIUM_LOCKED 0x01U +#define SCSI_MEDIUM_EJECTED 0x02U /** * @} */ @@ -128,16 +121,16 @@ extern uint8_t ReadFormatCapacity_Data []; typedef struct _SENSE_ITEM { - char Skey; + uint8_t Skey; union { struct _ASCs { - char ASC; - char ASCQ; + uint8_t ASC; + uint8_t ASCQ; } b; uint8_t ASC; - char *pData; + uint8_t *pData; } w; } USBD_SCSI_SenseTypeDef; /** diff --git a/system/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Src/usbd_msc.c b/system/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Src/usbd_msc.c index fdf53148b2..fe6e1c6a24 100644 --- a/system/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Src/usbd_msc.c +++ b/system/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Src/usbd_msc.c @@ -80,16 +80,16 @@ EndBSPDependencies */ /** @defgroup MSC_CORE_Private_FunctionPrototypes * @{ */ -uint8_t USBD_MSC_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx); -uint8_t USBD_MSC_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx); -uint8_t USBD_MSC_Setup(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); -uint8_t USBD_MSC_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum); -uint8_t USBD_MSC_DataOut(USBD_HandleTypeDef *pdev, uint8_t epnum); +uint8_t USBD_MSC_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx); +uint8_t USBD_MSC_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx); +uint8_t USBD_MSC_Setup(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); +uint8_t USBD_MSC_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum); +uint8_t USBD_MSC_DataOut(USBD_HandleTypeDef *pdev, uint8_t epnum); -uint8_t *USBD_MSC_GetHSCfgDesc(uint16_t *length); -uint8_t *USBD_MSC_GetFSCfgDesc(uint16_t *length); -uint8_t *USBD_MSC_GetOtherSpeedCfgDesc(uint16_t *length); -uint8_t *USBD_MSC_GetDeviceQualifierDescriptor(uint16_t *length); +uint8_t *USBD_MSC_GetHSCfgDesc(uint16_t *length); +uint8_t *USBD_MSC_GetFSCfgDesc(uint16_t *length); +uint8_t *USBD_MSC_GetOtherSpeedCfgDesc(uint16_t *length); +uint8_t *USBD_MSC_GetDeviceQualifierDescriptor(uint16_t *length); /** * @} @@ -121,134 +121,133 @@ USBD_ClassTypeDef USBD_MSC = /* USB Mass storage device Configuration Descriptor */ /* All Descriptors (Configuration, Interface, Endpoint, Class, Vendor */ -__ALIGN_BEGIN uint8_t USBD_MSC_CfgHSDesc[USB_MSC_CONFIG_DESC_SIZ] __ALIGN_END = +__ALIGN_BEGIN static uint8_t USBD_MSC_CfgHSDesc[USB_MSC_CONFIG_DESC_SIZ] __ALIGN_END = { - - 0x09, /* bLength: Configuation Descriptor size */ - USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */ + 0x09, /* bLength: Configuation Descriptor size */ + USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */ USB_MSC_CONFIG_DESC_SIZ, 0x00, - 0x01, /* bNumInterfaces: 1 interface */ - 0x01, /* bConfigurationValue: */ - 0x04, /* iConfiguration: */ - 0xC0, /* bmAttributes: */ - 0x32, /* MaxPower 100 mA */ + 0x01, /* bNumInterfaces: 1 interface */ + 0x01, /* bConfigurationValue: */ + 0x04, /* iConfiguration: */ + 0xC0, /* bmAttributes: */ + 0x32, /* MaxPower 100 mA */ /******************** Mass Storage interface ********************/ - 0x09, /* bLength: Interface Descriptor size */ - 0x04, /* bDescriptorType: */ - 0x00, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x02, /* bNumEndpoints*/ - 0x08, /* bInterfaceClass: MSC Class */ - 0x06, /* bInterfaceSubClass : SCSI transparent*/ - 0x50, /* nInterfaceProtocol */ - 0x05, /* iInterface: */ + 0x09, /* bLength: Interface Descriptor size */ + 0x04, /* bDescriptorType: */ + 0x00, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x02, /* bNumEndpoints */ + 0x08, /* bInterfaceClass: MSC Class */ + 0x06, /* bInterfaceSubClass : SCSI transparent */ + 0x50, /* nInterfaceProtocol */ + 0x05, /* iInterface: */ /******************** Mass Storage Endpoints ********************/ - 0x07, /*Endpoint descriptor length = 7*/ - 0x05, /*Endpoint descriptor type */ - MSC_EPIN_ADDR, /*Endpoint address (IN, address 1) */ - 0x02, /*Bulk endpoint type */ + 0x07, /* Endpoint descriptor length = 7 */ + 0x05, /* Endpoint descriptor type */ + MSC_EPIN_ADDR, /* Endpoint address (IN, address 1) */ + 0x02, /* Bulk endpoint type */ LOBYTE(MSC_MAX_HS_PACKET), HIBYTE(MSC_MAX_HS_PACKET), - 0x00, /*Polling interval in milliseconds */ + 0x00, /* Polling interval in milliseconds */ - 0x07, /*Endpoint descriptor length = 7 */ - 0x05, /*Endpoint descriptor type */ - MSC_EPOUT_ADDR, /*Endpoint address (OUT, address 1) */ - 0x02, /*Bulk endpoint type */ + 0x07, /* Endpoint descriptor length = 7 */ + 0x05, /* Endpoint descriptor type */ + MSC_EPOUT_ADDR, /* Endpoint address (OUT, address 1) */ + 0x02, /* Bulk endpoint type */ LOBYTE(MSC_MAX_HS_PACKET), HIBYTE(MSC_MAX_HS_PACKET), - 0x00 /*Polling interval in milliseconds*/ + 0x00 /* Polling interval in milliseconds */ }; /* USB Mass storage device Configuration Descriptor */ -/* All Descriptors (Configuration, Interface, Endpoint, Class, Vendor */ -__ALIGN_BEGIN uint8_t USBD_MSC_CfgFSDesc[USB_MSC_CONFIG_DESC_SIZ] __ALIGN_END = +/* All Descriptors (Configuration, Interface, Endpoint, Class, Vendor */ +__ALIGN_BEGIN static uint8_t USBD_MSC_CfgFSDesc[USB_MSC_CONFIG_DESC_SIZ] __ALIGN_END = { - 0x09, /* bLength: Configuation Descriptor size */ - USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */ + 0x09, /* bLength: Configuation Descriptor size */ + USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */ USB_MSC_CONFIG_DESC_SIZ, 0x00, - 0x01, /* bNumInterfaces: 1 interface */ - 0x01, /* bConfigurationValue: */ - 0x04, /* iConfiguration: */ - 0xC0, /* bmAttributes: */ - 0x32, /* MaxPower 100 mA */ + 0x01, /* bNumInterfaces: 1 interface */ + 0x01, /* bConfigurationValue: */ + 0x04, /* iConfiguration: */ + 0xC0, /* bmAttributes: */ + 0x32, /* MaxPower 100 mA */ /******************** Mass Storage interface ********************/ - 0x09, /* bLength: Interface Descriptor size */ - 0x04, /* bDescriptorType: */ - 0x00, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x02, /* bNumEndpoints*/ - 0x08, /* bInterfaceClass: MSC Class */ - 0x06, /* bInterfaceSubClass : SCSI transparent*/ - 0x50, /* nInterfaceProtocol */ - 0x05, /* iInterface: */ + 0x09, /* bLength: Interface Descriptor size */ + 0x04, /* bDescriptorType: */ + 0x00, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x02, /* bNumEndpoints*/ + 0x08, /* bInterfaceClass: MSC Class */ + 0x06, /* bInterfaceSubClass : SCSI transparent*/ + 0x50, /* nInterfaceProtocol */ + 0x05, /* iInterface: */ /******************** Mass Storage Endpoints ********************/ - 0x07, /*Endpoint descriptor length = 7*/ - 0x05, /*Endpoint descriptor type */ - MSC_EPIN_ADDR, /*Endpoint address (IN, address 1) */ - 0x02, /*Bulk endpoint type */ + 0x07, /* Endpoint descriptor length = 7 */ + 0x05, /* Endpoint descriptor type */ + MSC_EPIN_ADDR, /* Endpoint address (IN, address 1) */ + 0x02, /* Bulk endpoint type */ LOBYTE(MSC_MAX_FS_PACKET), HIBYTE(MSC_MAX_FS_PACKET), - 0x00, /*Polling interval in milliseconds */ + 0x00, /* Polling interval in milliseconds */ - 0x07, /*Endpoint descriptor length = 7 */ - 0x05, /*Endpoint descriptor type */ - MSC_EPOUT_ADDR, /*Endpoint address (OUT, address 1) */ - 0x02, /*Bulk endpoint type */ + 0x07, /* Endpoint descriptor length = 7 */ + 0x05, /* Endpoint descriptor type */ + MSC_EPOUT_ADDR, /* Endpoint address (OUT, address 1) */ + 0x02, /* Bulk endpoint type */ LOBYTE(MSC_MAX_FS_PACKET), HIBYTE(MSC_MAX_FS_PACKET), - 0x00 /*Polling interval in milliseconds*/ + 0x00 /* Polling interval in milliseconds */ }; -__ALIGN_BEGIN uint8_t USBD_MSC_OtherSpeedCfgDesc[USB_MSC_CONFIG_DESC_SIZ] __ALIGN_END = +__ALIGN_BEGIN static uint8_t USBD_MSC_OtherSpeedCfgDesc[USB_MSC_CONFIG_DESC_SIZ] __ALIGN_END = { - 0x09, /* bLength: Configuation Descriptor size */ + 0x09, /* bLength: Configuation Descriptor size */ USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION, USB_MSC_CONFIG_DESC_SIZ, 0x00, - 0x01, /* bNumInterfaces: 1 interface */ - 0x01, /* bConfigurationValue: */ - 0x04, /* iConfiguration: */ - 0xC0, /* bmAttributes: */ - 0x32, /* MaxPower 100 mA */ + 0x01, /* bNumInterfaces: 1 interface */ + 0x01, /* bConfigurationValue: */ + 0x04, /* iConfiguration: */ + 0xC0, /* bmAttributes: */ + 0x32, /* MaxPower 100 mA */ /******************** Mass Storage interface ********************/ - 0x09, /* bLength: Interface Descriptor size */ - 0x04, /* bDescriptorType: */ - 0x00, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x02, /* bNumEndpoints*/ - 0x08, /* bInterfaceClass: MSC Class */ - 0x06, /* bInterfaceSubClass : SCSI transparent command set*/ - 0x50, /* nInterfaceProtocol */ - 0x05, /* iInterface: */ + 0x09, /* bLength: Interface Descriptor size */ + 0x04, /* bDescriptorType: */ + 0x00, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x02, /* bNumEndpoints */ + 0x08, /* bInterfaceClass: MSC Class */ + 0x06, /* bInterfaceSubClass : SCSI transparent command set */ + 0x50, /* nInterfaceProtocol */ + 0x05, /* iInterface: */ /******************** Mass Storage Endpoints ********************/ - 0x07, /*Endpoint descriptor length = 7*/ - 0x05, /*Endpoint descriptor type */ - MSC_EPIN_ADDR, /*Endpoint address (IN, address 1) */ - 0x02, /*Bulk endpoint type */ + 0x07, /* Endpoint descriptor length = 7 */ + 0x05, /* Endpoint descriptor type */ + MSC_EPIN_ADDR, /* Endpoint address (IN, address 1) */ + 0x02, /* Bulk endpoint type */ 0x40, 0x00, - 0x00, /*Polling interval in milliseconds */ + 0x00, /* Polling interval in milliseconds */ - 0x07, /*Endpoint descriptor length = 7 */ - 0x05, /*Endpoint descriptor type */ - MSC_EPOUT_ADDR, /*Endpoint address (OUT, address 1) */ - 0x02, /*Bulk endpoint type */ + 0x07, /* Endpoint descriptor length = 7 */ + 0x05, /* Endpoint descriptor type */ + MSC_EPOUT_ADDR, /* Endpoint address (OUT, address 1) */ + 0x02, /* Bulk endpoint type */ 0x40, 0x00, - 0x00 /*Polling interval in milliseconds*/ + 0x00 /* Polling interval in milliseconds */ }; /* USB Standard Device Descriptor */ -__ALIGN_BEGIN uint8_t USBD_MSC_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_DESC] __ALIGN_END = +__ALIGN_BEGIN static uint8_t USBD_MSC_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_DESC] __ALIGN_END = { USB_LEN_DEV_QUALIFIER_DESC, USB_DESC_TYPE_DEVICE_QUALIFIER, @@ -279,37 +278,44 @@ __ALIGN_BEGIN uint8_t USBD_MSC_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_DESC] */ uint8_t USBD_MSC_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { + UNUSED(cfgidx); + USBD_MSC_BOT_HandleTypeDef *hmsc; + + hmsc = USBD_malloc(sizeof(USBD_MSC_BOT_HandleTypeDef)); + + if (hmsc == NULL) + { + pdev->pClassData = NULL; + return (uint8_t)USBD_EMEM; + } + + pdev->pClassData = (void *)hmsc; + if (pdev->dev_speed == USBD_SPEED_HIGH) { /* Open EP OUT */ - USBD_LL_OpenEP(pdev, MSC_EPOUT_ADDR, USBD_EP_TYPE_BULK, MSC_MAX_HS_PACKET); + (void)USBD_LL_OpenEP(pdev, MSC_EPOUT_ADDR, USBD_EP_TYPE_BULK, MSC_MAX_HS_PACKET); pdev->ep_out[MSC_EPOUT_ADDR & 0xFU].is_used = 1U; /* Open EP IN */ - USBD_LL_OpenEP(pdev, MSC_EPIN_ADDR, USBD_EP_TYPE_BULK, MSC_MAX_HS_PACKET); + (void)USBD_LL_OpenEP(pdev, MSC_EPIN_ADDR, USBD_EP_TYPE_BULK, MSC_MAX_HS_PACKET); pdev->ep_in[MSC_EPIN_ADDR & 0xFU].is_used = 1U; } else { /* Open EP OUT */ - USBD_LL_OpenEP(pdev, MSC_EPOUT_ADDR, USBD_EP_TYPE_BULK, MSC_MAX_FS_PACKET); + (void)USBD_LL_OpenEP(pdev, MSC_EPOUT_ADDR, USBD_EP_TYPE_BULK, MSC_MAX_FS_PACKET); pdev->ep_out[MSC_EPOUT_ADDR & 0xFU].is_used = 1U; /* Open EP IN */ - USBD_LL_OpenEP(pdev, MSC_EPIN_ADDR, USBD_EP_TYPE_BULK, MSC_MAX_FS_PACKET); + (void)USBD_LL_OpenEP(pdev, MSC_EPIN_ADDR, USBD_EP_TYPE_BULK, MSC_MAX_FS_PACKET); pdev->ep_in[MSC_EPIN_ADDR & 0xFU].is_used = 1U; } - pdev->pClassData = USBD_malloc(sizeof(USBD_MSC_BOT_HandleTypeDef)); - - if (pdev->pClassData == NULL) - { - return USBD_FAIL; - } /* Init the BOT layer */ MSC_BOT_Init(pdev); - return USBD_OK; + return (uint8_t)USBD_OK; } /** @@ -319,15 +325,16 @@ uint8_t USBD_MSC_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx) * @param cfgidx: configuration index * @retval status */ -uint8_t USBD_MSC_DeInit(USBD_HandleTypeDef *pdev, - uint8_t cfgidx) +uint8_t USBD_MSC_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { + UNUSED(cfgidx); + /* Close MSC EPs */ - USBD_LL_CloseEP(pdev, MSC_EPOUT_ADDR); + (void)USBD_LL_CloseEP(pdev, MSC_EPOUT_ADDR); pdev->ep_out[MSC_EPOUT_ADDR & 0xFU].is_used = 0U; /* Close EP IN */ - USBD_LL_CloseEP(pdev, MSC_EPIN_ADDR); + (void)USBD_LL_CloseEP(pdev, MSC_EPIN_ADDR); pdev->ep_in[MSC_EPIN_ADDR & 0xFU].is_used = 0U; /* De-Init the BOT layer */ @@ -336,11 +343,11 @@ uint8_t USBD_MSC_DeInit(USBD_HandleTypeDef *pdev, /* Free MSC Class Resources */ if (pdev->pClassData != NULL) { - USBD_free(pdev->pClassData); - pdev->pClassData = NULL; + (void)USBD_free(pdev->pClassData); + pdev->pClassData = NULL; } - return USBD_OK; + return (uint8_t)USBD_OK; } /** * @brief USBD_MSC_Setup @@ -351,139 +358,100 @@ uint8_t USBD_MSC_DeInit(USBD_HandleTypeDef *pdev, */ uint8_t USBD_MSC_Setup(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { - USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef *) pdev->pClassData; - uint8_t ret = USBD_OK; + USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef *)pdev->pClassData; + USBD_StatusTypeDef ret = USBD_OK; uint16_t status_info = 0U; switch (req->bmRequest & USB_REQ_TYPE_MASK) { /* Class request */ - case USB_REQ_TYPE_CLASS: - switch (req->bRequest) + case USB_REQ_TYPE_CLASS: + switch (req->bRequest) + { + case BOT_GET_MAX_LUN: + if ((req->wValue == 0U) && (req->wLength == 1U) && + ((req->bmRequest & 0x80U) == 0x80U)) { - case BOT_GET_MAX_LUN: - if ((req->wValue == 0U) && (req->wLength == 1U) && - ((req->bmRequest & 0x80U) == 0x80U)) - { - hmsc->max_lun = (uint32_t)((USBD_StorageTypeDef *)pdev->pUserData)->GetMaxLun(); - USBD_CtlSendData(pdev, (uint8_t *)(void *)&hmsc->max_lun, 1U); - } - else - { - USBD_CtlError(pdev, req); - ret = USBD_FAIL; - } - break; - - case BOT_RESET : - if ((req->wValue == 0U) && (req->wLength == 0U) && - ((req->bmRequest & 0x80U) != 0x80U)) - { - MSC_BOT_Reset(pdev); - } - else - { - USBD_CtlError(pdev, req); - ret = USBD_FAIL; - } - break; - - default: - USBD_CtlError(pdev, req); - ret = USBD_FAIL; - break; + hmsc->max_lun = (uint32_t)((USBD_StorageTypeDef *)pdev->pUserData)->GetMaxLun(); + (void)USBD_CtlSendData(pdev, (uint8_t *)&hmsc->max_lun, 1U); } + else + { + USBD_CtlError(pdev, req); + ret = USBD_FAIL; + } + break; + + case BOT_RESET : + if ((req->wValue == 0U) && (req->wLength == 0U) && + ((req->bmRequest & 0x80U) != 0x80U)) + { + MSC_BOT_Reset(pdev); + } + else + { + USBD_CtlError(pdev, req); + ret = USBD_FAIL; + } + break; + + default: + USBD_CtlError(pdev, req); + ret = USBD_FAIL; break; + } + break; /* Interface & Endpoint request */ - case USB_REQ_TYPE_STANDARD: - switch (req->bRequest) + case USB_REQ_TYPE_STANDARD: + switch (req->bRequest) + { + case USB_REQ_GET_STATUS: + if (pdev->dev_state == USBD_STATE_CONFIGURED) + { + (void)USBD_CtlSendData(pdev, (uint8_t *)&status_info, 2U); + } + else + { + USBD_CtlError(pdev, req); + ret = USBD_FAIL; + } + break; + + case USB_REQ_GET_INTERFACE: + if (pdev->dev_state == USBD_STATE_CONFIGURED) + { + (void)USBD_CtlSendData(pdev, (uint8_t *)&hmsc->interface, 1U); + } + else { - case USB_REQ_GET_STATUS: - if (pdev->dev_state == USBD_STATE_CONFIGURED) - { - USBD_CtlSendData(pdev, (uint8_t *)(void *)&status_info, 2U); - } - else - { - USBD_CtlError(pdev, req); - ret = USBD_FAIL; - } - break; - - case USB_REQ_GET_INTERFACE: - if (pdev->dev_state == USBD_STATE_CONFIGURED) - { - USBD_CtlSendData(pdev, (uint8_t *)(void *)&hmsc->interface, 1U); - } - else - { - USBD_CtlError(pdev, req); - ret = USBD_FAIL; - } - break; - - case USB_REQ_SET_INTERFACE: - if (pdev->dev_state == USBD_STATE_CONFIGURED) - { - hmsc->interface = (uint8_t)(req->wValue); - } - else - { - USBD_CtlError(pdev, req); - ret = USBD_FAIL; - } - break; - - case USB_REQ_CLEAR_FEATURE: - - /* Flush the FIFO and Clear the stall status */ - USBD_LL_FlushEP(pdev, (uint8_t)req->wIndex); - - /* Reactivate the EP */ - USBD_LL_CloseEP(pdev, (uint8_t)req->wIndex); - if ((((uint8_t)req->wIndex) & 0x80U) == 0x80U) - { - pdev->ep_in[(uint8_t)req->wIndex & 0xFU].is_used = 0U; - if (pdev->dev_speed == USBD_SPEED_HIGH) - { - /* Open EP IN */ - USBD_LL_OpenEP(pdev, MSC_EPIN_ADDR, USBD_EP_TYPE_BULK, - MSC_MAX_HS_PACKET); - } - else - { - /* Open EP IN */ - USBD_LL_OpenEP(pdev, MSC_EPIN_ADDR, USBD_EP_TYPE_BULK, - MSC_MAX_FS_PACKET); - } - pdev->ep_in[MSC_EPIN_ADDR & 0xFU].is_used = 1U; - } - else - { - pdev->ep_out[(uint8_t)req->wIndex & 0xFU].is_used = 0U; - if (pdev->dev_speed == USBD_SPEED_HIGH) - { - /* Open EP OUT */ - USBD_LL_OpenEP(pdev, MSC_EPOUT_ADDR, USBD_EP_TYPE_BULK, - MSC_MAX_HS_PACKET); - } - else - { - /* Open EP OUT */ - USBD_LL_OpenEP(pdev, MSC_EPOUT_ADDR, USBD_EP_TYPE_BULK, - MSC_MAX_FS_PACKET); - } - pdev->ep_out[MSC_EPOUT_ADDR & 0xFU].is_used = 1U; - } + USBD_CtlError(pdev, req); + ret = USBD_FAIL; + } + break; + + case USB_REQ_SET_INTERFACE: + if (pdev->dev_state == USBD_STATE_CONFIGURED) + { + hmsc->interface = (uint8_t)(req->wValue); + } + else + { + USBD_CtlError(pdev, req); + ret = USBD_FAIL; + } + break; + + case USB_REQ_CLEAR_FEATURE: + if (pdev->dev_state == USBD_STATE_CONFIGURED) + { + if (req->wValue == USB_FEATURE_EP_HALT) + { + /* Flush the FIFO */ + (void)USBD_LL_FlushEP(pdev, (uint8_t)req->wIndex); /* Handle BOT error */ MSC_BOT_CplClrFeature(pdev, (uint8_t)req->wIndex); - break; - - default: - USBD_CtlError(pdev, req); - ret = USBD_FAIL; - break; + } } break; @@ -491,9 +459,16 @@ uint8_t USBD_MSC_Setup(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) USBD_CtlError(pdev, req); ret = USBD_FAIL; break; + } + break; + + default: + USBD_CtlError(pdev, req); + ret = USBD_FAIL; + break; } - return ret; + return (uint8_t)ret; } /** @@ -507,7 +482,7 @@ uint8_t USBD_MSC_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum) { MSC_BOT_DataIn(pdev, epnum); - return USBD_OK; + return (uint8_t)USBD_OK; } /** @@ -521,7 +496,7 @@ uint8_t USBD_MSC_DataOut(USBD_HandleTypeDef *pdev, uint8_t epnum) { MSC_BOT_DataOut(pdev, epnum); - return USBD_OK; + return (uint8_t)USBD_OK; } /** @@ -532,7 +507,7 @@ uint8_t USBD_MSC_DataOut(USBD_HandleTypeDef *pdev, uint8_t epnum) */ uint8_t *USBD_MSC_GetHSCfgDesc(uint16_t *length) { - *length = sizeof(USBD_MSC_CfgHSDesc); + *length = (uint16_t)sizeof(USBD_MSC_CfgHSDesc); return USBD_MSC_CfgHSDesc; } @@ -545,7 +520,7 @@ uint8_t *USBD_MSC_GetHSCfgDesc(uint16_t *length) */ uint8_t *USBD_MSC_GetFSCfgDesc(uint16_t *length) { - *length = sizeof(USBD_MSC_CfgFSDesc); + *length = (uint16_t)sizeof(USBD_MSC_CfgFSDesc); return USBD_MSC_CfgFSDesc; } @@ -558,7 +533,7 @@ uint8_t *USBD_MSC_GetFSCfgDesc(uint16_t *length) */ uint8_t *USBD_MSC_GetOtherSpeedCfgDesc(uint16_t *length) { - *length = sizeof(USBD_MSC_OtherSpeedCfgDesc); + *length = (uint16_t)sizeof(USBD_MSC_OtherSpeedCfgDesc); return USBD_MSC_OtherSpeedCfgDesc; } @@ -570,7 +545,7 @@ uint8_t *USBD_MSC_GetOtherSpeedCfgDesc(uint16_t *length) */ uint8_t *USBD_MSC_GetDeviceQualifierDescriptor(uint16_t *length) { - *length = sizeof(USBD_MSC_DeviceQualifierDesc); + *length = (uint16_t)sizeof(USBD_MSC_DeviceQualifierDesc); return USBD_MSC_DeviceQualifierDesc; } @@ -580,15 +555,16 @@ uint8_t *USBD_MSC_GetDeviceQualifierDescriptor(uint16_t *length) * @param fops: storage callback * @retval status */ -uint8_t USBD_MSC_RegisterStorage(USBD_HandleTypeDef *pdev, - USBD_StorageTypeDef *fops) +uint8_t USBD_MSC_RegisterStorage(USBD_HandleTypeDef *pdev, USBD_StorageTypeDef *fops) { - if (fops != NULL) + if (fops == NULL) { - pdev->pUserData = fops; + return (uint8_t)USBD_FAIL; } - return USBD_OK; + pdev->pUserData = fops; + + return (uint8_t)USBD_OK; } /** diff --git a/system/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Src/usbd_msc_bot.c b/system/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Src/usbd_msc_bot.c index f8c1be8c44..ae68ac055c 100644 --- a/system/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Src/usbd_msc_bot.c +++ b/system/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Src/usbd_msc_bot.c @@ -76,11 +76,9 @@ EndBSPDependencies */ /** @defgroup MSC_BOT_Private_FunctionPrototypes * @{ */ -static void MSC_BOT_CBW_Decode(USBD_HandleTypeDef *pdev); -static void MSC_BOT_SendData(USBD_HandleTypeDef *pdev, uint8_t *pbuf, - uint16_t len); - -static void MSC_BOT_Abort(USBD_HandleTypeDef *pdev); +static void MSC_BOT_SendData(USBD_HandleTypeDef *pdev, uint8_t *pbuf, uint32_t len); +static void MSC_BOT_CBW_Decode(USBD_HandleTypeDef *pdev); +static void MSC_BOT_Abort(USBD_HandleTypeDef *pdev); /** * @} */ @@ -91,31 +89,31 @@ static void MSC_BOT_Abort(USBD_HandleTypeDef *pdev); */ - /** * @brief MSC_BOT_Init * Initialize the BOT Process * @param pdev: device instance * @retval None */ -void MSC_BOT_Init(USBD_HandleTypeDef *pdev) +void MSC_BOT_Init(USBD_HandleTypeDef *pdev) { - USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef *)pdev->pClassData; + USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef *)pdev->pClassData; hmsc->bot_state = USBD_BOT_IDLE; hmsc->bot_status = USBD_BOT_STATUS_NORMAL; hmsc->scsi_sense_tail = 0U; hmsc->scsi_sense_head = 0U; + hmsc->scsi_medium_state = SCSI_MEDIUM_UNLOCKED; ((USBD_StorageTypeDef *)pdev->pUserData)->Init(0U); - USBD_LL_FlushEP(pdev, MSC_EPOUT_ADDR); - USBD_LL_FlushEP(pdev, MSC_EPIN_ADDR); + (void)USBD_LL_FlushEP(pdev, MSC_EPOUT_ADDR); + (void)USBD_LL_FlushEP(pdev, MSC_EPIN_ADDR); /* Prapare EP to Receive First BOT Cmd */ - USBD_LL_PrepareReceive(pdev, MSC_EPOUT_ADDR, (uint8_t *)(void *)&hmsc->cbw, - USBD_BOT_CBW_LENGTH); + (void)USBD_LL_PrepareReceive(pdev, MSC_EPOUT_ADDR, (uint8_t *)&hmsc->cbw, + USBD_BOT_CBW_LENGTH); } /** @@ -124,16 +122,19 @@ void MSC_BOT_Init(USBD_HandleTypeDef *pdev) * @param pdev: device instance * @retval None */ -void MSC_BOT_Reset(USBD_HandleTypeDef *pdev) +void MSC_BOT_Reset(USBD_HandleTypeDef *pdev) { - USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef *)pdev->pClassData; + USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef *)pdev->pClassData; hmsc->bot_state = USBD_BOT_IDLE; hmsc->bot_status = USBD_BOT_STATUS_RECOVERY; + (void)USBD_LL_ClearStallEP(pdev, MSC_EPIN_ADDR); + (void)USBD_LL_ClearStallEP(pdev, MSC_EPOUT_ADDR); + /* Prapare EP to Receive First BOT Cmd */ - USBD_LL_PrepareReceive(pdev, MSC_EPOUT_ADDR, (uint8_t *)(void *)&hmsc->cbw, - USBD_BOT_CBW_LENGTH); + (void)USBD_LL_PrepareReceive(pdev, MSC_EPOUT_ADDR, (uint8_t *)&hmsc->cbw, + USBD_BOT_CBW_LENGTH); } /** @@ -144,7 +145,7 @@ void MSC_BOT_Reset(USBD_HandleTypeDef *pdev) */ void MSC_BOT_DeInit(USBD_HandleTypeDef *pdev) { - USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef *)pdev->pClassData; + USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef *)pdev->pClassData; hmsc->bot_state = USBD_BOT_IDLE; } @@ -155,27 +156,28 @@ void MSC_BOT_DeInit(USBD_HandleTypeDef *pdev) * @param epnum: endpoint index * @retval None */ -void MSC_BOT_DataIn(USBD_HandleTypeDef *pdev, - uint8_t epnum) +void MSC_BOT_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum) { - USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef *)pdev->pClassData; + UNUSED(epnum); + + USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef *)pdev->pClassData; switch (hmsc->bot_state) { - case USBD_BOT_DATA_IN: - if (SCSI_ProcessCmd(pdev, hmsc->cbw.bLUN, &hmsc->cbw.CB[0]) < 0) - { - MSC_BOT_SendCSW(pdev, USBD_CSW_CMD_FAILED); - } - break; + case USBD_BOT_DATA_IN: + if (SCSI_ProcessCmd(pdev, hmsc->cbw.bLUN, &hmsc->cbw.CB[0]) < 0) + { + MSC_BOT_SendCSW(pdev, USBD_CSW_CMD_FAILED); + } + break; - case USBD_BOT_SEND_DATA: - case USBD_BOT_LAST_DATA_IN: - MSC_BOT_SendCSW(pdev, USBD_CSW_CMD_PASSED); - break; + case USBD_BOT_SEND_DATA: + case USBD_BOT_LAST_DATA_IN: + MSC_BOT_SendCSW(pdev, USBD_CSW_CMD_PASSED); + break; - default: - break; + default: + break; } } /** @@ -185,10 +187,11 @@ void MSC_BOT_DataIn(USBD_HandleTypeDef *pdev, * @param epnum: endpoint index * @retval None */ -void MSC_BOT_DataOut(USBD_HandleTypeDef *pdev, - uint8_t epnum) +void MSC_BOT_DataOut(USBD_HandleTypeDef *pdev, uint8_t epnum) { - USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef *)pdev->pClassData; + UNUSED(epnum); + + USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef *)pdev->pClassData; switch (hmsc->bot_state) { @@ -197,7 +200,6 @@ void MSC_BOT_DataOut(USBD_HandleTypeDef *pdev, break; case USBD_BOT_DATA_OUT: - if (SCSI_ProcessCmd(pdev, hmsc->cbw.bLUN, &hmsc->cbw.CB[0]) < 0) { MSC_BOT_SendCSW(pdev, USBD_CSW_CMD_FAILED); @@ -215,19 +217,18 @@ void MSC_BOT_DataOut(USBD_HandleTypeDef *pdev, * @param pdev: device instance * @retval None */ -static void MSC_BOT_CBW_Decode(USBD_HandleTypeDef *pdev) +static void MSC_BOT_CBW_Decode(USBD_HandleTypeDef *pdev) { - USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef *)pdev->pClassData; + USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef *)pdev->pClassData; hmsc->csw.dTag = hmsc->cbw.dTag; hmsc->csw.dDataResidue = hmsc->cbw.dDataLength; if ((USBD_LL_GetRxDataSize(pdev, MSC_EPOUT_ADDR) != USBD_BOT_CBW_LENGTH) || (hmsc->cbw.dSignature != USBD_BOT_CBW_SIGNATURE) || - (hmsc->cbw.bLUN > 1U) || - (hmsc->cbw.bCBLength < 1U) || (hmsc->cbw.bCBLength > 16U)) + (hmsc->cbw.bLUN > 1U) || (hmsc->cbw.bCBLength < 1U) || + (hmsc->cbw.bCBLength > 16U)) { - SCSI_SenseCode(pdev, hmsc->cbw.bLUN, ILLEGAL_REQUEST, INVALID_CDB); hmsc->bot_status = USBD_BOT_STATUS_ERROR; @@ -246,7 +247,7 @@ static void MSC_BOT_CBW_Decode(USBD_HandleTypeDef *pdev) MSC_BOT_Abort(pdev); } } - /*Burst xfer handled internally*/ + /* Burst xfer handled internally */ else if ((hmsc->bot_state != USBD_BOT_DATA_IN) && (hmsc->bot_state != USBD_BOT_DATA_OUT) && (hmsc->bot_state != USBD_BOT_LAST_DATA_IN)) @@ -279,18 +280,17 @@ static void MSC_BOT_CBW_Decode(USBD_HandleTypeDef *pdev) * @param len: Data Length * @retval None */ -static void MSC_BOT_SendData(USBD_HandleTypeDef *pdev, uint8_t *pbuf, - uint16_t len) +static void MSC_BOT_SendData(USBD_HandleTypeDef *pdev, uint8_t *pbuf, uint32_t len) { - USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef *)pdev->pClassData; + USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef *)pdev->pClassData; - uint16_t length = (uint16_t)MIN(hmsc->cbw.dDataLength, len); + uint32_t length = MIN(hmsc->cbw.dDataLength, len); hmsc->csw.dDataResidue -= len; hmsc->csw.bStatus = USBD_CSW_CMD_PASSED; hmsc->bot_state = USBD_BOT_SEND_DATA; - USBD_LL_Transmit(pdev, MSC_EPIN_ADDR, pbuf, length); + (void)USBD_LL_Transmit(pdev, MSC_EPIN_ADDR, pbuf, length); } /** @@ -300,21 +300,20 @@ static void MSC_BOT_SendData(USBD_HandleTypeDef *pdev, uint8_t *pbuf, * @param status : CSW status * @retval None */ -void MSC_BOT_SendCSW(USBD_HandleTypeDef *pdev, - uint8_t CSW_Status) +void MSC_BOT_SendCSW(USBD_HandleTypeDef *pdev, uint8_t CSW_Status) { - USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef *)pdev->pClassData; + USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef *)pdev->pClassData; hmsc->csw.dSignature = USBD_BOT_CSW_SIGNATURE; hmsc->csw.bStatus = CSW_Status; hmsc->bot_state = USBD_BOT_IDLE; - USBD_LL_Transmit(pdev, MSC_EPIN_ADDR, (uint8_t *)(void *)&hmsc->csw, - USBD_BOT_CSW_LENGTH); + (void)USBD_LL_Transmit(pdev, MSC_EPIN_ADDR, (uint8_t *)&hmsc->csw, + USBD_BOT_CSW_LENGTH); /* Prepare EP to Receive next Cmd */ - USBD_LL_PrepareReceive(pdev, MSC_EPOUT_ADDR, (uint8_t *)(void *)&hmsc->cbw, - USBD_BOT_CBW_LENGTH); + (void)USBD_LL_PrepareReceive(pdev, MSC_EPOUT_ADDR, (uint8_t *)&hmsc->cbw, + USBD_BOT_CBW_LENGTH); } /** @@ -324,23 +323,23 @@ void MSC_BOT_SendCSW(USBD_HandleTypeDef *pdev, * @retval status */ -static void MSC_BOT_Abort(USBD_HandleTypeDef *pdev) +static void MSC_BOT_Abort(USBD_HandleTypeDef *pdev) { - USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef *)pdev->pClassData; + USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef *)pdev->pClassData; if ((hmsc->cbw.bmFlags == 0U) && (hmsc->cbw.dDataLength != 0U) && (hmsc->bot_status == USBD_BOT_STATUS_NORMAL)) { - USBD_LL_StallEP(pdev, MSC_EPOUT_ADDR); + (void)USBD_LL_StallEP(pdev, MSC_EPOUT_ADDR); } - USBD_LL_StallEP(pdev, MSC_EPIN_ADDR); + (void)USBD_LL_StallEP(pdev, MSC_EPIN_ADDR); if (hmsc->bot_status == USBD_BOT_STATUS_ERROR) { - USBD_LL_PrepareReceive(pdev, MSC_EPOUT_ADDR, (uint8_t *)(void *)&hmsc->cbw, - USBD_BOT_CBW_LENGTH); + (void)USBD_LL_StallEP(pdev, MSC_EPIN_ADDR); + (void)USBD_LL_StallEP(pdev, MSC_EPOUT_ADDR); } } @@ -352,14 +351,14 @@ static void MSC_BOT_Abort(USBD_HandleTypeDef *pdev) * @retval None */ -void MSC_BOT_CplClrFeature(USBD_HandleTypeDef *pdev, uint8_t epnum) +void MSC_BOT_CplClrFeature(USBD_HandleTypeDef *pdev, uint8_t epnum) { - USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef *)pdev->pClassData; + USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef *)pdev->pClassData; if (hmsc->bot_status == USBD_BOT_STATUS_ERROR) /* Bad CBW Signature */ { - USBD_LL_StallEP(pdev, MSC_EPIN_ADDR); - hmsc->bot_status = USBD_BOT_STATUS_NORMAL; + (void)USBD_LL_StallEP(pdev, MSC_EPIN_ADDR); + (void)USBD_LL_StallEP(pdev, MSC_EPOUT_ADDR); } else if (((epnum & 0x80U) == 0x80U) && (hmsc->bot_status != USBD_BOT_STATUS_RECOVERY)) { diff --git a/system/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Src/usbd_msc_data.c b/system/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Src/usbd_msc_data.c index aaafc3aa1e..d1c3a9772d 100644 --- a/system/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Src/usbd_msc_data.c +++ b/system/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Src/usbd_msc_data.c @@ -65,21 +65,48 @@ EndBSPDependencies */ * @{ */ - /* USB Mass storage Page 0 Inquiry Data */ -const uint8_t MSC_Page00_Inquiry_Data[] = +uint8_t MSC_Page00_Inquiry_Data[LENGTH_INQUIRY_PAGE00] = { 0x00, 0x00, 0x00, (LENGTH_INQUIRY_PAGE00 - 4U), 0x00, - 0x80, - 0x83 + 0x80 }; -/* USB Mass storage sense 6 Data */ -const uint8_t MSC_Mode_Sense6_data[] = + +/* USB Mass storage VPD Page 0x80 Inquiry Data for Unit Serial Number */ +uint8_t MSC_Page80_Inquiry_Data[LENGTH_INQUIRY_PAGE80] = +{ + 0x00, + 0x80, + 0x00, + LENGTH_INQUIRY_PAGE80, + 0x20, /* Put Product Serial number */ + 0x20, + 0x20, + 0x20 + }; + +/* USB Mass storage sense 6 Data */ +uint8_t MSC_Mode_Sense6_data[MODE_SENSE6_LEN] = { + 0x22, + 0x00, + 0x00, + 0x00, + 0x08, + 0x12, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, 0x00, 0x00, 0x00, @@ -89,11 +116,32 @@ const uint8_t MSC_Mode_Sense6_data[] = 0x00, 0x00 }; + + /* USB Mass storage sense 10 Data */ -const uint8_t MSC_Mode_Sense10_data[] = +uint8_t MSC_Mode_Sense10_data[MODE_SENSE10_LEN] = { 0x00, - 0x06, + 0x26, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x08, + 0x12, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, 0x00, 0x00, 0x00, diff --git a/system/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Src/usbd_msc_scsi.c b/system/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Src/usbd_msc_scsi.c index 78032c7622..5c36a6e8c8 100644 --- a/system/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Src/usbd_msc_scsi.c +++ b/system/Middlewares/ST/STM32_USB_Device_Library/Class/MSC/Src/usbd_msc_scsi.c @@ -30,7 +30,6 @@ EndBSPDependencies */ #include "usbd_msc_data.h" - /** @addtogroup STM32_USB_DEVICE_LIBRARY * @{ */ @@ -82,18 +81,25 @@ static int8_t SCSI_TestUnitReady(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t static int8_t SCSI_Inquiry(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *params); static int8_t SCSI_ReadFormatCapacity(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *params); static int8_t SCSI_ReadCapacity10(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *params); +static int8_t SCSI_ReadCapacity16(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *params); static int8_t SCSI_RequestSense(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *params); static int8_t SCSI_StartStopUnit(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *params); +static int8_t SCSI_AllowPreventRemovable(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *params); static int8_t SCSI_ModeSense6(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *params); static int8_t SCSI_ModeSense10(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *params); static int8_t SCSI_Write10(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *params); +static int8_t SCSI_Write12(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *params); static int8_t SCSI_Read10(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *params); +static int8_t SCSI_Read12(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *params); static int8_t SCSI_Verify10(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *params); static int8_t SCSI_CheckAddressRange(USBD_HandleTypeDef *pdev, uint8_t lun, uint32_t blk_offset, uint32_t blk_nbr); static int8_t SCSI_ProcessRead(USBD_HandleTypeDef *pdev, uint8_t lun); static int8_t SCSI_ProcessWrite(USBD_HandleTypeDef *pdev, uint8_t lun); + +static int8_t SCSI_UpdateBotData(USBD_MSC_BOT_HandleTypeDef *hmsc, + uint8_t *pBuff, uint16_t length); /** * @} */ @@ -114,61 +120,79 @@ static int8_t SCSI_ProcessWrite(USBD_HandleTypeDef *pdev, uint8_t lun); */ int8_t SCSI_ProcessCmd(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *cmd) { + int8_t ret; + USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef *)pdev->pClassData; + switch (cmd[0]) { - case SCSI_TEST_UNIT_READY: - SCSI_TestUnitReady(pdev, lun, cmd); - break; - - case SCSI_REQUEST_SENSE: - SCSI_RequestSense(pdev, lun, cmd); - break; - case SCSI_INQUIRY: - SCSI_Inquiry(pdev, lun, cmd); - break; - - case SCSI_START_STOP_UNIT: - SCSI_StartStopUnit(pdev, lun, cmd); - break; - - case SCSI_ALLOW_MEDIUM_REMOVAL: - SCSI_StartStopUnit(pdev, lun, cmd); - break; - - case SCSI_MODE_SENSE6: - SCSI_ModeSense6(pdev, lun, cmd); - break; - - case SCSI_MODE_SENSE10: - SCSI_ModeSense10(pdev, lun, cmd); - break; - - case SCSI_READ_FORMAT_CAPACITIES: - SCSI_ReadFormatCapacity(pdev, lun, cmd); - break; - - case SCSI_READ_CAPACITY10: - SCSI_ReadCapacity10(pdev, lun, cmd); - break; - - case SCSI_READ10: - SCSI_Read10(pdev, lun, cmd); - break; - - case SCSI_WRITE10: - SCSI_Write10(pdev, lun, cmd); - break; - - case SCSI_VERIFY10: - SCSI_Verify10(pdev, lun, cmd); - break; - - default: - SCSI_SenseCode(pdev, lun, ILLEGAL_REQUEST, INVALID_CDB); - return -1; + case SCSI_TEST_UNIT_READY: + ret = SCSI_TestUnitReady(pdev, lun, cmd); + break; + + case SCSI_REQUEST_SENSE: + ret = SCSI_RequestSense(pdev, lun, cmd); + break; + + case SCSI_INQUIRY: + ret = SCSI_Inquiry(pdev, lun, cmd); + break; + + case SCSI_START_STOP_UNIT: + ret = SCSI_StartStopUnit(pdev, lun, cmd); + break; + + case SCSI_ALLOW_MEDIUM_REMOVAL: + ret = SCSI_AllowPreventRemovable(pdev, lun, cmd); + break; + + case SCSI_MODE_SENSE6: + ret = SCSI_ModeSense6(pdev, lun, cmd); + break; + + case SCSI_MODE_SENSE10: + ret = SCSI_ModeSense10(pdev, lun, cmd); + break; + + case SCSI_READ_FORMAT_CAPACITIES: + ret = SCSI_ReadFormatCapacity(pdev, lun, cmd); + break; + + case SCSI_READ_CAPACITY10: + ret = SCSI_ReadCapacity10(pdev, lun, cmd); + break; + + case SCSI_READ_CAPACITY16: + ret = SCSI_ReadCapacity16(pdev, lun, cmd); + break; + + case SCSI_READ10: + ret = SCSI_Read10(pdev, lun, cmd); + break; + + case SCSI_READ12: + ret = SCSI_Read12(pdev, lun, cmd); + break; + + case SCSI_WRITE10: + ret = SCSI_Write10(pdev, lun, cmd); + break; + + case SCSI_WRITE12: + ret = SCSI_Write12(pdev, lun, cmd); + break; + + case SCSI_VERIFY10: + ret = SCSI_Verify10(pdev, lun, cmd); + break; + + default: + SCSI_SenseCode(pdev, lun, ILLEGAL_REQUEST, INVALID_CDB); + hmsc->bot_status = USBD_BOT_STATUS_ERROR; + ret = -1; + break; } - return 0; + return ret; } @@ -179,9 +203,10 @@ int8_t SCSI_ProcessCmd(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *cmd) * @param params: Command parameters * @retval status */ -static int8_t SCSI_TestUnitReady(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *params) +static int8_t SCSI_TestUnitReady(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *params) { - USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef *)pdev->pClassData; + UNUSED(params); + USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef *)pdev->pClassData; /* case 9 : Hi > D0 */ if (hmsc->cbw.dDataLength != 0U) @@ -191,6 +216,13 @@ static int8_t SCSI_TestUnitReady(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t return -1; } + if (hmsc->scsi_medium_state == SCSI_MEDIUM_EJECTED) + { + SCSI_SenseCode(pdev, lun, NOT_READY, MEDIUM_NOT_PRESENT); + hmsc->bot_state = USBD_BOT_NO_DATA; + return -1; + } + if (((USBD_StorageTypeDef *)pdev->pUserData)->IsReady(lun) != 0) { SCSI_SenseCode(pdev, lun, NOT_READY, MEDIUM_NOT_PRESENT); @@ -203,6 +235,7 @@ static int8_t SCSI_TestUnitReady(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t return 0; } + /** * @brief SCSI_Inquiry * Process Inquiry command @@ -210,44 +243,53 @@ static int8_t SCSI_TestUnitReady(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t * @param params: Command parameters * @retval status */ -static int8_t SCSI_Inquiry(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *params) +static int8_t SCSI_Inquiry(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *params) { uint8_t *pPage; uint16_t len; - USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef *)pdev->pClassData; + USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef *)pdev->pClassData; - if (params[1] & 0x01U)/*Evpd is set*/ + if (hmsc->cbw.dDataLength == 0U) { - len = LENGTH_INQUIRY_PAGE00; - hmsc->bot_data_length = len; + SCSI_SenseCode(pdev, hmsc->cbw.bLUN, ILLEGAL_REQUEST, INVALID_CDB); + return -1; + } - while (len) + if ((params[1] & 0x01U) != 0U) /* Evpd is set */ + { + if (params[2] == 0U) /* Request for Supported Vital Product Data Pages*/ + { + (void)SCSI_UpdateBotData(hmsc, MSC_Page00_Inquiry_Data, LENGTH_INQUIRY_PAGE00); + } + else if (params[2] == 0x80U) /* Request for VPD page 0x80 Unit Serial Number */ + { + (void)SCSI_UpdateBotData(hmsc, MSC_Page80_Inquiry_Data, LENGTH_INQUIRY_PAGE80); + } + else /* Request Not supported */ { - len--; - hmsc->bot_data[len] = MSC_Page00_Inquiry_Data[len]; + SCSI_SenseCode(pdev, hmsc->cbw.bLUN, ILLEGAL_REQUEST, + INVALID_FIELED_IN_COMMAND); + + return -1; } } else { - pPage = (uint8_t *)(void *) & ((USBD_StorageTypeDef *)pdev->pUserData)->pInquiry[lun * STANDARD_INQUIRY_DATA_LEN]; + pPage = (uint8_t *)&((USBD_StorageTypeDef *)pdev->pUserData)->pInquiry[lun * STANDARD_INQUIRY_DATA_LEN]; len = (uint16_t)pPage[4] + 5U; if (params[4] <= len) { len = params[4]; } - hmsc->bot_data_length = len; - while (len) - { - len--; - hmsc->bot_data[len] = pPage[len]; - } + (void)SCSI_UpdateBotData(hmsc, pPage, len); } return 0; } + /** * @brief SCSI_ReadCapacity10 * Process Read Capacity 10 command @@ -255,32 +297,88 @@ static int8_t SCSI_Inquiry(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *par * @param params: Command parameters * @retval status */ -static int8_t SCSI_ReadCapacity10(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *params) +static int8_t SCSI_ReadCapacity10(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *params) +{ + UNUSED(params); + int8_t ret; + USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef *)pdev->pClassData; + + ret = ((USBD_StorageTypeDef *)pdev->pUserData)->GetCapacity(lun, &hmsc->scsi_blk_nbr, &hmsc->scsi_blk_size); + + if ((ret != 0) || (hmsc->scsi_medium_state == SCSI_MEDIUM_EJECTED)) + { + SCSI_SenseCode(pdev, lun, NOT_READY, MEDIUM_NOT_PRESENT); + return -1; + } + + hmsc->bot_data[0] = (uint8_t)((hmsc->scsi_blk_nbr - 1U) >> 24); + hmsc->bot_data[1] = (uint8_t)((hmsc->scsi_blk_nbr - 1U) >> 16); + hmsc->bot_data[2] = (uint8_t)((hmsc->scsi_blk_nbr - 1U) >> 8); + hmsc->bot_data[3] = (uint8_t)(hmsc->scsi_blk_nbr - 1U); + + hmsc->bot_data[4] = (uint8_t)(hmsc->scsi_blk_size >> 24); + hmsc->bot_data[5] = (uint8_t)(hmsc->scsi_blk_size >> 16); + hmsc->bot_data[6] = (uint8_t)(hmsc->scsi_blk_size >> 8); + hmsc->bot_data[7] = (uint8_t)(hmsc->scsi_blk_size); + + hmsc->bot_data_length = 8U; + + return 0; + +} + + +/** +* @brief SCSI_ReadCapacity16 +* Process Read Capacity 16 command +* @param lun: Logical unit number +* @param params: Command parameters +* @retval status +*/ +static int8_t SCSI_ReadCapacity16(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *params) { - USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef *)pdev->pClassData; + UNUSED(params); + uint8_t idx; + int8_t ret; + USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef *)pdev->pClassData; - if (((USBD_StorageTypeDef *)pdev->pUserData)->GetCapacity(lun, &hmsc->scsi_blk_nbr, &hmsc->scsi_blk_size) != 0) + ret = ((USBD_StorageTypeDef *)pdev->pUserData)->GetCapacity(lun, &hmsc->scsi_blk_nbr, &hmsc->scsi_blk_size); + + if ((ret != 0) || (hmsc->scsi_medium_state == SCSI_MEDIUM_EJECTED)) { SCSI_SenseCode(pdev, lun, NOT_READY, MEDIUM_NOT_PRESENT); return -1; } - else + + hmsc->bot_data_length = ((uint32_t)params[10] << 24) | + ((uint32_t)params[11] << 16) | + ((uint32_t)params[12] << 8) | + (uint32_t)params[13]; + + for (idx = 0U; idx < hmsc->bot_data_length; idx++) { + hmsc->bot_data[idx] = 0U; + } - hmsc->bot_data[0] = (uint8_t)((hmsc->scsi_blk_nbr - 1U) >> 24); - hmsc->bot_data[1] = (uint8_t)((hmsc->scsi_blk_nbr - 1U) >> 16); - hmsc->bot_data[2] = (uint8_t)((hmsc->scsi_blk_nbr - 1U) >> 8); - hmsc->bot_data[3] = (uint8_t)(hmsc->scsi_blk_nbr - 1U); + hmsc->bot_data[4] = (uint8_t)((hmsc->scsi_blk_nbr - 1U) >> 24); + hmsc->bot_data[5] = (uint8_t)((hmsc->scsi_blk_nbr - 1U) >> 16); + hmsc->bot_data[6] = (uint8_t)((hmsc->scsi_blk_nbr - 1U) >> 8); + hmsc->bot_data[7] = (uint8_t)(hmsc->scsi_blk_nbr - 1U); - hmsc->bot_data[4] = (uint8_t)(hmsc->scsi_blk_size >> 24); - hmsc->bot_data[5] = (uint8_t)(hmsc->scsi_blk_size >> 16); - hmsc->bot_data[6] = (uint8_t)(hmsc->scsi_blk_size >> 8); - hmsc->bot_data[7] = (uint8_t)(hmsc->scsi_blk_size); + hmsc->bot_data[8] = (uint8_t)(hmsc->scsi_blk_size >> 24); + hmsc->bot_data[9] = (uint8_t)(hmsc->scsi_blk_size >> 16); + hmsc->bot_data[10] = (uint8_t)(hmsc->scsi_blk_size >> 8); + hmsc->bot_data[11] = (uint8_t)(hmsc->scsi_blk_size); - hmsc->bot_data_length = 8U; - return 0; - } + hmsc->bot_data_length = ((uint32_t)params[10] << 24) | + ((uint32_t)params[11] << 16) | + ((uint32_t)params[12] << 8) | + (uint32_t)params[13]; + + return 0; } + + /** * @brief SCSI_ReadFormatCapacity * Process Read Format Capacity command @@ -288,41 +386,45 @@ static int8_t SCSI_ReadCapacity10(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_ * @param params: Command parameters * @retval status */ -static int8_t SCSI_ReadFormatCapacity(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *params) +static int8_t SCSI_ReadFormatCapacity(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *params) { - USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef *)pdev->pClassData; - + UNUSED(params); uint16_t blk_size; uint32_t blk_nbr; uint16_t i; + int8_t ret; + USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef *)pdev->pClassData; - for (i = 0U; i < 12U ; i++) - { - hmsc->bot_data[i] = 0U; - } + ret = ((USBD_StorageTypeDef *)pdev->pUserData)->GetCapacity(lun, &blk_nbr, &blk_size); - if (((USBD_StorageTypeDef *)pdev->pUserData)->GetCapacity(lun, &blk_nbr, &blk_size) != 0U) + if ((ret != 0) || (hmsc->scsi_medium_state == SCSI_MEDIUM_EJECTED)) { SCSI_SenseCode(pdev, lun, NOT_READY, MEDIUM_NOT_PRESENT); return -1; } - else + + for (i = 0U; i < 12U ; i++) { - hmsc->bot_data[3] = 0x08U; - hmsc->bot_data[4] = (uint8_t)((blk_nbr - 1U) >> 24); - hmsc->bot_data[5] = (uint8_t)((blk_nbr - 1U) >> 16); - hmsc->bot_data[6] = (uint8_t)((blk_nbr - 1U) >> 8); - hmsc->bot_data[7] = (uint8_t)(blk_nbr - 1U); + hmsc->bot_data[i] = 0U; + } - hmsc->bot_data[8] = 0x02U; - hmsc->bot_data[9] = (uint8_t)(blk_size >> 16); - hmsc->bot_data[10] = (uint8_t)(blk_size >> 8); - hmsc->bot_data[11] = (uint8_t)(blk_size); + hmsc->bot_data[3] = 0x08U; + hmsc->bot_data[4] = (uint8_t)((blk_nbr - 1U) >> 24); + hmsc->bot_data[5] = (uint8_t)((blk_nbr - 1U) >> 16); + hmsc->bot_data[6] = (uint8_t)((blk_nbr - 1U) >> 8); + hmsc->bot_data[7] = (uint8_t)(blk_nbr - 1U); - hmsc->bot_data_length = 12U; - return 0; - } + hmsc->bot_data[8] = 0x02U; + hmsc->bot_data[9] = (uint8_t)(blk_size >> 16); + hmsc->bot_data[10] = (uint8_t)(blk_size >> 8); + hmsc->bot_data[11] = (uint8_t)(blk_size); + + hmsc->bot_data_length = 12U; + + return 0; } + + /** * @brief SCSI_ModeSense6 * Process Mode Sense6 command @@ -330,20 +432,23 @@ static int8_t SCSI_ReadFormatCapacity(USBD_HandleTypeDef *pdev, uint8_t lun, ui * @param params: Command parameters * @retval status */ -static int8_t SCSI_ModeSense6(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *params) +static int8_t SCSI_ModeSense6(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *params) { - USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef *)pdev->pClassData; - uint16_t len = 8U; - hmsc->bot_data_length = len; + UNUSED(lun); + USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef *)pdev->pClassData; + uint16_t len = MODE_SENSE6_LEN; - while (len) + if (params[4] <= len) { - len--; - hmsc->bot_data[len] = MSC_Mode_Sense6_data[len]; + len = params[4]; } + + (void)SCSI_UpdateBotData(hmsc, MSC_Mode_Sense6_data, len); + return 0; } + /** * @brief SCSI_ModeSense10 * Process Mode Sense10 command @@ -351,22 +456,23 @@ static int8_t SCSI_ModeSense6(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *p * @param params: Command parameters * @retval status */ -static int8_t SCSI_ModeSense10(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *params) +static int8_t SCSI_ModeSense10(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *params) { - uint16_t len = 8U; - USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef *)pdev->pClassData; - - hmsc->bot_data_length = len; + UNUSED(lun); + USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef *)pdev->pClassData; + uint16_t len = MODE_SENSE10_LEN; - while (len) + if (params[8] <= len) { - len--; - hmsc->bot_data[len] = MSC_Mode_Sense10_data[len]; + len = params[8]; } + (void)SCSI_UpdateBotData(hmsc, MSC_Mode_Sense10_data, len); + return 0; } + /** * @brief SCSI_RequestSense * Process Request Sense command @@ -374,13 +480,19 @@ static int8_t SCSI_ModeSense10(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t * * @param params: Command parameters * @retval status */ - -static int8_t SCSI_RequestSense(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *params) +static int8_t SCSI_RequestSense(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *params) { + UNUSED(lun); uint8_t i; - USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef *)pdev->pClassData; + USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef *)pdev->pClassData; - for (i = 0U ; i < REQUEST_SENSE_DATA_LEN; i++) + if (hmsc->cbw.dDataLength == 0U) + { + SCSI_SenseCode(pdev, hmsc->cbw.bLUN, ILLEGAL_REQUEST, INVALID_CDB); + return -1; + } + + for (i = 0U; i < REQUEST_SENSE_DATA_LEN; i++) { hmsc->bot_data[i] = 0U; } @@ -390,10 +502,9 @@ static int8_t SCSI_RequestSense(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t if ((hmsc->scsi_sense_head != hmsc->scsi_sense_tail)) { - - hmsc->bot_data[2] = hmsc->scsi_sense[hmsc->scsi_sense_head].Skey; - hmsc->bot_data[12] = hmsc->scsi_sense[hmsc->scsi_sense_head].w.b.ASCQ; - hmsc->bot_data[13] = hmsc->scsi_sense[hmsc->scsi_sense_head].w.b.ASC; + hmsc->bot_data[2] = (uint8_t)hmsc->scsi_sense[hmsc->scsi_sense_head].Skey; + hmsc->bot_data[12] = (uint8_t)hmsc->scsi_sense[hmsc->scsi_sense_head].w.b.ASC; + hmsc->bot_data[13] = (uint8_t)hmsc->scsi_sense[hmsc->scsi_sense_head].w.b.ASCQ; hmsc->scsi_sense_head++; if (hmsc->scsi_sense_head == SENSE_LIST_DEEPTH) @@ -401,36 +512,44 @@ static int8_t SCSI_RequestSense(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t hmsc->scsi_sense_head = 0U; } } + hmsc->bot_data_length = REQUEST_SENSE_DATA_LEN; if (params[4] <= REQUEST_SENSE_DATA_LEN) { hmsc->bot_data_length = params[4]; } + return 0; } + /** * @brief SCSI_SenseCode * Load the last error code in the error list * @param lun: Logical unit number * @param sKey: Sense Key -* @param ASC: Additional Sense Key +* @param ASC: Additional Sense Code * @retval none */ -void SCSI_SenseCode(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t sKey, uint8_t ASC) +void SCSI_SenseCode(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t sKey, uint8_t ASC) { - USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef *)pdev->pClassData; + UNUSED(lun); + USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef *)pdev->pClassData; - hmsc->scsi_sense[hmsc->scsi_sense_tail].Skey = sKey; - hmsc->scsi_sense[hmsc->scsi_sense_tail].w.ASC = ASC << 8; + hmsc->scsi_sense[hmsc->scsi_sense_tail].Skey = sKey; + hmsc->scsi_sense[hmsc->scsi_sense_tail].w.b.ASC = ASC; + hmsc->scsi_sense[hmsc->scsi_sense_tail].w.b.ASCQ = 0U; hmsc->scsi_sense_tail++; + if (hmsc->scsi_sense_tail == SENSE_LIST_DEEPTH) { hmsc->scsi_sense_tail = 0U; } } + + /** * @brief SCSI_StartStopUnit * Process Start Stop Unit command @@ -438,13 +557,67 @@ void SCSI_SenseCode(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t sKey, uint8_ * @param params: Command parameters * @retval status */ -static int8_t SCSI_StartStopUnit(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *params) +static int8_t SCSI_StartStopUnit(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *params) { - USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef *) pdev->pClassData; + UNUSED(lun); + USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef *)pdev->pClassData; + + if ((hmsc->scsi_medium_state == SCSI_MEDIUM_LOCKED) && ((params[4] & 0x3U) == 2U)) + { + SCSI_SenseCode(pdev, lun, ILLEGAL_REQUEST, INVALID_FIELED_IN_COMMAND); + + return -1; + } + + if ((params[4] & 0x3U) == 0x1U) /* START=1 */ + { + hmsc->scsi_medium_state = SCSI_MEDIUM_UNLOCKED; + } + else if ((params[4] & 0x3U) == 0x2U) /* START=0 and LOEJ Load Eject=1 */ + { + hmsc->scsi_medium_state = SCSI_MEDIUM_EJECTED; + } + else if ((params[4] & 0x3U) == 0x3U) /* START=1 and LOEJ Load Eject=1 */ + { + hmsc->scsi_medium_state = SCSI_MEDIUM_UNLOCKED; + } + else + { + /* .. */ + } + hmsc->bot_data_length = 0U; + + return 0; +} + + +/** +* @brief SCSI_AllowPreventRemovable +* Process Allow Prevent Removable medium command +* @param lun: Logical unit number +* @param params: Command parameters +* @retval status +*/ +static int8_t SCSI_AllowPreventRemovable(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *params) +{ + UNUSED(lun); + USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef *)pdev->pClassData; + + if (params[4] == 0U) + { + hmsc->scsi_medium_state = SCSI_MEDIUM_UNLOCKED; + } + else + { + hmsc->scsi_medium_state = SCSI_MEDIUM_LOCKED; + } + hmsc->bot_data_length = 0U; + return 0; } + /** * @brief SCSI_Read10 * Process Read10 command @@ -454,7 +627,7 @@ static int8_t SCSI_StartStopUnit(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t */ static int8_t SCSI_Read10(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *params) { - USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef *) pdev->pClassData; + USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef *)pdev->pClassData; if (hmsc->bot_state == USBD_BOT_IDLE) /* Idle */ { @@ -465,6 +638,13 @@ static int8_t SCSI_Read10(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *params return -1; } + if (hmsc->scsi_medium_state == SCSI_MEDIUM_EJECTED) + { + SCSI_SenseCode(pdev, lun, NOT_READY, MEDIUM_NOT_PRESENT); + + return -1; + } + if (((USBD_StorageTypeDef *)pdev->pUserData)->IsReady(lun) != 0) { SCSI_SenseCode(pdev, lun, NOT_READY, MEDIUM_NOT_PRESENT); @@ -484,7 +664,68 @@ static int8_t SCSI_Read10(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *params return -1; /* error */ } + /* cases 4,5 : Hi <> Dn */ + if (hmsc->cbw.dDataLength != (hmsc->scsi_blk_len * hmsc->scsi_blk_size)) + { + SCSI_SenseCode(pdev, hmsc->cbw.bLUN, ILLEGAL_REQUEST, INVALID_CDB); + return -1; + } + hmsc->bot_state = USBD_BOT_DATA_IN; + } + hmsc->bot_data_length = MSC_MEDIA_PACKET; + + return SCSI_ProcessRead(pdev, lun); +} + + +/** +* @brief SCSI_Read12 +* Process Read12 command +* @param lun: Logical unit number +* @param params: Command parameters +* @retval status +*/ +static int8_t SCSI_Read12(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *params) +{ + USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef *)pdev->pClassData; + + if (hmsc->bot_state == USBD_BOT_IDLE) /* Idle */ + { + /* case 10 : Ho <> Di */ + if ((hmsc->cbw.bmFlags & 0x80U) != 0x80U) + { + SCSI_SenseCode(pdev, hmsc->cbw.bLUN, ILLEGAL_REQUEST, INVALID_CDB); + return -1; + } + + if (hmsc->scsi_medium_state == SCSI_MEDIUM_EJECTED) + { + SCSI_SenseCode(pdev, lun, NOT_READY, MEDIUM_NOT_PRESENT); + return -1; + } + + if (((USBD_StorageTypeDef *)pdev->pUserData)->IsReady(lun) != 0) + { + SCSI_SenseCode(pdev, lun, NOT_READY, MEDIUM_NOT_PRESENT); + return -1; + } + + hmsc->scsi_blk_addr = ((uint32_t)params[2] << 24) | + ((uint32_t)params[3] << 16) | + ((uint32_t)params[4] << 8) | + (uint32_t)params[5]; + + hmsc->scsi_blk_len = ((uint32_t)params[6] << 24) | + ((uint32_t)params[7] << 16) | + ((uint32_t)params[8] << 8) | + (uint32_t)params[9]; + + if (SCSI_CheckAddressRange(pdev, lun, hmsc->scsi_blk_addr, + hmsc->scsi_blk_len) < 0) + { + return -1; /* error */ + } /* cases 4,5 : Hi <> Dn */ if (hmsc->cbw.dDataLength != (hmsc->scsi_blk_len * hmsc->scsi_blk_size)) @@ -492,12 +733,15 @@ static int8_t SCSI_Read10(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *params SCSI_SenseCode(pdev, hmsc->cbw.bLUN, ILLEGAL_REQUEST, INVALID_CDB); return -1; } + + hmsc->bot_state = USBD_BOT_DATA_IN; } hmsc->bot_data_length = MSC_MEDIA_PACKET; return SCSI_ProcessRead(pdev, lun); } + /** * @brief SCSI_Write10 * Process Write10 command @@ -505,14 +749,19 @@ static int8_t SCSI_Read10(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *params * @param params: Command parameters * @retval status */ - -static int8_t SCSI_Write10(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *params) +static int8_t SCSI_Write10(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *params) { - USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef *) pdev->pClassData; + USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef *)pdev->pClassData; uint32_t len; if (hmsc->bot_state == USBD_BOT_IDLE) /* Idle */ { + if (hmsc->cbw.dDataLength == 0U) + { + SCSI_SenseCode(pdev, hmsc->cbw.bLUN, ILLEGAL_REQUEST, INVALID_CDB); + return -1; + } + /* case 8 : Hi <> Do */ if ((hmsc->cbw.bmFlags & 0x80U) == 0x80U) { @@ -562,12 +811,97 @@ static int8_t SCSI_Write10(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *para /* Prepare EP to receive first data packet */ hmsc->bot_state = USBD_BOT_DATA_OUT; - USBD_LL_PrepareReceive(pdev, MSC_EPOUT_ADDR, hmsc->bot_data, len); + (void)USBD_LL_PrepareReceive(pdev, MSC_EPOUT_ADDR, hmsc->bot_data, len); + } + else /* Write Process ongoing */ + { + return SCSI_ProcessWrite(pdev, lun); + } + + return 0; +} + + +/** +* @brief SCSI_Write12 +* Process Write12 command +* @param lun: Logical unit number +* @param params: Command parameters +* @retval status +*/ +static int8_t SCSI_Write12(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *params) +{ + USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef *)pdev->pClassData; + uint32_t len; + + if (hmsc->bot_state == USBD_BOT_IDLE) /* Idle */ + { + if (hmsc->cbw.dDataLength == 0U) + { + SCSI_SenseCode(pdev, hmsc->cbw.bLUN, ILLEGAL_REQUEST, INVALID_CDB); + return -1; + } + + /* case 8 : Hi <> Do */ + if ((hmsc->cbw.bmFlags & 0x80U) == 0x80U) + { + SCSI_SenseCode(pdev, hmsc->cbw.bLUN, ILLEGAL_REQUEST, INVALID_CDB); + return -1; + } + + /* Check whether Media is ready */ + if (((USBD_StorageTypeDef *)pdev->pUserData)->IsReady(lun) != 0) + { + SCSI_SenseCode(pdev, lun, NOT_READY, MEDIUM_NOT_PRESENT); + hmsc->bot_state = USBD_BOT_NO_DATA; + return -1; + } + + /* Check If media is write-protected */ + if (((USBD_StorageTypeDef *)pdev->pUserData)->IsWriteProtected(lun) != 0) + { + SCSI_SenseCode(pdev, lun, NOT_READY, WRITE_PROTECTED); + hmsc->bot_state = USBD_BOT_NO_DATA; + return -1; + } + + hmsc->scsi_blk_addr = ((uint32_t)params[2] << 24) | + ((uint32_t)params[3] << 16) | + ((uint32_t)params[4] << 8) | + (uint32_t)params[5]; + + hmsc->scsi_blk_len = ((uint32_t)params[6] << 24) | + ((uint32_t)params[7] << 16) | + ((uint32_t)params[8] << 8) | + (uint32_t)params[9]; + + /* check if LBA address is in the right range */ + if (SCSI_CheckAddressRange(pdev, lun, hmsc->scsi_blk_addr, + hmsc->scsi_blk_len) < 0) + { + return -1; /* error */ + } + + len = hmsc->scsi_blk_len * hmsc->scsi_blk_size; + + /* cases 3,11,13 : Hn,Ho <> D0 */ + if (hmsc->cbw.dDataLength != len) + { + SCSI_SenseCode(pdev, hmsc->cbw.bLUN, ILLEGAL_REQUEST, INVALID_CDB); + return -1; + } + + len = MIN(len, MSC_MEDIA_PACKET); + + /* Prepare EP to receive first data packet */ + hmsc->bot_state = USBD_BOT_DATA_OUT; + (void)USBD_LL_PrepareReceive(pdev, MSC_EPOUT_ADDR, hmsc->bot_data, len); } else /* Write Process ongoing */ { return SCSI_ProcessWrite(pdev, lun); } + return 0; } @@ -579,10 +913,9 @@ static int8_t SCSI_Write10(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *para * @param params: Command parameters * @retval status */ - -static int8_t SCSI_Verify10(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *params) +static int8_t SCSI_Verify10(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *params) { - USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef *) pdev->pClassData; + USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef *)pdev->pClassData; if ((params[1] & 0x02U) == 0x02U) { @@ -590,12 +923,13 @@ static int8_t SCSI_Verify10(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *par return -1; /* Error, Verify Mode Not supported*/ } - if (SCSI_CheckAddressRange(pdev, lun, hmsc->scsi_blk_addr, - hmsc->scsi_blk_len) < 0) + if (SCSI_CheckAddressRange(pdev, lun, hmsc->scsi_blk_addr, hmsc->scsi_blk_len) < 0) { return -1; /* error */ } + hmsc->bot_data_length = 0U; + return 0; } @@ -610,13 +944,14 @@ static int8_t SCSI_Verify10(USBD_HandleTypeDef *pdev, uint8_t lun, uint8_t *par static int8_t SCSI_CheckAddressRange(USBD_HandleTypeDef *pdev, uint8_t lun, uint32_t blk_offset, uint32_t blk_nbr) { - USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef *) pdev->pClassData; + USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef *)pdev->pClassData; if ((blk_offset + blk_nbr) > hmsc->scsi_blk_nbr) { SCSI_SenseCode(pdev, lun, ILLEGAL_REQUEST, ADDRESS_OUT_OF_RANGE); return -1; } + return 0; } @@ -626,15 +961,14 @@ static int8_t SCSI_CheckAddressRange(USBD_HandleTypeDef *pdev, uint8_t lun, * @param lun: Logical unit number * @retval status */ -static int8_t SCSI_ProcessRead(USBD_HandleTypeDef *pdev, uint8_t lun) +static int8_t SCSI_ProcessRead(USBD_HandleTypeDef *pdev, uint8_t lun) { USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef *)pdev->pClassData; uint32_t len = hmsc->scsi_blk_len * hmsc->scsi_blk_size; len = MIN(len, MSC_MEDIA_PACKET); - if (((USBD_StorageTypeDef *)pdev->pUserData)->Read(lun, - hmsc->bot_data, + if (((USBD_StorageTypeDef *)pdev->pUserData)->Read(lun, hmsc->bot_data, hmsc->scsi_blk_addr, (len / hmsc->scsi_blk_size)) < 0) { @@ -642,7 +976,7 @@ static int8_t SCSI_ProcessRead(USBD_HandleTypeDef *pdev, uint8_t lun) return -1; } - USBD_LL_Transmit(pdev, MSC_EPIN_ADDR, hmsc->bot_data, len); + (void)USBD_LL_Transmit(pdev, MSC_EPIN_ADDR, hmsc->bot_data, len); hmsc->scsi_blk_addr += (len / hmsc->scsi_blk_size); hmsc->scsi_blk_len -= (len / hmsc->scsi_blk_size); @@ -654,6 +988,7 @@ static int8_t SCSI_ProcessRead(USBD_HandleTypeDef *pdev, uint8_t lun) { hmsc->bot_state = USBD_BOT_LAST_DATA_IN; } + return 0; } @@ -663,10 +998,9 @@ static int8_t SCSI_ProcessRead(USBD_HandleTypeDef *pdev, uint8_t lun) * @param lun: Logical unit number * @retval status */ - -static int8_t SCSI_ProcessWrite(USBD_HandleTypeDef *pdev, uint8_t lun) +static int8_t SCSI_ProcessWrite(USBD_HandleTypeDef *pdev, uint8_t lun) { - USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef *) pdev->pClassData; + USBD_MSC_BOT_HandleTypeDef *hmsc = (USBD_MSC_BOT_HandleTypeDef *)pdev->pClassData; uint32_t len = hmsc->scsi_blk_len * hmsc->scsi_blk_size; len = MIN(len, MSC_MEDIA_PACKET); @@ -676,7 +1010,6 @@ static int8_t SCSI_ProcessWrite(USBD_HandleTypeDef *pdev, uint8_t lun) (len / hmsc->scsi_blk_size)) < 0) { SCSI_SenseCode(pdev, lun, HARDWARE_ERROR, WRITE_FAULT); - return -1; } @@ -693,8 +1026,34 @@ static int8_t SCSI_ProcessWrite(USBD_HandleTypeDef *pdev, uint8_t lun) else { len = MIN((hmsc->scsi_blk_len * hmsc->scsi_blk_size), MSC_MEDIA_PACKET); + /* Prepare EP to Receive next packet */ - USBD_LL_PrepareReceive(pdev, MSC_EPOUT_ADDR, hmsc->bot_data, len); + (void)USBD_LL_PrepareReceive(pdev, MSC_EPOUT_ADDR, hmsc->bot_data, len); + } + + return 0; +} + + +/** +* @brief SCSI_UpdateBotData +* fill the requested Data to transmit buffer +* @param hmsc handler +* @param params: Data buffer +* @param length: Data length +* @retval status +*/ +static int8_t SCSI_UpdateBotData(USBD_MSC_BOT_HandleTypeDef *hmsc, + uint8_t *pBuff, uint16_t length) +{ + uint16_t len = length; + + hmsc->bot_data_length = len; + + while (len != 0U) + { + len--; + hmsc->bot_data[len] = pBuff[len]; } return 0; diff --git a/system/Middlewares/ST/STM32_USB_Device_Library/Class/Template/Inc/usbd_template.h b/system/Middlewares/ST/STM32_USB_Device_Library/Class/Template/Inc/usbd_template.h index eee8a550fe..8e9163bb21 100644 --- a/system/Middlewares/ST/STM32_USB_Device_Library/Class/Template/Inc/usbd_template.h +++ b/system/Middlewares/ST/STM32_USB_Device_Library/Class/Template/Inc/usbd_template.h @@ -41,10 +41,10 @@ extern "C" { /** @defgroup USBD_TEMPLATE_Exported_Defines * @{ */ -#define TEMPLATE_EPIN_ADDR 0x81 -#define TEMPLATE_EPIN_SIZE 0x10 +#define TEMPLATE_EPIN_ADDR 0x81U +#define TEMPLATE_EPIN_SIZE 0x10U -#define USB_TEMPLATE_CONFIG_DESC_SIZ 64 +#define USB_TEMPLATE_CONFIG_DESC_SIZ 64U /** * @} @@ -73,7 +73,7 @@ extern "C" { * @{ */ -extern USBD_ClassTypeDef USBD_TEMPLATE_ClassDriver; +extern USBD_ClassTypeDef USBD_TEMPLATE_ClassDriver; /** * @} */ diff --git a/system/Middlewares/ST/STM32_USB_Device_Library/Class/Template/Src/usbd_template.c b/system/Middlewares/ST/STM32_USB_Device_Library/Class/Template/Src/usbd_template.c index 88a5a5a7e1..1c8ea725e5 100644 --- a/system/Middlewares/ST/STM32_USB_Device_Library/Class/Template/Src/usbd_template.c +++ b/system/Middlewares/ST/STM32_USB_Device_Library/Class/Template/Src/usbd_template.c @@ -83,33 +83,19 @@ */ -static uint8_t USBD_TEMPLATE_Init(USBD_HandleTypeDef *pdev, - uint8_t cfgidx); - -static uint8_t USBD_TEMPLATE_DeInit(USBD_HandleTypeDef *pdev, - uint8_t cfgidx); - -static uint8_t USBD_TEMPLATE_Setup(USBD_HandleTypeDef *pdev, - USBD_SetupReqTypedef *req); - -static uint8_t *USBD_TEMPLATE_GetCfgDesc(uint16_t *length); - -static uint8_t *USBD_TEMPLATE_GetDeviceQualifierDesc(uint16_t *length); - -static uint8_t USBD_TEMPLATE_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum); - -static uint8_t USBD_TEMPLATE_DataOut(USBD_HandleTypeDef *pdev, uint8_t epnum); - -static uint8_t USBD_TEMPLATE_EP0_RxReady(USBD_HandleTypeDef *pdev); - -static uint8_t USBD_TEMPLATE_EP0_TxReady(USBD_HandleTypeDef *pdev); - -static uint8_t USBD_TEMPLATE_SOF(USBD_HandleTypeDef *pdev); - -static uint8_t USBD_TEMPLATE_IsoINIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum); - -static uint8_t USBD_TEMPLATE_IsoOutIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum); - +static uint8_t USBD_TEMPLATE_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx); +static uint8_t USBD_TEMPLATE_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx); +static uint8_t USBD_TEMPLATE_Setup(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); +static uint8_t USBD_TEMPLATE_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum); +static uint8_t USBD_TEMPLATE_DataOut(USBD_HandleTypeDef *pdev, uint8_t epnum); +static uint8_t USBD_TEMPLATE_EP0_RxReady(USBD_HandleTypeDef *pdev); +static uint8_t USBD_TEMPLATE_EP0_TxReady(USBD_HandleTypeDef *pdev); +static uint8_t USBD_TEMPLATE_SOF(USBD_HandleTypeDef *pdev); +static uint8_t USBD_TEMPLATE_IsoINIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum); +static uint8_t USBD_TEMPLATE_IsoOutIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum); + +static uint8_t *USBD_TEMPLATE_GetCfgDesc(uint16_t *length); +static uint8_t *USBD_TEMPLATE_GetDeviceQualifierDesc(uint16_t *length); /** * @} */ @@ -118,7 +104,7 @@ static uint8_t USBD_TEMPLATE_IsoOutIncomplete(USBD_HandleTypeDef *pdev, uint8_t * @{ */ -USBD_ClassTypeDef USBD_TEMPLATE_ClassDriver = +USBD_ClassTypeDef USBD_TEMPLATE_ClassDriver = { USBD_TEMPLATE_Init, USBD_TEMPLATE_DeInit, @@ -140,7 +126,7 @@ USBD_ClassTypeDef USBD_TEMPLATE_ClassDriver = #pragma data_alignment=4 #endif /* USB TEMPLATE device Configuration Descriptor */ -static uint8_t USBD_TEMPLATE_CfgDesc[USB_TEMPLATE_CONFIG_DESC_SIZ] = +__ALIGN_BEGIN static uint8_t USBD_TEMPLATE_CfgDesc[USB_TEMPLATE_CONFIG_DESC_SIZ] __ALIGN_END = { 0x09, /* bLength: Configuation Descriptor size */ USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION, /* bDescriptorType: Configuration */ @@ -162,7 +148,7 @@ static uint8_t USBD_TEMPLATE_CfgDesc[USB_TEMPLATE_CONFIG_DESC_SIZ] = #pragma data_alignment=4 #endif /* USB Standard Device Descriptor */ -static uint8_t USBD_TEMPLATE_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_DESC] = +__ALIGN_BEGIN static uint8_t USBD_TEMPLATE_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_DESC] __ALIGN_END = { USB_LEN_DEV_QUALIFIER_DESC, USB_DESC_TYPE_DEVICE_QUALIFIER, @@ -191,13 +177,10 @@ static uint8_t USBD_TEMPLATE_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_DESC] = * @param cfgidx: Configuration index * @retval status */ -static uint8_t USBD_TEMPLATE_Init(USBD_HandleTypeDef *pdev, - uint8_t cfgidx) +static uint8_t USBD_TEMPLATE_Init(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { - uint8_t ret = 0; - - return ret; + return (uint8_t)USBD_OK; } /** @@ -207,11 +190,10 @@ static uint8_t USBD_TEMPLATE_Init(USBD_HandleTypeDef *pdev, * @param cfgidx: Configuration index * @retval status */ -static uint8_t USBD_TEMPLATE_DeInit(USBD_HandleTypeDef *pdev, - uint8_t cfgidx) +static uint8_t USBD_TEMPLATE_DeInit(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { - return USBD_OK; + return (uint8_t)USBD_OK; } /** @@ -221,40 +203,40 @@ static uint8_t USBD_TEMPLATE_DeInit(USBD_HandleTypeDef *pdev, * @param req: usb requests * @retval status */ -static uint8_t USBD_TEMPLATE_Setup(USBD_HandleTypeDef *pdev, - USBD_SetupReqTypedef *req) +static uint8_t USBD_TEMPLATE_Setup(USBD_HandleTypeDef *pdev, + USBD_SetupReqTypedef *req) { USBD_StatusTypeDef ret = USBD_OK; switch (req->bmRequest & USB_REQ_TYPE_MASK) { - case USB_REQ_TYPE_CLASS : - switch (req->bRequest) - { - default: - USBD_CtlError(pdev, req); - ret = USBD_FAIL; - break; - } - break; - - case USB_REQ_TYPE_STANDARD: - switch (req->bRequest) - { - default: - USBD_CtlError(pdev, req); - ret = USBD_FAIL; - break; - } + case USB_REQ_TYPE_CLASS : + switch (req->bRequest) + { + default: + USBD_CtlError(pdev, req); + ret = USBD_FAIL; break; + } + break; + case USB_REQ_TYPE_STANDARD: + switch (req->bRequest) + { default: USBD_CtlError(pdev, req); ret = USBD_FAIL; break; + } + break; + + default: + USBD_CtlError(pdev, req); + ret = USBD_FAIL; + break; } - return ret; + return (uint8_t)ret; } @@ -264,9 +246,9 @@ static uint8_t USBD_TEMPLATE_Setup(USBD_HandleTypeDef *pdev, * @param length : pointer data length * @retval pointer to descriptor buffer */ -static uint8_t *USBD_TEMPLATE_GetCfgDesc(uint16_t *length) +static uint8_t *USBD_TEMPLATE_GetCfgDesc(uint16_t *length) { - *length = sizeof(USBD_TEMPLATE_CfgDesc); + *length = (uint16_t)sizeof(USBD_TEMPLATE_CfgDesc); return USBD_TEMPLATE_CfgDesc; } @@ -276,9 +258,9 @@ static uint8_t *USBD_TEMPLATE_GetCfgDesc(uint16_t *length) * @param length : pointer data length * @retval pointer to descriptor buffer */ -uint8_t *USBD_TEMPLATE_DeviceQualifierDescriptor(uint16_t *length) +uint8_t *USBD_TEMPLATE_DeviceQualifierDescriptor(uint16_t *length) { - *length = sizeof(USBD_TEMPLATE_DeviceQualifierDesc); + *length = (uint16_t)sizeof(USBD_TEMPLATE_DeviceQualifierDesc); return USBD_TEMPLATE_DeviceQualifierDesc; } @@ -290,11 +272,10 @@ uint8_t *USBD_TEMPLATE_DeviceQualifierDescriptor(uint16_t *length) * @param epnum: endpoint index * @retval status */ -static uint8_t USBD_TEMPLATE_DataIn(USBD_HandleTypeDef *pdev, - uint8_t epnum) +static uint8_t USBD_TEMPLATE_DataIn(USBD_HandleTypeDef *pdev, uint8_t epnum) { - return USBD_OK; + return (uint8_t)USBD_OK; } /** @@ -303,10 +284,10 @@ static uint8_t USBD_TEMPLATE_DataIn(USBD_HandleTypeDef *pdev, * @param pdev: device instance * @retval status */ -static uint8_t USBD_TEMPLATE_EP0_RxReady(USBD_HandleTypeDef *pdev) +static uint8_t USBD_TEMPLATE_EP0_RxReady(USBD_HandleTypeDef *pdev) { - return USBD_OK; + return (uint8_t)USBD_OK; } /** * @brief USBD_TEMPLATE_EP0_TxReady @@ -314,10 +295,10 @@ static uint8_t USBD_TEMPLATE_EP0_RxReady(USBD_HandleTypeDef *pdev) * @param pdev: device instance * @retval status */ -static uint8_t USBD_TEMPLATE_EP0_TxReady(USBD_HandleTypeDef *pdev) +static uint8_t USBD_TEMPLATE_EP0_TxReady(USBD_HandleTypeDef *pdev) { - return USBD_OK; + return (uint8_t)USBD_OK; } /** * @brief USBD_TEMPLATE_SOF @@ -325,10 +306,10 @@ static uint8_t USBD_TEMPLATE_EP0_TxReady(USBD_HandleTypeDef *pdev) * @param pdev: device instance * @retval status */ -static uint8_t USBD_TEMPLATE_SOF(USBD_HandleTypeDef *pdev) +static uint8_t USBD_TEMPLATE_SOF(USBD_HandleTypeDef *pdev) { - return USBD_OK; + return (uint8_t)USBD_OK; } /** * @brief USBD_TEMPLATE_IsoINIncomplete @@ -337,10 +318,10 @@ static uint8_t USBD_TEMPLATE_SOF(USBD_HandleTypeDef *pdev) * @param epnum: endpoint index * @retval status */ -static uint8_t USBD_TEMPLATE_IsoINIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum) +static uint8_t USBD_TEMPLATE_IsoINIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum) { - return USBD_OK; + return (uint8_t)USBD_OK; } /** * @brief USBD_TEMPLATE_IsoOutIncomplete @@ -349,10 +330,10 @@ static uint8_t USBD_TEMPLATE_IsoINIncomplete(USBD_HandleTypeDef *pdev, uint8_t * @param epnum: endpoint index * @retval status */ -static uint8_t USBD_TEMPLATE_IsoOutIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum) +static uint8_t USBD_TEMPLATE_IsoOutIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum) { - return USBD_OK; + return (uint8_t)USBD_OK; } /** * @brief USBD_TEMPLATE_DataOut @@ -361,11 +342,10 @@ static uint8_t USBD_TEMPLATE_IsoOutIncomplete(USBD_HandleTypeDef *pdev, uint8_t * @param epnum: endpoint index * @retval status */ -static uint8_t USBD_TEMPLATE_DataOut(USBD_HandleTypeDef *pdev, - uint8_t epnum) +static uint8_t USBD_TEMPLATE_DataOut(USBD_HandleTypeDef *pdev, uint8_t epnum) { - return USBD_OK; + return (uint8_t)USBD_OK; } /** @@ -374,9 +354,10 @@ static uint8_t USBD_TEMPLATE_DataOut(USBD_HandleTypeDef *pdev, * @param length : pointer data length * @retval pointer to descriptor buffer */ -uint8_t *USBD_TEMPLATE_GetDeviceQualifierDesc(uint16_t *length) +uint8_t *USBD_TEMPLATE_GetDeviceQualifierDesc(uint16_t *length) { - *length = sizeof(USBD_TEMPLATE_DeviceQualifierDesc); + *length = (uint16_t)sizeof(USBD_TEMPLATE_DeviceQualifierDesc); + return USBD_TEMPLATE_DeviceQualifierDesc; } diff --git a/system/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_conf_template.h b/system/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_conf_template.h index e47c41c21c..85e18ab781 100644 --- a/system/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_conf_template.h +++ b/system/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_conf_template.h @@ -44,12 +44,19 @@ extern "C" { * @{ */ -#define USBD_MAX_NUM_INTERFACES 1U -#define USBD_MAX_NUM_CONFIGURATION 1U -#define USBD_MAX_STR_DESC_SIZ 0x100U -#define USBD_SUPPORT_USER_STRING_DESC 0U -#define USBD_SELF_POWERED 1U -#define USBD_DEBUG_LEVEL 2U +#define USBD_MAX_NUM_INTERFACES 1U +#define USBD_MAX_NUM_CONFIGURATION 1U +#define USBD_MAX_STR_DESC_SIZ 0x100U +#define USBD_SELF_POWERED 1U +#define USBD_DEBUG_LEVEL 2U + +/* ECM, RNDIS, DFU Class Config */ +#define USBD_SUPPORT_USER_STRING_DESC 1U + +/* BillBoard Class Config */ +#define USBD_CLASS_USER_STRING_DESC 1U +#define USBD_CLASS_BOS_ENABLED 1U +#define USB_BB_MAX_NUM_ALT_MODE 0x2U /* MSC Class Config */ #define MSC_MEDIA_PACKET 8192U @@ -62,7 +69,7 @@ extern "C" { #define USBD_DFU_XFERS_IZE 1024U /* AUDIO Class Config */ -#define USBD_AUDIO_FREQ 22100U +#define USBD_AUDIO_FREQ 22100U /** @defgroup USBD_Exported_Macros * @{ @@ -73,6 +80,7 @@ extern "C" { #define USBD_free free #define USBD_memset memset #define USBD_memcpy memcpy +#define USBD_Delay HAL_Delay /* DEBUG macros */ #if (USBD_DEBUG_LEVEL > 0U) diff --git a/system/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h b/system/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h index 23928158a7..c7d2ba39e5 100644 --- a/system/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h +++ b/system/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h @@ -88,53 +88,50 @@ USBD_StatusTypeDef USBD_Start(USBD_HandleTypeDef *pdev); USBD_StatusTypeDef USBD_Stop(USBD_HandleTypeDef *pdev); USBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass); -USBD_StatusTypeDef USBD_RunTestMode(USBD_HandleTypeDef *pdev); -USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx); -USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx); +USBD_StatusTypeDef USBD_RunTestMode(USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx); +USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx); USBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup); USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev, uint8_t epnum, uint8_t *pdata); USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev, uint8_t epnum, uint8_t *pdata); -USBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef *pdev); -USBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef *pdev, USBD_SpeedTypeDef speed); -USBD_StatusTypeDef USBD_LL_Suspend(USBD_HandleTypeDef *pdev); -USBD_StatusTypeDef USBD_LL_Resume(USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef *pdev, USBD_SpeedTypeDef speed); +USBD_StatusTypeDef USBD_LL_Suspend(USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_LL_Resume(USBD_HandleTypeDef *pdev); USBD_StatusTypeDef USBD_LL_SOF(USBD_HandleTypeDef *pdev); -USBD_StatusTypeDef USBD_LL_IsoINIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum); -USBD_StatusTypeDef USBD_LL_IsoOUTIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum); +USBD_StatusTypeDef USBD_LL_IsoINIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum); +USBD_StatusTypeDef USBD_LL_IsoOUTIncomplete(USBD_HandleTypeDef *pdev, uint8_t epnum); -USBD_StatusTypeDef USBD_LL_DevConnected(USBD_HandleTypeDef *pdev); -USBD_StatusTypeDef USBD_LL_DevDisconnected(USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_LL_DevConnected(USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_LL_DevDisconnected(USBD_HandleTypeDef *pdev); /* USBD Low Level Driver */ -USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev); -USBD_StatusTypeDef USBD_LL_DeInit(USBD_HandleTypeDef *pdev); -USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev); -USBD_StatusTypeDef USBD_LL_Stop(USBD_HandleTypeDef *pdev); -USBD_StatusTypeDef USBD_LL_OpenEP(USBD_HandleTypeDef *pdev, - uint8_t ep_addr, - uint8_t ep_type, - uint16_t ep_mps); - -USBD_StatusTypeDef USBD_LL_CloseEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr); -USBD_StatusTypeDef USBD_LL_FlushEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr); -USBD_StatusTypeDef USBD_LL_StallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr); -USBD_StatusTypeDef USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr); -uint8_t USBD_LL_IsStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr); -USBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_addr); -USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev, - uint8_t ep_addr, - uint8_t *pbuf, - uint16_t size); - -USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, - uint8_t ep_addr, - uint8_t *pbuf, - uint16_t size); +USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_LL_DeInit(USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_LL_Stop(USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_LL_OpenEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr, + uint8_t ep_type, uint16_t ep_mps); + +USBD_StatusTypeDef USBD_LL_CloseEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr); +USBD_StatusTypeDef USBD_LL_FlushEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr); +USBD_StatusTypeDef USBD_LL_StallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr); +USBD_StatusTypeDef USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr); +USBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_addr); + +USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev, uint8_t ep_addr, + uint8_t *pbuf, uint32_t size); + +USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, uint8_t ep_addr, + uint8_t *pbuf, uint32_t size); + +uint8_t USBD_LL_IsStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr); uint32_t USBD_LL_GetRxDataSize(USBD_HandleTypeDef *pdev, uint8_t ep_addr); + void USBD_LL_Delay(uint32_t Delay); /** diff --git a/system/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h b/system/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h index 047fe2efe8..f973a8b1b2 100644 --- a/system/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h +++ b/system/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h @@ -73,16 +73,14 @@ extern "C" { * @{ */ -USBD_StatusTypeDef USBD_StdDevReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); -USBD_StatusTypeDef USBD_StdItfReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); -USBD_StatusTypeDef USBD_StdEPReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); - - -void USBD_CtlError(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); +USBD_StatusTypeDef USBD_StdDevReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); +USBD_StatusTypeDef USBD_StdItfReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); +USBD_StatusTypeDef USBD_StdEPReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); +void USBD_CtlError(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); void USBD_ParseSetupRequest(USBD_SetupReqTypedef *req, uint8_t *pdata); - void USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len); + /** * @} */ diff --git a/system/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h b/system/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h index a805e8b71c..0463e2f31f 100644 --- a/system/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h +++ b/system/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h @@ -65,6 +65,10 @@ extern "C" { #define USBD_SUPPORT_USER_STRING_DESC 0U #endif /* USBD_SUPPORT_USER_STRING_DESC */ +#ifndef USBD_CLASS_USER_STRING_DESC +#define USBD_CLASS_USER_STRING_DESC 0U +#endif /* USBD_CLASS_USER_STRING_DESC */ + #define USB_LEN_DEV_QUALIFIER_DESC 0x0AU #define USB_LEN_DEV_DESC 0x12U #define USB_LEN_CFG_DESC 0x09U @@ -165,6 +169,28 @@ typedef struct usb_setup_req uint16_t wLength; } USBD_SetupReqTypedef; +typedef struct +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t wDescriptorLengthLow; + uint8_t wDescriptorLengthHigh; + uint8_t bNumInterfaces; + uint8_t bConfigurationValue; + uint8_t iConfiguration; + uint8_t bmAttributes; + uint8_t bMaxPower; +} USBD_ConfigDescTypedef; + +typedef struct +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t wTotalLength; + uint8_t bNumDeviceCaps; +} USBD_BosDescTypedef; + + struct _USBD_HandleTypeDef; typedef struct _Device_cb @@ -203,34 +229,39 @@ typedef enum /* Following USB Device status */ typedef enum { - USBD_OK = 0U, + USBD_OK = 0U, USBD_BUSY, + USBD_EMEM, USBD_FAIL, } USBD_StatusTypeDef; /* USB Device descriptors structure */ typedef struct { - uint8_t *(*GetDeviceDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length); - uint8_t *(*GetLangIDStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length); - uint8_t *(*GetManufacturerStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length); - uint8_t *(*GetProductStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length); - uint8_t *(*GetSerialStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length); - uint8_t *(*GetConfigurationStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length); - uint8_t *(*GetInterfaceStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length); -#if (USBD_LPM_ENABLED == 1U) - uint8_t *(*GetBOSDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length); + uint8_t *(*GetDeviceDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length); + uint8_t *(*GetLangIDStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length); + uint8_t *(*GetManufacturerStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length); + uint8_t *(*GetProductStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length); + uint8_t *(*GetSerialStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length); + uint8_t *(*GetConfigurationStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length); + uint8_t *(*GetInterfaceStrDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length); +#if (USBD_CLASS_USER_STRING_DESC == 1) + uint8_t *(*GetUserStrDescriptor)(USBD_SpeedTypeDef speed, uint8_t idx, uint16_t *length); +#endif +#if ((USBD_LPM_ENABLED == 1U) || (USBD_CLASS_BOS_ENABLED == 1)) + uint8_t *(*GetBOSDescriptor)(USBD_SpeedTypeDef speed, uint16_t *length); #endif } USBD_DescriptorsTypeDef; /* USB Device handle structure */ typedef struct { - uint32_t status; - uint32_t is_used; - uint32_t total_length; - uint32_t rem_length; - uint32_t maxpacket; + uint32_t status; + uint32_t total_length; + uint32_t rem_length; + uint32_t maxpacket; + uint16_t is_used; + uint16_t bInterval; } USBD_EndpointTypeDef; /* USB Device handle structure */ @@ -251,6 +282,7 @@ typedef struct _USBD_HandleTypeDef uint8_t dev_connection_status; uint8_t dev_test_mode; uint32_t dev_remote_wakeup; + uint8_t ConfIdx; USBD_SetupReqTypedef request; USBD_DescriptorsTypeDef *pDesc; @@ -258,6 +290,8 @@ typedef struct _USBD_HandleTypeDef void *pClassData; void *pUserData; void *pData; + void *pBosDesc; + void *pConfDesc; } USBD_HandleTypeDef; /** @@ -269,8 +303,19 @@ typedef struct _USBD_HandleTypeDef /** @defgroup USBD_DEF_Exported_Macros * @{ */ -#define SWAPBYTE(addr) (((uint16_t)(*((uint8_t *)(addr)))) + \ - (((uint16_t)(*(((uint8_t *)(addr)) + 1U))) << 8U)) +__STATIC_INLINE uint16_t SWAPBYTE(uint8_t *addr) +{ + uint16_t _SwapVal, _Byte1, _Byte2; + uint8_t *_pbuff = addr; + + _Byte1 = *(uint8_t *)_pbuff; + _pbuff++; + _Byte2 = *(uint8_t *)_pbuff; + + _SwapVal = (_Byte2 << 8) | _Byte1; + + return _SwapVal; +} #define LOBYTE(x) ((uint8_t)((x) & 0x00FFU)) #define HIBYTE(x) ((uint8_t)(((x) & 0xFF00U) >> 8U)) diff --git a/system/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_desc_template.h b/system/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_desc_template.h index 35a5e63736..8fbbfaa634 100644 --- a/system/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_desc_template.h +++ b/system/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_desc_template.h @@ -26,11 +26,33 @@ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ -#define DEVICE_ID1 (0x1FFF7A10) -#define DEVICE_ID2 (0x1FFF7A14) -#define DEVICE_ID3 (0x1FFF7A18) +#define DEVICE_ID1 (UID_BASE) +#define DEVICE_ID2 (UID_BASE + 0x4U) +#define DEVICE_ID3 (UID_BASE + 0x8U) -#define USB_SIZ_STRING_SERIAL 0x1A +/* + * USB Billboard Class USER string desc Defines Template + * index should start form 0x10 to avoid using the reserved device string desc indexes + */ +#if (USBD_CLASS_USER_STRING_DESC == 1) +#define USBD_BB_IF_STRING_INDEX 0x10U +#define USBD_BB_URL_STRING_INDEX 0x11U +#define USBD_BB_ALTMODE0_STRING_INDEX 0x12U +#define USBD_BB_ALTMODE1_STRING_INDEX 0x13U +/* Add Specific USER string Desc */ +#define USBD_BB_IF_STR_DESC (uint8_t *)"STM32 BillBoard Interface" +#define USBD_BB_URL_STR_DESC (uint8_t *)"www.st.com" +#define USBD_BB_ALTMODE0_STR_DESC (uint8_t *)"STM32 Alternate0 Mode" +#define USBD_BB_ALTMODE1_STR_DESC (uint8_t *)"STM32 Alternate1 Mode" +#endif + +#define USB_SIZ_STRING_SERIAL 0x1AU + +#if (USBD_LPM_ENABLED == 1) +#define USB_SIZ_BOS_DESC 0x0CU +#elif (USBD_CLASS_BOS_ENABLED == 1) +#define USB_SIZ_BOS_DESC 0x5DU +#endif /* Exported macro ------------------------------------------------------------*/ /* Exported functions ------------------------------------------------------- */ diff --git a/system/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h b/system/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h index 629369eabb..b7159d53b6 100644 --- a/system/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h +++ b/system/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h @@ -77,27 +77,22 @@ extern "C" { * @{ */ -USBD_StatusTypeDef USBD_CtlSendData(USBD_HandleTypeDef *pdev, - uint8_t *pbuf, - uint16_t len); +USBD_StatusTypeDef USBD_CtlSendData(USBD_HandleTypeDef *pdev, + uint8_t *pbuf, uint32_t len); -USBD_StatusTypeDef USBD_CtlContinueSendData(USBD_HandleTypeDef *pdev, - uint8_t *pbuf, - uint16_t len); +USBD_StatusTypeDef USBD_CtlContinueSendData(USBD_HandleTypeDef *pdev, + uint8_t *pbuf, uint32_t len); -USBD_StatusTypeDef USBD_CtlPrepareRx(USBD_HandleTypeDef *pdev, - uint8_t *pbuf, - uint16_t len); +USBD_StatusTypeDef USBD_CtlPrepareRx(USBD_HandleTypeDef *pdev, + uint8_t *pbuf, uint32_t len); -USBD_StatusTypeDef USBD_CtlContinueRx(USBD_HandleTypeDef *pdev, - uint8_t *pbuf, - uint16_t len); +USBD_StatusTypeDef USBD_CtlContinueRx(USBD_HandleTypeDef *pdev, + uint8_t *pbuf, uint32_t len); -USBD_StatusTypeDef USBD_CtlSendStatus(USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_CtlSendStatus(USBD_HandleTypeDef *pdev); +USBD_StatusTypeDef USBD_CtlReceiveStatus(USBD_HandleTypeDef *pdev); -USBD_StatusTypeDef USBD_CtlReceiveStatus(USBD_HandleTypeDef *pdev); - -uint32_t USBD_GetRxCount(USBD_HandleTypeDef *pdev, uint8_t ep_addr); +uint32_t USBD_GetRxCount(USBD_HandleTypeDef *pdev, uint8_t ep_addr); /** * @} diff --git a/system/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_conf_template.c b/system/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_conf_template.c index dbc75d89f2..67b70aa0e3 100644 --- a/system/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_conf_template.c +++ b/system/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_conf_template.c @@ -34,6 +34,8 @@ */ USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev) { + UNUSED(pdev); + return USBD_OK; } @@ -44,6 +46,8 @@ USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev) */ USBD_StatusTypeDef USBD_LL_DeInit(USBD_HandleTypeDef *pdev) { + UNUSED(pdev); + return USBD_OK; } @@ -54,6 +58,8 @@ USBD_StatusTypeDef USBD_LL_DeInit(USBD_HandleTypeDef *pdev) */ USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev) { + UNUSED(pdev); + return USBD_OK; } @@ -64,6 +70,8 @@ USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev) */ USBD_StatusTypeDef USBD_LL_Stop(USBD_HandleTypeDef *pdev) { + UNUSED(pdev); + return USBD_OK; } @@ -78,6 +86,11 @@ USBD_StatusTypeDef USBD_LL_Stop(USBD_HandleTypeDef *pdev) USBD_StatusTypeDef USBD_LL_OpenEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t ep_type, uint16_t ep_mps) { + UNUSED(pdev); + UNUSED(ep_addr); + UNUSED(ep_type); + UNUSED(ep_mps); + return USBD_OK; } @@ -89,6 +102,9 @@ USBD_StatusTypeDef USBD_LL_OpenEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr, */ USBD_StatusTypeDef USBD_LL_CloseEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { + UNUSED(pdev); + UNUSED(ep_addr); + return USBD_OK; } @@ -100,6 +116,9 @@ USBD_StatusTypeDef USBD_LL_CloseEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) */ USBD_StatusTypeDef USBD_LL_FlushEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { + UNUSED(pdev); + UNUSED(ep_addr); + return USBD_OK; } @@ -111,6 +130,9 @@ USBD_StatusTypeDef USBD_LL_FlushEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) */ USBD_StatusTypeDef USBD_LL_StallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { + UNUSED(pdev); + UNUSED(ep_addr); + return USBD_OK; } @@ -123,6 +145,9 @@ USBD_StatusTypeDef USBD_LL_StallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) USBD_StatusTypeDef USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { + UNUSED(pdev); + UNUSED(ep_addr); + return USBD_OK; } @@ -134,7 +159,10 @@ USBD_StatusTypeDef USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, */ uint8_t USBD_LL_IsStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { - return 0; + UNUSED(pdev); + UNUSED(ep_addr); + + return 0U; } /** @@ -146,6 +174,9 @@ uint8_t USBD_LL_IsStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) USBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_addr) { + UNUSED(pdev); + UNUSED(ep_addr); + return USBD_OK; } @@ -158,8 +189,13 @@ USBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, * @retval USBD Status */ USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev, uint8_t ep_addr, - uint8_t *pbuf, uint16_t size) + uint8_t *pbuf, uint32_t size) { + UNUSED(pdev); + UNUSED(ep_addr); + UNUSED(pbuf); + UNUSED(size); + return USBD_OK; } @@ -173,8 +209,13 @@ USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev, uint8_t ep_addr, */ USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, - uint16_t size) + uint32_t size) { + UNUSED(pdev); + UNUSED(ep_addr); + UNUSED(pbuf); + UNUSED(size); + return USBD_OK; } @@ -186,6 +227,9 @@ USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, */ uint32_t USBD_LL_GetRxDataSize(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { + UNUSED(pdev); + UNUSED(ep_addr); + return 0U; } @@ -196,6 +240,7 @@ uint32_t USBD_LL_GetRxDataSize(USBD_HandleTypeDef *pdev, uint8_t ep_addr) */ void USBD_LL_Delay(uint32_t Delay) { + UNUSED(Delay); } /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c b/system/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c index 28f86383c1..6021cc0784 100644 --- a/system/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c +++ b/system/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c @@ -89,6 +89,8 @@ USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev, USBD_DescriptorsTypeDef *pdesc, uint8_t id) { + USBD_StatusTypeDef ret; + /* Check whether the USB Host handle is valid */ if (pdev == NULL) { @@ -98,12 +100,17 @@ USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev, return USBD_FAIL; } - /* Unlink previous class*/ + /* Unlink previous class */ if (pdev->pClass != NULL) { pdev->pClass = NULL; } + if (pdev->pConfDesc != NULL) + { + pdev->pConfDesc = NULL; + } + /* Assign USBD Descriptors */ if (pdesc != NULL) { @@ -113,10 +120,11 @@ USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev, /* Set Device initial State */ pdev->dev_state = USBD_STATE_DEFAULT; pdev->id = id; + /* Initialize low level driver */ - USBD_LL_Init(pdev); + ret = USBD_LL_Init(pdev); - return USBD_OK; + return ret; } /** @@ -127,19 +135,34 @@ USBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev, */ USBD_StatusTypeDef USBD_DeInit(USBD_HandleTypeDef *pdev) { + USBD_StatusTypeDef ret; + /* Set Default State */ pdev->dev_state = USBD_STATE_DEFAULT; /* Free Class Resources */ - pdev->pClass->DeInit(pdev, (uint8_t)pdev->dev_config); + if (pdev->pClass != NULL) + { + pdev->pClass->DeInit(pdev, (uint8_t)pdev->dev_config); + } + + if (pdev->pConfDesc != NULL) + { + pdev->pConfDesc = NULL; + } /* Stop the low level driver */ - USBD_LL_Stop(pdev); + ret = USBD_LL_Stop(pdev); + + if (ret != USBD_OK) + { + return ret; + } /* Initialize low level driver */ - USBD_LL_DeInit(pdev); + ret = USBD_LL_DeInit(pdev); - return USBD_OK; + return ret; } /** @@ -149,24 +172,30 @@ USBD_StatusTypeDef USBD_DeInit(USBD_HandleTypeDef *pdev) * @param pclass: Class handle * @retval USBD Status */ -USBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass) +USBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass) { - USBD_StatusTypeDef status = USBD_OK; - if (pclass != NULL) - { - /* link the class to the USB Device handle */ - pdev->pClass = pclass; - status = USBD_OK; - } - else + uint16_t len = 0U; + + if (pclass == NULL) { #if (USBD_DEBUG_LEVEL > 1U) USBD_ErrLog("Invalid Class handle"); #endif - status = USBD_FAIL; + return USBD_FAIL; } - return status; + /* link the class to the USB Device handle */ + pdev->pClass = pclass; + + /* Get Device Configuration Descriptor */ +#ifdef USE_USB_FS + pdev->pConfDesc = (void *)pdev->pClass->GetFSConfigDescriptor(&len); +#else /* USE_USB_HS */ + pdev->pConfDesc = (void *)pdev->pClass->GetHSConfigDescriptor(&len); +#endif /* USE_USB_FS */ + + + return USBD_OK; } /** @@ -175,12 +204,10 @@ USBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeD * @param pdev: Device Handle * @retval USBD Status */ -USBD_StatusTypeDef USBD_Start(USBD_HandleTypeDef *pdev) +USBD_StatusTypeDef USBD_Start(USBD_HandleTypeDef *pdev) { /* Start the low level driver */ - USBD_LL_Start(pdev); - - return USBD_OK; + return USBD_LL_Start(pdev); } /** @@ -189,15 +216,25 @@ USBD_StatusTypeDef USBD_Start(USBD_HandleTypeDef *pdev) * @param pdev: Device Handle * @retval USBD Status */ -USBD_StatusTypeDef USBD_Stop(USBD_HandleTypeDef *pdev) +USBD_StatusTypeDef USBD_Stop(USBD_HandleTypeDef *pdev) { + USBD_StatusTypeDef ret; + /* Free Class Resources */ - pdev->pClass->DeInit(pdev, (uint8_t)pdev->dev_config); + if (pdev->pClass != NULL) + { + pdev->pClass->DeInit(pdev, (uint8_t)pdev->dev_config); + } + + if (pdev->pConfDesc != NULL) + { + pdev->pConfDesc = NULL; + } /* Stop the low level driver */ - USBD_LL_Stop(pdev); + ret = USBD_LL_Stop(pdev); - return USBD_OK; + return ret; } /** @@ -206,7 +243,7 @@ USBD_StatusTypeDef USBD_Stop(USBD_HandleTypeDef *pdev) * @param pdev: device instance * @retval status */ -USBD_StatusTypeDef USBD_RunTestMode(USBD_HandleTypeDef *pdev) +USBD_StatusTypeDef USBD_RunTestMode(USBD_HandleTypeDef *pdev) { /* Prevent unused argument compilation warning */ UNUSED(pdev); @@ -222,17 +259,14 @@ USBD_StatusTypeDef USBD_RunTestMode(USBD_HandleTypeDef *pdev) * @retval status */ -USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx) +USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { USBD_StatusTypeDef ret = USBD_FAIL; if (pdev->pClass != NULL) { - /* Set configuration and Start the Class*/ - if (pdev->pClass->Init(pdev, cfgidx) == 0U) - { - ret = USBD_OK; - } + /* Set configuration and Start the Class */ + ret = (USBD_StatusTypeDef)pdev->pClass->Init(pdev, cfgidx); } return ret; @@ -245,10 +279,13 @@ USBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx * @param cfgidx: configuration index * @retval status: USBD_StatusTypeDef */ -USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx) +USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx) { - /* Clear configuration and De-initialize the Class process*/ - pdev->pClass->DeInit(pdev, cfgidx); + /* Clear configuration and De-initialize the Class process */ + if (pdev->pClass != NULL) + { + pdev->pClass->DeInit(pdev, cfgidx); + } return USBD_OK; } @@ -262,6 +299,8 @@ USBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef *pdev, uint8_t cfgidx */ USBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup) { + USBD_StatusTypeDef ret; + USBD_ParseSetupRequest(&pdev->request, psetup); pdev->ep0_state = USBD_EP0_SETUP; @@ -271,23 +310,23 @@ USBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup) switch (pdev->request.bmRequest & 0x1FU) { case USB_REQ_RECIPIENT_DEVICE: - USBD_StdDevReq(pdev, &pdev->request); + ret = USBD_StdDevReq(pdev, &pdev->request); break; case USB_REQ_RECIPIENT_INTERFACE: - USBD_StdItfReq(pdev, &pdev->request); + ret = USBD_StdItfReq(pdev, &pdev->request); break; case USB_REQ_RECIPIENT_ENDPOINT: - USBD_StdEPReq(pdev, &pdev->request); + ret = USBD_StdEPReq(pdev, &pdev->request); break; default: - USBD_LL_StallEP(pdev, (pdev->request.bmRequest & 0x80U)); + ret = USBD_LL_StallEP(pdev, (pdev->request.bmRequest & 0x80U)); break; } - return USBD_OK; + return ret; } /** @@ -301,6 +340,7 @@ USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev, uint8_t epnum, uint8_t *pdata) { USBD_EndpointTypeDef *pep; + USBD_StatusTypeDef ret; if (epnum == 0U) { @@ -312,8 +352,7 @@ USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev, { pep->rem_length -= pep->maxpacket; - USBD_CtlContinueRx(pdev, pdata, - (uint16_t)MIN(pep->rem_length, pep->maxpacket)); + (void)USBD_CtlContinueRx(pdev, pdata, MIN(pep->rem_length, pep->maxpacket)); } else { @@ -322,25 +361,32 @@ USBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev, { pdev->pClass->EP0_RxReady(pdev); } - USBD_CtlSendStatus(pdev); + (void)USBD_CtlSendStatus(pdev); } } else { +#if 0 if (pdev->ep0_state == USBD_EP0_STATUS_OUT) { /* * STATUS PHASE completed, update ep0_state to idle */ pdev->ep0_state = USBD_EP0_IDLE; - USBD_LL_StallEP(pdev, 0U); + (void)USBD_LL_StallEP(pdev, 0U); } +#endif } } else if ((pdev->pClass->DataOut != NULL) && (pdev->dev_state == USBD_STATE_CONFIGURED)) { - pdev->pClass->DataOut(pdev, epnum); + ret = (USBD_StatusTypeDef)pdev->pClass->DataOut(pdev, epnum); + + if (ret != USBD_OK) + { + return ret; + } } else { @@ -362,6 +408,7 @@ USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev, uint8_t epnum, uint8_t *pdata) { USBD_EndpointTypeDef *pep; + USBD_StatusTypeDef ret; if (epnum == 0U) { @@ -373,57 +420,62 @@ USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev, { pep->rem_length -= pep->maxpacket; - USBD_CtlContinueSendData(pdev, pdata, (uint16_t)pep->rem_length); + (void)USBD_CtlContinueSendData(pdev, pdata, pep->rem_length); /* Prepare endpoint for premature end of transfer */ - USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U); + (void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U); } else { /* last packet is MPS multiple, so send ZLP packet */ - if ((pep->total_length % pep->maxpacket == 0U) && + if ((pep->maxpacket == pep->rem_length) && (pep->total_length >= pep->maxpacket) && (pep->total_length < pdev->ep0_data_len)) { - USBD_CtlContinueSendData(pdev, NULL, 0U); + (void)USBD_CtlContinueSendData(pdev, NULL, 0U); pdev->ep0_data_len = 0U; /* Prepare endpoint for premature end of transfer */ - USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U); + (void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U); } else { - if (pdev->dev_state == USBD_STATE_CONFIGURED) + if ((pdev->pClass->EP0_TxSent != NULL) && + (pdev->dev_state == USBD_STATE_CONFIGURED)) { - if (pdev->pClass->EP0_TxSent != NULL) - { - pdev->pClass->EP0_TxSent(pdev); - } - USBD_LL_StallEP(pdev, 0x80U); + pdev->pClass->EP0_TxSent(pdev); + (void)USBD_LL_StallEP(pdev, 0x80U); } - USBD_CtlReceiveStatus(pdev); + (void)USBD_CtlReceiveStatus(pdev); } } } else { +#if 0 if ((pdev->ep0_state == USBD_EP0_STATUS_IN) || (pdev->ep0_state == USBD_EP0_IDLE)) { - USBD_LL_StallEP(pdev, 0x80U); + (void)USBD_LL_StallEP(pdev, 0x80U); } +#endif } if (pdev->dev_test_mode == 1U) { - USBD_RunTestMode(pdev); + (void)USBD_RunTestMode(pdev); pdev->dev_test_mode = 0U; } } else if ((pdev->pClass->DataIn != NULL) && (pdev->dev_state == USBD_STATE_CONFIGURED)) { - pdev->pClass->DataIn(pdev, epnum); + ret = (USBD_StatusTypeDef)pdev->pClass->DataIn(pdev, epnum); + + if (ret != USBD_OK) + { + return ret; + } } else { @@ -443,29 +495,29 @@ USBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev, USBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef *pdev) { - /* Open EP0 OUT */ - USBD_LL_OpenEP(pdev, 0x00U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE); - pdev->ep_out[0x00U & 0xFU].is_used = 1U; - - pdev->ep_out[0].maxpacket = USB_MAX_EP0_SIZE; - - /* Open EP0 IN */ - USBD_LL_OpenEP(pdev, 0x80U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE); - pdev->ep_in[0x80U & 0xFU].is_used = 1U; - - pdev->ep_in[0].maxpacket = USB_MAX_EP0_SIZE; - /* Upon Reset call user call back */ pdev->dev_state = USBD_STATE_DEFAULT; pdev->ep0_state = USBD_EP0_IDLE; pdev->dev_config = 0U; pdev->dev_remote_wakeup = 0U; - if (pdev->pClassData) + if (pdev->pClassData != NULL) { pdev->pClass->DeInit(pdev, (uint8_t)pdev->dev_config); } + /* Open EP0 OUT */ + (void)USBD_LL_OpenEP(pdev, 0x00U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE); + pdev->ep_out[0x00U & 0xFU].is_used = 1U; + + pdev->ep_out[0].maxpacket = USB_MAX_EP0_SIZE; + + /* Open EP0 IN */ + (void)USBD_LL_OpenEP(pdev, 0x80U, USBD_EP_TYPE_CTRL, USB_MAX_EP0_SIZE); + pdev->ep_in[0x80U & 0xFU].is_used = 1U; + + pdev->ep_in[0].maxpacket = USB_MAX_EP0_SIZE; + return USBD_OK; } @@ -492,8 +544,8 @@ USBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef *pdev, USBD_StatusTypeDef USBD_LL_Suspend(USBD_HandleTypeDef *pdev) { - pdev->dev_old_state = pdev->dev_state; - pdev->dev_state = USBD_STATE_SUSPENDED; + pdev->dev_old_state = pdev->dev_state; + pdev->dev_state = USBD_STATE_SUSPENDED; return USBD_OK; } @@ -591,7 +643,11 @@ USBD_StatusTypeDef USBD_LL_DevDisconnected(USBD_HandleTypeDef *pdev) { /* Free Class Resources */ pdev->dev_state = USBD_STATE_DEFAULT; - pdev->pClass->DeInit(pdev, (uint8_t)pdev->dev_config); + + if (pdev->pClass != NULL) + { + pdev->pClass->DeInit(pdev, (uint8_t)pdev->dev_config); + } return USBD_OK; } diff --git a/system/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c b/system/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c index 4561c8d67b..c31d40e0a0 100644 --- a/system/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c +++ b/system/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c @@ -71,27 +71,13 @@ /** @defgroup USBD_REQ_Private_FunctionPrototypes * @{ */ -static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev, - USBD_SetupReqTypedef *req); - -static void USBD_SetAddress(USBD_HandleTypeDef *pdev, - USBD_SetupReqTypedef *req); - -static void USBD_SetConfig(USBD_HandleTypeDef *pdev, - USBD_SetupReqTypedef *req); - -static void USBD_GetConfig(USBD_HandleTypeDef *pdev, - USBD_SetupReqTypedef *req); - -static void USBD_GetStatus(USBD_HandleTypeDef *pdev, - USBD_SetupReqTypedef *req); - -static void USBD_SetFeature(USBD_HandleTypeDef *pdev, - USBD_SetupReqTypedef *req); - -static void USBD_ClrFeature(USBD_HandleTypeDef *pdev, - USBD_SetupReqTypedef *req); - +static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); +static void USBD_SetAddress(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); +static USBD_StatusTypeDef USBD_SetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); +static void USBD_GetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); +static void USBD_GetStatus(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); +static void USBD_SetFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); +static void USBD_ClrFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req); static uint8_t USBD_GetLen(uint8_t *buf); /** @@ -111,58 +97,57 @@ static uint8_t USBD_GetLen(uint8_t *buf); * @param req: usb request * @retval status */ -USBD_StatusTypeDef USBD_StdDevReq(USBD_HandleTypeDef *pdev, - USBD_SetupReqTypedef *req) +USBD_StatusTypeDef USBD_StdDevReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { USBD_StatusTypeDef ret = USBD_OK; switch (req->bmRequest & USB_REQ_TYPE_MASK) { - case USB_REQ_TYPE_CLASS: - case USB_REQ_TYPE_VENDOR: - pdev->pClass->Setup(pdev, req); - break; - - case USB_REQ_TYPE_STANDARD: - switch (req->bRequest) - { - case USB_REQ_GET_DESCRIPTOR: - USBD_GetDescriptor(pdev, req); - break; + case USB_REQ_TYPE_CLASS: + case USB_REQ_TYPE_VENDOR: + ret = (USBD_StatusTypeDef)pdev->pClass->Setup(pdev, req); + break; - case USB_REQ_SET_ADDRESS: - USBD_SetAddress(pdev, req); - break; + case USB_REQ_TYPE_STANDARD: + switch (req->bRequest) + { + case USB_REQ_GET_DESCRIPTOR: + USBD_GetDescriptor(pdev, req); + break; - case USB_REQ_SET_CONFIGURATION: - USBD_SetConfig(pdev, req); - break; + case USB_REQ_SET_ADDRESS: + USBD_SetAddress(pdev, req); + break; - case USB_REQ_GET_CONFIGURATION: - USBD_GetConfig(pdev, req); - break; + case USB_REQ_SET_CONFIGURATION: + ret = USBD_SetConfig(pdev, req); + break; - case USB_REQ_GET_STATUS: - USBD_GetStatus(pdev, req); - break; + case USB_REQ_GET_CONFIGURATION: + USBD_GetConfig(pdev, req); + break; - case USB_REQ_SET_FEATURE: - USBD_SetFeature(pdev, req); - break; + case USB_REQ_GET_STATUS: + USBD_GetStatus(pdev, req); + break; - case USB_REQ_CLEAR_FEATURE: - USBD_ClrFeature(pdev, req); - break; + case USB_REQ_SET_FEATURE: + USBD_SetFeature(pdev, req); + break; - default: - USBD_CtlError(pdev, req); - break; - } + case USB_REQ_CLEAR_FEATURE: + USBD_ClrFeature(pdev, req); break; default: USBD_CtlError(pdev, req); break; + } + break; + + default: + USBD_CtlError(pdev, req); + break; } return ret; @@ -175,49 +160,48 @@ USBD_StatusTypeDef USBD_StdDevReq(USBD_HandleTypeDef *pdev, * @param req: usb request * @retval status */ -USBD_StatusTypeDef USBD_StdItfReq(USBD_HandleTypeDef *pdev, - USBD_SetupReqTypedef *req) +USBD_StatusTypeDef USBD_StdItfReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { USBD_StatusTypeDef ret = USBD_OK; switch (req->bmRequest & USB_REQ_TYPE_MASK) { - case USB_REQ_TYPE_CLASS: - case USB_REQ_TYPE_VENDOR: - case USB_REQ_TYPE_STANDARD: - switch (pdev->dev_state) - { - case USBD_STATE_DEFAULT: - case USBD_STATE_ADDRESSED: - case USBD_STATE_CONFIGURED: - - if (LOBYTE(req->wIndex) <= USBD_MAX_NUM_INTERFACES) - { - ret = (USBD_StatusTypeDef)pdev->pClass->Setup(pdev, req); + case USB_REQ_TYPE_CLASS: + case USB_REQ_TYPE_VENDOR: + case USB_REQ_TYPE_STANDARD: + switch (pdev->dev_state) + { + case USBD_STATE_DEFAULT: + case USBD_STATE_ADDRESSED: + case USBD_STATE_CONFIGURED: - if ((req->wLength == 0U) && (ret == USBD_OK)) - { - USBD_CtlSendStatus(pdev); - } - } - else - { - USBD_CtlError(pdev, req); - } - break; + if (LOBYTE(req->wIndex) <= USBD_MAX_NUM_INTERFACES) + { + ret = (USBD_StatusTypeDef)pdev->pClass->Setup(pdev, req); - default: - USBD_CtlError(pdev, req); - break; + if ((req->wLength == 0U) && (ret == USBD_OK)) + { + (void)USBD_CtlSendStatus(pdev); + } + } + else + { + USBD_CtlError(pdev, req); } break; default: USBD_CtlError(pdev, req); break; + } + break; + + default: + USBD_CtlError(pdev, req); + break; } - return USBD_OK; + return ret; } /** @@ -227,168 +211,159 @@ USBD_StatusTypeDef USBD_StdItfReq(USBD_HandleTypeDef *pdev, * @param req: usb request * @retval status */ -USBD_StatusTypeDef USBD_StdEPReq(USBD_HandleTypeDef *pdev, - USBD_SetupReqTypedef *req) +USBD_StatusTypeDef USBD_StdEPReq(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { USBD_EndpointTypeDef *pep; - uint8_t ep_addr; + uint8_t ep_addr; USBD_StatusTypeDef ret = USBD_OK; - ep_addr = LOBYTE(req->wIndex); + ep_addr = LOBYTE(req->wIndex); switch (req->bmRequest & USB_REQ_TYPE_MASK) { - case USB_REQ_TYPE_CLASS: - case USB_REQ_TYPE_VENDOR: - pdev->pClass->Setup(pdev, req); - break; + case USB_REQ_TYPE_CLASS: + case USB_REQ_TYPE_VENDOR: + ret = (USBD_StatusTypeDef)pdev->pClass->Setup(pdev, req); + break; - case USB_REQ_TYPE_STANDARD: - /* Check if it is a class request */ - if ((req->bmRequest & 0x60U) == 0x20U) + case USB_REQ_TYPE_STANDARD: + switch (req->bRequest) + { + case USB_REQ_SET_FEATURE: + switch (pdev->dev_state) { - ret = (USBD_StatusTypeDef)pdev->pClass->Setup(pdev, req); + case USBD_STATE_ADDRESSED: + if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) + { + (void)USBD_LL_StallEP(pdev, ep_addr); + (void)USBD_LL_StallEP(pdev, 0x80U); + } + else + { + USBD_CtlError(pdev, req); + } + break; + + case USBD_STATE_CONFIGURED: + if (req->wValue == USB_FEATURE_EP_HALT) + { + if ((ep_addr != 0x00U) && (ep_addr != 0x80U) && (req->wLength == 0x00U)) + { + (void)USBD_LL_StallEP(pdev, ep_addr); + } + } + (void)USBD_CtlSendStatus(pdev); + + break; - return ret; + default: + USBD_CtlError(pdev, req); + break; } + break; + + case USB_REQ_CLEAR_FEATURE: - switch (req->bRequest) + switch (pdev->dev_state) { - case USB_REQ_SET_FEATURE: - switch (pdev->dev_state) + case USBD_STATE_ADDRESSED: + if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) + { + (void)USBD_LL_StallEP(pdev, ep_addr); + (void)USBD_LL_StallEP(pdev, 0x80U); + } + else + { + USBD_CtlError(pdev, req); + } + break; + + case USBD_STATE_CONFIGURED: + if (req->wValue == USB_FEATURE_EP_HALT) + { + if ((ep_addr & 0x7FU) != 0x00U) { - case USBD_STATE_ADDRESSED: - if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) - { - USBD_LL_StallEP(pdev, ep_addr); - USBD_LL_StallEP(pdev, 0x80U); - } - else - { - USBD_CtlError(pdev, req); - } - break; - - case USBD_STATE_CONFIGURED: - if (req->wValue == USB_FEATURE_EP_HALT) - { - if ((ep_addr != 0x00U) && - (ep_addr != 0x80U) && (req->wLength == 0x00U)) - { - USBD_LL_StallEP(pdev, ep_addr); - } - } - USBD_CtlSendStatus(pdev); - - break; - - default: - USBD_CtlError(pdev, req); - break; + (void)USBD_LL_ClearStallEP(pdev, ep_addr); } + (void)USBD_CtlSendStatus(pdev); + (USBD_StatusTypeDef)pdev->pClass->Setup(pdev, req); + } + break; + + default: + USBD_CtlError(pdev, req); + break; + } + break; + + case USB_REQ_GET_STATUS: + switch (pdev->dev_state) + { + case USBD_STATE_ADDRESSED: + if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) + { + USBD_CtlError(pdev, req); break; + } + pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ + &pdev->ep_out[ep_addr & 0x7FU]; - case USB_REQ_CLEAR_FEATURE: + pep->status = 0x0000U; - switch (pdev->dev_state) + (void)USBD_CtlSendData(pdev, (uint8_t *)&pep->status, 2U); + break; + + case USBD_STATE_CONFIGURED: + if ((ep_addr & 0x80U) == 0x80U) + { + if (pdev->ep_in[ep_addr & 0xFU].is_used == 0U) { - case USBD_STATE_ADDRESSED: - if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) - { - USBD_LL_StallEP(pdev, ep_addr); - USBD_LL_StallEP(pdev, 0x80U); - } - else - { - USBD_CtlError(pdev, req); - } - break; - - case USBD_STATE_CONFIGURED: - if (req->wValue == USB_FEATURE_EP_HALT) - { - if ((ep_addr & 0x7FU) != 0x00U) - { - USBD_LL_ClearStallEP(pdev, ep_addr); - } - USBD_CtlSendStatus(pdev); - } - break; - - default: - USBD_CtlError(pdev, req); - break; + USBD_CtlError(pdev, req); + break; } - break; + } + else + { + if (pdev->ep_out[ep_addr & 0xFU].is_used == 0U) + { + USBD_CtlError(pdev, req); + break; + } + } + + pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ + &pdev->ep_out[ep_addr & 0x7FU]; - case USB_REQ_GET_STATUS: - switch (pdev->dev_state) + if ((ep_addr == 0x00U) || (ep_addr == 0x80U)) { - case USBD_STATE_ADDRESSED: - if ((ep_addr != 0x00U) && (ep_addr != 0x80U)) - { - USBD_CtlError(pdev, req); - break; - } - pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ - &pdev->ep_out[ep_addr & 0x7FU]; - - pep->status = 0x0000U; - - USBD_CtlSendData(pdev, (uint8_t *)(void *)&pep->status, 2U); - break; - - case USBD_STATE_CONFIGURED: - if ((ep_addr & 0x80U) == 0x80U) - { - if (pdev->ep_in[ep_addr & 0xFU].is_used == 0U) - { - USBD_CtlError(pdev, req); - break; - } - } - else - { - if (pdev->ep_out[ep_addr & 0xFU].is_used == 0U) - { - USBD_CtlError(pdev, req); - break; - } - } - - pep = ((ep_addr & 0x80U) == 0x80U) ? &pdev->ep_in[ep_addr & 0x7FU] : \ - &pdev->ep_out[ep_addr & 0x7FU]; - - if ((ep_addr == 0x00U) || (ep_addr == 0x80U)) - { - pep->status = 0x0000U; - } - else if (USBD_LL_IsStallEP(pdev, ep_addr)) - { - pep->status = 0x0001U; - } - else - { - pep->status = 0x0000U; - } - - USBD_CtlSendData(pdev, (uint8_t *)(void *)&pep->status, 2U); - break; - - default: - USBD_CtlError(pdev, req); - break; + pep->status = 0x0000U; + } + else if (USBD_LL_IsStallEP(pdev, ep_addr) != 0U) + { + pep->status = 0x0001U; + } + else + { + pep->status = 0x0000U; } - break; - default: - USBD_CtlError(pdev, req); + (void)USBD_CtlSendData(pdev, (uint8_t *)&pep->status, 2U); break; + + default: + USBD_CtlError(pdev, req); + break; } break; default: USBD_CtlError(pdev, req); break; + } + break; + + default: + USBD_CtlError(pdev, req); + break; } return ret; @@ -402,8 +377,7 @@ USBD_StatusTypeDef USBD_StdEPReq(USBD_HandleTypeDef *pdev, * @param req: usb request * @retval status */ -static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev, - USBD_SetupReqTypedef *req) +static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { uint16_t len = 0U; uint8_t *pbuf = NULL; @@ -411,11 +385,43 @@ static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev, switch (req->wValue >> 8) { -#if (USBD_LPM_ENABLED == 1U) - case USB_DESC_TYPE_BOS: - if (pdev->pDesc->GetBOSDescriptor != NULL) +#if ((USBD_LPM_ENABLED == 1U) || (USBD_CLASS_BOS_ENABLED == 1U)) + case USB_DESC_TYPE_BOS: + if (pdev->pDesc->GetBOSDescriptor != NULL) + { + pbuf = pdev->pDesc->GetBOSDescriptor(pdev->dev_speed, &len); + } + else + { + USBD_CtlError(pdev, req); + err++; + } + break; +#endif + case USB_DESC_TYPE_DEVICE: + pbuf = pdev->pDesc->GetDeviceDescriptor(pdev->dev_speed, &len); + break; + + case USB_DESC_TYPE_CONFIGURATION: + if (pdev->dev_speed == USBD_SPEED_HIGH) + { + pbuf = pdev->pClass->GetHSConfigDescriptor(&len); + pbuf[1] = USB_DESC_TYPE_CONFIGURATION; + } + else + { + pbuf = pdev->pClass->GetFSConfigDescriptor(&len); + pbuf[1] = USB_DESC_TYPE_CONFIGURATION; + } + break; + + case USB_DESC_TYPE_STRING: + switch ((uint8_t)(req->wValue)) + { + case USBD_IDX_LANGID_STR: + if (pdev->pDesc->GetLangIDStrDescriptor != NULL) { - pbuf = pdev->pDesc->GetBOSDescriptor(pdev->dev_speed, &len); + pbuf = pdev->pDesc->GetLangIDStrDescriptor(pdev->dev_speed, &len); } else { @@ -423,122 +429,47 @@ static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev, err++; } break; -#endif - case USB_DESC_TYPE_DEVICE: - pbuf = pdev->pDesc->GetDeviceDescriptor(pdev->dev_speed, &len); - break; - case USB_DESC_TYPE_CONFIGURATION: - if (pdev->dev_speed == USBD_SPEED_HIGH) + case USBD_IDX_MFC_STR: + if (pdev->pDesc->GetManufacturerStrDescriptor != NULL) { - pbuf = pdev->pClass->GetHSConfigDescriptor(&len); - pbuf[1] = USB_DESC_TYPE_CONFIGURATION; + pbuf = pdev->pDesc->GetManufacturerStrDescriptor(pdev->dev_speed, &len); } else { - pbuf = pdev->pClass->GetFSConfigDescriptor(&len); - pbuf[1] = USB_DESC_TYPE_CONFIGURATION; + USBD_CtlError(pdev, req); + err++; } break; - case USB_DESC_TYPE_STRING: - switch ((uint8_t)(req->wValue)) + case USBD_IDX_PRODUCT_STR: + if (pdev->pDesc->GetProductStrDescriptor != NULL) { - case USBD_IDX_LANGID_STR: - if (pdev->pDesc->GetLangIDStrDescriptor != NULL) - { - pbuf = pdev->pDesc->GetLangIDStrDescriptor(pdev->dev_speed, &len); - } - else - { - USBD_CtlError(pdev, req); - err++; - } - break; - - case USBD_IDX_MFC_STR: - if (pdev->pDesc->GetManufacturerStrDescriptor != NULL) - { - pbuf = pdev->pDesc->GetManufacturerStrDescriptor(pdev->dev_speed, &len); - } - else - { - USBD_CtlError(pdev, req); - err++; - } - break; - - case USBD_IDX_PRODUCT_STR: - if (pdev->pDesc->GetProductStrDescriptor != NULL) - { - pbuf = pdev->pDesc->GetProductStrDescriptor(pdev->dev_speed, &len); - } - else - { - USBD_CtlError(pdev, req); - err++; - } - break; - - case USBD_IDX_SERIAL_STR: - if (pdev->pDesc->GetSerialStrDescriptor != NULL) - { - pbuf = pdev->pDesc->GetSerialStrDescriptor(pdev->dev_speed, &len); - } - else - { - USBD_CtlError(pdev, req); - err++; - } - break; - - case USBD_IDX_CONFIG_STR: - if (pdev->pDesc->GetConfigurationStrDescriptor != NULL) - { - pbuf = pdev->pDesc->GetConfigurationStrDescriptor(pdev->dev_speed, &len); - } - else - { - USBD_CtlError(pdev, req); - err++; - } - break; - - case USBD_IDX_INTERFACE_STR: - if (pdev->pDesc->GetInterfaceStrDescriptor != NULL) - { - pbuf = pdev->pDesc->GetInterfaceStrDescriptor(pdev->dev_speed, &len); - } - else - { - USBD_CtlError(pdev, req); - err++; - } - break; + pbuf = pdev->pDesc->GetProductStrDescriptor(pdev->dev_speed, &len); + } + else + { + USBD_CtlError(pdev, req); + err++; + } + break; - default: -#if (USBD_SUPPORT_USER_STRING_DESC == 1U) - if (pdev->pClass->GetUsrStrDescriptor != NULL) - { - pbuf = pdev->pClass->GetUsrStrDescriptor(pdev, (req->wValue), &len); - } - else - { - USBD_CtlError(pdev, req); - err++; - } - break; -#else - USBD_CtlError(pdev, req); - err++; -#endif + case USBD_IDX_SERIAL_STR: + if (pdev->pDesc->GetSerialStrDescriptor != NULL) + { + pbuf = pdev->pDesc->GetSerialStrDescriptor(pdev->dev_speed, &len); + } + else + { + USBD_CtlError(pdev, req); + err++; } break; - case USB_DESC_TYPE_DEVICE_QUALIFIER: - if (pdev->dev_speed == USBD_SPEED_HIGH) + case USBD_IDX_CONFIG_STR: + if (pdev->pDesc->GetConfigurationStrDescriptor != NULL) { - pbuf = pdev->pClass->GetDeviceQualifierDescriptor(&len); + pbuf = pdev->pDesc->GetConfigurationStrDescriptor(pdev->dev_speed, &len); } else { @@ -547,11 +478,10 @@ static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev, } break; - case USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION: - if (pdev->dev_speed == USBD_SPEED_HIGH) + case USBD_IDX_INTERFACE_STR: + if (pdev->pDesc->GetInterfaceStrDescriptor != NULL) { - pbuf = pdev->pClass->GetOtherSpeedConfigDescriptor(&len); - pbuf[1] = USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION; + pbuf = pdev->pDesc->GetInterfaceStrDescriptor(pdev->dev_speed, &len); } else { @@ -561,9 +491,63 @@ static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev, break; default: +#if (USBD_SUPPORT_USER_STRING_DESC == 1U) + if (pdev->pClass->GetUsrStrDescriptor != NULL) + { + pbuf = pdev->pClass->GetUsrStrDescriptor(pdev, (req->wValue), &len); + } + else + { + USBD_CtlError(pdev, req); + err++; + } +#elif (USBD_CLASS_USER_STRING_DESC == 1U) + if (pdev->pDesc->GetUserStrDescriptor != NULL) + { + pbuf = pdev->pDesc->GetUserStrDescriptor(pdev->dev_speed, (req->wValue), &len); + } + else + { + USBD_CtlError(pdev, req); + err++; + } +#else USBD_CtlError(pdev, req); err++; +#endif break; + } + break; + + case USB_DESC_TYPE_DEVICE_QUALIFIER: + if (pdev->dev_speed == USBD_SPEED_HIGH) + { + pbuf = pdev->pClass->GetDeviceQualifierDescriptor(&len); + } + else + { + USBD_CtlError(pdev, req); + err++; + } + break; + + case USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION: + if (pdev->dev_speed == USBD_SPEED_HIGH) + { + pbuf = pdev->pClass->GetOtherSpeedConfigDescriptor(&len); + pbuf[1] = USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION; + } + else + { + USBD_CtlError(pdev, req); + err++; + } + break; + + default: + USBD_CtlError(pdev, req); + err++; + break; } if (err != 0U) @@ -572,13 +556,19 @@ static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev, } else { - if ((len != 0U) && (req->wLength != 0U)) + if (req->wLength != 0U) { - len = MIN(len, req->wLength); - (void)USBD_CtlSendData(pdev, pbuf, len); + if (len != 0U) + { + len = MIN(len, req->wLength); + (void)USBD_CtlSendData(pdev, pbuf, len); + } + else + { + USBD_CtlError(pdev, req); + } } - - if (req->wLength == 0U) + else { (void)USBD_CtlSendStatus(pdev); } @@ -592,8 +582,7 @@ static void USBD_GetDescriptor(USBD_HandleTypeDef *pdev, * @param req: usb request * @retval status */ -static void USBD_SetAddress(USBD_HandleTypeDef *pdev, - USBD_SetupReqTypedef *req) +static void USBD_SetAddress(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { uint8_t dev_addr; @@ -608,8 +597,8 @@ static void USBD_SetAddress(USBD_HandleTypeDef *pdev, else { pdev->dev_address = dev_addr; - USBD_LL_SetUSBAddress(pdev, dev_addr); - USBD_CtlSendStatus(pdev); + (void)USBD_LL_SetUSBAddress(pdev, dev_addr); + (void)USBD_CtlSendStatus(pdev); if (dev_addr != 0U) { @@ -634,8 +623,9 @@ static void USBD_SetAddress(USBD_HandleTypeDef *pdev, * @param req: usb request * @retval status */ -static void USBD_SetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) +static USBD_StatusTypeDef USBD_SetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { + USBD_StatusTypeDef ret = USBD_OK; static uint8_t cfgidx; cfgidx = (uint8_t)(req->wValue); @@ -643,63 +633,77 @@ static void USBD_SetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) if (cfgidx > USBD_MAX_NUM_CONFIGURATION) { USBD_CtlError(pdev, req); + return USBD_FAIL; } - else + + switch (pdev->dev_state) { - switch (pdev->dev_state) + case USBD_STATE_ADDRESSED: + if (cfgidx != 0U) { - case USBD_STATE_ADDRESSED: - if (cfgidx) - { - pdev->dev_config = cfgidx; - pdev->dev_state = USBD_STATE_CONFIGURED; - if (USBD_SetClassConfig(pdev, cfgidx) == USBD_FAIL) - { - USBD_CtlError(pdev, req); - return; - } - USBD_CtlSendStatus(pdev); - } - else - { - USBD_CtlSendStatus(pdev); - } - break; + pdev->dev_config = cfgidx; - case USBD_STATE_CONFIGURED: - if (cfgidx == 0U) - { - pdev->dev_state = USBD_STATE_ADDRESSED; - pdev->dev_config = cfgidx; - USBD_ClrClassConfig(pdev, cfgidx); - USBD_CtlSendStatus(pdev); - } - else if (cfgidx != pdev->dev_config) - { - /* Clear old configuration */ - USBD_ClrClassConfig(pdev, (uint8_t)pdev->dev_config); + ret = USBD_SetClassConfig(pdev, cfgidx); - /* set new configuration */ - pdev->dev_config = cfgidx; - if (USBD_SetClassConfig(pdev, cfgidx) == USBD_FAIL) - { - USBD_CtlError(pdev, req); - return; - } - USBD_CtlSendStatus(pdev); - } - else - { - USBD_CtlSendStatus(pdev); - } - break; + if (ret != USBD_OK) + { + USBD_CtlError(pdev, req); + } + else + { + (void)USBD_CtlSendStatus(pdev); + pdev->dev_state = USBD_STATE_CONFIGURED; + } + } + else + { + (void)USBD_CtlSendStatus(pdev); + } + break; - default: + case USBD_STATE_CONFIGURED: + if (cfgidx == 0U) + { + pdev->dev_state = USBD_STATE_ADDRESSED; + pdev->dev_config = cfgidx; + (void)USBD_ClrClassConfig(pdev, cfgidx); + (void)USBD_CtlSendStatus(pdev); + } + else if (cfgidx != pdev->dev_config) + { + /* Clear old configuration */ + (void)USBD_ClrClassConfig(pdev, (uint8_t)pdev->dev_config); + + /* set new configuration */ + pdev->dev_config = cfgidx; + + ret = USBD_SetClassConfig(pdev, cfgidx); + + if (ret != USBD_OK) + { USBD_CtlError(pdev, req); - USBD_ClrClassConfig(pdev, cfgidx); - break; + (void)USBD_ClrClassConfig(pdev, (uint8_t)pdev->dev_config); + pdev->dev_state = USBD_STATE_ADDRESSED; + } + else + { + (void)USBD_CtlSendStatus(pdev); + } + } + else + { + (void)USBD_CtlSendStatus(pdev); } + break; + + default: + USBD_CtlError(pdev, req); + (void)USBD_ClrClassConfig(pdev, cfgidx); + ret = USBD_FAIL; + break; } + + return ret; } /** @@ -719,19 +723,19 @@ static void USBD_GetConfig(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { switch (pdev->dev_state) { - case USBD_STATE_DEFAULT: - case USBD_STATE_ADDRESSED: - pdev->dev_default_config = 0U; - USBD_CtlSendData(pdev, (uint8_t *)(void *)&pdev->dev_default_config, 1U); - break; + case USBD_STATE_DEFAULT: + case USBD_STATE_ADDRESSED: + pdev->dev_default_config = 0U; + (void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_default_config, 1U); + break; - case USBD_STATE_CONFIGURED: - USBD_CtlSendData(pdev, (uint8_t *)(void *)&pdev->dev_config, 1U); - break; + case USBD_STATE_CONFIGURED: + (void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_config, 1U); + break; - default: - USBD_CtlError(pdev, req); - break; + default: + USBD_CtlError(pdev, req); + break; } } } @@ -747,32 +751,32 @@ static void USBD_GetStatus(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { switch (pdev->dev_state) { - case USBD_STATE_DEFAULT: - case USBD_STATE_ADDRESSED: - case USBD_STATE_CONFIGURED: - if (req->wLength != 0x2U) - { - USBD_CtlError(pdev, req); - break; - } + case USBD_STATE_DEFAULT: + case USBD_STATE_ADDRESSED: + case USBD_STATE_CONFIGURED: + if (req->wLength != 0x2U) + { + USBD_CtlError(pdev, req); + break; + } #if (USBD_SELF_POWERED == 1U) - pdev->dev_config_status = USB_CONFIG_SELF_POWERED; + pdev->dev_config_status = USB_CONFIG_SELF_POWERED; #else - pdev->dev_config_status = 0U; + pdev->dev_config_status = 0U; #endif - if (pdev->dev_remote_wakeup) - { - pdev->dev_config_status |= USB_CONFIG_REMOTE_WAKEUP; - } + if (pdev->dev_remote_wakeup != 0U) + { + pdev->dev_config_status |= USB_CONFIG_REMOTE_WAKEUP; + } - USBD_CtlSendData(pdev, (uint8_t *)(void *)&pdev->dev_config_status, 2U); - break; + (void)USBD_CtlSendData(pdev, (uint8_t *)&pdev->dev_config_status, 2U); + break; - default: - USBD_CtlError(pdev, req); - break; + default: + USBD_CtlError(pdev, req); + break; } } @@ -784,13 +788,12 @@ static void USBD_GetStatus(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) * @param req: usb request * @retval status */ -static void USBD_SetFeature(USBD_HandleTypeDef *pdev, - USBD_SetupReqTypedef *req) +static void USBD_SetFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) { pdev->dev_remote_wakeup = 1U; - USBD_CtlSendStatus(pdev); + (void)USBD_CtlSendStatus(pdev); } } @@ -802,8 +805,7 @@ static void USBD_SetFeature(USBD_HandleTypeDef *pdev, * @param req: usb request * @retval status */ -static void USBD_ClrFeature(USBD_HandleTypeDef *pdev, - USBD_SetupReqTypedef *req) +static void USBD_ClrFeature(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { switch (pdev->dev_state) { @@ -813,7 +815,7 @@ static void USBD_ClrFeature(USBD_HandleTypeDef *pdev, if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) { pdev->dev_remote_wakeup = 0U; - USBD_CtlSendStatus(pdev); + (void)USBD_CtlSendStatus(pdev); } break; @@ -833,12 +835,23 @@ static void USBD_ClrFeature(USBD_HandleTypeDef *pdev, void USBD_ParseSetupRequest(USBD_SetupReqTypedef *req, uint8_t *pdata) { - req->bmRequest = *(uint8_t *)(pdata); - req->bRequest = *(uint8_t *)(pdata + 1U); - req->wValue = SWAPBYTE(pdata + 2U); - req->wIndex = SWAPBYTE(pdata + 4U); - req->wLength = SWAPBYTE(pdata + 6U); + uint8_t *pbuff = pdata; + + req->bmRequest = *(uint8_t *)(pbuff); + pbuff++; + req->bRequest = *(uint8_t *)(pbuff); + + pbuff++; + req->wValue = SWAPBYTE(pbuff); + + pbuff++; + pbuff++; + req->wIndex = SWAPBYTE(pbuff); + + pbuff++; + pbuff++; + req->wLength = SWAPBYTE(pbuff); } /** @@ -849,11 +862,12 @@ void USBD_ParseSetupRequest(USBD_SetupReqTypedef *req, uint8_t *pdata) * @retval None */ -void USBD_CtlError(USBD_HandleTypeDef *pdev, - USBD_SetupReqTypedef *req) +void USBD_CtlError(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req) { - USBD_LL_StallEP(pdev, 0x80U); - USBD_LL_StallEP(pdev, 0U); + UNUSED(req); + + (void)USBD_LL_StallEP(pdev, 0x80U); + (void)USBD_LL_StallEP(pdev, 0U); } @@ -868,18 +882,29 @@ void USBD_CtlError(USBD_HandleTypeDef *pdev, void USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len) { uint8_t idx = 0U; + uint8_t *pdesc; + + if (desc == NULL) + { + return; + } + + pdesc = desc; + *len = ((uint16_t)USBD_GetLen(pdesc) * 2U) + 2U; - if (desc != NULL) + unicode[idx] = *(uint8_t *)len; + idx++; + unicode[idx] = USB_DESC_TYPE_STRING; + idx++; + + while (*pdesc != (uint8_t)'\0') { - *len = (uint16_t)USBD_GetLen(desc) * 2U + 2U; - unicode[idx++] = *(uint8_t *)(void *)len; - unicode[idx++] = USB_DESC_TYPE_STRING; + unicode[idx] = *pdesc; + pdesc++; + idx++; - while (*desc != '\0') - { - unicode[idx++] = *desc++; - unicode[idx++] = 0U; - } + unicode[idx] = 0U; + idx++; } } @@ -892,11 +917,12 @@ void USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len) static uint8_t USBD_GetLen(uint8_t *buf) { uint8_t len = 0U; + uint8_t *pbuff = buf; - while (*buf != '\0') + while (*pbuff != (uint8_t)'\0') { len++; - buf++; + pbuff++; } return len; diff --git a/system/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_desc_template.c b/system/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_desc_template.c index ed0dfe2319..403936ddb0 100644 --- a/system/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_desc_template.c +++ b/system/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_desc_template.c @@ -46,9 +46,14 @@ uint8_t *USBD_Class_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *leng uint8_t *USBD_Class_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length); uint8_t *USBD_Class_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length); uint8_t *USBD_Class_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length); -#ifdef USBD_SUPPORT_USER_STRING_DESC -uint8_t *USBD_Class_USRStringDesc(USBD_SpeedTypeDef speed, uint8_t idx, uint16_t *length); -#endif /* USBD_SUPPORT_USER_STRING_DESC */ + +#if (USBD_CLASS_USER_STRING_DESC == 1) +uint8_t *USBD_Class_UserStrDescriptor(USBD_SpeedTypeDef speed, uint8_t idx, uint16_t *length); +#endif /* USB_CLASS_USER_STRING_DESC */ + +#if ((USBD_LPM_ENABLED == 1) || (USBD_CLASS_BOS_ENABLED == 1)) +uint8_t *USBD_USR_BOSDescriptor(USBD_SpeedTypeDef speed , uint16_t *length); +#endif /* Private variables ---------------------------------------------------------*/ USBD_DescriptorsTypeDef Class_Desc = @@ -60,17 +65,29 @@ USBD_DescriptorsTypeDef Class_Desc = USBD_Class_SerialStrDescriptor, USBD_Class_ConfigStrDescriptor, USBD_Class_InterfaceStrDescriptor, +#if (USBD_CLASS_USER_STRING_DESC == 1) + USBD_CLASS_UserStrDescriptor, +#endif + +#if ((USBD_LPM_ENABLED == 1) || (USBD_CLASS_BOS_ENABLED == 1)) + USBD_USR_BOSDescriptor, +#endif }; /* USB Standard Device Descriptor */ #if defined ( __ICCARM__ ) /*!< IAR Compiler */ #pragma data_alignment=4 #endif -__ALIGN_BEGIN uint8_t USBD_DeviceDesc[USB_LEN_DEV_DESC] __ALIGN_END = +__ALIGN_BEGIN uint8_t USBD_DeviceDesc[USB_LEN_DEV_DESC] __ALIGN_END = { 0x12, /* bLength */ USB_DESC_TYPE_DEVICE, /* bDescriptorType */ +#if ((USBD_LPM_ENABLED == 1) || (USBD_CLASS_BOS_ENABLED == 1)) + 0x01, /*bcdUSB */ /* changed to USB version 2.01 + in order to support BOS Desc */ +#else 0x00, /* bcdUSB */ +#endif 0x02, 0x00, /* bDeviceClass */ 0x00, /* bDeviceSubClass */ @@ -88,11 +105,123 @@ __ALIGN_BEGIN uint8_t USBD_DeviceDesc[USB_LEN_DEV_DESC] __ALIGN_END = USBD_MAX_NUM_CONFIGURATION /* bNumConfigurations */ }; /* USB_DeviceDescriptor */ + +/* USB Device LPM BOS descriptor */ +#if (USBD_LPM_ENABLED == 1) +#if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 +#endif +__ALIGN_BEGIN uint8_t USBD_BOSDesc[USB_SIZ_BOS_DESC] __ALIGN_END = +{ + 0x5, + USB_DESC_TYPE_BOS, + 0xC, + 0x0, + 0x1, /* 1 device capability */ + /* device capability */ + 0x7, + USB_DEVICE_CAPABITY_TYPE, + 0x2, + 0x6, /*LPM capability bit set */ + 0x0, + 0x0, + 0x0 +}; +#endif + +/* USB Device Billboard BOS descriptor Template */ +#if (USBD_CLASS_BOS_ENABLED == 1) +#if defined ( __ICCARM__ ) /*!< IAR Compiler */ + #pragma data_alignment=4 +#endif +__ALIGN_BEGIN uint8_t USBD_BOSDesc[USB_SIZ_BOS_DESC] __ALIGN_END = +{ +0x05, /* bLength */ +USB_DESC_TYPE_BOS, /* Device Descriptor Type */ +USB_SIZ_BOS_DESC, /* Total length of BOS descriptor and all of its sub descs */ +0x00, +0x04, /* The number of separate device capability descriptors in the BOS */ + + /* ----------- Device Capability Descriptor: CONTAINER_ID ---------- */ +0x14, /* bLength */ +0x10, /* bDescriptorType: DEVICE CAPABILITY Type */ +0x04, /* bDevCapabilityType: CONTAINER_ID */ +0x00, /* bReserved */ +0xa7, 0xd6, 0x1b, 0xfa, /* ContainerID: This is a Unique 128-bit number GUID */ +0x91, 0xa6, 0xa8, 0x4e, +0xa8, 0x21, 0x9f, 0x2b, +0xaf, 0xf7, 0x94, 0xd4, + + /* ----------- Device Capability Descriptor: BillBoard ---------- */ +0x34, /* bLength */ +0x10, /* bDescriptorType: DEVICE CAPABILITY Type */ +0x0D, /* bDevCapabilityType: BILLBOARD_CAPABILITY */ +USBD_BB_URL_STRING_INDEX, /* iAddtionalInfoURL: Index of string descriptor providing a URL where the user can go to get more + detailed information about the product and the various Alternate Modes it supports */ + +0x02, /* bNumberOfAlternateModes: Number of Alternate modes supported. The + maximum value that this field can be set to is MAX_NUM_ALT_MODE. */ + +0x00, /* bPreferredAlternateMode: Index of the preferred Alternate Mode. System + software may use this information to provide the user with a better user experience. */ + +0x00, 0x00, /* VCONN Power needed by the adapter for full functionality 000b = 1W */ + +0x01,0x00,0x00,0x00, /* bmConfigured. 01b: Alternate Mode configuration not attempted or exited */ +0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00, +0x21, 0x01, /* bcdVersion = 0x0121 */ +0x00, /* bAdditionalFailureInfo */ +0x00, /* bReserved */ +LOBYTE(USBD_VID), +HIBYTE(USBD_VID), /* wSVID[0]: Standard or Vendor ID. This shall match one of the SVIDs + returned in response to a USB PD Discover SVIDs command */ + +0x00, /* bAlternateMode[0] Index of the Alternate Mode within the SVID as + returned in response to a Discover Modes command. Example: + 0 � first Mode entry + 1 � second mode entry */ + +USBD_BB_ALTMODE0_STRING_INDEX, /* iAlternateModeString[0]: Index of string descriptor describing protocol. + It is optional to support this string. */ +LOBYTE(USBD_VID), +HIBYTE(USBD_VID), /* wSVID[1]: Standard or Vendor ID. This shall match one of the SVIDs + returned in response to a USB PD Discover SVIDs command */ + +0x01, /* bAlternateMode[1] Index of the Alternate Mode within the SVID as + returned in response to a Discover Modes command. Example: + 0 � first Mode entry + 1 � second Mode entry */ + +USBD_BB_ALTMODE1_STRING_INDEX, /* iAlternateModeString[1]: Index of string descriptor describing protocol. + It is optional to support this string. */ + /* Alternate Mode Desc */ + /* ----------- Device Capability Descriptor: BillBoard Alternate Mode Desc ---------- */ +0x08, /* bLength */ +0x10, /* bDescriptorType: Device Descriptor Type */ +0x0F, /* bDevCapabilityType: BILLBOARD ALTERNATE MODE CAPABILITY */ +0x00, /* bIndex: Index of Alternate Mode described in the Billboard Capability Desc */ +0x10, 0x00, 0x00, 0x00, /* dwAlternateModeVdo: contents of the Mode VDO for the alternate mode identified by bIndex */ + +0x08, /* bLength */ +0x10, /* bDescriptorType: Device Descriptor Type */ +0x0F, /* bDevCapabilityType: BILLBOARD ALTERNATE MODE CAPABILITY */ +0x01, /* bIndex: Index of Alternate Mode described in the Billboard Capability Desc */ +0x20, 0x00, 0x00, 0x00, /* dwAlternateModeVdo: contents of the Mode VDO for the alternate mode identified by bIndex */ +}; +#endif + + /* USB Standard Device Descriptor */ #if defined ( __ICCARM__ ) /*!< IAR Compiler */ #pragma data_alignment=4 #endif -__ALIGN_BEGIN uint8_t USBD_LangIDDesc[USB_LEN_LANGID_STR_DESC] __ALIGN_END = +__ALIGN_BEGIN uint8_t USBD_LangIDDesc[USB_LEN_LANGID_STR_DESC] __ALIGN_END = { USB_LEN_LANGID_STR_DESC, USB_DESC_TYPE_STRING, @@ -100,7 +229,10 @@ __ALIGN_BEGIN uint8_t USBD_LangIDDesc[USB_LEN_LANGID_STR_DESC] __ALIGN_END = HIBYTE(USBD_LANGID_STRING), }; -uint8_t USBD_StringSerial[USB_SIZ_STRING_SERIAL] = +#if defined ( __ICCARM__ ) /*!< IAR Compiler */ +#pragma data_alignment=4 +#endif +__ALIGN_BEGIN uint8_t USBD_StringSerial[USB_SIZ_STRING_SERIAL] = { USB_SIZ_STRING_SERIAL, USB_DESC_TYPE_STRING, @@ -123,6 +255,8 @@ static void Get_SerialNum(void); */ uint8_t *USBD_Class_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { + UNUSED(speed); + *length = sizeof(USBD_DeviceDesc); return (uint8_t *)USBD_DeviceDesc; } @@ -135,6 +269,8 @@ uint8_t *USBD_Class_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) */ uint8_t *USBD_Class_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { + UNUSED(speed); + *length = sizeof(USBD_LangIDDesc); return (uint8_t *)USBD_LangIDDesc; } @@ -166,6 +302,8 @@ uint8_t *USBD_Class_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *leng */ uint8_t *USBD_Class_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { + UNUSED(speed); + USBD_GetString((uint8_t *)USBD_MANUFACTURER_STRING, USBD_StrDesc, length); return USBD_StrDesc; } @@ -178,6 +316,8 @@ uint8_t *USBD_Class_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t */ uint8_t *USBD_Class_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { + UNUSED(speed); + *length = USB_SIZ_STRING_SERIAL; /* Update the serial number string descriptor with the data from the unique ID*/ @@ -246,6 +386,40 @@ static void Get_SerialNum(void) } } + +#if ((USBD_LPM_ENABLED == 1) || (USBD_CLASS_BOS_ENABLED == 1)) +/** + * @brief USBD_USR_BOSDescriptor + * return the BOS descriptor + * @param speed : current device speed + * @param length : pointer to data length variable + * @retval pointer to descriptor buffer + */ +uint8_t *USBD_USR_BOSDescriptor(USBD_SpeedTypeDef speed , uint16_t *length) +{ + *length = sizeof(USBD_BOSDesc); + return (uint8_t*)USBD_BOSDesc; +} +#endif + + +#if (USBD_CLASS_USER_STRING_DESC == 1) +/** + * @brief Returns the Class User string descriptor. + * @param speed: Current device speed + * @param idx: index of string descriptor + * @param length: Pointer to data length variable + * @retval Pointer to descriptor buffer + */ +uint8_t *USBD_Class_UserStrDescriptor(USBD_SpeedTypeDef speed, uint8_t idx, uint16_t *length) +{ + static uint8_t USBD_StrDesc[255]; + + return USBD_StrDesc; +} +#endif + + /** * @brief Convert Hex 32Bits value into char * @param value: value to convert diff --git a/system/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c b/system/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c index 7e969de646..8ac5491ffe 100644 --- a/system/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c +++ b/system/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c @@ -85,15 +85,15 @@ * @retval status */ USBD_StatusTypeDef USBD_CtlSendData(USBD_HandleTypeDef *pdev, - uint8_t *pbuf, uint16_t len) + uint8_t *pbuf, uint32_t len) { /* Set EP0 State */ pdev->ep0_state = USBD_EP0_DATA_IN; pdev->ep_in[0].total_length = len; - pdev->ep_in[0].rem_length = len; + pdev->ep_in[0].rem_length = len; /* Start the transfer */ - USBD_LL_Transmit(pdev, 0x00U, pbuf, len); + (void)USBD_LL_Transmit(pdev, 0x00U, pbuf, len); return USBD_OK; } @@ -107,10 +107,10 @@ USBD_StatusTypeDef USBD_CtlSendData(USBD_HandleTypeDef *pdev, * @retval status */ USBD_StatusTypeDef USBD_CtlContinueSendData(USBD_HandleTypeDef *pdev, - uint8_t *pbuf, uint16_t len) + uint8_t *pbuf, uint32_t len) { /* Start the next transfer */ - USBD_LL_Transmit(pdev, 0x00U, pbuf, len); + (void)USBD_LL_Transmit(pdev, 0x00U, pbuf, len); return USBD_OK; } @@ -124,15 +124,15 @@ USBD_StatusTypeDef USBD_CtlContinueSendData(USBD_HandleTypeDef *pdev, * @retval status */ USBD_StatusTypeDef USBD_CtlPrepareRx(USBD_HandleTypeDef *pdev, - uint8_t *pbuf, uint16_t len) + uint8_t *pbuf, uint32_t len) { /* Set EP0 State */ pdev->ep0_state = USBD_EP0_DATA_OUT; pdev->ep_out[0].total_length = len; - pdev->ep_out[0].rem_length = len; + pdev->ep_out[0].rem_length = len; /* Start the transfer */ - USBD_LL_PrepareReceive(pdev, 0U, pbuf, len); + (void)USBD_LL_PrepareReceive(pdev, 0U, pbuf, len); return USBD_OK; } @@ -146,9 +146,9 @@ USBD_StatusTypeDef USBD_CtlPrepareRx(USBD_HandleTypeDef *pdev, * @retval status */ USBD_StatusTypeDef USBD_CtlContinueRx(USBD_HandleTypeDef *pdev, - uint8_t *pbuf, uint16_t len) + uint8_t *pbuf, uint32_t len) { - USBD_LL_PrepareReceive(pdev, 0U, pbuf, len); + (void)USBD_LL_PrepareReceive(pdev, 0U, pbuf, len); return USBD_OK; } @@ -165,7 +165,7 @@ USBD_StatusTypeDef USBD_CtlSendStatus(USBD_HandleTypeDef *pdev) pdev->ep0_state = USBD_EP0_STATUS_IN; /* Start the transfer */ - USBD_LL_Transmit(pdev, 0x00U, NULL, 0U); + (void)USBD_LL_Transmit(pdev, 0x00U, NULL, 0U); return USBD_OK; } @@ -182,7 +182,7 @@ USBD_StatusTypeDef USBD_CtlReceiveStatus(USBD_HandleTypeDef *pdev) pdev->ep0_state = USBD_EP0_STATUS_OUT; /* Start the transfer */ - USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U); + (void)USBD_LL_PrepareReceive(pdev, 0U, NULL, 0U); return USBD_OK; } diff --git a/system/Middlewares/ST/STM32_USB_Device_Library/Release_Notes.html b/system/Middlewares/ST/STM32_USB_Device_Library/Release_Notes.html index a7462bc882..c1432a6b65 100644 --- a/system/Middlewares/ST/STM32_USB_Device_Library/Release_Notes.html +++ b/system/Middlewares/ST/STM32_USB_Device_Library/Release_Notes.html @@ -923,7 +923,30 @@

    Update History

    -

    V2.5.3 / 30-April-2019

    Main +

    V2.6.0 / 27-December-2019

    Main +Changes

    + + + + + + + + + + + + + + + + + + + + + +
    • Integration of three new USB device Class drivers:
      • USB CDC ECM Class driver
      • USB CDC RNDIS Microsoft Class driver
      • USB Billboard Class driver
    • Fix mondatory misra-c 2012 violations
    • update user core and class template files
    • USB Core:
      • Fix unexpected EP0 stall during enumeration phase 
      • Improve APIs error management and prevent accessing NULL pointers
    • USB MSC Class:
      • Fix USBCV specific class tests
      • Fix mutliple error with SCSI commands handling
      • Protect medium access when host ask for medium ejection
    • USB CDC Class:
      • Add new function to inform user that current IN transfer is completed
      • update transmit and receive APIs to transfer up to 64KB
    • USB AUDIO Class:
      • Fix audio sync start buffer size
      • update user callback periodicTC args by adding pointer to user buffer and size
    • USB CustomHID Class:
      • Rework the OUT transfer complete and prevent automaticly re-enabling the OUT EP 
      • Add new user API to restart the OUT transfer: USBD_CUSTOM_HID_ReceivePacket()

    V2.5.3 / 30-April-2019

    Main Changes

    diff --git a/system/Middlewares/ST/STM32_USB_Host_Library/Class/AUDIO/Src/usbh_audio.c b/system/Middlewares/ST/STM32_USB_Host_Library/Class/AUDIO/Src/usbh_audio.c index 927522025e..4cdfe9da6b 100644 --- a/system/Middlewares/ST/STM32_USB_Host_Library/Class/AUDIO/Src/usbh_audio.c +++ b/system/Middlewares/ST/STM32_USB_Host_Library/Class/AUDIO/Src/usbh_audio.c @@ -277,7 +277,7 @@ static USBH_StatusTypeDef USBH_AUDIO_InterfaceInit(USBH_HandleTypeDef *phost) { USBH_AUDIO_BuildHeadphonePath(phost); - AUDIO_Handle->headphone.Pipe = USBH_AllocPipe(phost, AUDIO_Handle->headphone.Ep); + AUDIO_Handle->headphone.Pipe = USBH_AllocPipe(phost, AUDIO_Handle->headphone.Ep); /* Open pipe for IN endpoint */ USBH_OpenPipe(phost, @@ -289,13 +289,12 @@ static USBH_StatusTypeDef USBH_AUDIO_InterfaceInit(USBH_HandleTypeDef *phost) AUDIO_Handle->headphone.EpSize); USBH_LL_SetToggle(phost, AUDIO_Handle->headphone.Pipe, 0U); - } if (AUDIO_Handle->microphone.supported == 1U) { USBH_AUDIO_BuildMicrophonePath(phost); - AUDIO_Handle->microphone.Pipe = USBH_AllocPipe(phost, AUDIO_Handle->microphone.Ep); + AUDIO_Handle->microphone.Pipe = USBH_AllocPipe(phost, AUDIO_Handle->microphone.Ep); /* Open pipe for IN endpoint */ USBH_OpenPipe(phost, @@ -389,143 +388,178 @@ static USBH_StatusTypeDef USBH_AUDIO_ClassRequest(USBH_HandleTypeDef *phost) /* Switch AUDIO REQ state machine */ switch (AUDIO_Handle->req_state) { - case AUDIO_REQ_INIT: - case AUDIO_REQ_SET_DEFAULT_IN_INTERFACE: - if (AUDIO_Handle->microphone.supported == 1U) - { - req_status = USBH_SetInterface(phost, - AUDIO_Handle->microphone.interface, - 0U); + case AUDIO_REQ_INIT: + case AUDIO_REQ_SET_DEFAULT_IN_INTERFACE: + if (AUDIO_Handle->microphone.supported == 1U) + { + req_status = USBH_SetInterface(phost, + AUDIO_Handle->microphone.interface, + 0U); - if (req_status == USBH_OK) - { - AUDIO_Handle->req_state = AUDIO_REQ_SET_DEFAULT_OUT_INTERFACE; - } + if (req_status == USBH_OK) + { + AUDIO_Handle->req_state = AUDIO_REQ_SET_DEFAULT_OUT_INTERFACE; + } + else if (req_status == USBH_NOT_SUPPORTED) + { + USBH_ErrLog("Control error: AUDIO: Device Set interface request failed"); + status = USBH_FAIL; } else { - AUDIO_Handle->req_state = AUDIO_REQ_SET_DEFAULT_OUT_INTERFACE; + /* .. */ + } + } + else + { + AUDIO_Handle->req_state = AUDIO_REQ_SET_DEFAULT_OUT_INTERFACE; #if (USBH_USE_OS == 1U) - phost->os_msg = (uint32_t)USBH_URB_EVENT; + phost->os_msg = (uint32_t)USBH_URB_EVENT; #if (osCMSIS < 0x20000U) - (void)osMessagePut(phost->os_event, phost->os_msg, 0U); + (void)osMessagePut(phost->os_event, phost->os_msg, 0U); #else - (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, NULL); + (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, NULL); #endif #endif - } - break; + } + break; - case AUDIO_REQ_SET_DEFAULT_OUT_INTERFACE: - if (AUDIO_Handle->headphone.supported == 1U) - { - req_status = USBH_SetInterface(phost, - AUDIO_Handle->headphone.interface, - 0U); + case AUDIO_REQ_SET_DEFAULT_OUT_INTERFACE: + if (AUDIO_Handle->headphone.supported == 1U) + { + req_status = USBH_SetInterface(phost, + AUDIO_Handle->headphone.interface, + 0U); - if (req_status == USBH_OK) - { - AUDIO_Handle->req_state = AUDIO_REQ_CS_REQUESTS; - AUDIO_Handle->cs_req_state = AUDIO_REQ_GET_VOLUME; + if (req_status == USBH_OK) + { + AUDIO_Handle->req_state = AUDIO_REQ_CS_REQUESTS; + AUDIO_Handle->cs_req_state = AUDIO_REQ_GET_VOLUME; - AUDIO_Handle->temp_feature = AUDIO_Handle->headphone.asociated_feature; - AUDIO_Handle->temp_channels = AUDIO_Handle->headphone.asociated_channels; - } + AUDIO_Handle->temp_feature = AUDIO_Handle->headphone.asociated_feature; + AUDIO_Handle->temp_channels = AUDIO_Handle->headphone.asociated_channels; + } + else if (req_status == USBH_NOT_SUPPORTED) + { + USBH_ErrLog("Control error: AUDIO: Device Set interface request failed"); + status = USBH_FAIL; } else { - AUDIO_Handle->req_state = AUDIO_REQ_CS_REQUESTS; - AUDIO_Handle->cs_req_state = AUDIO_REQ_GET_VOLUME; + /* .. */ + } + } + else + { + AUDIO_Handle->req_state = AUDIO_REQ_CS_REQUESTS; + AUDIO_Handle->cs_req_state = AUDIO_REQ_GET_VOLUME; #if (USBH_USE_OS == 1U) - phost->os_msg = (uint32_t)USBH_URB_EVENT; + phost->os_msg = (uint32_t)USBH_URB_EVENT; #if (osCMSIS < 0x20000U) - (void)osMessagePut(phost->os_event, phost->os_msg, 0U); + (void)osMessagePut(phost->os_event, phost->os_msg, 0U); #else - (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, NULL); + (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, NULL); #endif #endif - } - break; + } + break; + + case AUDIO_REQ_CS_REQUESTS: + if (USBH_AUDIO_HandleCSRequest(phost) == USBH_OK) + { + AUDIO_Handle->req_state = AUDIO_REQ_SET_IN_INTERFACE; + } + break; - case AUDIO_REQ_CS_REQUESTS: - if (USBH_AUDIO_HandleCSRequest(phost) == USBH_OK) + case AUDIO_REQ_SET_IN_INTERFACE: + if (AUDIO_Handle->microphone.supported == 1U) + { + req_status = USBH_SetInterface(phost, + AUDIO_Handle->microphone.interface, + AUDIO_Handle->microphone.AltSettings); + + if (req_status == USBH_OK) { - AUDIO_Handle->req_state = AUDIO_REQ_SET_IN_INTERFACE; + AUDIO_Handle->req_state = AUDIO_REQ_SET_OUT_INTERFACE; } - break; - - case AUDIO_REQ_SET_IN_INTERFACE: - if (AUDIO_Handle->microphone.supported == 1U) + else if (req_status == USBH_NOT_SUPPORTED) { - req_status = USBH_SetInterface(phost, - AUDIO_Handle->microphone.interface, - AUDIO_Handle->microphone.AltSettings); - - if (req_status == USBH_OK) - { - AUDIO_Handle->req_state = AUDIO_REQ_SET_OUT_INTERFACE; - } + USBH_ErrLog("Control error: AUDIO: Device Set interface request failed"); + status = USBH_FAIL; } else { - AUDIO_Handle->req_state = AUDIO_REQ_SET_OUT_INTERFACE; + /* .. */ + } + } + else + { + AUDIO_Handle->req_state = AUDIO_REQ_SET_OUT_INTERFACE; #if (USBH_USE_OS == 1U) - phost->os_msg = (uint32_t)USBH_URB_EVENT; + phost->os_msg = (uint32_t)USBH_URB_EVENT; #if (osCMSIS < 0x20000U) - (void)osMessagePut(phost->os_event, phost->os_msg, 0U); + (void)osMessagePut(phost->os_event, phost->os_msg, 0U); #else - (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, NULL); + (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, NULL); #endif #endif + } + break; + case AUDIO_REQ_SET_OUT_INTERFACE: + if (AUDIO_Handle->headphone.supported == 1U) + { + req_status = USBH_SetInterface(phost, + AUDIO_Handle->headphone.interface, + AUDIO_Handle->headphone.AltSettings); + + if (req_status == USBH_OK) + { + AUDIO_Handle->req_state = AUDIO_REQ_IDLE; } - break; - case AUDIO_REQ_SET_OUT_INTERFACE: - if (AUDIO_Handle->headphone.supported == 1U) + else if (req_status == USBH_NOT_SUPPORTED) { - req_status = USBH_SetInterface(phost, - AUDIO_Handle->headphone.interface, - AUDIO_Handle->headphone.AltSettings); - - if (req_status == USBH_OK) - { - AUDIO_Handle->req_state = AUDIO_REQ_IDLE; - } - + USBH_ErrLog("Control error: AUDIO: Device Set interface request failed"); + status = USBH_FAIL; } else { - AUDIO_Handle->req_state = AUDIO_REQ_IDLE; + /* .. */ + } + } + else + { + AUDIO_Handle->req_state = AUDIO_REQ_IDLE; #if (USBH_USE_OS == 1U) - phost->os_msg = (uint32_t)USBH_URB_EVENT; + phost->os_msg = (uint32_t)USBH_URB_EVENT; #if (osCMSIS < 0x20000U) - (void)osMessagePut(phost->os_event, phost->os_msg, 0U); + (void)osMessagePut(phost->os_event, phost->os_msg, 0U); #else - (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, NULL); + (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, NULL); #endif #endif - } - break; - case AUDIO_REQ_IDLE: - AUDIO_Handle->play_state = AUDIO_PLAYBACK_INIT; - phost->pUser(phost, HOST_USER_CLASS_ACTIVE); - status = USBH_OK; + } + break; + case AUDIO_REQ_IDLE: + AUDIO_Handle->play_state = AUDIO_PLAYBACK_INIT; + phost->pUser(phost, HOST_USER_CLASS_ACTIVE); + status = USBH_OK; #if (USBH_USE_OS == 1U) - phost->os_msg = (uint32_t)USBH_CLASS_EVENT; + phost->os_msg = (uint32_t)USBH_CLASS_EVENT; #if (osCMSIS < 0x20000U) - (void)osMessagePut(phost->os_event, phost->os_msg, 0U); + (void)osMessagePut(phost->os_event, phost->os_msg, 0U); #else - (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, NULL); + (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, NULL); #endif #endif - break; + break; - default: - break; + default: + break; } return status; } diff --git a/system/Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Src/usbh_cdc.c b/system/Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Src/usbh_cdc.c index d89b8638db..e32d00de56 100644 --- a/system/Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Src/usbh_cdc.c +++ b/system/Middlewares/ST/STM32_USB_Host_Library/Class/CDC/Src/usbh_cdc.c @@ -307,15 +307,24 @@ static USBH_StatusTypeDef USBH_CDC_InterfaceDeInit(USBH_HandleTypeDef *phost) */ static USBH_StatusTypeDef USBH_CDC_ClassRequest(USBH_HandleTypeDef *phost) { - USBH_StatusTypeDef status = USBH_FAIL ; + USBH_StatusTypeDef status; CDC_HandleTypeDef *CDC_Handle = (CDC_HandleTypeDef *) phost->pActiveClass->pData; - /*Issue the get line coding request*/ - status = GetLineCoding(phost, &CDC_Handle->LineCoding); + /* Issue the get line coding request */ + status = GetLineCoding(phost, &CDC_Handle->LineCoding); if (status == USBH_OK) { phost->pUser(phost, HOST_USER_CLASS_ACTIVE); } + else if (status == USBH_NOT_SUPPORTED) + { + USBH_ErrLog("Control error: CDC: Device Get Line Coding configuration failed"); + } + else + { + /* .. */ + } + return status; } @@ -392,7 +401,7 @@ static USBH_StatusTypeDef USBH_CDC_Process(USBH_HandleTypeDef *phost) if (req_status == USBH_OK) { /*Change the state to waiting*/ - CDC_Handle->state = CDC_IDLE_STATE ; + CDC_Handle->state = CDC_IDLE_STATE; } break; diff --git a/system/Middlewares/ST/STM32_USB_Host_Library/Class/HID/Src/usbh_hid.c b/system/Middlewares/ST/STM32_USB_Host_Library/Class/HID/Src/usbh_hid.c index be9b308db6..c8aba02a3d 100644 --- a/system/Middlewares/ST/STM32_USB_Host_Library/Class/HID/Src/usbh_hid.c +++ b/system/Middlewares/ST/STM32_USB_Host_Library/Class/HID/Src/usbh_hid.c @@ -286,64 +286,78 @@ static USBH_StatusTypeDef USBH_HID_ClassRequest(USBH_HandleTypeDef *phost) /* Switch HID state machine */ switch (HID_Handle->ctl_state) { - case HID_REQ_INIT: - case HID_REQ_GET_HID_DESC: + case HID_REQ_INIT: + case HID_REQ_GET_HID_DESC: - /* Get HID Desc */ - if (USBH_HID_GetHIDDescriptor(phost, USB_HID_DESC_SIZE) == USBH_OK) - { - - USBH_HID_ParseHIDDesc(&HID_Handle->HID_Desc, phost->device.Data); - HID_Handle->ctl_state = HID_REQ_GET_REPORT_DESC; - } - - break; - case HID_REQ_GET_REPORT_DESC: + USBH_HID_ParseHIDDesc(&HID_Handle->HID_Desc, phost->device.CfgDesc_Raw); + HID_Handle->ctl_state = HID_REQ_GET_REPORT_DESC; - /* Get Report Desc */ - if (USBH_HID_GetHIDReportDescriptor(phost, HID_Handle->HID_Desc.wItemLength) == USBH_OK) - { - /* The descriptor is available in phost->device.Data */ + break; + case HID_REQ_GET_REPORT_DESC: - HID_Handle->ctl_state = HID_REQ_SET_IDLE; - } + /* Get Report Desc */ + classReqStatus = USBH_HID_GetHIDReportDescriptor(phost, HID_Handle->HID_Desc.wItemLength); + if (classReqStatus == USBH_OK) + { + /* The descriptor is available in phost->device.Data */ + HID_Handle->ctl_state = HID_REQ_SET_IDLE; + } + else if (classReqStatus == USBH_NOT_SUPPORTED) + { + USBH_ErrLog("Control error: HID: Device Get Report Descriptor request failed"); + status = USBH_FAIL; + } + else + { + /* .. */ + } - break; + break; - case HID_REQ_SET_IDLE: + case HID_REQ_SET_IDLE: - classReqStatus = USBH_HID_SetIdle(phost, 0U, 0U); + classReqStatus = USBH_HID_SetIdle(phost, 0U, 0U); - /* set Idle */ - if (classReqStatus == USBH_OK) + /* set Idle */ + if (classReqStatus == USBH_OK) + { + HID_Handle->ctl_state = HID_REQ_SET_PROTOCOL; + } + else + { + if (classReqStatus == USBH_NOT_SUPPORTED) { HID_Handle->ctl_state = HID_REQ_SET_PROTOCOL; } - else - { - if (classReqStatus == USBH_NOT_SUPPORTED) - { - HID_Handle->ctl_state = HID_REQ_SET_PROTOCOL; - } - } - break; + } + break; - case HID_REQ_SET_PROTOCOL: - /* set protocol */ - if (USBH_HID_SetProtocol(phost, 0U) == USBH_OK) - { - HID_Handle->ctl_state = HID_REQ_IDLE; + case HID_REQ_SET_PROTOCOL: + /* set protocol */ + classReqStatus = USBH_HID_SetProtocol(phost, 0U); + if (classReqStatus == USBH_OK) + { + HID_Handle->ctl_state = HID_REQ_IDLE; - /* all requests performed*/ - phost->pUser(phost, HOST_USER_CLASS_ACTIVE); - status = USBH_OK; - } - break; + /* all requests performed*/ + phost->pUser(phost, HOST_USER_CLASS_ACTIVE); + status = USBH_OK; + } + else if (classReqStatus == USBH_NOT_SUPPORTED) + { + USBH_ErrLog("Control error: HID: Device Set protocol request failed"); + status = USBH_FAIL; + } + else + { + /* .. */ + } + break; - case HID_REQ_IDLE: - default: - break; + case HID_REQ_IDLE: + default: + break; } return status; @@ -687,14 +701,33 @@ USBH_StatusTypeDef USBH_HID_SetProtocol(USBH_HandleTypeDef *phost, */ static void USBH_HID_ParseHIDDesc(HID_DescTypeDef *desc, uint8_t *buf) { + USBH_DescHeader_t *pdesc = (USBH_DescHeader_t *)buf; + uint16_t CfgDescLen; + uint16_t ptr; + + CfgDescLen = LE16(buf + 2U); + + if (CfgDescLen > USB_CONFIGURATION_DESC_SIZE) + { + ptr = USB_LEN_CFG_DESC; - desc->bLength = *(uint8_t *)(buf + 0); - desc->bDescriptorType = *(uint8_t *)(buf + 1); - desc->bcdHID = LE16(buf + 2); - desc->bCountryCode = *(uint8_t *)(buf + 4); - desc->bNumDescriptors = *(uint8_t *)(buf + 5); - desc->bReportDescriptorType = *(uint8_t *)(buf + 6); - desc->wItemLength = LE16(buf + 7); + while (ptr < CfgDescLen) + { + pdesc = USBH_GetNextDesc((uint8_t *)pdesc, &ptr); + + if (pdesc->bDescriptorType == USB_DESC_TYPE_HID) + { + desc->bLength = *(uint8_t *)((uint8_t *)pdesc + 0U); + desc->bDescriptorType = *(uint8_t *)((uint8_t *)pdesc + 1U); + desc->bcdHID = LE16((uint8_t *)pdesc + 2U); + desc->bCountryCode = *(uint8_t *)((uint8_t *)pdesc + 4U); + desc->bNumDescriptors = *(uint8_t *)((uint8_t *)pdesc + 5U); + desc->bReportDescriptorType = *(uint8_t *)((uint8_t *)pdesc + 6U); + desc->wItemLength = LE16((uint8_t *)pdesc + 7U); + break; + } + } + } } /** diff --git a/system/Middlewares/ST/STM32_USB_Host_Library/Class/MSC/Inc/usbh_msc.h b/system/Middlewares/ST/STM32_USB_Host_Library/Class/MSC/Inc/usbh_msc.h index f3c139ff10..d452582369 100644 --- a/system/Middlewares/ST/STM32_USB_Host_Library/Class/MSC/Inc/usbh_msc.h +++ b/system/Middlewares/ST/STM32_USB_Host_Library/Class/MSC/Inc/usbh_msc.h @@ -107,7 +107,8 @@ MSC_LUNTypeDef; /* Structure for MSC process */ typedef struct _MSC_Process { - uint32_t max_lun; + uint8_t max_lun; + uint8_t Reserved[3]; uint8_t InPipe; uint8_t OutPipe; uint8_t OutEp; @@ -171,28 +172,18 @@ extern USBH_ClassTypeDef USBH_msc; /** @defgroup USBH_MSC_CORE_Exported_FunctionsPrototype * @{ */ +uint8_t USBH_MSC_IsReady(USBH_HandleTypeDef *phost); +uint8_t USBH_MSC_GetMaxLUN(USBH_HandleTypeDef *phost); +uint8_t USBH_MSC_UnitIsReady(USBH_HandleTypeDef *phost, uint8_t lun); -/* Common APIs */ -uint8_t USBH_MSC_IsReady(USBH_HandleTypeDef *phost); +USBH_StatusTypeDef USBH_MSC_GetLUNInfo(USBH_HandleTypeDef *phost, uint8_t lun, + MSC_LUNTypeDef *info); -/* APIs for LUN */ -uint8_t USBH_MSC_GetMaxLUN(USBH_HandleTypeDef *phost); +USBH_StatusTypeDef USBH_MSC_Read(USBH_HandleTypeDef *phost, uint8_t lun, + uint32_t address, uint8_t *pbuf, uint32_t length); -uint8_t USBH_MSC_UnitIsReady(USBH_HandleTypeDef *phost, uint8_t lun); - -USBH_StatusTypeDef USBH_MSC_GetLUNInfo(USBH_HandleTypeDef *phost, uint8_t lun, MSC_LUNTypeDef *info); - -USBH_StatusTypeDef USBH_MSC_Read(USBH_HandleTypeDef *phost, - uint8_t lun, - uint32_t address, - uint8_t *pbuf, - uint32_t length); - -USBH_StatusTypeDef USBH_MSC_Write(USBH_HandleTypeDef *phost, - uint8_t lun, - uint32_t address, - uint8_t *pbuf, - uint32_t length); +USBH_StatusTypeDef USBH_MSC_Write(USBH_HandleTypeDef *phost, uint8_t lun, + uint32_t address, uint8_t *pbuf, uint32_t length); /** * @} */ diff --git a/system/Middlewares/ST/STM32_USB_Host_Library/Class/MSC/Src/usbh_msc.c b/system/Middlewares/ST/STM32_USB_Host_Library/Class/MSC/Src/usbh_msc.c index 410cad388e..929132e7f2 100644 --- a/system/Middlewares/ST/STM32_USB_Host_Library/Class/MSC/Src/usbh_msc.c +++ b/system/Middlewares/ST/STM32_USB_Host_Library/Class/MSC/Src/usbh_msc.c @@ -274,7 +274,7 @@ static USBH_StatusTypeDef USBH_MSC_ClassRequest(USBH_HandleTypeDef *phost) case MSC_REQ_IDLE: case MSC_REQ_GET_MAX_LUN: /* Issue GetMaxLUN request */ - status = USBH_MSC_BOT_REQ_GetMaxLUN(phost, (uint8_t *)&MSC_Handle->max_lun); + status = USBH_MSC_BOT_REQ_GetMaxLUN(phost, &MSC_Handle->max_lun); /* When devices do not support the GetMaxLun request, this should be considred as only one logical unit is supported */ @@ -286,8 +286,8 @@ static USBH_StatusTypeDef USBH_MSC_ClassRequest(USBH_HandleTypeDef *phost) if (status == USBH_OK) { - MSC_Handle->max_lun = ((MSC_Handle->max_lun & 0xFFU) > MAX_SUPPORTED_LUN) ? MAX_SUPPORTED_LUN : ((MSC_Handle->max_lun & 0xFFU) + 1U); - USBH_UsrLog("Number of supported LUN: %lu", MSC_Handle->max_lun); + MSC_Handle->max_lun = (MSC_Handle->max_lun > MAX_SUPPORTED_LUN) ? MAX_SUPPORTED_LUN : (MSC_Handle->max_lun + 1U); + USBH_UsrLog("Number of supported LUN: %d", MSC_Handle->max_lun); for (i = 0U; i < MSC_Handle->max_lun; i++) { @@ -297,7 +297,7 @@ static USBH_StatusTypeDef USBH_MSC_ClassRequest(USBH_HandleTypeDef *phost) } break; - case MSC_REQ_ERROR : + case MSC_REQ_ERROR: /* a Clear Feature should be issued here */ if (USBH_ClrFeature(phost, 0x00U) == USBH_OK) { diff --git a/system/Middlewares/ST/STM32_USB_Host_Library/Core/Inc/usbh_def.h b/system/Middlewares/ST/STM32_USB_Host_Library/Core/Inc/usbh_def.h index c9078badf3..8ce334dc3c 100644 --- a/system/Middlewares/ST/STM32_USB_Host_Library/Core/Inc/usbh_def.h +++ b/system/Middlewares/ST/STM32_USB_Host_Library/Core/Inc/usbh_def.h @@ -53,6 +53,9 @@ extern "C" { #define TRUE 1U #endif +#ifndef USBH_DEV_RESET_TIMEOUT +#define USBH_DEV_RESET_TIMEOUT 1000U +#endif #define ValBit(VAR,POS) (VAR & (1 << POS)) #define SetBit(VAR,POS) (VAR |= (1 << POS)) @@ -416,12 +419,12 @@ typedef struct /* Attached device structure */ typedef struct { -#if (USBH_KEEP_CFG_DESCRIPTOR == 1U) uint8_t CfgDesc_Raw[USBH_MAX_SIZE_CONFIGURATION]; -#endif uint8_t Data[USBH_MAX_DATA_BUFFER]; uint8_t address; uint8_t speed; + uint8_t EnumCnt; + uint8_t RstCnt; __IO uint8_t is_connected; __IO uint8_t is_disconnected; __IO uint8_t is_ReEnumerated; @@ -459,6 +462,7 @@ typedef struct _USBH_HandleTypeDef uint32_t ClassNumber; uint32_t Pipes[16]; __IO uint32_t Timer; + uint32_t Timeout; uint8_t id; void *pData; void (* pUser)(struct _USBH_HandleTypeDef *pHandle, uint8_t id); diff --git a/system/Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_core.c b/system/Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_core.c index 6cbfd0c74e..76874c4f26 100644 --- a/system/Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_core.c +++ b/system/Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_core.c @@ -184,6 +184,8 @@ USBH_StatusTypeDef USBH_DeInit(USBH_HandleTypeDef *phost) phost->device.is_connected = 0U; phost->device.is_disconnected = 0U; phost->device.is_ReEnumerated = 0U; + phost->device.RstCnt = 0U; + phost->device.EnumCnt = 0U; if (phost->pData != NULL) { @@ -226,6 +228,8 @@ static USBH_StatusTypeDef DeInitStateMachine(USBH_HandleTypeDef *phost) phost->device.address = USBH_ADDRESS_DEFAULT; phost->device.speed = USBH_SPEED_FULL; + phost->device.RstCnt = 0U; + phost->device.EnumCnt = 0U; return USBH_OK; } @@ -425,7 +429,7 @@ USBH_StatusTypeDef USBH_ReEnumerate(USBH_HandleTypeDef *phost) { phost->device.is_ReEnumerated = 1U; - /*Stop Host */ + /* Stop Host */ USBH_Stop(phost); phost->device.is_disconnected = 1U; @@ -474,6 +478,10 @@ USBH_StatusTypeDef USBH_Process(USBH_HandleTypeDef *phost) USBH_Delay(200U); USBH_LL_ResetPort(phost); + /* Make sure to start with Default address */ + phost->device.address = USBH_ADDRESS_DEFAULT; + phost->Timeout = 0U; + #if (USBH_USE_OS == 1U) phost->os_msg = (uint32_t)USBH_PORT_EVENT; #if (osCMSIS < 0x20000U) @@ -490,8 +498,39 @@ USBH_StatusTypeDef USBH_Process(USBH_HandleTypeDef *phost) if (phost->device.PortEnabled == 1U) { USBH_UsrLog("USB Device Reset Completed"); + phost->device.RstCnt = 0U; phost->gState = HOST_DEV_ATTACHED; } + else + { + if (phost->Timeout > USBH_DEV_RESET_TIMEOUT) + { + phost->device.RstCnt++; + if (phost->device.RstCnt > 3U) + { + /* Buggy Device can't complete reset */ + USBH_UsrLog("USB Reset Failed, Please unplug the Device."); + phost->gState = HOST_ABORT_STATE; + } + else + { + phost->gState = HOST_IDLE; + } + } + else + { + phost->Timeout += 10U; + USBH_Delay(10U); + } + } +#if (USBH_USE_OS == 1U) + phost->os_msg = (uint32_t)USBH_PORT_EVENT; +#if (osCMSIS < 0x20000U) + (void)osMessagePut(phost->os_event, phost->os_msg, 0U); +#else + (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, NULL); +#endif +#endif break; case HOST_DEV_ATTACHED : @@ -511,24 +550,15 @@ USBH_StatusTypeDef USBH_Process(USBH_HandleTypeDef *phost) phost->Control.pipe_out = USBH_AllocPipe(phost, 0x00U); phost->Control.pipe_in = USBH_AllocPipe(phost, 0x80U); - /* Open Control pipes */ - USBH_OpenPipe(phost, - phost->Control.pipe_in, - 0x80U, - phost->device.address, - phost->device.speed, - USBH_EP_CONTROL, - (uint16_t)phost->Control.pipe_size); + USBH_OpenPipe(phost, phost->Control.pipe_in, 0x80U, + phost->device.address, phost->device.speed, + USBH_EP_CONTROL, (uint16_t)phost->Control.pipe_size); /* Open Control pipes */ - USBH_OpenPipe(phost, - phost->Control.pipe_out, - 0x00U, - phost->device.address, - phost->device.speed, - USBH_EP_CONTROL, - (uint16_t)phost->Control.pipe_size); + USBH_OpenPipe(phost, phost->Control.pipe_out, 0x00U, + phost->device.address, phost->device.speed, + USBH_EP_CONTROL, (uint16_t)phost->Control.pipe_size); #if (USBH_USE_OS == 1U) phost->os_msg = (uint32_t)USBH_PORT_EVENT; @@ -542,7 +572,8 @@ USBH_StatusTypeDef USBH_Process(USBH_HandleTypeDef *phost) case HOST_ENUMERATION: /* Check for enumeration status */ - if (USBH_HandleEnum(phost) == USBH_OK) + status = USBH_HandleEnum(phost); + if (status == USBH_OK) { /* The function shall return USBH_OK when full enumeration is complete */ USBH_UsrLog("Enumeration done."); @@ -553,13 +584,19 @@ USBH_StatusTypeDef USBH_Process(USBH_HandleTypeDef *phost) { USBH_UsrLog("This device has only 1 configuration."); phost->gState = HOST_SET_CONFIGURATION; - } else { phost->gState = HOST_INPUT; } - +#if (USBH_USE_OS == 1U) + phost->os_msg = (uint32_t)USBH_STATE_CHANGED_EVENT; +#if (osCMSIS < 0x20000U) + (void)osMessagePut(phost->os_event, phost->os_msg, 0U); +#else + (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, NULL); +#endif +#endif } break; @@ -641,6 +678,7 @@ USBH_StatusTypeDef USBH_Process(USBH_HandleTypeDef *phost) if (phost->pClass[idx]->ClassCode == phost->device.CfgDesc.Itf_Desc[0].bInterfaceClass) { phost->pActiveClass = phost->pClass[idx]; + break; } } @@ -687,21 +725,29 @@ USBH_StatusTypeDef USBH_Process(USBH_HandleTypeDef *phost) { phost->gState = HOST_CLASS; } + else if (status == USBH_FAIL) + { + phost->gState = HOST_ABORT_STATE; + USBH_ErrLog("Device not responding Please Unplug."); + } + else + { + /* .. */ + } } else { phost->gState = HOST_ABORT_STATE; USBH_ErrLog("Invalid Class Driver."); - + } #if (USBH_USE_OS == 1U) - phost->os_msg = (uint32_t)USBH_STATE_CHANGED_EVENT; + phost->os_msg = (uint32_t)USBH_STATE_CHANGED_EVENT; #if (osCMSIS < 0x20000U) - (void)osMessagePut(phost->os_event, phost->os_msg, 0U); + (void)osMessagePut(phost->os_event, phost->os_msg, 0U); #else - (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, NULL); + (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, NULL); #endif #endif - } break; case HOST_CLASS: @@ -770,52 +816,96 @@ USBH_StatusTypeDef USBH_Process(USBH_HandleTypeDef *phost) static USBH_StatusTypeDef USBH_HandleEnum(USBH_HandleTypeDef *phost) { USBH_StatusTypeDef Status = USBH_BUSY; + USBH_StatusTypeDef ReqStatus = USBH_BUSY; switch (phost->EnumState) { case ENUM_IDLE: /* Get Device Desc for only 1st 8 bytes : To get EP0 MaxPacketSize */ - if (USBH_Get_DevDesc(phost, 8U) == USBH_OK) + ReqStatus = USBH_Get_DevDesc(phost, 8U); + if (ReqStatus == USBH_OK) { phost->Control.pipe_size = phost->device.DevDesc.bMaxPacketSize; phost->EnumState = ENUM_GET_FULL_DEV_DESC; /* modify control channels configuration for MaxPacket size */ - USBH_OpenPipe(phost, - phost->Control.pipe_in, - 0x80U, - phost->device.address, - phost->device.speed, - USBH_EP_CONTROL, + USBH_OpenPipe(phost, phost->Control.pipe_in, 0x80U, phost->device.address, + phost->device.speed, USBH_EP_CONTROL, (uint16_t)phost->Control.pipe_size); /* Open Control pipes */ - USBH_OpenPipe(phost, - phost->Control.pipe_out, - 0x00U, - phost->device.address, - phost->device.speed, - USBH_EP_CONTROL, + USBH_OpenPipe(phost, phost->Control.pipe_out, 0x00U, phost->device.address, + phost->device.speed, USBH_EP_CONTROL, (uint16_t)phost->Control.pipe_size); } + else if (ReqStatus == USBH_NOT_SUPPORTED) + { + USBH_ErrLog("Control error: Get Device Descriptor request failed"); + phost->device.EnumCnt++; + if (phost->device.EnumCnt > 3U) + { + /* Buggy Device can't complete get device desc request */ + USBH_UsrLog("Control error, Device not Responding Please unplug the Device."); + phost->gState = HOST_ABORT_STATE; + } + else + { + /* free control pipes */ + USBH_FreePipe(phost, phost->Control.pipe_out); + USBH_FreePipe(phost, phost->Control.pipe_in); + + /* Reset the USB Device */ + phost->gState = HOST_IDLE; + } + } + else + { + /* .. */ + } break; case ENUM_GET_FULL_DEV_DESC: /* Get FULL Device Desc */ - if (USBH_Get_DevDesc(phost, USB_DEVICE_DESC_SIZE) == USBH_OK) + ReqStatus = USBH_Get_DevDesc(phost, USB_DEVICE_DESC_SIZE); + if (ReqStatus == USBH_OK) { USBH_UsrLog("PID: %xh", phost->device.DevDesc.idProduct); USBH_UsrLog("VID: %xh", phost->device.DevDesc.idVendor); phost->EnumState = ENUM_SET_ADDR; + } + else if (ReqStatus == USBH_NOT_SUPPORTED) + { + USBH_ErrLog("Control error: Get Full Device Descriptor request failed"); + phost->device.EnumCnt++; + if (phost->device.EnumCnt > 3U) + { + /* Buggy Device can't complete get device desc request */ + USBH_UsrLog("Control error, Device not Responding Please unplug the Device."); + phost->gState = HOST_ABORT_STATE; + } + else + { + /* Free control pipes */ + USBH_FreePipe(phost, phost->Control.pipe_out); + USBH_FreePipe(phost, phost->Control.pipe_in); + /* Reset the USB Device */ + phost->EnumState = ENUM_IDLE; + phost->gState = HOST_IDLE; + } + } + else + { + /* .. */ } break; case ENUM_SET_ADDR: /* set address */ - if (USBH_SetAddress(phost, USBH_DEVICE_ADDRESS) == USBH_OK) + ReqStatus = USBH_SetAddress(phost, USBH_DEVICE_ADDRESS); + if (ReqStatus == USBH_OK) { USBH_Delay(2U); phost->device.address = USBH_DEVICE_ADDRESS; @@ -825,52 +915,105 @@ static USBH_StatusTypeDef USBH_HandleEnum(USBH_HandleTypeDef *phost) phost->EnumState = ENUM_GET_CFG_DESC; /* modify control channels to update device address */ - USBH_OpenPipe(phost, - phost->Control.pipe_in, - 0x80U, - phost->device.address, - phost->device.speed, - USBH_EP_CONTROL, + USBH_OpenPipe(phost, phost->Control.pipe_in, 0x80U, phost->device.address, + phost->device.speed, USBH_EP_CONTROL, (uint16_t)phost->Control.pipe_size); /* Open Control pipes */ - USBH_OpenPipe(phost, - phost->Control.pipe_out, - 0x00U, - phost->device.address, - phost->device.speed, - USBH_EP_CONTROL, + USBH_OpenPipe(phost, phost->Control.pipe_out, 0x00U, phost->device.address, + phost->device.speed, USBH_EP_CONTROL, (uint16_t)phost->Control.pipe_size); } + else if (ReqStatus == USBH_NOT_SUPPORTED) + { + USBH_ErrLog("Control error: Device Set Address request failed"); + + /* Buggy Device can't complete get device desc request */ + USBH_UsrLog("Control error, Device not Responding Please unplug the Device."); + phost->gState = HOST_ABORT_STATE; + phost->EnumState = ENUM_IDLE; + } + else + { + /* .. */ + } break; case ENUM_GET_CFG_DESC: /* get standard configuration descriptor */ - if (USBH_Get_CfgDesc(phost, - USB_CONFIGURATION_DESC_SIZE) == USBH_OK) + ReqStatus = USBH_Get_CfgDesc(phost, USB_CONFIGURATION_DESC_SIZE); + if (ReqStatus == USBH_OK) { phost->EnumState = ENUM_GET_FULL_CFG_DESC; } + else if (ReqStatus == USBH_NOT_SUPPORTED) + { + USBH_ErrLog("Control error: Get Device configuration descriptor request failed"); + phost->device.EnumCnt++; + if (phost->device.EnumCnt > 3U) + { + /* Buggy Device can't complete get device desc request */ + USBH_UsrLog("Control error, Device not Responding Please unplug the Device."); + phost->gState = HOST_ABORT_STATE; + } + else + { + /* Free control pipes */ + USBH_FreePipe(phost, phost->Control.pipe_out); + USBH_FreePipe(phost, phost->Control.pipe_in); + + /* Reset the USB Device */ + phost->EnumState = ENUM_IDLE; + phost->gState = HOST_IDLE; + } + } + else + { + /* .. */ + } break; case ENUM_GET_FULL_CFG_DESC: /* get FULL config descriptor (config, interface, endpoints) */ - if (USBH_Get_CfgDesc(phost, - phost->device.CfgDesc.wTotalLength) == USBH_OK) + ReqStatus = USBH_Get_CfgDesc(phost, phost->device.CfgDesc.wTotalLength); + if (ReqStatus == USBH_OK) { phost->EnumState = ENUM_GET_MFC_STRING_DESC; } + else if (ReqStatus == USBH_NOT_SUPPORTED) + { + USBH_ErrLog("Control error: Get Device configuration descriptor request failed"); + phost->device.EnumCnt++; + if (phost->device.EnumCnt > 3U) + { + /* Buggy Device can't complete get device desc request */ + USBH_UsrLog("Control error, Device not Responding Please unplug the Device."); + phost->gState = HOST_ABORT_STATE; + } + else + { + /* Free control pipes */ + USBH_FreePipe(phost, phost->Control.pipe_out); + USBH_FreePipe(phost, phost->Control.pipe_in); + + /* Reset the USB Device */ + phost->EnumState = ENUM_IDLE; + phost->gState = HOST_IDLE; + } + } + else + { + /* .. */ + } break; case ENUM_GET_MFC_STRING_DESC: if (phost->device.DevDesc.iManufacturer != 0U) { /* Check that Manufacturer String is available */ - - if (USBH_Get_StringDesc(phost, - phost->device.DevDesc.iManufacturer, - phost->device.Data, - 0xFFU) == USBH_OK) + ReqStatus = USBH_Get_StringDesc(phost, phost->device.DevDesc.iManufacturer, + phost->device.Data, 0xFFU); + if (ReqStatus == USBH_OK) { /* User callback for Manufacturing string */ USBH_UsrLog("Manufacturer : %s", (char *)(void *)phost->device.Data); @@ -885,6 +1028,24 @@ static USBH_StatusTypeDef USBH_HandleEnum(USBH_HandleTypeDef *phost) #endif #endif } + else if (ReqStatus == USBH_NOT_SUPPORTED) + { + USBH_UsrLog("Manufacturer : N/A"); + phost->EnumState = ENUM_GET_PRODUCT_STRING_DESC; + +#if (USBH_USE_OS == 1U) + phost->os_msg = (uint32_t)USBH_STATE_CHANGED_EVENT; +#if (osCMSIS < 0x20000U) + (void)osMessagePut(phost->os_event, phost->os_msg, 0U); +#else + (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, NULL); +#endif +#endif + } + else + { + /* .. */ + } } else { @@ -906,15 +1067,32 @@ static USBH_StatusTypeDef USBH_HandleEnum(USBH_HandleTypeDef *phost) if (phost->device.DevDesc.iProduct != 0U) { /* Check that Product string is available */ - if (USBH_Get_StringDesc(phost, - phost->device.DevDesc.iProduct, - phost->device.Data, - 0xFFU) == USBH_OK) + ReqStatus = USBH_Get_StringDesc(phost, phost->device.DevDesc.iProduct, + phost->device.Data, 0xFFU); + if (ReqStatus == USBH_OK) { /* User callback for Product string */ USBH_UsrLog("Product : %s", (char *)(void *)phost->device.Data); phost->EnumState = ENUM_GET_SERIALNUM_STRING_DESC; } + else if (ReqStatus == USBH_NOT_SUPPORTED) + { + USBH_UsrLog("Product : N/A"); + phost->EnumState = ENUM_GET_SERIALNUM_STRING_DESC; + +#if (USBH_USE_OS == 1U) + phost->os_msg = (uint32_t)USBH_STATE_CHANGED_EVENT; +#if (osCMSIS < 0x20000U) + (void)osMessagePut(phost->os_event, phost->os_msg, 0U); +#else + (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, NULL); +#endif +#endif + } + else + { + /* .. */ + } } else { @@ -936,29 +1114,28 @@ static USBH_StatusTypeDef USBH_HandleEnum(USBH_HandleTypeDef *phost) if (phost->device.DevDesc.iSerialNumber != 0U) { /* Check that Serial number string is available */ - if (USBH_Get_StringDesc(phost, - phost->device.DevDesc.iSerialNumber, - phost->device.Data, - 0xFFU) == USBH_OK) + ReqStatus = USBH_Get_StringDesc(phost, phost->device.DevDesc.iSerialNumber, + phost->device.Data, 0xFFU); + if (ReqStatus == USBH_OK) { /* User callback for Serial number string */ USBH_UsrLog("Serial Number : %s", (char *)(void *)phost->device.Data); Status = USBH_OK; } + else if (ReqStatus == USBH_NOT_SUPPORTED) + { + USBH_UsrLog("Serial Number : N/A"); + Status = USBH_OK; + } + else + { + /* .. */ + } } else { USBH_UsrLog("Serial Number : N/A"); Status = USBH_OK; - -#if (USBH_USE_OS == 1U) - phost->os_msg = (uint32_t)USBH_STATE_CHANGED_EVENT; -#if (osCMSIS < 0x20000U) - (void)osMessagePut(phost->os_event, phost->os_msg, 0U); -#else - (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, NULL); -#endif -#endif } break; @@ -989,7 +1166,7 @@ void USBH_LL_SetTimer(USBH_HandleTypeDef *phost, uint32_t time) */ void USBH_LL_IncTimer(USBH_HandleTypeDef *phost) { - phost->Timer ++; + phost->Timer++; USBH_HandleSof(phost); } diff --git a/system/Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_ctlreq.c b/system/Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_ctlreq.c index b3391900a9..13e777e301 100644 --- a/system/Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_ctlreq.c +++ b/system/Middlewares/ST/STM32_USB_Host_Library/Core/Src/usbh_ctlreq.c @@ -132,13 +132,8 @@ USBH_StatusTypeDef USBH_Get_CfgDesc(USBH_HandleTypeDef *phost, { USBH_StatusTypeDef status; - uint8_t *pData; + uint8_t *pData = phost->device.CfgDesc_Raw;; -#if (USBH_KEEP_CFG_DESCRIPTOR == 1U) - pData = phost->device.CfgDesc_Raw; -#else - pData = phost->device.Data; -#endif if ((status = USBH_GetDescriptor(phost, (USB_REQ_RECIPIENT_DEVICE | USB_REQ_TYPE_STANDARD), USB_DESC_CONFIGURATION, pData, length)) == USBH_OK) { @@ -575,29 +570,29 @@ USBH_StatusTypeDef USBH_CtlReq(USBH_HandleTypeDef *phost, uint8_t *buff, case CMD_WAIT: status = USBH_HandleControl(phost); - if (status == USBH_OK) + if ((status == USBH_OK) || (status == USBH_NOT_SUPPORTED)) { - /* Commands successfully sent and Response Received */ + /* Transaction completed, move control state to idle */ phost->RequestState = CMD_SEND; phost->Control.state = CTRL_IDLE; - status = USBH_OK; } - else if (status == USBH_NOT_SUPPORTED) + else if (status == USBH_FAIL) { - /* Commands successfully sent and Response Received */ + /* Failure Mode */ phost->RequestState = CMD_SEND; - phost->Control.state = CTRL_IDLE; - status = USBH_NOT_SUPPORTED; } else { - if (status == USBH_FAIL) - { - /* Failure Mode */ - phost->RequestState = CMD_SEND; - status = USBH_FAIL; - } + /* .. */ } +#if (USBH_USE_OS == 1U) + phost->os_msg = (uint32_t)USBH_CONTROL_EVENT; +#if (osCMSIS < 0x20000U) + (void)osMessagePut(phost->os_event, phost->os_msg, 0U); +#else + (void)osMessageQueuePut(phost->os_event, &phost->os_msg, 0U, NULL); +#endif +#endif break; default: @@ -968,6 +963,11 @@ static USBH_StatusTypeDef USBH_HandleControl(USBH_HandleTypeDef *phost) phost->pUser(phost, HOST_USER_UNRECOVERED_ERROR); phost->Control.errorcount = 0U; USBH_ErrLog("Control error: Device not responding"); + + /* Free control pipes */ + USBH_FreePipe(phost, phost->Control.pipe_out); + USBH_FreePipe(phost, phost->Control.pipe_in); + phost->gState = HOST_IDLE; status = USBH_FAIL; } diff --git a/system/Middlewares/ST/STM32_USB_Host_Library/Release_Notes.html b/system/Middlewares/ST/STM32_USB_Host_Library/Release_Notes.html index 86c4104435..beaf939523 100644 --- a/system/Middlewares/ST/STM32_USB_Host_Library/Release_Notes.html +++ b/system/Middlewares/ST/STM32_USB_Host_Library/Release_Notes.html @@ -917,7 +917,10 @@

    -

    Update History

    V3.3.3 / 29-April-2019

    Main Changes

    • Fix misra-C 2012 high severity violations
    • Core driver:
      • usbh_core.c: Rework USB host Core process in order to improve Device connection / disconnection robustness
    • MSC Class
      • usbh_msc.c
        • Update USBH_MSC_GetMaxLUN() to prevent corruption of supported LUNs
    • HID Class
      • prevent +

        Update History

        V3.3.4 / 08-January-2020

        Main Changes

        • Core driver:
          • Improve enumeration phase and avoid silent responses.
          • Add device reset trial mechanism during enumeration phase.
        • MSC Class
          • usbh_msc.c
            • update max_lun field to be uint8_t instead of  uint32_t.
        • HID Class
          • Get +HID descriptor by parsing the device descriptor in order to improve +interoperability with buggy devices that Stall host Get HID descriptor +request.

        V3.3.3 / 29-April-2019

        Main Changes

        • Fix misra-C 2012 high severity violations
        • Core driver:
          • usbh_core.c: Rework USB host Core process in order to improve Device connection / disconnection robustness
        • MSC Class
          • usbh_msc.c
            • Update USBH_MSC_GetMaxLUN() to prevent corruption of supported LUNs
        • HID Class
          • prevent race between USB buffer and Application fifo buffer, this was ensured by allocating a dedicated buffer for received report
          • Prevent overflow on USB buffer for devices that could have report size greater than 4bytes

        V3.3.2 / 24-January-2019

        Main Changes

        • Core driver:
          • usbh_core.c: fix on USBH_Deinit() API, prevent freeing pActiveClass->pData diff --git a/system/STM32F0xx/system_stm32f0xx.c b/system/STM32F0xx/system_stm32f0xx.c index 7569eb7b4f..de51a5dd5a 100644 --- a/system/STM32F0xx/system_stm32f0xx.c +++ b/system/STM32F0xx/system_stm32f0xx.c @@ -6,7 +6,7 @@ * * 1. This file provides two functions and one global variable to be called from * user application: - * - SystemInit(): This function is called at startup just after reset and + * - SystemInit(): This function is called at startup just after reset and * before branch to main program. This call is made inside * the "startup_stm32f0xx.s" file. * @@ -101,7 +101,7 @@ 2) by calling HAL API function HAL_RCC_GetHCLKFreq() 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency Note: If you use this function to configure the system clock there is no need to - call the 2 first functions listed above, since SystemCoreClock variable is + call the 2 first functions listed above, since SystemCoreClock variable is updated automatically. */ uint32_t SystemCoreClock = 8000000; @@ -271,7 +271,7 @@ void SystemCoreClockUpdate (void) #else /* HSI used as PLL clock source : SystemCoreClock = HSI/2 * PLLMUL */ SystemCoreClock = (HSI_VALUE >> 1) * pllmull; -#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || +#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || STM32F091xC || STM32F098xx || STM32F030xC */ } diff --git a/system/STM32F4xx/system_stm32f4xx.c b/system/STM32F4xx/system_stm32f4xx.c index 143c538a28..1c165b088d 100644 --- a/system/STM32F4xx/system_stm32f4xx.c +++ b/system/STM32F4xx/system_stm32f4xx.c @@ -22,29 +22,13 @@ ****************************************************************************** * @attention * - *

            © COPYRIGHT 2017 STMicroelectronics

            +*

            © Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

            * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ diff --git a/system/STM32F7xx/system_stm32f7xx.c b/system/STM32F7xx/system_stm32f7xx.c index 013a7b4d6b..ccbf5667b4 100644 --- a/system/STM32F7xx/system_stm32f7xx.c +++ b/system/STM32F7xx/system_stm32f7xx.c @@ -22,29 +22,13 @@ ****************************************************************************** * @attention * - *

            © COPYRIGHT 2016 STMicroelectronics

            + *

            © Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

            * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ diff --git a/system/STM32G0xx/system_stm32g0xx.c b/system/STM32G0xx/system_stm32g0xx.c index 9e3b84a41f..2421b0c161 100644 --- a/system/STM32G0xx/system_stm32g0xx.c +++ b/system/STM32G0xx/system_stm32g0xx.c @@ -243,8 +243,10 @@ void SystemCoreClockUpdate(void) } pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL); + SystemCoreClock = pllvco/pllr; break; + case RCC_CFGR_SWS_HSI: /* HSI used as system clock */ default: /* HSI used as system clock */ hsidiv = (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV))>> RCC_CR_HSIDIV_Pos));