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Incorrect clock settings for NUCLEO-H563ZI #2505

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dojyorin opened this issue Aug 29, 2024 · 2 comments · Fixed by #2506
Closed

Incorrect clock settings for NUCLEO-H563ZI #2505

dojyorin opened this issue Aug 29, 2024 · 2 comments · Fixed by #2506
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@dojyorin
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When I used CubeMX to verify clock settings of NUCLEO-H563ZI, an error occurred.
I also looked at reference datasheet for H563ZI chip and found some parts that were not optimized.

The maximum clock for ADC/DAC components is 125MHz, but HCLK is 250MHz, so input clock is too high.
As an idea, by setting PLL2 to N = 125 R = 4 it is possible to supply 125MHz from PLL2R to ADC/DAC.

The LPUART will accept up to 250MHz, but PLL2Q is set to 32MHz, which may result in reduced performance.
I think using a PCLK3 (250MHz) would be fine.

The H563ZI Generic board seems to have same problem.

PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_HSI;

@fpistm
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fpistm commented Aug 29, 2024

Hi @dojyorin
I didn't check the ADC/DAC but for LPUART, it is correct this allows to get low baudrate (9600) else it will not be available.
Feel free to provide a PR to fix ADC/DAC

@fpistm
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fpistm commented Sep 2, 2024

After checking the only issue is for the ADC/DAC.

@fpistm fpistm added this to the 2.9.0 milestone Sep 3, 2024
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