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variant(h5): add STM32H562R(G-I)T support
Signed-off-by: Frederic Pillon <[email protected]>
1 parent f432c02 commit fb119ab

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4 files changed

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4 files changed

+289
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README.md

+1
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@@ -546,6 +546,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d
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| :yellow_heart: | STM32H503CB | Generic Board | **2.9.0** | |
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| :green_heart: | STM32H503KB | Generic Board | *2.8.1* | |
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| :green_heart: | STM32H503RB | Generic Board | *2.7.0* | |
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| :yellow_heart: | STM32H562RGT<br>STM32H562RIT | Generic Board | **2.9.0** | |
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| :green_heart: | STM32H563IIKxQ | Generic Board | *2.6.0* | |
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| :green_heart: | STM32H563RG<br>STM32H563RI | Generic Board | *2.8.1* | |
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| :green_heart: | STM32H563ZG<br>STM32H563ZI | Generic Board | *2.6.0* | |

boards.txt

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@@ -8478,6 +8478,24 @@ GenH5.menu.pnum.GENERIC_H503RBTX.build.product_line=STM32H503xx
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GenH5.menu.pnum.GENERIC_H503RBTX.build.variant=STM32H5xx/H503RBT
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GenH5.menu.pnum.GENERIC_H503RBTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H5xx/STM32H503.svd
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# Generic H562RGTx
8482+
GenH5.menu.pnum.GENERIC_H562RGTX=Generic H562RGTx
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GenH5.menu.pnum.GENERIC_H562RGTX.upload.maximum_size=1048576
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GenH5.menu.pnum.GENERIC_H562RGTX.upload.maximum_data_size=655360
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GenH5.menu.pnum.GENERIC_H562RGTX.build.board=GENERIC_H562RGTX
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GenH5.menu.pnum.GENERIC_H562RGTX.build.product_line=STM32H562xx
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GenH5.menu.pnum.GENERIC_H562RGTX.build.variant=STM32H5xx/H562R(G-I)T
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GenH5.menu.pnum.GENERIC_H562RGTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H5xx/STM32H562.svd
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# Generic H562RITx
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GenH5.menu.pnum.GENERIC_H562RITX=Generic H562RITx
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GenH5.menu.pnum.GENERIC_H562RITX.upload.maximum_size=2097152
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GenH5.menu.pnum.GENERIC_H562RITX.upload.maximum_data_size=655360
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GenH5.menu.pnum.GENERIC_H562RITX.build.board=GENERIC_H562RITX
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GenH5.menu.pnum.GENERIC_H562RITX.build.product_line=STM32H562xx
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GenH5.menu.pnum.GENERIC_H562RITX.build.variant=STM32H5xx/H562R(G-I)T
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GenH5.menu.pnum.GENERIC_H562RITX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H5xx/STM32H562.svd
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# Generic H563IIKxQ
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GenH5.menu.pnum.GENERIC_H563IIKXQ=Generic H563IIKxQ
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GenH5.menu.pnum.GENERIC_H563IIKXQ.upload.maximum_size=2097152

variants/STM32H5xx/H562R(G-I)T/generic_clock.c

+83-2
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@@ -20,8 +20,89 @@
2020
*/
2121
WEAK void SystemClock_Config(void)
2222
{
23-
/* SystemClock_Config can be generated by STM32CubeMX */
24-
#warning "SystemClock_Config() is empty. Default clock at reset is used."
23+
RCC_OscInitTypeDef RCC_OscInitStruct = {};
24+
RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
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RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {};
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27+
/** Configure the main internal regulator output voltage
28+
*/
29+
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0);
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31+
while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
32+
33+
/** Initializes the RCC Oscillators according to the specified parameters
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* in the RCC_OscInitTypeDef structure.
35+
*/
36+
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_CSI;
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RCC_OscInitStruct.LSIState = RCC_LSI_ON;
38+
RCC_OscInitStruct.CSIState = RCC_CSI_ON;
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RCC_OscInitStruct.CSICalibrationValue = RCC_CSICALIBRATION_DEFAULT;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLL1_SOURCE_CSI;
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RCC_OscInitStruct.PLL.PLLM = 1;
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RCC_OscInitStruct.PLL.PLLN = 120;
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RCC_OscInitStruct.PLL.PLLP = 2;
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RCC_OscInitStruct.PLL.PLLQ = 10;
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RCC_OscInitStruct.PLL.PLLR = 2;
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RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_2;
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RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1_VCORANGE_WIDE;
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RCC_OscInitStruct.PLL.PLLFRACN = 0;
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if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
51+
Error_Handler();
52+
}
53+
54+
/** Initializes the CPU, AHB and APB buses clocks
55+
*/
56+
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
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| RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2
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| RCC_CLOCKTYPE_PCLK3;
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
60+
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
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RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
63+
RCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV1;
64+
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if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) {
66+
Error_Handler();
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}
68+
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/** Initializes the peripherals clock
70+
*/
71+
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_DAC
72+
| RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_SDMMC1
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| RCC_PERIPHCLK_USB;
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PeriphClkInitStruct.PLL2.PLL2Source = RCC_PLL2_SOURCE_CSI;
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PeriphClkInitStruct.PLL2.PLL2M = 1;
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PeriphClkInitStruct.PLL2.PLL2N = 125;
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PeriphClkInitStruct.PLL2.PLL2P = 2;
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PeriphClkInitStruct.PLL2.PLL2Q = 2;
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PeriphClkInitStruct.PLL2.PLL2R = 5;
80+
PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2_VCIRANGE_2;
81+
PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2_VCORANGE_WIDE;
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PeriphClkInitStruct.PLL2.PLL2FRACN = 0.0;
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PeriphClkInitStruct.PLL2.PLL2ClockOut = RCC_PLL2_DIVR;
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PeriphClkInitStruct.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_PLL2R;
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PeriphClkInitStruct.PLL3.PLL3Source = RCC_PLL3_SOURCE_CSI;
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PeriphClkInitStruct.PLL3.PLL3M = 1;
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PeriphClkInitStruct.PLL3.PLL3N = 40;
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PeriphClkInitStruct.PLL3.PLL3P = 2;
89+
PeriphClkInitStruct.PLL3.PLL3Q = 5;
90+
PeriphClkInitStruct.PLL3.PLL3R = 2;
91+
PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3_VCIRANGE_0;
92+
PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3_VCORANGE_MEDIUM;
93+
PeriphClkInitStruct.PLL3.PLL3FRACN = 0.0;
94+
PeriphClkInitStruct.PLL3.PLL3ClockOut = RCC_PLL3_DIVQ;
95+
PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PLL3Q;
96+
PeriphClkInitStruct.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_PLL2R;
97+
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL1Q;
98+
99+
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
100+
Error_Handler();
101+
}
102+
103+
/** Configure the programming delay
104+
*/
105+
__HAL_FLASH_SET_PROGRAM_DELAY(FLASH_PROGRAMMING_DELAY_2);
25106
}
26107

27108
#endif /* ARDUINO_GENERIC_* */
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@@ -0,0 +1,187 @@
1+
/*
2+
******************************************************************************
3+
**
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** @file : LinkerScript.ld
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**
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** @author : Auto-generated by STM32CubeIDE
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**
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** @brief : Linker script for STM32H562RGTx Device from STM32H5 series
9+
** 1024KBytes FLASH
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** 640KBytes RAM
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**
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** Set heap size, stack size and stack location according
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** to application requirements.
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**
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** Set memory bank area and size if external memory is used
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**
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** Target : STMicroelectronics STM32
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**
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** Distribution: The file is distributed as is, without any warranty
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** of any kind.
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**
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******************************************************************************
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** @attention
24+
**
25+
** Copyright (c) 2024 STMicroelectronics.
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** All rights reserved.
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**
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** This software is licensed under terms that can be found in the LICENSE file
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** in the root directory of this software component.
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** If no LICENSE file comes with this software, it is provided AS-IS.
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**
32+
******************************************************************************
33+
*/
34+
35+
/* Entry Point */
36+
ENTRY(Reset_Handler)
37+
38+
/* Highest address of the user mode stack */
39+
_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
40+
41+
_Min_Heap_Size = 0x200; /* required amount of heap */
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_Min_Stack_Size = 0x400; /* required amount of stack */
43+
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/* Memories definition */
45+
MEMORY
46+
{
47+
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = LD_MAX_DATA_SIZE
48+
FLASH (rx) : ORIGIN = 0x08000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
49+
}
50+
51+
/* Sections */
52+
SECTIONS
53+
{
54+
/* The startup code into "FLASH" Rom type memory */
55+
.isr_vector :
56+
{
57+
. = ALIGN(4);
58+
KEEP(*(.isr_vector)) /* Startup code */
59+
. = ALIGN(4);
60+
} >FLASH
61+
62+
/* The program code and other data into "FLASH" Rom type memory */
63+
.text :
64+
{
65+
. = ALIGN(4);
66+
*(.text) /* .text sections (code) */
67+
*(.text*) /* .text* sections (code) */
68+
*(.glue_7) /* glue arm to thumb code */
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*(.glue_7t) /* glue thumb to arm code */
70+
*(.eh_frame)
71+
72+
KEEP (*(.init))
73+
KEEP (*(.fini))
74+
75+
. = ALIGN(4);
76+
_etext = .; /* define a global symbols at end of code */
77+
} >FLASH
78+
79+
/* Constant data into "FLASH" Rom type memory */
80+
.rodata :
81+
{
82+
. = ALIGN(4);
83+
*(.rodata) /* .rodata sections (constants, strings, etc.) */
84+
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
85+
. = ALIGN(4);
86+
} >FLASH
87+
88+
.ARM.extab (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
89+
{
90+
. = ALIGN(4);
91+
*(.ARM.extab* .gnu.linkonce.armextab.*)
92+
. = ALIGN(4);
93+
} >FLASH
94+
95+
.ARM (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
96+
{
97+
. = ALIGN(4);
98+
__exidx_start = .;
99+
*(.ARM.exidx*)
100+
__exidx_end = .;
101+
. = ALIGN(4);
102+
} >FLASH
103+
104+
.preinit_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
105+
{
106+
. = ALIGN(4);
107+
PROVIDE_HIDDEN (__preinit_array_start = .);
108+
KEEP (*(.preinit_array*))
109+
PROVIDE_HIDDEN (__preinit_array_end = .);
110+
. = ALIGN(4);
111+
} >FLASH
112+
113+
.init_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
114+
{
115+
. = ALIGN(4);
116+
PROVIDE_HIDDEN (__init_array_start = .);
117+
KEEP (*(SORT(.init_array.*)))
118+
KEEP (*(.init_array*))
119+
PROVIDE_HIDDEN (__init_array_end = .);
120+
. = ALIGN(4);
121+
} >FLASH
122+
123+
.fini_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
124+
{
125+
. = ALIGN(4);
126+
PROVIDE_HIDDEN (__fini_array_start = .);
127+
KEEP (*(SORT(.fini_array.*)))
128+
KEEP (*(.fini_array*))
129+
PROVIDE_HIDDEN (__fini_array_end = .);
130+
. = ALIGN(4);
131+
} >FLASH
132+
133+
/* Used by the startup to initialize data */
134+
_sidata = LOADADDR(.data);
135+
136+
/* Initialized data sections into "RAM" Ram type memory */
137+
.data :
138+
{
139+
. = ALIGN(4);
140+
_sdata = .; /* create a global symbol at data start */
141+
*(.data) /* .data sections */
142+
*(.data*) /* .data* sections */
143+
*(.RamFunc) /* .RamFunc sections */
144+
*(.RamFunc*) /* .RamFunc* sections */
145+
146+
. = ALIGN(4);
147+
_edata = .; /* define a global symbol at data end */
148+
149+
} >RAM AT> FLASH
150+
151+
/* Uninitialized data section into "RAM" Ram type memory */
152+
. = ALIGN(4);
153+
.bss :
154+
{
155+
/* This is used by the startup in order to initialize the .bss section */
156+
_sbss = .; /* define a global symbol at bss start */
157+
__bss_start__ = _sbss;
158+
*(.bss)
159+
*(.bss*)
160+
*(COMMON)
161+
162+
. = ALIGN(4);
163+
_ebss = .; /* define a global symbol at bss end */
164+
__bss_end__ = _ebss;
165+
} >RAM
166+
167+
/* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
168+
._user_heap_stack :
169+
{
170+
. = ALIGN(8);
171+
PROVIDE ( end = . );
172+
PROVIDE ( _end = . );
173+
. = . + _Min_Heap_Size;
174+
. = . + _Min_Stack_Size;
175+
. = ALIGN(8);
176+
} >RAM
177+
178+
/* Remove information from the compiler libraries */
179+
/DISCARD/ :
180+
{
181+
libc.a ( * )
182+
libm.a ( * )
183+
libgcc.a ( * )
184+
}
185+
186+
.ARM.attributes 0 : { *(.ARM.attributes) }
187+
}

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