Skip to content

Commit f07b55b

Browse files
fpistmfpistm
committed
[H7] Update STM32H7xx HAL Drivers to v1.8.0
Included in STM32CubeH7 FW v1.7.0 Signed-off-by: Frederic Pillon <[email protected]>
1 parent 69b6ab9 commit f07b55b

Some content is hidden

Large Commits have some content hidden by default. Use the searchbox below for content that may be hidden.

46 files changed

+2035
-1297
lines changed

Diff for: ‎system/Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h

+17-18
Original file line numberDiff line numberDiff line change
@@ -241,7 +241,7 @@
241241
#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL
242242
#endif
243243

244-
#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4)
244+
#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4)
245245
#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID
246246
#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID
247247
#endif
@@ -313,8 +313,8 @@
313313
#endif /* STM32L4 */
314314

315315
#if defined(STM32G0)
316-
#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1
317-
#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2
316+
#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1
317+
#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2
318318
#endif
319319

320320
#if defined(STM32H7)
@@ -955,7 +955,7 @@
955955
#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
956956
#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
957957

958-
#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7)
958+
#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4)
959959
#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID
960960
#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID
961961
#endif
@@ -1450,7 +1450,7 @@
14501450
#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
14511451
#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
14521452

1453-
#if defined(STM32L4) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
1453+
#if defined(STM32L4) || defined(STM32L5) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
14541454

14551455
#define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt
14561456
#define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End
@@ -1472,7 +1472,7 @@
14721472
#define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT
14731473
#define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT
14741474

1475-
#endif /* STM32L4 || STM32F4 || STM32F7 || STM32H7 */
1475+
#endif /* STM32L4 || STM32L5 || STM32F4 || STM32F7 || STM32H7 */
14761476
/**
14771477
* @}
14781478
*/
@@ -1563,10 +1563,10 @@
15631563
*/
15641564

15651565
#if defined(STM32G0)
1566-
#define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD
1567-
#define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD
1568-
#define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD
1569-
#define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler
1566+
#define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD
1567+
#define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD
1568+
#define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD
1569+
#define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler
15701570
#endif
15711571
#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD
15721572
#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg
@@ -3243,9 +3243,8 @@
32433243
#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
32443244
#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
32453245

3246-
#if defined(STM32L4)
3246+
#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL)
32473247
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
3248-
#elif defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL)
32493248
#else
32503249
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
32513250
#endif
@@ -3373,7 +3372,7 @@
33733372
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
33743373
* @{
33753374
*/
3376-
#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5)
3375+
#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4)
33773376
#else
33783377
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
33793378
#endif
@@ -3481,9 +3480,9 @@
34813480
#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG
34823481
#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT
34833482
#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT
3484-
#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS
3485-
#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT
3486-
#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND
3483+
#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS
3484+
#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT
3485+
#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND
34873486
/* alias CMSIS for compatibilities */
34883487
#define SDIO_IRQn SDMMC1_IRQn
34893488
#define SDIO_IRQHandler SDMMC1_IRQHandler
@@ -3751,9 +3750,9 @@
37513750
/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose
37523751
* @{
37533752
*/
3754-
#if defined (STM32L4)
3753+
#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7)
37553754
#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE
3756-
#endif
3755+
#endif /* STM32L4 || STM32F4 || STM32F7 */
37573756
/**
37583757
* @}
37593758
*/

Diff for: ‎system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h

+2-2
Original file line numberDiff line numberDiff line change
@@ -296,8 +296,8 @@ void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
296296
* @{
297297
*/
298298
#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
299-
#define IS_GPIO_PIN(__PIN__) ((((__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\
300-
(((__PIN__) & ~GPIO_PIN_MASK) == 0x00U))
299+
#define IS_GPIO_PIN(__PIN__) ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\
300+
(((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00U))
301301
#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\
302302
((MODE) == GPIO_MODE_OUTPUT_PP) ||\
303303
((MODE) == GPIO_MODE_OUTPUT_OD) ||\

Diff for: ‎system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h

+1-2
Original file line numberDiff line numberDiff line change
@@ -303,7 +303,6 @@ extern "C" {
303303
#define GPIO_AF13_PSSI ((uint8_t)0x0D) /* PSSI Alternate Function mapping */
304304
#endif /* PSSI */
305305
#define GPIO_AF13_TIM1 ((uint8_t)0x0D) /* TIM1 Alternate Function mapping */
306-
#define GPIO_AF13_TIM8 ((uint8_t)0x0D) /* TIM8 Alternate Function mapping : available on STM32H74xxx/STM32H75xxx */
307306

308307
/**
309308
* @brief AF 14 selection
@@ -364,7 +363,7 @@ extern "C" {
364363
#define GPIOI_PIN_AVAILABLE GPIO_PIN_All
365364
#define GPIOJ_PIN_AVAILABLE GPIO_PIN_All
366365
#define GPIOH_PIN_AVAILABLE GPIO_PIN_All
367-
#define GPIOK_PIN_AVAILABLE (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_3 | GPIO_PIN_4 | \
366+
#define GPIOK_PIN_AVAILABLE (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | \
368367
GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7)
369368

370369
/**

Diff for: ‎system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hrtim.h

+1-16
Original file line numberDiff line numberDiff line change
@@ -654,11 +654,6 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!<
654654
* @{
655655
* @brief Constants defining timer high-resolution clock prescaler ratio.
656656
*/
657-
#define HRTIM_PRESCALERRATIO_MUL32 (0x00000000U) /*!< fHRCK: fHRTIM x 32U = 4.608 GHz - Resolution: 217 ps - Min PWM frequency: 70.3 kHz (fHRTIM=144MHz) */
658-
#define HRTIM_PRESCALERRATIO_MUL16 (0x00000001U) /*!< fHRCK: fHRTIM x 16U = 2.304 GHz - Resolution: 434 ps - Min PWM frequency: 35.1 KHz (fHRTIM=144MHz) */
659-
#define HRTIM_PRESCALERRATIO_MUL8 (0x00000002U) /*!< fHRCK: fHRTIM x 8U = 1.152 GHz - Resolution: 868 ps - Min PWM frequency: 17.6 kHz (fHRTIM=144MHz) */
660-
#define HRTIM_PRESCALERRATIO_MUL4 (0x00000003U) /*!< fHRCK: fHRTIM x 4U = 576 MHz - Resolution: 1.73 ns - Min PWM frequency: 8.8 kHz (fHRTIM=144MHz) */
661-
#define HRTIM_PRESCALERRATIO_MUL2 (0x00000004U) /*!< fHRCK: fHRTIM x 2U = 288 MHz - Resolution: 3.47 ns - Min PWM frequency: 4.4 kHz (fHRTIM=144MHz) */
662657
#define HRTIM_PRESCALERRATIO_DIV1 (0x00000005U) /*!< fHRCK: fHRTIM = 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz) */
663658
#define HRTIM_PRESCALERRATIO_DIV2 (0x00000006U) /*!< fHRCK: fHRTIM / 2U = 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz) */
664659
#define HRTIM_PRESCALERRATIO_DIV4 (0x00000007U) /*!< fHRCK: fHRTIM / 4U = 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz) */
@@ -2083,12 +2078,7 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!<
20832078
((FAULT) == HRTIM_FAULT_5))
20842079

20852080
#define IS_HRTIM_PRESCALERRATIO(PRESCALERRATIO)\
2086-
(((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL32) || \
2087-
((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL16) || \
2088-
((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL8) || \
2089-
((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL4) || \
2090-
((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL2) || \
2091-
((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV1) || \
2081+
(((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV1) || \
20922082
((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV2) || \
20932083
((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV4))
20942084

@@ -3117,11 +3107,6 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!<
31173107
* @arg 0x0 to 0x4 for timers A to E
31183108
* @param __PRESCALER__ specifies the clock prescaler new value.
31193109
* This parameter can be one of the following values:
3120-
* @arg HRTIM_PRESCALERRATIO_MUL32: fHRCK: 4.608 GHz - Resolution: 217 ps - Min PWM frequency: 70.3 kHz (fHRTIM=144MHz)
3121-
* @arg HRTIM_PRESCALERRATIO_MUL16: fHRCK: 2.304 GHz - Resolution: 434 ps - Min PWM frequency: 35.1 KHz (fHRTIM=144MHz)
3122-
* @arg HRTIM_PRESCALERRATIO_MUL8: fHRCK: 1.152 GHz - Resolution: 868 ps - Min PWM frequency: 17.6 kHz (fHRTIM=144MHz)
3123-
* @arg HRTIM_PRESCALERRATIO_MUL4: fHRCK: 576 MHz - Resolution: 1.73 ns - Min PWM frequency: 8.8 kHz (fHRTIM=144MHz)
3124-
* @arg HRTIM_PRESCALERRATIO_MUL2: fHRCK: 288 MHz - Resolution: 3.47 ns - Min PWM frequency: 4.4 kHz (fHRTIM=144MHz)
31253110
* @arg HRTIM_PRESCALERRATIO_DIV1: fHRCK: 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz)
31263111
* @arg HRTIM_PRESCALERRATIO_DIV2: fHRCK: 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz)
31273112
* @arg HRTIM_PRESCALERRATIO_DIV4: fHRCK: 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz)

Diff for: ‎system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_nand.h

+25-25
Original file line numberDiff line numberDiff line change
@@ -271,33 +271,33 @@ uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
271271
/** @defgroup NAND_Private_Constants NAND Private Constants
272272
* @{
273273
*/
274-
#define NAND_DEVICE ((uint32_t)0x80000000U)
275-
#define NAND_WRITE_TIMEOUT ((uint32_t)0x01000000U)
276-
277-
#define CMD_AREA ((uint32_t)(1UL<<16U)) /* A16 = CLE high */
278-
#define ADDR_AREA ((uint32_t)(1UL<<17U)) /* A17 = ALE high */
279-
280-
#define NAND_CMD_AREA_A ((uint8_t)0x00U)
281-
#define NAND_CMD_AREA_B ((uint8_t)0x01U)
282-
#define NAND_CMD_AREA_C ((uint8_t)0x50U)
283-
#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30U)
284-
285-
#define NAND_CMD_WRITE0 ((uint8_t)0x80U)
286-
#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10U)
287-
#define NAND_CMD_ERASE0 ((uint8_t)0x60U)
288-
#define NAND_CMD_ERASE1 ((uint8_t)0xD0U)
289-
#define NAND_CMD_READID ((uint8_t)0x90U)
290-
#define NAND_CMD_STATUS ((uint8_t)0x70U)
291-
#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7AU)
292-
#define NAND_CMD_RESET ((uint8_t)0xFFU)
274+
#define NAND_DEVICE 0x80000000UL
275+
#define NAND_WRITE_TIMEOUT 0x01000000UL
276+
277+
#define CMD_AREA (1UL<<16U) /* A16 = CLE high */
278+
#define ADDR_AREA (1UL<<17U) /* A17 = ALE high */
279+
280+
#define NAND_CMD_AREA_A 0x00U
281+
#define NAND_CMD_AREA_B 0x01U
282+
#define NAND_CMD_AREA_C 0x50U
283+
#define NAND_CMD_AREA_TRUE1 0x30U
284+
285+
#define NAND_CMD_WRITE0 0x80U
286+
#define NAND_CMD_WRITE_TRUE1 0x10U
287+
#define NAND_CMD_ERASE0 0x60U
288+
#define NAND_CMD_ERASE1 0xD0U
289+
#define NAND_CMD_READID 0x90U
290+
#define NAND_CMD_STATUS 0x70U
291+
#define NAND_CMD_LOCK_STATUS 0x7AU
292+
#define NAND_CMD_RESET 0xFFU
293293

294294
/* NAND memory status */
295-
#define NAND_VALID_ADDRESS ((uint32_t)0x00000100U)
296-
#define NAND_INVALID_ADDRESS ((uint32_t)0x00000200U)
297-
#define NAND_TIMEOUT_ERROR ((uint32_t)0x00000400U)
298-
#define NAND_BUSY ((uint32_t)0x00000000U)
299-
#define NAND_ERROR ((uint32_t)0x00000001U)
300-
#define NAND_READY ((uint32_t)0x00000040U)
295+
#define NAND_VALID_ADDRESS 0x00000100UL
296+
#define NAND_INVALID_ADDRESS 0x00000200UL
297+
#define NAND_TIMEOUT_ERROR 0x00000400UL
298+
#define NAND_BUSY 0x00000000UL
299+
#define NAND_ERROR 0x00000001UL
300+
#define NAND_READY 0x00000040UL
301301
/**
302302
* @}
303303
*/

Diff for: ‎system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_nor.h

+15-15
Original file line numberDiff line numberDiff line change
@@ -245,29 +245,29 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres
245245
* @{
246246
*/
247247
/* NOR device IDs addresses */
248-
#define MC_ADDRESS ((uint16_t)0x0000U)
249-
#define DEVICE_CODE1_ADDR ((uint16_t)0x0001U)
250-
#define DEVICE_CODE2_ADDR ((uint16_t)0x000EU)
251-
#define DEVICE_CODE3_ADDR ((uint16_t)0x000FU)
248+
#define MC_ADDRESS ((uint16_t)0x0000)
249+
#define DEVICE_CODE1_ADDR ((uint16_t)0x0001)
250+
#define DEVICE_CODE2_ADDR ((uint16_t)0x000E)
251+
#define DEVICE_CODE3_ADDR ((uint16_t)0x000F)
252252

253253
/* NOR CFI IDs addresses */
254-
#define CFI1_ADDRESS ((uint16_t)0x61U)
255-
#define CFI2_ADDRESS ((uint16_t)0x62U)
256-
#define CFI3_ADDRESS ((uint16_t)0x63U)
257-
#define CFI4_ADDRESS ((uint16_t)0x64U)
254+
#define CFI1_ADDRESS ((uint16_t)0x61)
255+
#define CFI2_ADDRESS ((uint16_t)0x62)
256+
#define CFI3_ADDRESS ((uint16_t)0x63)
257+
#define CFI4_ADDRESS ((uint16_t)0x64)
258258

259259
/* NOR operation wait timeout */
260-
#define NOR_TMEOUT ((uint16_t)0xFFFFU)
260+
#define NOR_TMEOUT ((uint16_t)0xFFFF)
261261

262262
/* NOR memory data width */
263-
#define NOR_MEMORY_8B ((uint8_t)0x0U)
264-
#define NOR_MEMORY_16B ((uint8_t)0x1U)
263+
#define NOR_MEMORY_8B ((uint8_t)0x0)
264+
#define NOR_MEMORY_16B ((uint8_t)0x1)
265265

266266
/* NOR memory device read/write start address */
267-
#define NOR_MEMORY_ADRESS1 ((uint32_t)0x60000000U)
268-
#define NOR_MEMORY_ADRESS2 ((uint32_t)0x64000000U)
269-
#define NOR_MEMORY_ADRESS3 ((uint32_t)0x68000000U)
270-
#define NOR_MEMORY_ADRESS4 ((uint32_t)0x6C000000U)
267+
#define NOR_MEMORY_ADRESS1 ((uint32_t)0x60000000)
268+
#define NOR_MEMORY_ADRESS2 ((uint32_t)0x64000000)
269+
#define NOR_MEMORY_ADRESS3 ((uint32_t)0x68000000)
270+
#define NOR_MEMORY_ADRESS4 ((uint32_t)0x6C000000)
271271
/**
272272
* @}
273273
*/

Diff for: ‎system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_ospi.h

+18-13
Original file line numberDiff line numberDiff line change
@@ -259,6 +259,9 @@ typedef struct
259259
This parameter can be a value of @ref OSPIM_IOPort */
260260
uint32_t IOHighPort; /* It indicates which port of the OSPI IO Manager is used for the IO[7:4] pins.
261261
This parameter can be a value of @ref OSPIM_IOPort */
262+
uint32_t Req2AckTime; /* It indicates the minimum switching duration (in number of clock cycles) expected
263+
if some signals are multiplexed in the OSPI IO Manager with the other OSPI.
264+
This parameter can be a value between 1 and 256 */
262265
}OSPIM_CfgTypeDef;
263266

264267
#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
@@ -683,7 +686,7 @@ typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi);
683686
* @{
684687
*/
685688
/** @brief Reset OSPI handle state.
686-
* @param __HANDLE__: OSPI handle.
689+
* @param __HANDLE__ specifies the OSPI Handle.
687690
* @retval None
688691
*/
689692
#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
@@ -697,20 +700,20 @@ typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi);
697700
#endif
698701

699702
/** @brief Enable the OSPI peripheral.
700-
* @param __HANDLE__: specifies the OSPI Handle.
703+
* @param __HANDLE__ specifies the OSPI Handle.
701704
* @retval None
702705
*/
703706
#define __HAL_OSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, OCTOSPI_CR_EN)
704707

705708
/** @brief Disable the OSPI peripheral.
706-
* @param __HANDLE__: specifies the OSPI Handle.
709+
* @param __HANDLE__ specifies the OSPI Handle.
707710
* @retval None
708711
*/
709712
#define __HAL_OSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, OCTOSPI_CR_EN)
710713

711714
/** @brief Enable the specified OSPI interrupt.
712-
* @param __HANDLE__: specifies the OSPI Handle.
713-
* @param __INTERRUPT__: specifies the OSPI interrupt source to enable.
715+
* @param __HANDLE__ specifies the OSPI Handle.
716+
* @param __INTERRUPT__ specifies the OSPI interrupt source to enable.
714717
* This parameter can be one of the following values:
715718
* @arg HAL_OSPI_IT_TO: OSPI Timeout interrupt
716719
* @arg HAL_OSPI_IT_SM: OSPI Status match interrupt
@@ -723,8 +726,8 @@ typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi);
723726

724727

725728
/** @brief Disable the specified OSPI interrupt.
726-
* @param __HANDLE__: specifies the OSPI Handle.
727-
* @param __INTERRUPT__: specifies the OSPI interrupt source to disable.
729+
* @param __HANDLE__ specifies the OSPI Handle.
730+
* @param __INTERRUPT__ specifies the OSPI interrupt source to disable.
728731
* This parameter can be one of the following values:
729732
* @arg HAL_OSPI_IT_TO: OSPI Timeout interrupt
730733
* @arg HAL_OSPI_IT_SM: OSPI Status match interrupt
@@ -736,8 +739,8 @@ typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi);
736739
#define __HAL_OSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
737740

738741
/** @brief Check whether the specified OSPI interrupt source is enabled or not.
739-
* @param __HANDLE__: specifies the OSPI Handle.
740-
* @param __INTERRUPT__: specifies the OSPI interrupt source to check.
742+
* @param __HANDLE__ specifies the OSPI Handle.
743+
* @param __INTERRUPT__ specifies the OSPI interrupt source to check.
741744
* This parameter can be one of the following values:
742745
* @arg HAL_OSPI_IT_TO: OSPI Timeout interrupt
743746
* @arg HAL_OSPI_IT_SM: OSPI Status match interrupt
@@ -750,8 +753,8 @@ typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi);
750753

751754
/**
752755
* @brief Check whether the selected OSPI flag is set or not.
753-
* @param __HANDLE__: specifies the OSPI Handle.
754-
* @param __FLAG__: specifies the OSPI flag to check.
756+
* @param __HANDLE__ specifies the OSPI Handle.
757+
* @param __FLAG__ specifies the OSPI flag to check.
755758
* This parameter can be one of the following values:
756759
* @arg HAL_OSPI_FLAG_BUSY: OSPI Busy flag
757760
* @arg HAL_OSPI_FLAG_TO: OSPI Timeout flag
@@ -764,8 +767,8 @@ typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi);
764767
#define __HAL_OSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? SET : RESET)
765768

766769
/** @brief Clears the specified OSPI's flag status.
767-
* @param __HANDLE__: specifies the OSPI Handle.
768-
* @param __FLAG__: specifies the OSPI clear register flag that needs to be set
770+
* @param __HANDLE__ specifies the OSPI Handle.
771+
* @param __FLAG__ specifies the OSPI clear register flag that needs to be set
769772
* This parameter can be one of the following values:
770773
* @arg HAL_OSPI_FLAG_TO: OSPI Timeout flag
771774
* @arg HAL_OSPI_FLAG_SM: OSPI Status match flag
@@ -1046,6 +1049,8 @@ HAL_StatusTypeDef HAL_OSPIM_Config (OSPI_HandleTypeDef *hospi,
10461049
((PORT) == HAL_OSPIM_IOPORT_7_HIGH) || \
10471050
((PORT) == HAL_OSPIM_IOPORT_8_LOW) || \
10481051
((PORT) == HAL_OSPIM_IOPORT_8_HIGH))
1052+
1053+
#define IS_OSPIM_REQ2ACKTIME(TIME) (((TIME) >= 1U) && ((TIME) <= 256U))
10491054
/**
10501055
@endcond
10511056
*/

0 commit comments

Comments
 (0)