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2 | 2 | ****************************************************************************** |
3 | 3 | * @file stm32f4xx_hal_conf_template.h |
4 | 4 | * @author MCD Application Team |
5 | | - * @version V1.5.1 |
6 | | - * @date 01-July-2016 |
| 5 | + * @version V1.7.1 |
| 6 | + * @date 14-April-2017 |
7 | 7 | * @brief HAL configuration template file. |
8 | 8 | * This file should be copied to the application folder and renamed |
9 | 9 | * to stm32f4xx_hal_conf.h. |
10 | 10 | ****************************************************************************** |
11 | 11 | * @attention |
12 | 12 | * |
13 | | - * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
| 13 | + * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
14 | 14 | * |
15 | 15 | * Redistribution and use in source and binary forms, with or without modification, |
16 | 16 | * are permitted provided that the following conditions are met: |
|
97 | 97 | // #define HAL_SPDIFRX_MODULE_ENABLED |
98 | 98 | // #define HAL_DFSDM_MODULE_ENABLED |
99 | 99 | // #define HAL_LPTIM_MODULE_ENABLED |
| 100 | +//#define HAL_MMC_MODULE_ENABLED |
100 | 101 |
|
101 | 102 | /* ########################## HSE/HSI Values adaptation ##################### */ |
102 | 103 | /** |
|
105 | 106 | * (when HSE is used as system clock source, directly or through the PLL). |
106 | 107 | */ |
107 | 108 | #if !defined (HSE_VALUE) |
108 | | - #define HSE_VALUE ((uint32_t)25000000U) /*!< Value of the External oscillator in Hz */ |
| 109 | + #define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */ |
109 | 110 | #endif /* HSE_VALUE */ |
110 | 111 |
|
111 | 112 | #if !defined (HSE_STARTUP_TIMEOUT) |
112 | | - #define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */ |
| 113 | + #define HSE_STARTUP_TIMEOUT 100U /*!< Time out for HSE start up, in ms */ |
113 | 114 | #endif /* HSE_STARTUP_TIMEOUT */ |
114 | 115 |
|
115 | 116 | /** |
|
118 | 119 | * (when HSI is used as system clock source, directly or through the PLL). |
119 | 120 | */ |
120 | 121 | #if !defined (HSI_VALUE) |
121 | | - #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ |
| 122 | + #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz */ |
122 | 123 | #endif /* HSI_VALUE */ |
123 | 124 |
|
124 | 125 | /** |
125 | 126 | * @brief Internal Low Speed oscillator (LSI) value. |
126 | 127 | */ |
127 | 128 | #if !defined (LSI_VALUE) |
128 | | - #define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/ |
| 129 | + #define LSI_VALUE 32000U /*!< LSI Typical Value in Hz */ |
129 | 130 | #endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz |
130 | 131 | The real value may vary depending on the variations |
131 | 132 | in voltage and temperature.*/ |
132 | 133 | /** |
133 | 134 | * @brief External Low Speed oscillator (LSE) value. |
134 | 135 | */ |
135 | 136 | #if !defined (LSE_VALUE) |
136 | | - #define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External Low Speed oscillator in Hz */ |
| 137 | + #define LSE_VALUE 32768U /*!< Value of the External Low Speed oscillator in Hz */ |
137 | 138 | #endif /* LSE_VALUE */ |
138 | 139 |
|
139 | 140 | #if !defined (LSE_STARTUP_TIMEOUT) |
140 | | - #define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */ |
| 141 | + #define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */ |
141 | 142 | #endif /* LSE_STARTUP_TIMEOUT */ |
142 | 143 |
|
143 | 144 | /** |
|
146 | 147 | * frequency, this source is inserted directly through I2S_CKIN pad. |
147 | 148 | */ |
148 | 149 | #if !defined (EXTERNAL_CLOCK_VALUE) |
149 | | - #define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000U) /*!< Value of the Internal oscillator in Hz*/ |
| 150 | + #define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the External oscillator in Hz*/ |
150 | 151 | #endif /* EXTERNAL_CLOCK_VALUE */ |
151 | 152 |
|
152 | 153 | /* Tip: To avoid modifying this file each time you need to use different HSE, |
|
156 | 157 | /** |
157 | 158 | * @brief This is the HAL system configuration section |
158 | 159 | */ |
159 | | -#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */ |
160 | | -#define TICK_INT_PRIORITY ((uint32_t)0x0FU) /*!< tick interrupt priority */ |
| 160 | +#define VDD_VALUE 3300U /*!< Value of VDD in mv */ |
| 161 | +#define TICK_INT_PRIORITY 0x0FU /*!< tick interrupt priority */ |
161 | 162 | #define USE_RTOS 0U |
162 | 163 | #define PREFETCH_ENABLE 1U |
163 | 164 | #define INSTRUCTION_CACHE_ENABLE 1U |
|
185 | 186 | /* Definition of the Ethernet driver buffers size and count */ |
186 | 187 | #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ |
187 | 188 | #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ |
188 | | -#define ETH_RXBUFNB ((uint32_t)4U) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ |
189 | | -#define ETH_TXBUFNB ((uint32_t)4U) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ |
| 189 | +#define ETH_RXBUFNB 4U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ |
| 190 | +#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ |
190 | 191 |
|
191 | 192 | /* Section 2: PHY configuration section */ |
192 | 193 |
|
193 | 194 | /* DP83848 PHY Address*/ |
194 | 195 | #define DP83848_PHY_ADDRESS 0x01U |
195 | 196 | /* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ |
196 | | -#define PHY_RESET_DELAY ((uint32_t)0x000000FFU) |
| 197 | +#define PHY_RESET_DELAY 0x000000FFU |
197 | 198 | /* PHY Configuration delay */ |
198 | | -#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFFU) |
| 199 | +#define PHY_CONFIG_DELAY 0x00000FFFU |
199 | 200 |
|
200 | | -#define PHY_READ_TO ((uint32_t)0x0000FFFFU) |
201 | | -#define PHY_WRITE_TO ((uint32_t)0x0000FFFFU) |
| 201 | +#define PHY_READ_TO 0x0000FFFFU |
| 202 | +#define PHY_WRITE_TO 0x0000FFFFU |
202 | 203 |
|
203 | 204 | /* Section 3: Common PHY Registers */ |
204 | 205 |
|
205 | | -#define PHY_BCR ((uint16_t)0x0000U) /*!< Transceiver Basic Control Register */ |
206 | | -#define PHY_BSR ((uint16_t)0x0001U) /*!< Transceiver Basic Status Register */ |
| 206 | +#define PHY_BCR ((uint16_t)0x0000) /*!< Transceiver Basic Control Register */ |
| 207 | +#define PHY_BSR ((uint16_t)0x0001) /*!< Transceiver Basic Status Register */ |
207 | 208 |
|
208 | | -#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */ |
209 | | -#define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */ |
210 | | -#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */ |
211 | | -#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */ |
212 | | -#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */ |
213 | | -#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */ |
214 | | -#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */ |
215 | | -#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U) /*!< Restart auto-negotiation function */ |
216 | | -#define PHY_POWERDOWN ((uint16_t)0x0800U) /*!< Select the power down mode */ |
217 | | -#define PHY_ISOLATE ((uint16_t)0x0400U) /*!< Isolate PHY from MII */ |
| 209 | +#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */ |
| 210 | +#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */ |
| 211 | +#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */ |
| 212 | +#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */ |
| 213 | +#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */ |
| 214 | +#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */ |
| 215 | +#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */ |
| 216 | +#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */ |
| 217 | +#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */ |
| 218 | +#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */ |
218 | 219 |
|
219 | | -#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */ |
220 | | -#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */ |
221 | | -#define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */ |
| 220 | +#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */ |
| 221 | +#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */ |
| 222 | +#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */ |
222 | 223 |
|
223 | 224 | /* Section 4: Extended PHY Registers */ |
224 | 225 |
|
225 | | -#define PHY_SR ((uint16_t)0x0010U) /*!< PHY status register Offset */ |
226 | | -#define PHY_MICR ((uint16_t)0x0011U) /*!< MII Interrupt Control Register */ |
227 | | -#define PHY_MISR ((uint16_t)0x0012U) /*!< MII Interrupt Status and Misc. Control Register */ |
| 226 | +#define PHY_SR ((uint16_t)0x0010) /*!< PHY status register Offset */ |
| 227 | +#define PHY_MICR ((uint16_t)0x0011) /*!< MII Interrupt Control Register */ |
| 228 | +#define PHY_MISR ((uint16_t)0x0012) /*!< MII Interrupt Status and Misc. Control Register */ |
228 | 229 |
|
229 | | -#define PHY_LINK_STATUS ((uint16_t)0x0001U) /*!< PHY Link mask */ |
230 | | -#define PHY_SPEED_STATUS ((uint16_t)0x0002U) /*!< PHY Speed mask */ |
231 | | -#define PHY_DUPLEX_STATUS ((uint16_t)0x0004U) /*!< PHY Duplex mask */ |
| 230 | +#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */ |
| 231 | +#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */ |
| 232 | +#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */ |
232 | 233 |
|
233 | | -#define PHY_MICR_INT_EN ((uint16_t)0x0002U) /*!< PHY Enable interrupts */ |
234 | | -#define PHY_MICR_INT_OE ((uint16_t)0x0001U) /*!< PHY Enable output interrupt events */ |
| 234 | +#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */ |
| 235 | +#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */ |
235 | 236 |
|
236 | | -#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020U) /*!< Enable Interrupt on change of link status */ |
237 | | -#define PHY_LINK_INTERRUPT ((uint16_t)0x2000U) /*!< PHY link status interrupt mask */ |
| 237 | +#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */ |
| 238 | +#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */ |
238 | 239 |
|
239 | 240 | /* ################## SPI peripheral configuration ########################## */ |
240 | 241 |
|
|
426 | 427 | #include "stm32f4xx_hal_lptim.h" |
427 | 428 | #endif /* HAL_LPTIM_MODULE_ENABLED */ |
428 | 429 |
|
| 430 | +#ifdef HAL_MMC_MODULE_ENABLED |
| 431 | + #include "stm32f4xx_hal_mmc.h" |
| 432 | +#endif /* HAL_MMC_MODULE_ENABLED */ |
| 433 | + |
429 | 434 | /* Exported macro ------------------------------------------------------------*/ |
430 | 435 | #ifdef USE_FULL_ASSERT |
431 | 436 | /** |
|
436 | 441 | * If expr is true, it returns no value. |
437 | 442 | * @retval None |
438 | 443 | */ |
439 | | - #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) |
| 444 | + #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) |
440 | 445 | /* Exported functions ------------------------------------------------------- */ |
441 | 446 | void assert_failed(uint8_t* file, uint32_t line); |
442 | 447 | #else |
443 | | - #define assert_param(expr) ((void)0) |
| 448 | + #define assert_param(expr) ((void)0U) |
444 | 449 | #endif /* USE_FULL_ASSERT */ |
445 | 450 |
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446 | 451 |
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