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system(F1): update STM32F1xx CMSIS Drivers to v4.3.4
Included in STM32CubeF1 FW v1.8.5 Signed-off-by: Frederic Pillon <[email protected]>
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53 files changed

+765
-694
lines changed

Diff for: ‎system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f100xb.h

+14-16
Original file line numberDiff line numberDiff line change
@@ -9,18 +9,17 @@
99
* This file contains:
1010
* - Data structures and the address mapping for all peripherals
1111
* - Peripheral's registers declarations and bits definition
12-
* - Macros to access peripheral’s registers hardware
12+
* - Macros to access peripheral's registers hardware
1313
*
1414
******************************************************************************
1515
* @attention
1616
*
17-
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
18-
* All rights reserved.</center></h2>
17+
* Copyright (c) 2017-2021 STMicroelectronics.
18+
* All rights reserved.
1919
*
20-
* This software component is licensed by ST under BSD 3-Clause license,
21-
* the "License"; You may not use this file except in compliance with the
22-
* License. You may obtain a copy of the License at:
23-
* opensource.org/licenses/BSD-3-Clause
20+
* This software is licensed under terms that can be found in the LICENSE file
21+
* in the root directory of this software component.
22+
* If no LICENSE file comes with this software, it is provided AS-IS.
2423
*
2524
******************************************************************************
2625
*/
@@ -1350,7 +1349,7 @@ typedef struct
13501349
#define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
13511350
#define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
13521351

1353-
/*!< RTC congiguration */
1352+
/*!< RTC configuration */
13541353
#define RCC_BDCR_RTCSEL_NOCLOCK 0x00000000U /*!< No clock */
13551354
#define RCC_BDCR_RTCSEL_LSE 0x00000100U /*!< LSE oscillator clock used as RTC clock */
13561355
#define RCC_BDCR_RTCSEL_LSI 0x00000200U /*!< LSI oscillator clock used as RTC clock */
@@ -3380,7 +3379,7 @@ typedef struct
33803379
#define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!< ADC DMA transfer enable */
33813380
#define ADC_CR2_ALIGN_Pos (11U)
33823381
#define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
3383-
#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */
3382+
#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignment */
33843383

33853384
#define ADC_CR2_JEXTSEL_Pos (12U)
33863385
#define ADC_CR2_JEXTSEL_Msk (0x7UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00007000 */
@@ -5927,14 +5926,14 @@ typedef struct
59275926
#define USBWakeUp_IRQn CEC_IRQn
59285927
#define OTG_FS_WKUP_IRQn CEC_IRQn
59295928
#define TIM1_BRK_TIM9_IRQn TIM1_BRK_TIM15_IRQn
5930-
#define TIM1_BRK_IRQn TIM1_BRK_TIM15_IRQn
59315929
#define TIM9_IRQn TIM1_BRK_TIM15_IRQn
5932-
#define TIM1_TRG_COM_IRQn TIM1_TRG_COM_TIM17_IRQn
5930+
#define TIM1_BRK_IRQn TIM1_BRK_TIM15_IRQn
59335931
#define TIM11_IRQn TIM1_TRG_COM_TIM17_IRQn
5932+
#define TIM1_TRG_COM_IRQn TIM1_TRG_COM_TIM17_IRQn
59345933
#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_TIM17_IRQn
59355934
#define TIM1_UP_IRQn TIM1_UP_TIM16_IRQn
5936-
#define TIM1_UP_TIM10_IRQn TIM1_UP_TIM16_IRQn
59375935
#define TIM10_IRQn TIM1_UP_TIM16_IRQn
5936+
#define TIM1_UP_TIM10_IRQn TIM1_UP_TIM16_IRQn
59385937
#define TIM6_IRQn TIM6_DAC_IRQn
59395938

59405939

@@ -5943,14 +5942,14 @@ typedef struct
59435942
#define USBWakeUp_IRQHandler CEC_IRQHandler
59445943
#define OTG_FS_WKUP_IRQHandler CEC_IRQHandler
59455944
#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_TIM15_IRQHandler
5946-
#define TIM1_BRK_IRQHandler TIM1_BRK_TIM15_IRQHandler
59475945
#define TIM9_IRQHandler TIM1_BRK_TIM15_IRQHandler
5948-
#define TIM1_TRG_COM_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
5946+
#define TIM1_BRK_IRQHandler TIM1_BRK_TIM15_IRQHandler
59495947
#define TIM11_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
5948+
#define TIM1_TRG_COM_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
59505949
#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
59515950
#define TIM1_UP_IRQHandler TIM1_UP_TIM16_IRQHandler
5952-
#define TIM1_UP_TIM10_IRQHandler TIM1_UP_TIM16_IRQHandler
59535951
#define TIM10_IRQHandler TIM1_UP_TIM16_IRQHandler
5952+
#define TIM1_UP_TIM10_IRQHandler TIM1_UP_TIM16_IRQHandler
59545953
#define TIM6_IRQHandler TIM6_DAC_IRQHandler
59555954

59565955

@@ -5971,4 +5970,3 @@ typedef struct
59715970

59725971

59735972

5974-
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Diff for: ‎system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f100xe.h

+16-18
Original file line numberDiff line numberDiff line change
@@ -9,18 +9,17 @@
99
* This file contains:
1010
* - Data structures and the address mapping for all peripherals
1111
* - Peripheral's registers declarations and bits definition
12-
* - Macros to access peripheral’s registers hardware
12+
* - Macros to access peripheral's registers hardware
1313
*
1414
******************************************************************************
1515
* @attention
1616
*
17-
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
18-
* All rights reserved.</center></h2>
17+
* Copyright (c) 2017-2021 STMicroelectronics.
18+
* All rights reserved.
1919
*
20-
* This software component is licensed by ST under BSD 3-Clause license,
21-
* the "License"; You may not use this file except in compliance with the
22-
* License. You may obtain a copy of the License at:
23-
* opensource.org/licenses/BSD-3-Clause
20+
* This software is licensed under terms that can be found in the LICENSE file
21+
* in the root directory of this software component.
22+
* If no LICENSE file comes with this software, it is provided AS-IS.
2423
*
2524
******************************************************************************
2625
*/
@@ -1679,7 +1678,7 @@ typedef struct
16791678
#define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
16801679
#define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
16811680

1682-
/*!< RTC congiguration */
1681+
/*!< RTC configuration */
16831682
#define RCC_BDCR_RTCSEL_NOCLOCK 0x00000000U /*!< No clock */
16841683
#define RCC_BDCR_RTCSEL_LSE 0x00000100U /*!< LSE oscillator clock used as RTC clock */
16851684
#define RCC_BDCR_RTCSEL_LSI 0x00000200U /*!< LSI oscillator clock used as RTC clock */
@@ -3727,7 +3726,7 @@ typedef struct
37273726
#define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!< ADC DMA transfer enable */
37283727
#define ADC_CR2_ALIGN_Pos (11U)
37293728
#define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
3730-
#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */
3729+
#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignment */
37313730

37323731
#define ADC_CR2_JEXTSEL_Pos (12U)
37333732
#define ADC_CR2_JEXTSEL_Msk (0x7UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00007000 */
@@ -6529,20 +6528,20 @@ typedef struct
65296528
#define ADC1_2_IRQn ADC1_IRQn
65306529
#define OTG_FS_WKUP_IRQn CEC_IRQn
65316530
#define USBWakeUp_IRQn CEC_IRQn
6532-
#define TIM8_BRK_IRQn TIM12_IRQn
65336531
#define TIM8_BRK_TIM12_IRQn TIM12_IRQn
6532+
#define TIM8_BRK_IRQn TIM12_IRQn
65346533
#define TIM8_UP_IRQn TIM13_IRQn
65356534
#define TIM8_UP_TIM13_IRQn TIM13_IRQn
65366535
#define TIM8_TRG_COM_TIM14_IRQn TIM14_IRQn
65376536
#define TIM8_TRG_COM_IRQn TIM14_IRQn
6538-
#define TIM9_IRQn TIM1_BRK_TIM15_IRQn
65396537
#define TIM1_BRK_IRQn TIM1_BRK_TIM15_IRQn
65406538
#define TIM1_BRK_TIM9_IRQn TIM1_BRK_TIM15_IRQn
6541-
#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_TIM17_IRQn
6539+
#define TIM9_IRQn TIM1_BRK_TIM15_IRQn
65426540
#define TIM1_TRG_COM_IRQn TIM1_TRG_COM_TIM17_IRQn
6541+
#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_TIM17_IRQn
65436542
#define TIM11_IRQn TIM1_TRG_COM_TIM17_IRQn
6544-
#define TIM10_IRQn TIM1_UP_TIM16_IRQn
65456543
#define TIM1_UP_TIM10_IRQn TIM1_UP_TIM16_IRQn
6544+
#define TIM10_IRQn TIM1_UP_TIM16_IRQn
65466545
#define TIM1_UP_IRQn TIM1_UP_TIM16_IRQn
65476546
#define TIM6_IRQn TIM6_DAC_IRQn
65486547

@@ -6551,20 +6550,20 @@ typedef struct
65516550
#define ADC1_2_IRQHandler ADC1_IRQHandler
65526551
#define OTG_FS_WKUP_IRQHandler CEC_IRQHandler
65536552
#define USBWakeUp_IRQHandler CEC_IRQHandler
6554-
#define TIM8_BRK_IRQHandler TIM12_IRQHandler
65556553
#define TIM8_BRK_TIM12_IRQHandler TIM12_IRQHandler
6554+
#define TIM8_BRK_IRQHandler TIM12_IRQHandler
65566555
#define TIM8_UP_IRQHandler TIM13_IRQHandler
65576556
#define TIM8_UP_TIM13_IRQHandler TIM13_IRQHandler
65586557
#define TIM8_TRG_COM_TIM14_IRQHandler TIM14_IRQHandler
65596558
#define TIM8_TRG_COM_IRQHandler TIM14_IRQHandler
6560-
#define TIM9_IRQHandler TIM1_BRK_TIM15_IRQHandler
65616559
#define TIM1_BRK_IRQHandler TIM1_BRK_TIM15_IRQHandler
65626560
#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_TIM15_IRQHandler
6563-
#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
6561+
#define TIM9_IRQHandler TIM1_BRK_TIM15_IRQHandler
65646562
#define TIM1_TRG_COM_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
6563+
#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
65656564
#define TIM11_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
6566-
#define TIM10_IRQHandler TIM1_UP_TIM16_IRQHandler
65676565
#define TIM1_UP_TIM10_IRQHandler TIM1_UP_TIM16_IRQHandler
6566+
#define TIM10_IRQHandler TIM1_UP_TIM16_IRQHandler
65686567
#define TIM1_UP_IRQHandler TIM1_UP_TIM16_IRQHandler
65696568
#define TIM6_IRQHandler TIM6_DAC_IRQHandler
65706569

@@ -6586,4 +6585,3 @@ typedef struct
65866585

65876586

65886587

6589-
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Diff for: ‎system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f101x6.h

+8-10
Original file line numberDiff line numberDiff line change
@@ -9,18 +9,17 @@
99
* This file contains:
1010
* - Data structures and the address mapping for all peripherals
1111
* - Peripheral's registers declarations and bits definition
12-
* - Macros to access peripheral’s registers hardware
12+
* - Macros to access peripheral's registers hardware
1313
*
1414
******************************************************************************
1515
* @attention
1616
*
17-
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
18-
* All rights reserved.</center></h2>
17+
* Copyright (c) 2017-2021 STMicroelectronics.
18+
* All rights reserved.
1919
*
20-
* This software component is licensed by ST under BSD 3-Clause license,
21-
* the "License"; You may not use this file except in compliance with the
22-
* License. You may obtain a copy of the License at:
23-
* opensource.org/licenses/BSD-3-Clause
20+
* This software is licensed under terms that can be found in the LICENSE file
21+
* in the root directory of this software component.
22+
* If no LICENSE file comes with this software, it is provided AS-IS.
2423
*
2524
******************************************************************************
2625
*/
@@ -1203,7 +1202,7 @@ typedef struct
12031202
#define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
12041203
#define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
12051204

1206-
/*!< RTC congiguration */
1205+
/*!< RTC configuration */
12071206
#define RCC_BDCR_RTCSEL_NOCLOCK 0x00000000U /*!< No clock */
12081207
#define RCC_BDCR_RTCSEL_LSE 0x00000100U /*!< LSE oscillator clock used as RTC clock */
12091208
#define RCC_BDCR_RTCSEL_LSI 0x00000200U /*!< LSI oscillator clock used as RTC clock */
@@ -3166,7 +3165,7 @@ typedef struct
31663165
#define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!< ADC DMA transfer enable */
31673166
#define ADC_CR2_ALIGN_Pos (11U)
31683167
#define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
3169-
#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */
3168+
#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignment */
31703169

31713170
#define ADC_CR2_JEXTSEL_Pos (12U)
31723171
#define ADC_CR2_JEXTSEL_Msk (0x7UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00007000 */
@@ -5314,4 +5313,3 @@ typedef struct
53145313

53155314

53165315

5317-
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Diff for: ‎system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f101xb.h

+8-10
Original file line numberDiff line numberDiff line change
@@ -9,18 +9,17 @@
99
* This file contains:
1010
* - Data structures and the address mapping for all peripherals
1111
* - Peripheral's registers declarations and bits definition
12-
* - Macros to access peripheral’s registers hardware
12+
* - Macros to access peripheral's registers hardware
1313
*
1414
******************************************************************************
1515
* @attention
1616
*
17-
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
18-
* All rights reserved.</center></h2>
17+
* Copyright (c) 2017-2021 STMicroelectronics.
18+
* All rights reserved.
1919
*
20-
* This software component is licensed by ST under BSD 3-Clause license,
21-
* the "License"; You may not use this file except in compliance with the
22-
* License. You may obtain a copy of the License at:
23-
* opensource.org/licenses/BSD-3-Clause
20+
* This software is licensed under terms that can be found in the LICENSE file
21+
* in the root directory of this software component.
22+
* If no LICENSE file comes with this software, it is provided AS-IS.
2423
*
2524
******************************************************************************
2625
*/
@@ -1248,7 +1247,7 @@ typedef struct
12481247
#define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
12491248
#define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
12501249

1251-
/*!< RTC congiguration */
1250+
/*!< RTC configuration */
12521251
#define RCC_BDCR_RTCSEL_NOCLOCK 0x00000000U /*!< No clock */
12531252
#define RCC_BDCR_RTCSEL_LSE 0x00000100U /*!< LSE oscillator clock used as RTC clock */
12541253
#define RCC_BDCR_RTCSEL_LSI 0x00000200U /*!< LSI oscillator clock used as RTC clock */
@@ -3228,7 +3227,7 @@ typedef struct
32283227
#define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!< ADC DMA transfer enable */
32293228
#define ADC_CR2_ALIGN_Pos (11U)
32303229
#define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
3231-
#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */
3230+
#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignment */
32323231

32333232
#define ADC_CR2_JEXTSEL_Pos (12U)
32343233
#define ADC_CR2_JEXTSEL_Msk (0x7UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00007000 */
@@ -5445,4 +5444,3 @@ typedef struct
54455444

54465445

54475446

5448-
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Diff for: ‎system/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f101xe.h

+9-11
Original file line numberDiff line numberDiff line change
@@ -9,18 +9,17 @@
99
* This file contains:
1010
* - Data structures and the address mapping for all peripherals
1111
* - Peripheral's registers declarations and bits definition
12-
* - Macros to access peripheral’s registers hardware
12+
* - Macros to access peripheral's registers hardware
1313
*
1414
******************************************************************************
1515
* @attention
1616
*
17-
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
18-
* All rights reserved.</center></h2>
17+
* Copyright (c) 2017-2021 STMicroelectronics.
18+
* All rights reserved.
1919
*
20-
* This software component is licensed by ST under BSD 3-Clause license,
21-
* the "License"; You may not use this file except in compliance with the
22-
* License. You may obtain a copy of the License at:
23-
* opensource.org/licenses/BSD-3-Clause
20+
* This software is licensed under terms that can be found in the LICENSE file
21+
* in the root directory of this software component.
22+
* If no LICENSE file comes with this software, it is provided AS-IS.
2423
*
2524
******************************************************************************
2625
*/
@@ -1637,7 +1636,7 @@ typedef struct
16371636
#define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
16381637
#define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
16391638

1640-
/*!< RTC congiguration */
1639+
/*!< RTC configuration */
16411640
#define RCC_BDCR_RTCSEL_NOCLOCK 0x00000000U /*!< No clock */
16421641
#define RCC_BDCR_RTCSEL_LSE 0x00000100U /*!< LSE oscillator clock used as RTC clock */
16431642
#define RCC_BDCR_RTCSEL_LSI 0x00000200U /*!< LSI oscillator clock used as RTC clock */
@@ -3623,7 +3622,7 @@ typedef struct
36233622
#define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!< ADC DMA transfer enable */
36243623
#define ADC_CR2_ALIGN_Pos (11U)
36253624
#define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
3626-
#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */
3625+
#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignment */
36273626

36283627
#define ADC_CR2_JEXTSEL_Pos (12U)
36293628
#define ADC_CR2_JEXTSEL_Msk (0x7UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00007000 */
@@ -5293,7 +5292,7 @@ typedef struct
52935292
/* */
52945293
/******************************************************************************/
52955294
/*
5296-
* @brief Specific device feature definitions (not present on all devices in the STM32F1 serie)
5295+
* @brief Specific device feature definitions (not present on all devices in the STM32F1 series)
52975296
*/
52985297
#define SPI_I2S_SUPPORT /*!< I2S support */
52995298
#define SPI_CRC_ERROR_WORKAROUND_FEATURE
@@ -6502,4 +6501,3 @@ typedef struct
65026501

65036502

65046503

6505-
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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