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fpistmfpistm
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Merge pull request #1060 from fpistm/CubeUpdateH7
Update to latest STM32CubeH7
2 parents 69b6ab9 + 46aca90 commit d3ba7fe

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69 files changed

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Diff for: ‎system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h742xx.h

+5-18
Original file line numberDiff line numberDiff line change
@@ -8403,6 +8403,9 @@ typedef struct
84038403
#define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk /*!< Peripheral burst transfer configuration */
84048404
#define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
84058405
#define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
8406+
#define DMA_SxCR_TRBUFF_Pos (20U)
8407+
#define DMA_SxCR_TRBUFF_Msk (0x1UL << DMA_SxCR_TRBUFF_Pos) /*!< 0x00100000 */
8408+
#define DMA_SxCR_TRBUFF DMA_SxCR_TRBUFF_Msk /*!< bufferable transfers enabled/disable */
84068409
#define DMA_SxCR_CT_Pos (19U)
84078410
#define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
84088411
#define DMA_SxCR_CT DMA_SxCR_CT_Msk /*!< Current target (only in double buffer mode) */
@@ -14529,12 +14532,6 @@ typedef struct
1452914532
#define RCC_AHB2ENR_DCMIEN_Pos (0U)
1453014533
#define RCC_AHB2ENR_DCMIEN_Msk (0x1UL << RCC_AHB2ENR_DCMIEN_Pos) /*!< 0x00000001 */
1453114534
#define RCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMIEN_Msk
14532-
#define RCC_AHB2ENR_CRYPEN_Pos (4U)
14533-
#define RCC_AHB2ENR_CRYPEN_Msk (0x1UL << RCC_AHB2ENR_CRYPEN_Pos) /*!< 0x00000010 */
14534-
#define RCC_AHB2ENR_CRYPEN RCC_AHB2ENR_CRYPEN_Msk
14535-
#define RCC_AHB2ENR_HASHEN_Pos (5U)
14536-
#define RCC_AHB2ENR_HASHEN_Msk (0x1UL << RCC_AHB2ENR_HASHEN_Pos) /*!< 0x00000020 */
14537-
#define RCC_AHB2ENR_HASHEN RCC_AHB2ENR_HASHEN_Msk
1453814535
#define RCC_AHB2ENR_RNGEN_Pos (6U)
1453914536
#define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00000040 */
1454014537
#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
@@ -14848,12 +14845,6 @@ typedef struct
1484814845
#define RCC_AHB2RSTR_DCMIRST_Pos (0U)
1484914846
#define RCC_AHB2RSTR_DCMIRST_Msk (0x1UL << RCC_AHB2RSTR_DCMIRST_Pos) /*!< 0x00000001 */
1485014847
#define RCC_AHB2RSTR_DCMIRST RCC_AHB2RSTR_DCMIRST_Msk
14851-
#define RCC_AHB2RSTR_CRYPRST_Pos (4U)
14852-
#define RCC_AHB2RSTR_CRYPRST_Msk (0x1UL << RCC_AHB2RSTR_CRYPRST_Pos) /*!< 0x00000010 */
14853-
#define RCC_AHB2RSTR_CRYPRST RCC_AHB2RSTR_CRYPRST_Msk
14854-
#define RCC_AHB2RSTR_HASHRST_Pos (5U)
14855-
#define RCC_AHB2RSTR_HASHRST_Msk (0x1UL << RCC_AHB2RSTR_HASHRST_Pos) /*!< 0x00000020 */
14856-
#define RCC_AHB2RSTR_HASHRST RCC_AHB2RSTR_HASHRST_Msk
1485714848
#define RCC_AHB2RSTR_RNGRST_Pos (6U)
1485814849
#define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00000040 */
1485914850
#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
@@ -15223,12 +15214,6 @@ typedef struct
1522315214
#define RCC_AHB2LPENR_DCMILPEN_Pos (0U)
1522415215
#define RCC_AHB2LPENR_DCMILPEN_Msk (0x1UL << RCC_AHB2LPENR_DCMILPEN_Pos) /*!< 0x00000001 */
1522515216
#define RCC_AHB2LPENR_DCMILPEN RCC_AHB2LPENR_DCMILPEN_Msk
15226-
#define RCC_AHB2LPENR_CRYPLPEN_Pos (4U)
15227-
#define RCC_AHB2LPENR_CRYPLPEN_Msk (0x1UL << RCC_AHB2LPENR_CRYPLPEN_Pos) /*!< 0x00000010 */
15228-
#define RCC_AHB2LPENR_CRYPLPEN RCC_AHB2LPENR_CRYPLPEN_Msk
15229-
#define RCC_AHB2LPENR_HASHLPEN_Pos (5U)
15230-
#define RCC_AHB2LPENR_HASHLPEN_Msk (0x1UL << RCC_AHB2LPENR_HASHLPEN_Pos) /*!< 0x00000020 */
15231-
#define RCC_AHB2LPENR_HASHLPEN RCC_AHB2LPENR_HASHLPEN_Msk
1523215217
#define RCC_AHB2LPENR_RNGLPEN_Pos (6U)
1523315218
#define RCC_AHB2LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */
1523415219
#define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk
@@ -20369,6 +20354,8 @@ typedef struct
2036920354
/* DBG */
2037020355
/* */
2037120356
/******************************************************************************/
20357+
/********************************* DEVICE ID ********************************/
20358+
#define STM32H7_DEV_ID 0x450UL
2037220359

2037320360
/******************** Bit definition for DBGMCU_IDCODE register *************/
2037420361
#define DBGMCU_IDCODE_DEV_ID_Pos (0U)

Diff for: ‎system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h

+5-18
Original file line numberDiff line numberDiff line change
@@ -8498,6 +8498,9 @@ typedef struct
84988498
#define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk /*!< Peripheral burst transfer configuration */
84998499
#define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
85008500
#define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
8501+
#define DMA_SxCR_TRBUFF_Pos (20U)
8502+
#define DMA_SxCR_TRBUFF_Msk (0x1UL << DMA_SxCR_TRBUFF_Pos) /*!< 0x00100000 */
8503+
#define DMA_SxCR_TRBUFF DMA_SxCR_TRBUFF_Msk /*!< bufferable transfers enabled/disable */
85018504
#define DMA_SxCR_CT_Pos (19U)
85028505
#define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
85038506
#define DMA_SxCR_CT DMA_SxCR_CT_Msk /*!< Current target (only in double buffer mode) */
@@ -15162,12 +15165,6 @@ typedef struct
1516215165
#define RCC_AHB2ENR_DCMIEN_Pos (0U)
1516315166
#define RCC_AHB2ENR_DCMIEN_Msk (0x1UL << RCC_AHB2ENR_DCMIEN_Pos) /*!< 0x00000001 */
1516415167
#define RCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMIEN_Msk
15165-
#define RCC_AHB2ENR_CRYPEN_Pos (4U)
15166-
#define RCC_AHB2ENR_CRYPEN_Msk (0x1UL << RCC_AHB2ENR_CRYPEN_Pos) /*!< 0x00000010 */
15167-
#define RCC_AHB2ENR_CRYPEN RCC_AHB2ENR_CRYPEN_Msk
15168-
#define RCC_AHB2ENR_HASHEN_Pos (5U)
15169-
#define RCC_AHB2ENR_HASHEN_Msk (0x1UL << RCC_AHB2ENR_HASHEN_Pos) /*!< 0x00000020 */
15170-
#define RCC_AHB2ENR_HASHEN RCC_AHB2ENR_HASHEN_Msk
1517115168
#define RCC_AHB2ENR_RNGEN_Pos (6U)
1517215169
#define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00000040 */
1517315170
#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
@@ -15487,12 +15484,6 @@ typedef struct
1548715484
#define RCC_AHB2RSTR_DCMIRST_Pos (0U)
1548815485
#define RCC_AHB2RSTR_DCMIRST_Msk (0x1UL << RCC_AHB2RSTR_DCMIRST_Pos) /*!< 0x00000001 */
1548915486
#define RCC_AHB2RSTR_DCMIRST RCC_AHB2RSTR_DCMIRST_Msk
15490-
#define RCC_AHB2RSTR_CRYPRST_Pos (4U)
15491-
#define RCC_AHB2RSTR_CRYPRST_Msk (0x1UL << RCC_AHB2RSTR_CRYPRST_Pos) /*!< 0x00000010 */
15492-
#define RCC_AHB2RSTR_CRYPRST RCC_AHB2RSTR_CRYPRST_Msk
15493-
#define RCC_AHB2RSTR_HASHRST_Pos (5U)
15494-
#define RCC_AHB2RSTR_HASHRST_Msk (0x1UL << RCC_AHB2RSTR_HASHRST_Pos) /*!< 0x00000020 */
15495-
#define RCC_AHB2RSTR_HASHRST RCC_AHB2RSTR_HASHRST_Msk
1549615487
#define RCC_AHB2RSTR_RNGRST_Pos (6U)
1549715488
#define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00000040 */
1549815489
#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
@@ -15868,12 +15859,6 @@ typedef struct
1586815859
#define RCC_AHB2LPENR_DCMILPEN_Pos (0U)
1586915860
#define RCC_AHB2LPENR_DCMILPEN_Msk (0x1UL << RCC_AHB2LPENR_DCMILPEN_Pos) /*!< 0x00000001 */
1587015861
#define RCC_AHB2LPENR_DCMILPEN RCC_AHB2LPENR_DCMILPEN_Msk
15871-
#define RCC_AHB2LPENR_CRYPLPEN_Pos (4U)
15872-
#define RCC_AHB2LPENR_CRYPLPEN_Msk (0x1UL << RCC_AHB2LPENR_CRYPLPEN_Pos) /*!< 0x00000010 */
15873-
#define RCC_AHB2LPENR_CRYPLPEN RCC_AHB2LPENR_CRYPLPEN_Msk
15874-
#define RCC_AHB2LPENR_HASHLPEN_Pos (5U)
15875-
#define RCC_AHB2LPENR_HASHLPEN_Msk (0x1UL << RCC_AHB2LPENR_HASHLPEN_Pos) /*!< 0x00000020 */
15876-
#define RCC_AHB2LPENR_HASHLPEN RCC_AHB2LPENR_HASHLPEN_Msk
1587715862
#define RCC_AHB2LPENR_RNGLPEN_Pos (6U)
1587815863
#define RCC_AHB2LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */
1587915864
#define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk
@@ -21017,6 +21002,8 @@ typedef struct
2101721002
/* DBG */
2101821003
/* */
2101921004
/******************************************************************************/
21005+
/********************************* DEVICE ID ********************************/
21006+
#define STM32H7_DEV_ID 0x450UL
2102021007

2102121008
/******************** Bit definition for DBGMCU_IDCODE register *************/
2102221009
#define DBGMCU_IDCODE_DEV_ID_Pos (0U)

Diff for: ‎system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h745xx.h

+5-18
Original file line numberDiff line numberDiff line change
@@ -8601,6 +8601,9 @@ typedef struct
86018601
#define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk /*!< Peripheral burst transfer configuration */
86028602
#define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
86038603
#define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
8604+
#define DMA_SxCR_TRBUFF_Pos (20U)
8605+
#define DMA_SxCR_TRBUFF_Msk (0x1UL << DMA_SxCR_TRBUFF_Pos) /*!< 0x00100000 */
8606+
#define DMA_SxCR_TRBUFF DMA_SxCR_TRBUFF_Msk /*!< bufferable transfers enabled/disable */
86048607
#define DMA_SxCR_CT_Pos (19U)
86058608
#define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
86068609
#define DMA_SxCR_CT DMA_SxCR_CT_Msk /*!< Current target (only in double buffer mode) */
@@ -15753,12 +15756,6 @@ typedef struct
1575315756
#define RCC_AHB2ENR_DCMIEN_Pos (0U)
1575415757
#define RCC_AHB2ENR_DCMIEN_Msk (0x1UL << RCC_AHB2ENR_DCMIEN_Pos) /*!< 0x00000001 */
1575515758
#define RCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMIEN_Msk
15756-
#define RCC_AHB2ENR_CRYPEN_Pos (4U)
15757-
#define RCC_AHB2ENR_CRYPEN_Msk (0x1UL << RCC_AHB2ENR_CRYPEN_Pos) /*!< 0x00000010 */
15758-
#define RCC_AHB2ENR_CRYPEN RCC_AHB2ENR_CRYPEN_Msk
15759-
#define RCC_AHB2ENR_HASHEN_Pos (5U)
15760-
#define RCC_AHB2ENR_HASHEN_Msk (0x1UL << RCC_AHB2ENR_HASHEN_Pos) /*!< 0x00000020 */
15761-
#define RCC_AHB2ENR_HASHEN RCC_AHB2ENR_HASHEN_Msk
1576215759
#define RCC_AHB2ENR_RNGEN_Pos (6U)
1576315760
#define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00000040 */
1576415761
#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
@@ -16084,12 +16081,6 @@ typedef struct
1608416081
#define RCC_AHB2RSTR_DCMIRST_Pos (0U)
1608516082
#define RCC_AHB2RSTR_DCMIRST_Msk (0x1UL << RCC_AHB2RSTR_DCMIRST_Pos) /*!< 0x00000001 */
1608616083
#define RCC_AHB2RSTR_DCMIRST RCC_AHB2RSTR_DCMIRST_Msk
16087-
#define RCC_AHB2RSTR_CRYPRST_Pos (4U)
16088-
#define RCC_AHB2RSTR_CRYPRST_Msk (0x1UL << RCC_AHB2RSTR_CRYPRST_Pos) /*!< 0x00000010 */
16089-
#define RCC_AHB2RSTR_CRYPRST RCC_AHB2RSTR_CRYPRST_Msk
16090-
#define RCC_AHB2RSTR_HASHRST_Pos (5U)
16091-
#define RCC_AHB2RSTR_HASHRST_Msk (0x1UL << RCC_AHB2RSTR_HASHRST_Pos) /*!< 0x00000020 */
16092-
#define RCC_AHB2RSTR_HASHRST RCC_AHB2RSTR_HASHRST_Msk
1609316084
#define RCC_AHB2RSTR_RNGRST_Pos (6U)
1609416085
#define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00000040 */
1609516086
#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
@@ -16477,12 +16468,6 @@ typedef struct
1647716468
#define RCC_AHB2LPENR_DCMILPEN_Pos (0U)
1647816469
#define RCC_AHB2LPENR_DCMILPEN_Msk (0x1UL << RCC_AHB2LPENR_DCMILPEN_Pos) /*!< 0x00000001 */
1647916470
#define RCC_AHB2LPENR_DCMILPEN RCC_AHB2LPENR_DCMILPEN_Msk
16480-
#define RCC_AHB2LPENR_CRYPLPEN_Pos (4U)
16481-
#define RCC_AHB2LPENR_CRYPLPEN_Msk (0x1UL << RCC_AHB2LPENR_CRYPLPEN_Pos) /*!< 0x00000010 */
16482-
#define RCC_AHB2LPENR_CRYPLPEN RCC_AHB2LPENR_CRYPLPEN_Msk
16483-
#define RCC_AHB2LPENR_HASHLPEN_Pos (5U)
16484-
#define RCC_AHB2LPENR_HASHLPEN_Msk (0x1UL << RCC_AHB2LPENR_HASHLPEN_Pos) /*!< 0x00000020 */
16485-
#define RCC_AHB2LPENR_HASHLPEN RCC_AHB2LPENR_HASHLPEN_Msk
1648616471
#define RCC_AHB2LPENR_RNGLPEN_Pos (6U)
1648716472
#define RCC_AHB2LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */
1648816473
#define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk
@@ -21671,6 +21656,8 @@ typedef struct
2167121656
/* DBG */
2167221657
/* */
2167321658
/******************************************************************************/
21659+
/********************************* DEVICE ID ********************************/
21660+
#define STM32H7_DEV_ID 0x450UL
2167421661

2167521662
/******************** Bit definition for DBGMCU_IDCODE register *************/
2167621663
#define DBGMCU_IDCODE_DEV_ID_Pos (0U)

Diff for: ‎system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h747xx.h

+5-18
Original file line numberDiff line numberDiff line change
@@ -8684,6 +8684,9 @@ typedef struct
86848684
#define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk /*!< Peripheral burst transfer configuration */
86858685
#define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
86868686
#define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
8687+
#define DMA_SxCR_TRBUFF_Pos (20U)
8688+
#define DMA_SxCR_TRBUFF_Msk (0x1UL << DMA_SxCR_TRBUFF_Pos) /*!< 0x00100000 */
8689+
#define DMA_SxCR_TRBUFF DMA_SxCR_TRBUFF_Msk /*!< bufferable transfers enabled/disable */
86878690
#define DMA_SxCR_CT_Pos (19U)
86888691
#define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
86898692
#define DMA_SxCR_CT DMA_SxCR_CT_Msk /*!< Current target (only in double buffer mode) */
@@ -18913,12 +18916,6 @@ typedef struct
1891318916
#define RCC_AHB2ENR_DCMIEN_Pos (0U)
1891418917
#define RCC_AHB2ENR_DCMIEN_Msk (0x1UL << RCC_AHB2ENR_DCMIEN_Pos) /*!< 0x00000001 */
1891518918
#define RCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMIEN_Msk
18916-
#define RCC_AHB2ENR_CRYPEN_Pos (4U)
18917-
#define RCC_AHB2ENR_CRYPEN_Msk (0x1UL << RCC_AHB2ENR_CRYPEN_Pos) /*!< 0x00000010 */
18918-
#define RCC_AHB2ENR_CRYPEN RCC_AHB2ENR_CRYPEN_Msk
18919-
#define RCC_AHB2ENR_HASHEN_Pos (5U)
18920-
#define RCC_AHB2ENR_HASHEN_Msk (0x1UL << RCC_AHB2ENR_HASHEN_Pos) /*!< 0x00000020 */
18921-
#define RCC_AHB2ENR_HASHEN RCC_AHB2ENR_HASHEN_Msk
1892218919
#define RCC_AHB2ENR_RNGEN_Pos (6U)
1892318920
#define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00000040 */
1892418921
#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
@@ -19247,12 +19244,6 @@ typedef struct
1924719244
#define RCC_AHB2RSTR_DCMIRST_Pos (0U)
1924819245
#define RCC_AHB2RSTR_DCMIRST_Msk (0x1UL << RCC_AHB2RSTR_DCMIRST_Pos) /*!< 0x00000001 */
1924919246
#define RCC_AHB2RSTR_DCMIRST RCC_AHB2RSTR_DCMIRST_Msk
19250-
#define RCC_AHB2RSTR_CRYPRST_Pos (4U)
19251-
#define RCC_AHB2RSTR_CRYPRST_Msk (0x1UL << RCC_AHB2RSTR_CRYPRST_Pos) /*!< 0x00000010 */
19252-
#define RCC_AHB2RSTR_CRYPRST RCC_AHB2RSTR_CRYPRST_Msk
19253-
#define RCC_AHB2RSTR_HASHRST_Pos (5U)
19254-
#define RCC_AHB2RSTR_HASHRST_Msk (0x1UL << RCC_AHB2RSTR_HASHRST_Pos) /*!< 0x00000020 */
19255-
#define RCC_AHB2RSTR_HASHRST RCC_AHB2RSTR_HASHRST_Msk
1925619247
#define RCC_AHB2RSTR_RNGRST_Pos (6U)
1925719248
#define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00000040 */
1925819249
#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
@@ -19643,12 +19634,6 @@ typedef struct
1964319634
#define RCC_AHB2LPENR_DCMILPEN_Pos (0U)
1964419635
#define RCC_AHB2LPENR_DCMILPEN_Msk (0x1UL << RCC_AHB2LPENR_DCMILPEN_Pos) /*!< 0x00000001 */
1964519636
#define RCC_AHB2LPENR_DCMILPEN RCC_AHB2LPENR_DCMILPEN_Msk
19646-
#define RCC_AHB2LPENR_CRYPLPEN_Pos (4U)
19647-
#define RCC_AHB2LPENR_CRYPLPEN_Msk (0x1UL << RCC_AHB2LPENR_CRYPLPEN_Pos) /*!< 0x00000010 */
19648-
#define RCC_AHB2LPENR_CRYPLPEN RCC_AHB2LPENR_CRYPLPEN_Msk
19649-
#define RCC_AHB2LPENR_HASHLPEN_Pos (5U)
19650-
#define RCC_AHB2LPENR_HASHLPEN_Msk (0x1UL << RCC_AHB2LPENR_HASHLPEN_Pos) /*!< 0x00000020 */
19651-
#define RCC_AHB2LPENR_HASHLPEN RCC_AHB2LPENR_HASHLPEN_Msk
1965219637
#define RCC_AHB2LPENR_RNGLPEN_Pos (6U)
1965319638
#define RCC_AHB2LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */
1965419639
#define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk
@@ -24844,6 +24829,8 @@ typedef struct
2484424829
/* DBG */
2484524830
/* */
2484624831
/******************************************************************************/
24832+
/********************************* DEVICE ID ********************************/
24833+
#define STM32H7_DEV_ID 0x450UL
2484724834

2484824835
/******************** Bit definition for DBGMCU_IDCODE register *************/
2484924836
#define DBGMCU_IDCODE_DEV_ID_Pos (0U)

Diff for: ‎system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h

+5
Original file line numberDiff line numberDiff line change
@@ -8691,6 +8691,9 @@ typedef struct
86918691
#define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk /*!< Peripheral burst transfer configuration */
86928692
#define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
86938693
#define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
8694+
#define DMA_SxCR_TRBUFF_Pos (20U)
8695+
#define DMA_SxCR_TRBUFF_Msk (0x1UL << DMA_SxCR_TRBUFF_Pos) /*!< 0x00100000 */
8696+
#define DMA_SxCR_TRBUFF DMA_SxCR_TRBUFF_Msk /*!< bufferable transfers enabled/disable */
86948697
#define DMA_SxCR_CT_Pos (19U)
86958698
#define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
86968699
#define DMA_SxCR_CT DMA_SxCR_CT_Msk /*!< Current target (only in double buffer mode) */
@@ -21285,6 +21288,8 @@ typedef struct
2128521288
/* DBG */
2128621289
/* */
2128721290
/******************************************************************************/
21291+
/********************************* DEVICE ID ********************************/
21292+
#define STM32H7_DEV_ID 0x450UL
2128821293

2128921294
/******************** Bit definition for DBGMCU_IDCODE register *************/
2129021295
#define DBGMCU_IDCODE_DEV_ID_Pos (0U)

Diff for: ‎system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h753xx.h

+5
Original file line numberDiff line numberDiff line change
@@ -8691,6 +8691,9 @@ typedef struct
86918691
#define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk /*!< Peripheral burst transfer configuration */
86928692
#define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
86938693
#define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
8694+
#define DMA_SxCR_TRBUFF_Pos (20U)
8695+
#define DMA_SxCR_TRBUFF_Msk (0x1UL << DMA_SxCR_TRBUFF_Pos) /*!< 0x00100000 */
8696+
#define DMA_SxCR_TRBUFF DMA_SxCR_TRBUFF_Msk /*!< bufferable transfers enabled/disable */
86948697
#define DMA_SxCR_CT_Pos (19U)
86958698
#define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
86968699
#define DMA_SxCR_CT DMA_SxCR_CT_Msk /*!< Current target (only in double buffer mode) */
@@ -21286,6 +21289,8 @@ typedef struct
2128621289
/* DBG */
2128721290
/* */
2128821291
/******************************************************************************/
21292+
/********************************* DEVICE ID ********************************/
21293+
#define STM32H7_DEV_ID 0x450UL
2128921294

2129021295
/******************** Bit definition for DBGMCU_IDCODE register *************/
2129121296
#define DBGMCU_IDCODE_DEV_ID_Pos (0U)

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