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Merge pull request #1684 from ABOSTM/UPDATE_WB
system(WB) update STM32WBxx HAL Drivers to v1.10.1 and CMSIS Drivers to v1.10.1
2 parents 6588dee + 059c4f3 commit cf51e49

13 files changed

+327
-208
lines changed

‎system/Drivers/CMSIS/Device/ST/STM32WBxx/Include/stm32wb10xx.h

+66-33
Original file line numberDiff line numberDiff line change
@@ -150,7 +150,7 @@ typedef struct
150150
__IO uint32_t SMPR; /*!< ADC sampling time register, Address offset: 0x14 */
151151
uint32_t RESERVED1; /*!< Reserved, 0x18 */
152152
uint32_t RESERVED2; /*!< Reserved, 0x1C */
153-
__IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */
153+
__IO uint32_t TR; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */
154154
__IO uint32_t RESERVED3; /*!< Reserved, 0x24 */
155155
__IO uint32_t CHSELR; /*!< ADC group regular sequencer register, Address offset: 0x28 */
156156
__IO uint32_t RESERVED4; /*!< Reserved, 0x2C */
@@ -163,6 +163,10 @@ typedef struct
163163
__IO uint32_t CALFACT; /*!< ADC Calibration factor register, Address offset: 0xB4 */
164164
} ADC_TypeDef;
165165

166+
/* Legacy registers naming */
167+
#define TR1 TR
168+
169+
166170
typedef struct
167171
{
168172
uint32_t RESERVED1; /*!< Reserved, Address offset: ADC1 base address + 0x300 */
@@ -1293,38 +1297,67 @@ typedef struct
12931297
#define ADC_SMPR_SMPSEL18_Msk (0x1UL << ADC_SMPR_SMPSEL18_Pos) /*!< 0x04000000 */
12941298
#define ADC_SMPR_SMPSEL18 ADC_SMPR_SMPSEL18_Msk /*!< ADC channel 18 sampling time selection */
12951299

1296-
/******************** Bit definition for ADC_TR1 register *******************/
1297-
#define ADC_TR1_LT1_Pos (0U)
1298-
#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */
1299-
#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */
1300-
#define ADC_TR1_LT1_0 (0x001UL << ADC_TR1_LT1_Pos) /*!< 0x00000001 */
1301-
#define ADC_TR1_LT1_1 (0x002UL << ADC_TR1_LT1_Pos) /*!< 0x00000002 */
1302-
#define ADC_TR1_LT1_2 (0x004UL << ADC_TR1_LT1_Pos) /*!< 0x00000004 */
1303-
#define ADC_TR1_LT1_3 (0x008UL << ADC_TR1_LT1_Pos) /*!< 0x00000008 */
1304-
#define ADC_TR1_LT1_4 (0x010UL << ADC_TR1_LT1_Pos) /*!< 0x00000010 */
1305-
#define ADC_TR1_LT1_5 (0x020UL << ADC_TR1_LT1_Pos) /*!< 0x00000020 */
1306-
#define ADC_TR1_LT1_6 (0x040UL << ADC_TR1_LT1_Pos) /*!< 0x00000040 */
1307-
#define ADC_TR1_LT1_7 (0x080UL << ADC_TR1_LT1_Pos) /*!< 0x00000080 */
1308-
#define ADC_TR1_LT1_8 (0x100UL << ADC_TR1_LT1_Pos) /*!< 0x00000100 */
1309-
#define ADC_TR1_LT1_9 (0x200UL << ADC_TR1_LT1_Pos) /*!< 0x00000200 */
1310-
#define ADC_TR1_LT1_10 (0x400UL << ADC_TR1_LT1_Pos) /*!< 0x00000400 */
1311-
#define ADC_TR1_LT1_11 (0x800UL << ADC_TR1_LT1_Pos) /*!< 0x00000800 */
1312-
1313-
#define ADC_TR1_HT1_Pos (16U)
1314-
#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */
1315-
#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */
1316-
#define ADC_TR1_HT1_0 (0x001UL << ADC_TR1_HT1_Pos) /*!< 0x00010000 */
1317-
#define ADC_TR1_HT1_1 (0x002UL << ADC_TR1_HT1_Pos) /*!< 0x00020000 */
1318-
#define ADC_TR1_HT1_2 (0x004UL << ADC_TR1_HT1_Pos) /*!< 0x00040000 */
1319-
#define ADC_TR1_HT1_3 (0x008UL << ADC_TR1_HT1_Pos) /*!< 0x00080000 */
1320-
#define ADC_TR1_HT1_4 (0x010UL << ADC_TR1_HT1_Pos) /*!< 0x00100000 */
1321-
#define ADC_TR1_HT1_5 (0x020UL << ADC_TR1_HT1_Pos) /*!< 0x00200000 */
1322-
#define ADC_TR1_HT1_6 (0x040UL << ADC_TR1_HT1_Pos) /*!< 0x00400000 */
1323-
#define ADC_TR1_HT1_7 (0x080UL << ADC_TR1_HT1_Pos) /*!< 0x00800000 */
1324-
#define ADC_TR1_HT1_8 (0x100UL << ADC_TR1_HT1_Pos) /*!< 0x01000000 */
1325-
#define ADC_TR1_HT1_9 (0x200UL << ADC_TR1_HT1_Pos) /*!< 0x02000000 */
1326-
#define ADC_TR1_HT1_10 (0x400UL << ADC_TR1_HT1_Pos) /*!< 0x04000000 */
1327-
#define ADC_TR1_HT1_11 (0x800UL << ADC_TR1_HT1_Pos) /*!< 0x08000000 */
1300+
/******************** Bit definition for ADC_TR register *******************/
1301+
#define ADC_TR_LT_Pos (0U)
1302+
#define ADC_TR_LT_Msk (0xFFFUL << ADC_TR_LT_Pos) /*!< 0x00000FFF */
1303+
#define ADC_TR_LT ADC_TR_LT_Msk /*!< ADC analog watchdog 1 threshold low */
1304+
#define ADC_TR_LT_0 (0x001UL << ADC_TR_LT_Pos) /*!< 0x00000001 */
1305+
#define ADC_TR_LT_1 (0x002UL << ADC_TR_LT_Pos) /*!< 0x00000002 */
1306+
#define ADC_TR_LT_2 (0x004UL << ADC_TR_LT_Pos) /*!< 0x00000004 */
1307+
#define ADC_TR_LT_3 (0x008UL << ADC_TR_LT_Pos) /*!< 0x00000008 */
1308+
#define ADC_TR_LT_4 (0x010UL << ADC_TR_LT_Pos) /*!< 0x00000010 */
1309+
#define ADC_TR_LT_5 (0x020UL << ADC_TR_LT_Pos) /*!< 0x00000020 */
1310+
#define ADC_TR_LT_6 (0x040UL << ADC_TR_LT_Pos) /*!< 0x00000040 */
1311+
#define ADC_TR_LT_7 (0x080UL << ADC_TR_LT_Pos) /*!< 0x00000080 */
1312+
#define ADC_TR_LT_8 (0x100UL << ADC_TR_LT_Pos) /*!< 0x00000100 */
1313+
#define ADC_TR_LT_9 (0x200UL << ADC_TR_LT_Pos) /*!< 0x00000200 */
1314+
#define ADC_TR_LT_10 (0x400UL << ADC_TR_LT_Pos) /*!< 0x00000400 */
1315+
#define ADC_TR_LT_11 (0x800UL << ADC_TR_LT_Pos) /*!< 0x00000800 */
1316+
1317+
#define ADC_TR_HT_Pos (16U)
1318+
#define ADC_TR_HT_Msk (0xFFFUL << ADC_TR_HT_Pos) /*!< 0x0FFF0000 */
1319+
#define ADC_TR_HT ADC_TR_HT_Msk /*!< ADC Analog watchdog 1 threshold high */
1320+
#define ADC_TR_HT_0 (0x001UL << ADC_TR_HT_Pos) /*!< 0x00010000 */
1321+
#define ADC_TR_HT_1 (0x002UL << ADC_TR_HT_Pos) /*!< 0x00020000 */
1322+
#define ADC_TR_HT_2 (0x004UL << ADC_TR_HT_Pos) /*!< 0x00040000 */
1323+
#define ADC_TR_HT_3 (0x008UL << ADC_TR_HT_Pos) /*!< 0x00080000 */
1324+
#define ADC_TR_HT_4 (0x010UL << ADC_TR_HT_Pos) /*!< 0x00100000 */
1325+
#define ADC_TR_HT_5 (0x020UL << ADC_TR_HT_Pos) /*!< 0x00200000 */
1326+
#define ADC_TR_HT_6 (0x040UL << ADC_TR_HT_Pos) /*!< 0x00400000 */
1327+
#define ADC_TR_HT_7 (0x080UL << ADC_TR_HT_Pos) /*!< 0x00800000 */
1328+
#define ADC_TR_HT_8 (0x100UL << ADC_TR_HT_Pos) /*!< 0x01000000 */
1329+
#define ADC_TR_HT_9 (0x200UL << ADC_TR_HT_Pos) /*!< 0x02000000 */
1330+
#define ADC_TR_HT_10 (0x400UL << ADC_TR_HT_Pos) /*!< 0x04000000 */
1331+
#define ADC_TR_HT_11 (0x800UL << ADC_TR_HT_Pos) /*!< 0x08000000 */
1332+
1333+
/* Legacy definitions */
1334+
#define ADC_TR1_LT1 ADC_TR_LT
1335+
#define ADC_TR1_LT1_0 ADC_TR_LT_0
1336+
#define ADC_TR1_LT1_1 ADC_TR_LT_1
1337+
#define ADC_TR1_LT1_2 ADC_TR_LT_2
1338+
#define ADC_TR1_LT1_3 ADC_TR_LT_3
1339+
#define ADC_TR1_LT1_4 ADC_TR_LT_4
1340+
#define ADC_TR1_LT1_5 ADC_TR_LT_5
1341+
#define ADC_TR1_LT1_6 ADC_TR_LT_6
1342+
#define ADC_TR1_LT1_7 ADC_TR_LT_7
1343+
#define ADC_TR1_LT1_8 ADC_TR_LT_8
1344+
#define ADC_TR1_LT1_9 ADC_TR_LT_9
1345+
#define ADC_TR1_LT1_10 ADC_TR_LT_10
1346+
#define ADC_TR1_LT1_11 ADC_TR_LT_11
1347+
1348+
#define ADC_TR1_HT1 ADC_TR_HT
1349+
#define ADC_TR1_HT1_0 ADC_TR_HT_0
1350+
#define ADC_TR1_HT1_1 ADC_TR_HT_1
1351+
#define ADC_TR1_HT1_2 ADC_TR_HT_2
1352+
#define ADC_TR1_HT1_3 ADC_TR_HT_3
1353+
#define ADC_TR1_HT1_4 ADC_TR_HT_4
1354+
#define ADC_TR1_HT1_5 ADC_TR_HT_5
1355+
#define ADC_TR1_HT1_6 ADC_TR_HT_6
1356+
#define ADC_TR1_HT1_7 ADC_TR_HT_7
1357+
#define ADC_TR1_HT1_8 ADC_TR_HT_8
1358+
#define ADC_TR1_HT1_9 ADC_TR_HT_9
1359+
#define ADC_TR1_HT1_10 ADC_TR_HT_10
1360+
#define ADC_TR1_HT1_11 ADC_TR_HT_11
13281361

13291362
/******************** Bit definition for ADC_CHSELR register ****************/
13301363
#define ADC_CHSELR_CHSEL_Pos (0U)

‎system/Drivers/CMSIS/Device/ST/STM32WBxx/Include/stm32wb15xx.h

+66-33
Original file line numberDiff line numberDiff line change
@@ -152,7 +152,7 @@ typedef struct
152152
__IO uint32_t SMPR; /*!< ADC sampling time register, Address offset: 0x14 */
153153
uint32_t RESERVED1; /*!< Reserved, 0x18 */
154154
uint32_t RESERVED2; /*!< Reserved, 0x1C */
155-
__IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */
155+
__IO uint32_t TR; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */
156156
__IO uint32_t RESERVED3; /*!< Reserved, 0x24 */
157157
__IO uint32_t CHSELR; /*!< ADC group regular sequencer register, Address offset: 0x28 */
158158
__IO uint32_t RESERVED4; /*!< Reserved, 0x2C */
@@ -165,6 +165,10 @@ typedef struct
165165
__IO uint32_t CALFACT; /*!< ADC Calibration factor register, Address offset: 0xB4 */
166166
} ADC_TypeDef;
167167

168+
/* Legacy registers naming */
169+
#define TR1 TR
170+
171+
168172
typedef struct
169173
{
170174
uint32_t RESERVED1; /*!< Reserved, Address offset: ADC1 base address + 0x300 */
@@ -1308,38 +1312,67 @@ typedef struct
13081312
#define ADC_SMPR_SMPSEL18_Msk (0x1UL << ADC_SMPR_SMPSEL18_Pos) /*!< 0x04000000 */
13091313
#define ADC_SMPR_SMPSEL18 ADC_SMPR_SMPSEL18_Msk /*!< ADC channel 18 sampling time selection */
13101314

1311-
/******************** Bit definition for ADC_TR1 register *******************/
1312-
#define ADC_TR1_LT1_Pos (0U)
1313-
#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */
1314-
#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */
1315-
#define ADC_TR1_LT1_0 (0x001UL << ADC_TR1_LT1_Pos) /*!< 0x00000001 */
1316-
#define ADC_TR1_LT1_1 (0x002UL << ADC_TR1_LT1_Pos) /*!< 0x00000002 */
1317-
#define ADC_TR1_LT1_2 (0x004UL << ADC_TR1_LT1_Pos) /*!< 0x00000004 */
1318-
#define ADC_TR1_LT1_3 (0x008UL << ADC_TR1_LT1_Pos) /*!< 0x00000008 */
1319-
#define ADC_TR1_LT1_4 (0x010UL << ADC_TR1_LT1_Pos) /*!< 0x00000010 */
1320-
#define ADC_TR1_LT1_5 (0x020UL << ADC_TR1_LT1_Pos) /*!< 0x00000020 */
1321-
#define ADC_TR1_LT1_6 (0x040UL << ADC_TR1_LT1_Pos) /*!< 0x00000040 */
1322-
#define ADC_TR1_LT1_7 (0x080UL << ADC_TR1_LT1_Pos) /*!< 0x00000080 */
1323-
#define ADC_TR1_LT1_8 (0x100UL << ADC_TR1_LT1_Pos) /*!< 0x00000100 */
1324-
#define ADC_TR1_LT1_9 (0x200UL << ADC_TR1_LT1_Pos) /*!< 0x00000200 */
1325-
#define ADC_TR1_LT1_10 (0x400UL << ADC_TR1_LT1_Pos) /*!< 0x00000400 */
1326-
#define ADC_TR1_LT1_11 (0x800UL << ADC_TR1_LT1_Pos) /*!< 0x00000800 */
1327-
1328-
#define ADC_TR1_HT1_Pos (16U)
1329-
#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */
1330-
#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */
1331-
#define ADC_TR1_HT1_0 (0x001UL << ADC_TR1_HT1_Pos) /*!< 0x00010000 */
1332-
#define ADC_TR1_HT1_1 (0x002UL << ADC_TR1_HT1_Pos) /*!< 0x00020000 */
1333-
#define ADC_TR1_HT1_2 (0x004UL << ADC_TR1_HT1_Pos) /*!< 0x00040000 */
1334-
#define ADC_TR1_HT1_3 (0x008UL << ADC_TR1_HT1_Pos) /*!< 0x00080000 */
1335-
#define ADC_TR1_HT1_4 (0x010UL << ADC_TR1_HT1_Pos) /*!< 0x00100000 */
1336-
#define ADC_TR1_HT1_5 (0x020UL << ADC_TR1_HT1_Pos) /*!< 0x00200000 */
1337-
#define ADC_TR1_HT1_6 (0x040UL << ADC_TR1_HT1_Pos) /*!< 0x00400000 */
1338-
#define ADC_TR1_HT1_7 (0x080UL << ADC_TR1_HT1_Pos) /*!< 0x00800000 */
1339-
#define ADC_TR1_HT1_8 (0x100UL << ADC_TR1_HT1_Pos) /*!< 0x01000000 */
1340-
#define ADC_TR1_HT1_9 (0x200UL << ADC_TR1_HT1_Pos) /*!< 0x02000000 */
1341-
#define ADC_TR1_HT1_10 (0x400UL << ADC_TR1_HT1_Pos) /*!< 0x04000000 */
1342-
#define ADC_TR1_HT1_11 (0x800UL << ADC_TR1_HT1_Pos) /*!< 0x08000000 */
1315+
/******************** Bit definition for ADC_TR register *******************/
1316+
#define ADC_TR_LT_Pos (0U)
1317+
#define ADC_TR_LT_Msk (0xFFFUL << ADC_TR_LT_Pos) /*!< 0x00000FFF */
1318+
#define ADC_TR_LT ADC_TR_LT_Msk /*!< ADC analog watchdog 1 threshold low */
1319+
#define ADC_TR_LT_0 (0x001UL << ADC_TR_LT_Pos) /*!< 0x00000001 */
1320+
#define ADC_TR_LT_1 (0x002UL << ADC_TR_LT_Pos) /*!< 0x00000002 */
1321+
#define ADC_TR_LT_2 (0x004UL << ADC_TR_LT_Pos) /*!< 0x00000004 */
1322+
#define ADC_TR_LT_3 (0x008UL << ADC_TR_LT_Pos) /*!< 0x00000008 */
1323+
#define ADC_TR_LT_4 (0x010UL << ADC_TR_LT_Pos) /*!< 0x00000010 */
1324+
#define ADC_TR_LT_5 (0x020UL << ADC_TR_LT_Pos) /*!< 0x00000020 */
1325+
#define ADC_TR_LT_6 (0x040UL << ADC_TR_LT_Pos) /*!< 0x00000040 */
1326+
#define ADC_TR_LT_7 (0x080UL << ADC_TR_LT_Pos) /*!< 0x00000080 */
1327+
#define ADC_TR_LT_8 (0x100UL << ADC_TR_LT_Pos) /*!< 0x00000100 */
1328+
#define ADC_TR_LT_9 (0x200UL << ADC_TR_LT_Pos) /*!< 0x00000200 */
1329+
#define ADC_TR_LT_10 (0x400UL << ADC_TR_LT_Pos) /*!< 0x00000400 */
1330+
#define ADC_TR_LT_11 (0x800UL << ADC_TR_LT_Pos) /*!< 0x00000800 */
1331+
1332+
#define ADC_TR_HT_Pos (16U)
1333+
#define ADC_TR_HT_Msk (0xFFFUL << ADC_TR_HT_Pos) /*!< 0x0FFF0000 */
1334+
#define ADC_TR_HT ADC_TR_HT_Msk /*!< ADC Analog watchdog 1 threshold high */
1335+
#define ADC_TR_HT_0 (0x001UL << ADC_TR_HT_Pos) /*!< 0x00010000 */
1336+
#define ADC_TR_HT_1 (0x002UL << ADC_TR_HT_Pos) /*!< 0x00020000 */
1337+
#define ADC_TR_HT_2 (0x004UL << ADC_TR_HT_Pos) /*!< 0x00040000 */
1338+
#define ADC_TR_HT_3 (0x008UL << ADC_TR_HT_Pos) /*!< 0x00080000 */
1339+
#define ADC_TR_HT_4 (0x010UL << ADC_TR_HT_Pos) /*!< 0x00100000 */
1340+
#define ADC_TR_HT_5 (0x020UL << ADC_TR_HT_Pos) /*!< 0x00200000 */
1341+
#define ADC_TR_HT_6 (0x040UL << ADC_TR_HT_Pos) /*!< 0x00400000 */
1342+
#define ADC_TR_HT_7 (0x080UL << ADC_TR_HT_Pos) /*!< 0x00800000 */
1343+
#define ADC_TR_HT_8 (0x100UL << ADC_TR_HT_Pos) /*!< 0x01000000 */
1344+
#define ADC_TR_HT_9 (0x200UL << ADC_TR_HT_Pos) /*!< 0x02000000 */
1345+
#define ADC_TR_HT_10 (0x400UL << ADC_TR_HT_Pos) /*!< 0x04000000 */
1346+
#define ADC_TR_HT_11 (0x800UL << ADC_TR_HT_Pos) /*!< 0x08000000 */
1347+
1348+
/* Legacy definitions */
1349+
#define ADC_TR1_LT1 ADC_TR_LT
1350+
#define ADC_TR1_LT1_0 ADC_TR_LT_0
1351+
#define ADC_TR1_LT1_1 ADC_TR_LT_1
1352+
#define ADC_TR1_LT1_2 ADC_TR_LT_2
1353+
#define ADC_TR1_LT1_3 ADC_TR_LT_3
1354+
#define ADC_TR1_LT1_4 ADC_TR_LT_4
1355+
#define ADC_TR1_LT1_5 ADC_TR_LT_5
1356+
#define ADC_TR1_LT1_6 ADC_TR_LT_6
1357+
#define ADC_TR1_LT1_7 ADC_TR_LT_7
1358+
#define ADC_TR1_LT1_8 ADC_TR_LT_8
1359+
#define ADC_TR1_LT1_9 ADC_TR_LT_9
1360+
#define ADC_TR1_LT1_10 ADC_TR_LT_10
1361+
#define ADC_TR1_LT1_11 ADC_TR_LT_11
1362+
1363+
#define ADC_TR1_HT1 ADC_TR_HT
1364+
#define ADC_TR1_HT1_0 ADC_TR_HT_0
1365+
#define ADC_TR1_HT1_1 ADC_TR_HT_1
1366+
#define ADC_TR1_HT1_2 ADC_TR_HT_2
1367+
#define ADC_TR1_HT1_3 ADC_TR_HT_3
1368+
#define ADC_TR1_HT1_4 ADC_TR_HT_4
1369+
#define ADC_TR1_HT1_5 ADC_TR_HT_5
1370+
#define ADC_TR1_HT1_6 ADC_TR_HT_6
1371+
#define ADC_TR1_HT1_7 ADC_TR_HT_7
1372+
#define ADC_TR1_HT1_8 ADC_TR_HT_8
1373+
#define ADC_TR1_HT1_9 ADC_TR_HT_9
1374+
#define ADC_TR1_HT1_10 ADC_TR_HT_10
1375+
#define ADC_TR1_HT1_11 ADC_TR_HT_11
13431376

13441377
/******************** Bit definition for ADC_CHSELR register ****************/
13451378
#define ADC_CHSELR_CHSEL_Pos (0U)

‎system/Drivers/CMSIS/Device/ST/STM32WBxx/Include/stm32wbxx.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -69,7 +69,7 @@
6969
*/
7070
#define __STM32WBxx_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */
7171
#define __STM32WBxx_CMSIS_VERSION_SUB1 (0x0AU) /*!< [23:16] sub1 version */
72-
#define __STM32WBxx_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
72+
#define __STM32WBxx_CMSIS_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */
7373
#define __STM32WBxx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
7474
#define __STM32WBxx_CMSIS_DEVICE_VERSION ((__STM32WBxx_CMSIS_VERSION_MAIN << 24)\
7575
|(__STM32WBxx_CMSIS_VERSION_SUB1 << 16)\

‎system/Drivers/CMSIS/Device/ST/STM32WBxx/README.md

+1
Original file line numberDiff line numberDiff line change
@@ -39,6 +39,7 @@ Tag v1.7.0 | Tag v5.6.0_cm4 | Tag v1.10.0
3939
Tag v1.8.0 | Tag v5.6.0_cm4 | Tag v1.11.0
4040
Tag v1.9.0 | Tag v5.6.0_cm4 | Tag v1.12.0
4141
Tag v1.10.0 | Tag v5.6.0_cm4 | Tag v1.13.0
42+
Tag v1.10.1 | Tag v5.6.0_cm4 | Tag v1.13.3
4243

4344
The full **STM32CubeWB** MCU package is available [here](https://github.com/STMicroelectronics/STM32CubeWB).
4445

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