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Merge pull request #2489 from fpistm/STM32CubeWBA_update
chore(wba): update to latest STM32CubeWBA v1.4.1
2 parents 6a03b54 + 91c9559 commit c7175b3

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Diff for: ‎cmake/boards_db.cmake

+164
Original file line numberDiff line numberDiff line change
@@ -73174,6 +73174,170 @@ target_compile_options(GENERIC_G4A1VETX_xusb_HSFS INTERFACE
7317473174
"SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
7317573175
)
7317673176

73177+
# GENERIC_H503CBTX
73178+
# -----------------------------------------------------------------------------
73179+
73180+
set(GENERIC_H503CBTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H5xx/H503CB(T-U)")
73181+
set(GENERIC_H503CBTX_MAXSIZE 131072)
73182+
set(GENERIC_H503CBTX_MAXDATASIZE 32768)
73183+
set(GENERIC_H503CBTX_MCU cortex-m33)
73184+
set(GENERIC_H503CBTX_FPCONF "-")
73185+
add_library(GENERIC_H503CBTX INTERFACE)
73186+
target_compile_options(GENERIC_H503CBTX INTERFACE
73187+
"SHELL:-DSTM32H503xx "
73188+
"SHELL:"
73189+
"SHELL:"
73190+
"SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
73191+
-mcpu=${GENERIC_H503CBTX_MCU}
73192+
)
73193+
target_compile_definitions(GENERIC_H503CBTX INTERFACE
73194+
"STM32H5xx"
73195+
"ARDUINO_GENERIC_H503CBTX"
73196+
"BOARD_NAME=\"GENERIC_H503CBTX\""
73197+
"BOARD_ID=GENERIC_H503CBTX"
73198+
"VARIANT_H=\"variant_generic.h\""
73199+
)
73200+
target_include_directories(GENERIC_H503CBTX INTERFACE
73201+
${CMAKE_CURRENT_LIST_DIR}/../system/STM32H5xx
73202+
${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Inc
73203+
${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Src
73204+
${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/
73205+
${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/
73206+
${GENERIC_H503CBTX_VARIANT_PATH}
73207+
)
73208+
73209+
target_link_options(GENERIC_H503CBTX INTERFACE
73210+
"LINKER:--default-script=${GENERIC_H503CBTX_VARIANT_PATH}/ldscript.ld"
73211+
"LINKER:--defsym=LD_FLASH_OFFSET=0x0"
73212+
"LINKER:--defsym=LD_MAX_SIZE=131072"
73213+
"LINKER:--defsym=LD_MAX_DATA_SIZE=32768"
73214+
"SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
73215+
-mcpu=${GENERIC_H503CBTX_MCU}
73216+
)
73217+
73218+
add_library(GENERIC_H503CBTX_serial_disabled INTERFACE)
73219+
target_compile_options(GENERIC_H503CBTX_serial_disabled INTERFACE
73220+
"SHELL:"
73221+
)
73222+
add_library(GENERIC_H503CBTX_serial_generic INTERFACE)
73223+
target_compile_options(GENERIC_H503CBTX_serial_generic INTERFACE
73224+
"SHELL:-DHAL_UART_MODULE_ENABLED"
73225+
)
73226+
add_library(GENERIC_H503CBTX_serial_none INTERFACE)
73227+
target_compile_options(GENERIC_H503CBTX_serial_none INTERFACE
73228+
"SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE"
73229+
)
73230+
add_library(GENERIC_H503CBTX_usb_CDC INTERFACE)
73231+
target_compile_options(GENERIC_H503CBTX_usb_CDC INTERFACE
73232+
"SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB"
73233+
)
73234+
add_library(GENERIC_H503CBTX_usb_CDCgen INTERFACE)
73235+
target_compile_options(GENERIC_H503CBTX_usb_CDCgen INTERFACE
73236+
"SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC"
73237+
)
73238+
add_library(GENERIC_H503CBTX_usb_HID INTERFACE)
73239+
target_compile_options(GENERIC_H503CBTX_usb_HID INTERFACE
73240+
"SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE"
73241+
)
73242+
add_library(GENERIC_H503CBTX_usb_none INTERFACE)
73243+
target_compile_options(GENERIC_H503CBTX_usb_none INTERFACE
73244+
"SHELL:"
73245+
)
73246+
add_library(GENERIC_H503CBTX_xusb_FS INTERFACE)
73247+
target_compile_options(GENERIC_H503CBTX_xusb_FS INTERFACE
73248+
"SHELL:"
73249+
)
73250+
add_library(GENERIC_H503CBTX_xusb_HS INTERFACE)
73251+
target_compile_options(GENERIC_H503CBTX_xusb_HS INTERFACE
73252+
"SHELL:-DUSE_USB_HS"
73253+
)
73254+
add_library(GENERIC_H503CBTX_xusb_HSFS INTERFACE)
73255+
target_compile_options(GENERIC_H503CBTX_xusb_HSFS INTERFACE
73256+
"SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
73257+
)
73258+
73259+
# GENERIC_H503CBUX
73260+
# -----------------------------------------------------------------------------
73261+
73262+
set(GENERIC_H503CBUX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H5xx/H503CB(T-U)")
73263+
set(GENERIC_H503CBUX_MAXSIZE 131072)
73264+
set(GENERIC_H503CBUX_MAXDATASIZE 32768)
73265+
set(GENERIC_H503CBUX_MCU cortex-m33)
73266+
set(GENERIC_H503CBUX_FPCONF "-")
73267+
add_library(GENERIC_H503CBUX INTERFACE)
73268+
target_compile_options(GENERIC_H503CBUX INTERFACE
73269+
"SHELL:-DSTM32H503xx "
73270+
"SHELL:"
73271+
"SHELL:"
73272+
"SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
73273+
-mcpu=${GENERIC_H503CBUX_MCU}
73274+
)
73275+
target_compile_definitions(GENERIC_H503CBUX INTERFACE
73276+
"STM32H5xx"
73277+
"ARDUINO_GENERIC_H503CBUX"
73278+
"BOARD_NAME=\"GENERIC_H503CBUX\""
73279+
"BOARD_ID=GENERIC_H503CBUX"
73280+
"VARIANT_H=\"variant_generic.h\""
73281+
)
73282+
target_include_directories(GENERIC_H503CBUX INTERFACE
73283+
${CMAKE_CURRENT_LIST_DIR}/../system/STM32H5xx
73284+
${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Inc
73285+
${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Src
73286+
${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/
73287+
${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/
73288+
${GENERIC_H503CBUX_VARIANT_PATH}
73289+
)
73290+
73291+
target_link_options(GENERIC_H503CBUX INTERFACE
73292+
"LINKER:--default-script=${GENERIC_H503CBUX_VARIANT_PATH}/ldscript.ld"
73293+
"LINKER:--defsym=LD_FLASH_OFFSET=0x0"
73294+
"LINKER:--defsym=LD_MAX_SIZE=131072"
73295+
"LINKER:--defsym=LD_MAX_DATA_SIZE=32768"
73296+
"SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
73297+
-mcpu=${GENERIC_H503CBUX_MCU}
73298+
)
73299+
73300+
add_library(GENERIC_H503CBUX_serial_disabled INTERFACE)
73301+
target_compile_options(GENERIC_H503CBUX_serial_disabled INTERFACE
73302+
"SHELL:"
73303+
)
73304+
add_library(GENERIC_H503CBUX_serial_generic INTERFACE)
73305+
target_compile_options(GENERIC_H503CBUX_serial_generic INTERFACE
73306+
"SHELL:-DHAL_UART_MODULE_ENABLED"
73307+
)
73308+
add_library(GENERIC_H503CBUX_serial_none INTERFACE)
73309+
target_compile_options(GENERIC_H503CBUX_serial_none INTERFACE
73310+
"SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE"
73311+
)
73312+
add_library(GENERIC_H503CBUX_usb_CDC INTERFACE)
73313+
target_compile_options(GENERIC_H503CBUX_usb_CDC INTERFACE
73314+
"SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB"
73315+
)
73316+
add_library(GENERIC_H503CBUX_usb_CDCgen INTERFACE)
73317+
target_compile_options(GENERIC_H503CBUX_usb_CDCgen INTERFACE
73318+
"SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC"
73319+
)
73320+
add_library(GENERIC_H503CBUX_usb_HID INTERFACE)
73321+
target_compile_options(GENERIC_H503CBUX_usb_HID INTERFACE
73322+
"SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE"
73323+
)
73324+
add_library(GENERIC_H503CBUX_usb_none INTERFACE)
73325+
target_compile_options(GENERIC_H503CBUX_usb_none INTERFACE
73326+
"SHELL:"
73327+
)
73328+
add_library(GENERIC_H503CBUX_xusb_FS INTERFACE)
73329+
target_compile_options(GENERIC_H503CBUX_xusb_FS INTERFACE
73330+
"SHELL:"
73331+
)
73332+
add_library(GENERIC_H503CBUX_xusb_HS INTERFACE)
73333+
target_compile_options(GENERIC_H503CBUX_xusb_HS INTERFACE
73334+
"SHELL:-DUSE_USB_HS"
73335+
)
73336+
add_library(GENERIC_H503CBUX_xusb_HSFS INTERFACE)
73337+
target_compile_options(GENERIC_H503CBUX_xusb_HSFS INTERFACE
73338+
"SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
73339+
)
73340+
7317773341
# GENERIC_H503KBUX
7317873342
# -----------------------------------------------------------------------------
7317973343

Diff for: ‎libraries/SrcWrapper/CMakeLists.txt

+1
Original file line numberDiff line numberDiff line change
@@ -114,6 +114,7 @@ add_library(SrcWrapper_bin OBJECT EXCLUDE_FROM_ALL
114114
src/HAL/stm32yyxx_hal_sd.c
115115
src/HAL/stm32yyxx_hal_sd_ex.c
116116
src/HAL/stm32yyxx_hal_sdadc.c
117+
src/HAL/stm32yyxx_hal_sdio.c
117118
src/HAL/stm32yyxx_hal_sdram.c
118119
src/HAL/stm32yyxx_hal_smartcard.c
119120
src/HAL/stm32yyxx_hal_smartcard_ex.c

Diff for: ‎system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba50xx.h

+30-27
Original file line numberDiff line numberDiff line change
@@ -253,14 +253,14 @@ typedef struct
253253
*/
254254
typedef struct
255255
{
256-
__IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
257-
__IO uint32_t SCR; /*!< Debug MCU status and configuration register, Address offset: 0x04 */
258-
__IO uint32_t APB1LFZR; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */
259-
__IO uint32_t APB1HFZR; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */
260-
__IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */
261-
uint32_t RESERVED1[4];/*!< Reserved, 0x14 - 0x20 */
262-
__IO uint32_t APB7FZR; /*!< Debug MCU APB7 freeze register, Address offset: 0x24 */
263-
__IO uint32_t AHB1FZR; /*!< Debug MCU AHB1 freeze register, Address offset: 0x28 */
256+
__IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
257+
__IO uint32_t SCR; /*!< Debug MCU status and configuration register, Address offset: 0x04 */
258+
__IO uint32_t APB1LFZR; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */
259+
__IO uint32_t APB1HFZR; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */
260+
__IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */
261+
uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x14 - 0x20 */
262+
__IO uint32_t APB7FZR; /*!< Debug MCU APB7 freeze register, Address offset: 0x24 */
263+
__IO uint32_t AHB1FZR; /*!< Debug MCU AHB1 freeze register, Address offset: 0x28 */
264264
} DBGMCU_TypeDef;
265265

266266
/**
@@ -617,11 +617,11 @@ typedef struct
617617
*/
618618
typedef struct
619619
{
620-
__IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
621-
__IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
622-
__IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
620+
__IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
621+
__IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
622+
__IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
623623
uint32_t RESERVED;
624-
__IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */
624+
__IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */
625625
} RNG_TypeDef;
626626

627627
/*
@@ -693,18 +693,18 @@ typedef struct
693693
*/
694694
typedef struct
695695
{
696-
__IO uint32_t SECCFGR; /*!< SYSCFG secure configuration register, Address offset: 0x00 */
697-
__IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */
698-
__IO uint32_t FPUIMR; /*!< SYSCFG FPU interrupt mask register, Address offset: 0x08 */
699-
__IO uint32_t CNSLCKR; /*!< SYSCFG CPU non-secure lock register, Address offset: 0x0C */
700-
__IO uint32_t CSLCKR; /*!< SYSCFG CPU secure lock register, Address offset: 0x10 */
701-
__IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x14 */
702-
__IO uint32_t MESR; /*!< SYSCFG Memory Erase Status register, Address offset: 0x18 */
703-
__IO uint32_t CCCSR; /*!< SYSCFG Conpensaion Cell Control&Status register, Address offset: 0x1C */
704-
__IO uint32_t CCVR; /*!< SYSCFG Conpensaion Cell value register, Address offset: 0x20 */
705-
__IO uint32_t CCCR; /*!< SYSCFG Conpensaion Cell Code register, Address offset: 0x24 */
706-
uint32_t RESERVED1; /*!< RESERVED1, Address offset: 0x28 */
707-
__IO uint32_t RSSCMDR; /*!< SYSCFG RSS command mode register, Address offset: 0x2C */
696+
__IO uint32_t SECCFGR; /*!< SYSCFG secure configuration register, Address offset: 0x00 */
697+
__IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */
698+
__IO uint32_t FPUIMR; /*!< SYSCFG FPU interrupt mask register, Address offset: 0x08 */
699+
__IO uint32_t CNSLCKR; /*!< SYSCFG CPU non-secure lock register, Address offset: 0x0C */
700+
__IO uint32_t CSLCKR; /*!< SYSCFG CPU secure lock register, Address offset: 0x10 */
701+
__IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x14 */
702+
__IO uint32_t MESR; /*!< SYSCFG Memory Erase Status register, Address offset: 0x18 */
703+
__IO uint32_t CCCSR; /*!< SYSCFG Conpensaion Cell Control&Status register, Address offset: 0x1C */
704+
__IO uint32_t CCVR; /*!< SYSCFG Conpensaion Cell value register, Address offset: 0x20 */
705+
__IO uint32_t CCCR; /*!< SYSCFG Conpensaion Cell Code register, Address offset: 0x24 */
706+
uint32_t RESERVED1; /*!< RESERVED1, Address offset: 0x28 */
707+
__IO uint32_t RSSCMDR; /*!< SYSCFG RSS command mode register, Address offset: 0x2C */
708708
} SYSCFG_TypeDef;
709709

710710
/**
@@ -4256,7 +4256,7 @@ typedef struct
42564256
#define I2C_CR1_ADDRACLR_Pos (30U)
42574257
#define I2C_CR1_ADDRACLR_Msk (0x1UL << I2C_CR1_ADDRACLR_Pos) /*!< 0x40000000 */
42584258
#define I2C_CR1_ADDRACLR I2C_CR1_ADDRACLR_Msk /*!< ADDRACLR enable */
4259-
#define I2C_CR1_STOPFACLR_Pos (30U)
4259+
#define I2C_CR1_STOPFACLR_Pos (31U)
42604260
#define I2C_CR1_STOPFACLR_Msk (0x1UL << I2C_CR1_STOPFACLR_Pos) /*!< 0x80000000 */
42614261
#define I2C_CR1_STOPFACLR I2C_CR1_STOPFACLR_Msk /*!< STOPFACLR enable */
42624262

@@ -4942,7 +4942,6 @@ typedef struct
49424942
#define LPTIM_CCR2_CCR2_Msk (0xFFFFUL << LPTIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
49434943
#define LPTIM_CCR2_CCR2 LPTIM_CCR2_CCR2_Msk /*!< Compare register 2 */
49444944

4945-
49464945
/******************************************************************************/
49474946
/* */
49484947
/* Public Key Accelerator (PKA) */
@@ -6669,6 +6668,9 @@ typedef struct
66696668
#define RNG_HTCR_HTCFG_Pos (0U)
66706669
#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */
66716670
#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk
6671+
/******************** RNG Nist Compliance Values *******************/
6672+
#define RNG_CR_NIST_VALUE (0x00F02D00U)
6673+
#define RNG_HTCR_NIST_VALUE (0xAAC7U)
66726674

66736675

66746676
/******************************************************************************/
@@ -10293,7 +10295,8 @@ typedef struct
1029310295

1029410296
/****************** TIM Instances : supporting OCxREF clear *******************/
1029510297
#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
10296-
((INSTANCE) == TIM2_NS))
10298+
((INSTANCE) == TIM2_NS) || \
10299+
((INSTANCE) == TIM16_NS))
1029710300

1029810301
/********* TIM Instances : supporting bitfield OCCS in SMCR register **********/
1029910302
#define IS_TIM_OCCS_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \

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