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system(G0) update STM32G0xx HAL Drivers to v1.4.4
Included in STM32CubeG0 FW v1.5.1 Signed-off-by: Alexandre Bourdiol <[email protected]>
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‎system/Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h

+168-12
Original file line numberDiff line numberDiff line change
@@ -7,13 +7,12 @@
77
******************************************************************************
88
* @attention
99
*
10-
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
11-
* All rights reserved.</center></h2>
10+
* Copyright (c) 2021 STMicroelectronics.
11+
* All rights reserved.
1212
*
13-
* This software component is licensed by ST under BSD 3-Clause license,
14-
* the "License"; You may not use this file except in compliance with the
15-
* License. You may obtain a copy of the License at:
16-
* opensource.org/licenses/BSD-3-Clause
13+
* This software is licensed under terms that can be found in the LICENSE file
14+
* in the root directory of this software component.
15+
* If no LICENSE file comes with this software, it is provided AS-IS.
1716
*
1817
******************************************************************************
1918
*/
@@ -105,6 +104,12 @@ extern "C" {
105104
#if defined(STM32H7)
106105
#define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT
107106
#endif /* STM32H7 */
107+
108+
#if defined(STM32U5)
109+
#define ADC_SAMPLETIME_5CYCLE ADC_SAMPLETIME_5CYCLES
110+
#define ADC_SAMPLETIME_391CYCLES_5 ADC_SAMPLETIME_391CYCLES
111+
#define ADC4_SAMPLETIME_160CYCLES_5 ADC4_SAMPLETIME_814CYCLES_5
112+
#endif /* STM32U5 */
108113
/**
109114
* @}
110115
*/
@@ -214,18 +219,21 @@ extern "C" {
214219
* @{
215220
*/
216221
#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
222+
#if defined(STM32U5)
223+
#define MPU_DEVICE_nGnRnE MPU_DEVICE_NGNRNE
224+
#define MPU_DEVICE_nGnRE MPU_DEVICE_NGNRE
225+
#define MPU_DEVICE_nGRE MPU_DEVICE_NGRE
226+
#endif /* STM32U5 */
217227
/**
218228
* @}
219229
*/
220230

221231
/** @defgroup CRC_Aliases CRC API aliases
222232
* @{
223233
*/
224-
#if defined(STM32WL) || defined(STM32WB) || defined(STM32L5) || defined(STM32L4)
225-
#else
226234
#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */
227235
#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */
228-
#endif
236+
229237
/**
230238
* @}
231239
*/
@@ -260,6 +268,13 @@ extern "C" {
260268
#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL
261269
#endif
262270

271+
#if defined(STM32U5)
272+
#define DAC_TRIGGER_STOP_LPTIM1_OUT DAC_TRIGGER_STOP_LPTIM1_CH1
273+
#define DAC_TRIGGER_STOP_LPTIM3_OUT DAC_TRIGGER_STOP_LPTIM3_CH1
274+
#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1
275+
#define DAC_TRIGGER_LPTIM3_OUT DAC_TRIGGER_LPTIM3_CH1
276+
#endif
277+
263278
#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4)
264279
#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID
265280
#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID
@@ -402,6 +417,10 @@ extern "C" {
402417
#define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT
403418

404419
#endif /* STM32H7 */
420+
421+
#if defined(STM32U5)
422+
#define GPDMA1_REQUEST_DCMI GPDMA1_REQUEST_DCMI_PSSI
423+
#endif /* STM32U5 */
405424
/**
406425
* @}
407426
*/
@@ -624,12 +643,12 @@ extern "C" {
624643
#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
625644
#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
626645

627-
#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB)
646+
#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5)
628647
#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
629648
#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
630649
#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
631650
#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
632-
#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB*/
651+
#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB || STM32U5*/
633652

634653
#if defined(STM32L1)
635654
#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
@@ -645,6 +664,24 @@ extern "C" {
645664
#endif /* STM32F0 || STM32F3 || STM32F1 */
646665

647666
#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1
667+
668+
#if defined(STM32U5)
669+
#define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ
670+
#endif /* STM32U5 */
671+
#if defined(STM32U5)
672+
#define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP
673+
#define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1
674+
#endif /* STM32U5 */
675+
/**
676+
* @}
677+
*/
678+
679+
/** @defgroup HAL_GTZC_Aliased_Defines HAL GTZC Aliased Defines maintained for legacy purpose
680+
* @{
681+
*/
682+
#if defined(STM32U5)
683+
#define GTZC_PERIPH_DCMI GTZC_PERIPH_DCMI_PSSI
684+
#endif /* STM32U5 */
648685
/**
649686
* @}
650687
*/
@@ -882,9 +919,19 @@ extern "C" {
882919
#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS
883920
#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS
884921

922+
923+
/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
924+
* @{
925+
*/
926+
#define HAL_LPTIM_ReadCompare HAL_LPTIM_ReadCapturedValue
927+
/**
928+
* @}
929+
*/
930+
885931
#if defined(STM32U5)
886932
#define LPTIM_ISR_CC1 LPTIM_ISR_CC1IF
887933
#define LPTIM_ISR_CC2 LPTIM_ISR_CC2IF
934+
#define LPTIM_CHANNEL_ALL 0x00000000U
888935
#endif /* STM32U5 */
889936
/**
890937
* @}
@@ -1224,6 +1271,10 @@ extern "C" {
12241271
#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2
12251272
#endif
12261273

1274+
#if defined(STM32U5) || defined(STM32MP2)
1275+
#define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS
1276+
#define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK
1277+
#endif
12271278
/**
12281279
* @}
12291280
*/
@@ -1440,6 +1491,19 @@ extern "C" {
14401491
* @{
14411492
*/
14421493
#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback
1494+
/**
1495+
* @}
1496+
*/
1497+
1498+
/** @defgroup HAL_DCACHE_Aliased_Functions HAL DCACHE Aliased Functions maintained for legacy purpose
1499+
* @{
1500+
*/
1501+
1502+
#if defined(STM32U5)
1503+
#define HAL_DCACHE_CleanInvalidateByAddr HAL_DCACHE_CleanInvalidByAddr
1504+
#define HAL_DCACHE_CleanInvalidateByAddr_IT HAL_DCACHE_CleanInvalidByAddr_IT
1505+
#endif /* STM32U5 */
1506+
14431507
/**
14441508
* @}
14451509
*/
@@ -1641,6 +1705,79 @@ extern "C" {
16411705

16421706
#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL
16431707

1708+
#if defined (STM32U5)
1709+
#define PWR_SRAM1_PAGE1_STOP_RETENTION PWR_SRAM1_PAGE1_STOP
1710+
#define PWR_SRAM1_PAGE2_STOP_RETENTION PWR_SRAM1_PAGE2_STOP
1711+
#define PWR_SRAM1_PAGE3_STOP_RETENTION PWR_SRAM1_PAGE3_STOP
1712+
#define PWR_SRAM1_PAGE4_STOP_RETENTION PWR_SRAM1_PAGE4_STOP
1713+
#define PWR_SRAM1_PAGE5_STOP_RETENTION PWR_SRAM1_PAGE5_STOP
1714+
#define PWR_SRAM1_PAGE6_STOP_RETENTION PWR_SRAM1_PAGE6_STOP
1715+
#define PWR_SRAM1_PAGE7_STOP_RETENTION PWR_SRAM1_PAGE7_STOP
1716+
#define PWR_SRAM1_PAGE8_STOP_RETENTION PWR_SRAM1_PAGE8_STOP
1717+
#define PWR_SRAM1_PAGE9_STOP_RETENTION PWR_SRAM1_PAGE9_STOP
1718+
#define PWR_SRAM1_PAGE10_STOP_RETENTION PWR_SRAM1_PAGE10_STOP
1719+
#define PWR_SRAM1_PAGE11_STOP_RETENTION PWR_SRAM1_PAGE11_STOP
1720+
#define PWR_SRAM1_PAGE12_STOP_RETENTION PWR_SRAM1_PAGE12_STOP
1721+
#define PWR_SRAM1_FULL_STOP_RETENTION PWR_SRAM1_FULL_STOP
1722+
1723+
#define PWR_SRAM2_PAGE1_STOP_RETENTION PWR_SRAM2_PAGE1_STOP
1724+
#define PWR_SRAM2_PAGE2_STOP_RETENTION PWR_SRAM2_PAGE2_STOP
1725+
#define PWR_SRAM2_FULL_STOP_RETENTION PWR_SRAM2_FULL_STOP
1726+
1727+
#define PWR_SRAM3_PAGE1_STOP_RETENTION PWR_SRAM3_PAGE1_STOP
1728+
#define PWR_SRAM3_PAGE2_STOP_RETENTION PWR_SRAM3_PAGE2_STOP
1729+
#define PWR_SRAM3_PAGE3_STOP_RETENTION PWR_SRAM3_PAGE3_STOP
1730+
#define PWR_SRAM3_PAGE4_STOP_RETENTION PWR_SRAM3_PAGE4_STOP
1731+
#define PWR_SRAM3_PAGE5_STOP_RETENTION PWR_SRAM3_PAGE5_STOP
1732+
#define PWR_SRAM3_PAGE6_STOP_RETENTION PWR_SRAM3_PAGE6_STOP
1733+
#define PWR_SRAM3_PAGE7_STOP_RETENTION PWR_SRAM3_PAGE7_STOP
1734+
#define PWR_SRAM3_PAGE8_STOP_RETENTION PWR_SRAM3_PAGE8_STOP
1735+
#define PWR_SRAM3_PAGE9_STOP_RETENTION PWR_SRAM3_PAGE9_STOP
1736+
#define PWR_SRAM3_PAGE10_STOP_RETENTION PWR_SRAM3_PAGE10_STOP
1737+
#define PWR_SRAM3_PAGE11_STOP_RETENTION PWR_SRAM3_PAGE11_STOP
1738+
#define PWR_SRAM3_PAGE12_STOP_RETENTION PWR_SRAM3_PAGE12_STOP
1739+
#define PWR_SRAM3_PAGE13_STOP_RETENTION PWR_SRAM3_PAGE13_STOP
1740+
#define PWR_SRAM3_FULL_STOP_RETENTION PWR_SRAM3_FULL_STOP
1741+
1742+
#define PWR_SRAM4_FULL_STOP_RETENTION PWR_SRAM4_FULL_STOP
1743+
1744+
#define PWR_SRAM5_PAGE1_STOP_RETENTION PWR_SRAM5_PAGE1_STOP
1745+
#define PWR_SRAM5_PAGE2_STOP_RETENTION PWR_SRAM5_PAGE2_STOP
1746+
#define PWR_SRAM5_PAGE3_STOP_RETENTION PWR_SRAM5_PAGE3_STOP
1747+
#define PWR_SRAM5_PAGE4_STOP_RETENTION PWR_SRAM5_PAGE4_STOP
1748+
#define PWR_SRAM5_PAGE5_STOP_RETENTION PWR_SRAM5_PAGE5_STOP
1749+
#define PWR_SRAM5_PAGE6_STOP_RETENTION PWR_SRAM5_PAGE6_STOP
1750+
#define PWR_SRAM5_PAGE7_STOP_RETENTION PWR_SRAM5_PAGE7_STOP
1751+
#define PWR_SRAM5_PAGE8_STOP_RETENTION PWR_SRAM5_PAGE8_STOP
1752+
#define PWR_SRAM5_PAGE9_STOP_RETENTION PWR_SRAM5_PAGE9_STOP
1753+
#define PWR_SRAM5_PAGE10_STOP_RETENTION PWR_SRAM5_PAGE10_STOP
1754+
#define PWR_SRAM5_PAGE11_STOP_RETENTION PWR_SRAM5_PAGE11_STOP
1755+
#define PWR_SRAM5_PAGE12_STOP_RETENTION PWR_SRAM5_PAGE12_STOP
1756+
#define PWR_SRAM5_PAGE13_STOP_RETENTION PWR_SRAM5_PAGE13_STOP
1757+
#define PWR_SRAM5_FULL_STOP_RETENTION PWR_SRAM5_FULL_STOP
1758+
1759+
#define PWR_ICACHE_FULL_STOP_RETENTION PWR_ICACHE_FULL_STOP
1760+
#define PWR_DCACHE1_FULL_STOP_RETENTION PWR_DCACHE1_FULL_STOP
1761+
#define PWR_DCACHE2_FULL_STOP_RETENTION PWR_DCACHE2_FULL_STOP
1762+
#define PWR_DMA2DRAM_FULL_STOP_RETENTION PWR_DMA2DRAM_FULL_STOP
1763+
#define PWR_PERIPHRAM_FULL_STOP_RETENTION PWR_PERIPHRAM_FULL_STOP
1764+
#define PWR_PKA32RAM_FULL_STOP_RETENTION PWR_PKA32RAM_FULL_STOP
1765+
#define PWR_GRAPHICPRAM_FULL_STOP_RETENTION PWR_GRAPHICPRAM_FULL_STOP
1766+
#define PWR_DSIRAM_FULL_STOP_RETENTION PWR_DSIRAM_FULL_STOP
1767+
1768+
#define PWR_SRAM2_PAGE1_STANDBY_RETENTION PWR_SRAM2_PAGE1_STANDBY
1769+
#define PWR_SRAM2_PAGE2_STANDBY_RETENTION PWR_SRAM2_PAGE2_STANDBY
1770+
#define PWR_SRAM2_FULL_STANDBY_RETENTION PWR_SRAM2_FULL_STANDBY
1771+
1772+
#define PWR_SRAM1_FULL_RUN_RETENTION PWR_SRAM1_FULL_RUN
1773+
#define PWR_SRAM2_FULL_RUN_RETENTION PWR_SRAM2_FULL_RUN
1774+
#define PWR_SRAM3_FULL_RUN_RETENTION PWR_SRAM3_FULL_RUN
1775+
#define PWR_SRAM4_FULL_RUN_RETENTION PWR_SRAM4_FULL_RUN
1776+
#define PWR_SRAM5_FULL_RUN_RETENTION PWR_SRAM5_FULL_RUN
1777+
1778+
#define PWR_ALL_RAM_RUN_RETENTION_MASK PWR_ALL_RAM_RUN_MASK
1779+
#endif
1780+
16441781
/**
16451782
* @}
16461783
*/
@@ -3399,7 +3536,22 @@ extern "C" {
33993536
#define __HAL_RCC_APB2_CLK_Disable_Clear __HAL_RCC_APB2_CLK_ENABLE
34003537
#define __HAL_RCC_APB3_CLK_Disable_Clear __HAL_RCC_APB3_CLK_ENABLE
34013538
#define IS_RCC_MSIPLLModeSelection IS_RCC_MSIPLLMODE_SELECT
3539+
#define RCC_PERIPHCLK_CLK48 RCC_PERIPHCLK_ICLK
3540+
#define RCC_CLK48CLKSOURCE_HSI48 RCC_ICLK_CLKSOURCE_HSI48
3541+
#define RCC_CLK48CLKSOURCE_PLL2 RCC_ICLK_CLKSOURCE_PLL2
3542+
#define RCC_CLK48CLKSOURCE_PLL1 RCC_ICLK_CLKSOURCE_PLL1
3543+
#define RCC_CLK48CLKSOURCE_MSIK RCC_ICLK_CLKSOURCE_MSIK
3544+
#define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
3545+
#define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
3546+
#define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
3547+
#define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
3548+
#define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
3549+
#define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
3550+
#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC12_CLK_SLEEP_ENABLE
3551+
#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC12_CLK_SLEEP_DISABLE
3552+
#define __HAL_RCC_GET_CLK48_SOURCE __HAL_RCC_GET_ICLK_SOURCE
34023553
#endif
3554+
34033555
/**
34043556
* @}
34053557
*/
@@ -3480,10 +3632,15 @@ extern "C" {
34803632
#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
34813633
#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
34823634

3635+
#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32L1)
34833636
#define eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE
34843637
#define eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE
34853638
#define eMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE
34863639

3640+
#define SDMMC_NSpeed_CLK_DIV SDMMC_NSPEED_CLK_DIV
3641+
#define SDMMC_HSpeed_CLK_DIV SDMMC_HSPEED_CLK_DIV
3642+
#endif
3643+
34873644
#if defined(STM32F4) || defined(STM32F2)
34883645
#define SD_SDMMC_DISABLED SD_SDIO_DISABLED
34893646
#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY
@@ -3826,5 +3983,4 @@ extern "C" {
38263983

38273984
#endif /* STM32_HAL_LEGACY */
38283985

3829-
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
38303986

‎system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32_assert_template.h

+5-7
Original file line numberDiff line numberDiff line change
@@ -8,13 +8,12 @@
88
******************************************************************************
99
* @attention
1010
*
11-
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
12-
* All rights reserved.</center></h2>
11+
* Copyright (c) 2018 STMicroelectronics.
12+
* All rights reserved.
1313
*
14-
* This software component is licensed by ST under BSD 3-Clause license,
15-
* the "License"; You may not use this file except in compliance with the
16-
* License. You may obtain a copy of the License at:
17-
* opensource.org/licenses/BSD-3-Clause
14+
* This software is licensed under terms that can be found in the LICENSE file
15+
* in the root directory of this software component.
16+
* If no LICENSE file comes with this software, it is provided AS-IS.
1817
*
1918
******************************************************************************
2019
*/
@@ -54,4 +53,3 @@ void assert_failed(uint8_t *file, uint32_t line);
5453
#endif /* STM32_ASSERT_H */
5554

5655

57-
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

‎system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h

+5-7
Original file line numberDiff line numberDiff line change
@@ -7,13 +7,12 @@
77
******************************************************************************
88
* @attention
99
*
10-
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
11-
* All rights reserved.</center></h2>
10+
* Copyright (c) 2018 STMicroelectronics.
11+
* All rights reserved.
1212
*
13-
* This software component is licensed by ST under BSD 3-Clause license,
14-
* the "License"; You may not use this file except in compliance with the
15-
* License. You may obtain a copy of the License at:
16-
* opensource.org/licenses/BSD-3-Clause
13+
* This software is licensed under terms that can be found in the LICENSE file
14+
* in the root directory of this software component.
15+
* If no LICENSE file comes with this software, it is provided AS-IS.
1716
*
1817
******************************************************************************
1918
*/
@@ -836,4 +835,3 @@ void HAL_SYSCFG_StrobeDBattpinsConfig(uint32_t ConfigDeadBattery);
836835

837836
#endif /* STM32G0xx_HAL_H */
838837

839-
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

‎system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_adc.h

+5-8
Original file line numberDiff line numberDiff line change
@@ -6,13 +6,12 @@
66
******************************************************************************
77
* @attention
88
*
9-
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
10-
* All rights reserved.</center></h2>
9+
* Copyright (c) 2018 STMicroelectronics.
10+
* All rights reserved.
1111
*
12-
* This software component is licensed by ST under BSD 3-Clause license,
13-
* the "License"; You may not use this file except in compliance with the
14-
* License. You may obtain a copy of the License at:
15-
* opensource.org/licenses/BSD-3-Clause
12+
* This software is licensed under terms that can be found in the LICENSE file
13+
* in the root directory of this software component.
14+
* If no LICENSE file comes with this software, it is provided AS-IS.
1615
*
1716
******************************************************************************
1817
*/
@@ -1751,5 +1750,3 @@ HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc);
17511750

17521751

17531752
#endif /* STM32G0xx_HAL_ADC_H */
1754-
1755-
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

‎system/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_adc_ex.h

+5-9
Original file line numberDiff line numberDiff line change
@@ -6,13 +6,12 @@
66
******************************************************************************
77
* @attention
88
*
9-
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
10-
* All rights reserved.</center></h2>
9+
* Copyright (c) 2018 STMicroelectronics.
10+
* All rights reserved.
1111
*
12-
* This software component is licensed by ST under BSD 3-Clause license,
13-
* the "License"; You may not use this file except in compliance with the
14-
* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
@@ -184,6 +183,3 @@ HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *had
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#endif
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#endif /* STM32G0xx_HAL_ADC_EX_H */
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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