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Merge pull request #2526 from nedseb/main
variant(wb55): add STeaMi board
2 parents 511ed73 + 0847b47 commit c35b8ef

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Diff for: ‎README.md

+6
Original file line numberDiff line numberDiff line change
@@ -88,6 +88,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d
8888
- [Midatronics boards](#midatronics-boards)
8989
- [SparkFun boards](#sparkfun-boards)
9090
- [ELV Boards](#elv-boards)
91+
- [STeaMi board](#steami-board)
9192

9293
> [!Note]
9394
> - :green_heart: board support is available since the specified release version.
@@ -865,6 +866,11 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d
865866
| :----: | :-------: | ---- | :-----: | :---- |
866867
| :green_heart: | STM32WLE5JB | ELV-BM-TRX1 | *2.8.0* | |
867868

869+
### [STeaMi Board](https://www.steami.cc/)
870+
871+
| Status | Device(s) | Name | Release | Notes |
872+
| :----: | :-------: | ---- | :-----: | :---- |
873+
| :yellow_heart: | STM32WB55RGV | [STeaMi](https://www.steami.cc/) | **2.9.0** | |
868874
## Next release
869875

870876
See [milestones](https://github.com/stm32duino/Arduino_Core_STM32/milestones) to have an overview of the next release content.

Diff for: ‎boards.txt

+85
Original file line numberDiff line numberDiff line change
@@ -13630,6 +13630,47 @@ ELV_Modular_System.menu.upload_method.serialMethod.upload.protocol=serial
1363013630
ELV_Modular_System.menu.upload_method.serialMethod.upload.options=-c {serial.port.file}
1363113631
ELV_Modular_System.menu.upload_method.serialMethod.upload.tool=stm32CubeProg
1363213632

13633+
################################################################################
13634+
# STeaMi board
13635+
STeaMi.name=STeaMi Board
13636+
STeaMi.build.core=arduino
13637+
STeaMi.build.variant_h=variant_{build.board}.h
13638+
STeaMi.build.st_extra_flags=-D{build.product_line} {build.xSerial}
13639+
STeaMi.build.flash_offset=0x0
13640+
STeaMi.upload.maximum_size=0
13641+
STeaMi.upload.maximum_data_size=0
13642+
STeaMi.vid.0=0x0d28
13643+
STeaMi.pid.0=0x0204
13644+
13645+
STeaMi.menu.pnum.STEAM32_WB55RG=STeaMi
13646+
STeaMi.menu.pnum.STEAM32_WB55RG.node="STeaMi,DAPLINK"
13647+
STeaMi.menu.pnum.STEAM32_WB55RG.upload.maximum_size=524288
13648+
STeaMi.menu.pnum.STEAM32_WB55RG.upload.maximum_data_size=196608
13649+
STeaMi.menu.pnum.STEAM32_WB55RG.build.mcu=cortex-m4
13650+
STeaMi.menu.pnum.STEAM32_WB55RG.build.fpu=-mfpu=fpv4-sp-d16
13651+
STeaMi.menu.pnum.STEAM32_WB55RG.build.float-abi=-mfloat-abi=hard
13652+
STeaMi.menu.pnum.STEAM32_WB55RG.build.board=STEAM32_WB55RG
13653+
STeaMi.menu.pnum.STEAM32_WB55RG.build.series=STM32WBxx
13654+
STeaMi.menu.pnum.STEAM32_WB55RG.build.product_line=STM32WB55xx
13655+
STeaMi.menu.pnum.STEAM32_WB55RG.build.variant=STM32WBxx/WB55R(C-E-G)V
13656+
STeaMi.menu.pnum.STEAM32_WB55RG.debug.server.openocd.scripts.0=interface/cmsis-dap.cfg
13657+
STeaMi.menu.pnum.STEAM32_WB55RG.debug.server.openocd.scripts.1={runtime.platform.path}/debugger/select_swd.cfg
13658+
STeaMi.menu.pnum.STEAM32_WB55RG.openocd.target=stm32wbx
13659+
STeaMi.menu.pnum.STEAM32_WB55RG.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32WBxx/STM32WB55_CM4.svd
13660+
13661+
# Upload menu
13662+
STeaMi.menu.upload_method.MassStorage=Mass Storage
13663+
STeaMi.menu.upload_method.MassStorage.upload.protocol=
13664+
STeaMi.menu.upload_method.MassStorage.upload.tool=massStorageCopy
13665+
13666+
STeaMi.menu.upload_method.OpenOCDDapLink=OpenOCD DapLink (SWD)
13667+
STeaMi.menu.upload_method.OpenOCDDapLink.upload.protocol=cmsis-dap
13668+
STeaMi.menu.upload_method.OpenOCDDapLink.upload.tool=openocd_upload
13669+
13670+
STeaMi.menu.upload_method.OpenOCDSTLink=OpenOCD STLink (SWD)
13671+
STeaMi.menu.upload_method.OpenOCDSTLink.upload.protocol=stlink
13672+
STeaMi.menu.upload_method.OpenOCDSTLink.upload.tool=openocd_upload
13673+
1363313674
################################################################################
1363413675
# Serialx activation
1363513676
Nucleo_144.menu.xserial.generic=Enabled (generic 'Serial')
@@ -13862,6 +13903,12 @@ ELV_Modular_System.menu.xserial.none.build.xSerial=-DHAL_UART_MODULE_ENABLED -DH
1386213903
ELV_Modular_System.menu.xserial.disabled=Disabled (no Serial support)
1386313904
ELV_Modular_System.menu.xserial.disabled.build.xSerial=
1386413905

13906+
STeaMi.menu.xserial.generic=Enabled (generic 'Serial')
13907+
STeaMi.menu.xserial.none=Enabled (no generic 'Serial')
13908+
STeaMi.menu.xserial.none.build.xSerial=-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE
13909+
STeaMi.menu.xserial.disabled=Disabled (no Serial support)
13910+
STeaMi.menu.xserial.disabled.build.xSerial=
13911+
1386513912
# USB connectivity
1386613913
Nucleo_144.menu.usb.none=None
1386713914
Nucleo_144.menu.usb.CDCgen=CDC (generic 'Serial' supersede U(S)ART)
@@ -14961,6 +15008,26 @@ ELV_Modular_System.menu.opt.ogstd.build.flags.optimize=-Og
1496115008
ELV_Modular_System.menu.opt.o0std=No Optimization (-O0)
1496215009
ELV_Modular_System.menu.opt.o0std.build.flags.optimize=-O0
1496315010

15011+
STeaMi.menu.opt.osstd=Smallest (-Os default)
15012+
STeaMi.menu.opt.oslto=Smallest (-Os) with LTO
15013+
STeaMi.menu.opt.oslto.build.flags.optimize=-Os -flto
15014+
STeaMi.menu.opt.o1std=Fast (-O1)
15015+
STeaMi.menu.opt.o1std.build.flags.optimize=-O1
15016+
STeaMi.menu.opt.o1lto=Fast (-O1) with LTO
15017+
STeaMi.menu.opt.o1lto.build.flags.optimize=-O1 -flto
15018+
STeaMi.menu.opt.o2std=Faster (-O2)
15019+
STeaMi.menu.opt.o2std.build.flags.optimize=-O2
15020+
STeaMi.menu.opt.o2lto=Faster (-O2) with LTO
15021+
STeaMi.menu.opt.o2lto.build.flags.optimize=-O2 -flto
15022+
STeaMi.menu.opt.o3std=Fastest (-O3)
15023+
STeaMi.menu.opt.o3std.build.flags.optimize=-O3
15024+
STeaMi.menu.opt.o3lto=Fastest (-O3) with LTO
15025+
STeaMi.menu.opt.o3lto.build.flags.optimize=-O3 -flto
15026+
STeaMi.menu.opt.ogstd=Debug (-Og)
15027+
STeaMi.menu.opt.ogstd.build.flags.optimize=-Og
15028+
STeaMi.menu.opt.o0std=No Optimization (-O0)
15029+
STeaMi.menu.opt.o0std.build.flags.optimize=-O0
15030+
1496415031
# Debug information
1496515032
Nucleo_144.menu.dbg.none=None
1496615033
Nucleo_144.menu.dbg.enable_sym=Symbols Enabled (-g)
@@ -15254,6 +15321,14 @@ ELV_Modular_System.menu.dbg.enable_log.build.flags.debug=
1525415321
ELV_Modular_System.menu.dbg.enable_all=Core Logs and Symbols Enabled (-g)
1525515322
ELV_Modular_System.menu.dbg.enable_all.build.flags.debug=-g
1525615323

15324+
STeaMi.menu.dbg.none=None
15325+
STeaMi.menu.dbg.enable_sym=Symbols Enabled (-g)
15326+
STeaMi.menu.dbg.enable_sym.build.flags.debug=-g -DNDEBUG
15327+
STeaMi.menu.dbg.enable_log=Core logs Enabled
15328+
STeaMi.menu.dbg.enable_log.build.flags.debug=
15329+
STeaMi.menu.dbg.enable_all=Core Logs and Symbols Enabled (-g)
15330+
STeaMi.menu.dbg.enable_all.build.flags.debug=-g
15331+
1525715332
# C Runtime Library
1525815333
Nucleo_144.menu.rtlib.nano=Newlib Nano (default)
1525915334
Nucleo_144.menu.rtlib.nanofp=Newlib Nano + Float Printf
@@ -15624,3 +15699,13 @@ ELV_Modular_System.menu.rtlib.nanofps=Newlib Nano + Float Printf/Scanf
1562415699
ELV_Modular_System.menu.rtlib.nanofps.build.flags.ldspecs=--specs=nano.specs -u _printf_float -u _scanf_float
1562515700
ELV_Modular_System.menu.rtlib.full=Newlib Standard
1562615701
ELV_Modular_System.menu.rtlib.full.build.flags.ldspecs=
15702+
15703+
STeaMi.menu.rtlib.nano=Newlib Nano (default)
15704+
STeaMi.menu.rtlib.nanofp=Newlib Nano + Float Printf
15705+
STeaMi.menu.rtlib.nanofp.build.flags.ldspecs=--specs=nano.specs -u _printf_float
15706+
STeaMi.menu.rtlib.nanofs=Newlib Nano + Float Scanf
15707+
STeaMi.menu.rtlib.nanofs.build.flags.ldspecs=--specs=nano.specs -u _scanf_float
15708+
STeaMi.menu.rtlib.nanofps=Newlib Nano + Float Printf/Scanf
15709+
STeaMi.menu.rtlib.nanofps.build.flags.ldspecs=--specs=nano.specs -u _printf_float -u _scanf_float
15710+
STeaMi.menu.rtlib.full=Newlib Standard
15711+
STeaMi.menu.rtlib.full.build.flags.ldspecs=

Diff for: ‎cmake/boards_db.cmake

+54
Original file line numberDiff line numberDiff line change
@@ -108286,6 +108286,60 @@ target_compile_options(ST3DP001_EVAL_xusb_HSFS INTERFACE
108286108286
"SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
108287108287
)
108288108288

108289+
# STEAM32_WB55RG
108290+
# -----------------------------------------------------------------------------
108291+
108292+
set(STEAM32_WB55RG_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32WBxx/WB55R(C-E-G)V")
108293+
set(STEAM32_WB55RG_MAXSIZE 524288)
108294+
set(STEAM32_WB55RG_MAXDATASIZE 196608)
108295+
set(STEAM32_WB55RG_MCU cortex-m4)
108296+
set(STEAM32_WB55RG_FPCONF "fpv4-sp-d16-hard")
108297+
add_library(STEAM32_WB55RG INTERFACE)
108298+
target_compile_options(STEAM32_WB55RG INTERFACE
108299+
"SHELL:-DSTM32WB55xx "
108300+
"SHELL:"
108301+
"SHELL:"
108302+
"SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
108303+
-mcpu=${STEAM32_WB55RG_MCU}
108304+
)
108305+
target_compile_definitions(STEAM32_WB55RG INTERFACE
108306+
"STM32WBxx"
108307+
"ARDUINO_STEAM32_WB55RG"
108308+
"BOARD_NAME=\"STEAM32_WB55RG\""
108309+
"BOARD_ID=STEAM32_WB55RG"
108310+
"VARIANT_H=\"variant_STEAM32_WB55RG.h\""
108311+
)
108312+
target_include_directories(STEAM32_WB55RG INTERFACE
108313+
${CMAKE_CURRENT_LIST_DIR}/../system/STM32WBxx
108314+
${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WBxx_HAL_Driver/Inc
108315+
${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WBxx_HAL_Driver/Src
108316+
${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBxx/Include/
108317+
${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/
108318+
${STEAM32_WB55RG_VARIANT_PATH}
108319+
)
108320+
108321+
target_link_options(STEAM32_WB55RG INTERFACE
108322+
"LINKER:--default-script=${STEAM32_WB55RG_VARIANT_PATH}/ldscript.ld"
108323+
"LINKER:--defsym=LD_FLASH_OFFSET=0x0"
108324+
"LINKER:--defsym=LD_MAX_SIZE=524288"
108325+
"LINKER:--defsym=LD_MAX_DATA_SIZE=196608"
108326+
"SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
108327+
-mcpu=${STEAM32_WB55RG_MCU}
108328+
)
108329+
108330+
add_library(STEAM32_WB55RG_serial_disabled INTERFACE)
108331+
target_compile_options(STEAM32_WB55RG_serial_disabled INTERFACE
108332+
"SHELL:"
108333+
)
108334+
add_library(STEAM32_WB55RG_serial_generic INTERFACE)
108335+
target_compile_options(STEAM32_WB55RG_serial_generic INTERFACE
108336+
"SHELL:-DHAL_UART_MODULE_ENABLED"
108337+
)
108338+
add_library(STEAM32_WB55RG_serial_none INTERFACE)
108339+
target_compile_options(STEAM32_WB55RG_serial_none INTERFACE
108340+
"SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE"
108341+
)
108342+
108289108343
# STEVAL_MKBOXPRO
108290108344
# -----------------------------------------------------------------------------
108291108345

Diff for: ‎cmake/scripts/cmake_easy_setup.py

100644100755
File mode changed.

Diff for: ‎cmake/scripts/update_boarddb.py

+3-2
Original file line numberDiff line numberDiff line change
@@ -13,7 +13,7 @@ def get_fpconf(config):
1313

1414

1515
def boardstxt_filter(key):
16-
# Remove menu entry labels
16+
# Remove menu entry labels and oopenocd config if any
1717
# In our data model, they conflict with the actual configuration
1818
# they are associated to
1919
# i.e. Nucleo_144.menu.pnum.NUCLEO_F207ZG would be both
@@ -22,7 +22,8 @@ def boardstxt_filter(key):
2222

2323
if key[-1] == "svd_file":
2424
return True
25-
25+
if len(key) >= 5 and key[-2] == "scripts" and key[-3] == "openocd":
26+
return True
2627
if key[0] == "menu":
2728
# menu.xserial=U(S)ART support
2829
return True

Diff for: ‎debugger/select_swd.cfg

+9
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,9 @@
1+
transport select swd
2+
3+
set ENABLE_LOW_POWER 1
4+
set STOP_WATCHDOG 1
5+
set CLOCK_FREQ 4000
6+
7+
reset_config none separate
8+
9+
set CONNECT_UNDER_RESET 1

Diff for: ‎variants/STM32WBxx/WB55R(C-E-G)V/CMakeLists.txt

+1
Original file line numberDiff line numberDiff line change
@@ -23,6 +23,7 @@ add_library(variant_bin STATIC EXCLUDE_FROM_ALL
2323
PeripheralPins.c
2424
variant_generic.cpp
2525
variant_P_NUCLEO_WB55RG.cpp
26+
variant_STEAM32_WB55RG.cpp
2627
)
2728
target_link_libraries(variant_bin PUBLIC variant_usage)
2829

Diff for: ‎variants/STM32WBxx/WB55R(C-E-G)V/variant_STEAM32_WB55RG.cpp

+160
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,160 @@
1+
/*
2+
*******************************************************************************
3+
* Copyright (c) 2021, STMicroelectronics
4+
* All rights reserved.
5+
*
6+
* This software component is licensed by ST under BSD 3-Clause license,
7+
* the "License"; You may not use this file except in compliance with the
8+
* License. You may obtain a copy of the License at:
9+
* opensource.org/licenses/BSD-3-Clause
10+
*
11+
*******************************************************************************
12+
*/
13+
#include "variant_STEAM32_WB55RG.h"
14+
15+
#if defined(ARDUINO_STEAM32_WB55RG)
16+
#include "lock_resource.h"
17+
#include "pins_arduino.h"
18+
19+
// Pin number
20+
const PinName digitalPin[] = {
21+
PC_4, // P0/D0/A1
22+
PA_5, // P1/D1/A3
23+
PC_5, // P2/D2/A5
24+
PA_2, // P3/D3/A0
25+
PA_4, // P4/D4/A2
26+
PA_7, // P5/D5
27+
PC_3, // P6/D6
28+
PA_9, // P7/D7
29+
PA_15, // P8/D8
30+
PC_2, // P9/D9
31+
PA_6, // P10/D10/A4
32+
PA_8, // P11/D11
33+
PC_6, // P12/D12
34+
PB_13, // P13/D13
35+
PB_14, // P14/D14
36+
PB_15, // P15/D15
37+
PE_4, // P16/D16
38+
PC_0, // P19/D17
39+
PC_1, // P20/D18
40+
PB_2, // D19
41+
PD_0, // D20
42+
PB_8, // D21
43+
PB_9, // D22
44+
PC_13, // D23
45+
PB_12, // D24
46+
PB_0, // D25
47+
PD_1, // D26
48+
PB_6, // D27
49+
PB_7, // D28
50+
PC_10, // D29
51+
PH_3, // D30
52+
PC_11, // D31
53+
PC_12, // D32
54+
PA_0, // D33
55+
PA_3, // D34
56+
PA_10, // D35
57+
PA_12, // D36
58+
PB_1, // D37
59+
PB_10, // D38
60+
PB_11, // D39
61+
PA_11, // D40
62+
PB_4, // D41
63+
PB_5, // D42
64+
PA_1, // D43
65+
};
66+
67+
// Analog (Ax) pin number array
68+
const uint32_t analogInputPin[] = {
69+
3, // A0
70+
0, // A1
71+
4, // A2
72+
1, // A3
73+
10, // A4
74+
2 // A5
75+
};
76+
77+
// ----------------------------------------------------------------------------
78+
#ifdef __cplusplus
79+
extern "C" {
80+
#endif
81+
82+
/**
83+
* @brief System Clock Configuration
84+
* @param None
85+
* @retval None
86+
*/
87+
WEAK void SystemClock_Config(void)
88+
{
89+
RCC_OscInitTypeDef RCC_OscInitStruct = {};
90+
RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
91+
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {};
92+
93+
/* This prevents concurrent access to RCC registers by CPU2 (M0+) */
94+
hsem_lock(CFG_HW_RCC_SEMID, HSEM_LOCK_DEFAULT_RETRY);
95+
96+
__HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
97+
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
98+
99+
/* This prevents the CPU2 (M0+) to disable the HSI48 oscillator */
100+
hsem_lock(CFG_HW_CLK48_CONFIG_SEMID, HSEM_LOCK_DEFAULT_RETRY);
101+
102+
/* Initializes the CPU, AHB and APB busses clocks */
103+
RCC_OscInitStruct.OscillatorType =
104+
RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_LSE;
105+
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
106+
RCC_OscInitStruct.LSEState = RCC_LSE_ON;
107+
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
108+
RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
109+
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
110+
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
111+
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
112+
RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV2;
113+
RCC_OscInitStruct.PLL.PLLN = 16;
114+
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
115+
RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
116+
RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
117+
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
118+
Error_Handler();
119+
}
120+
121+
/* Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers */
122+
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4 | RCC_CLOCKTYPE_HCLK2 | RCC_CLOCKTYPE_HCLK |
123+
RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
124+
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSE;
125+
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
126+
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
127+
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
128+
RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV1;
129+
RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
130+
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
131+
Error_Handler();
132+
}
133+
134+
/* Initializes the peripherals clocks */
135+
/* RNG needs to be configured like in M0 core, i.e. with HSI48 */
136+
PeriphClkInitStruct.PeriphClockSelection =
137+
RCC_PERIPHCLK_SMPS | RCC_PERIPHCLK_RFWAKEUP | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_USB;
138+
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
139+
PeriphClkInitStruct.RngClockSelection = RCC_RNGCLKSOURCE_HSI48;
140+
PeriphClkInitStruct.RFWakeUpClockSelection = RCC_RFWKPCLKSOURCE_LSE;
141+
PeriphClkInitStruct.SmpsClockSelection = RCC_SMPSCLKSOURCE_HSE;
142+
PeriphClkInitStruct.SmpsDivSelection = RCC_SMPSCLKDIV_RANGE1;
143+
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
144+
Error_Handler();
145+
}
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LL_PWR_SMPS_SetStartupCurrent(LL_PWR_SMPS_STARTUP_CURRENT_80MA);
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LL_PWR_SMPS_SetOutputVoltageLevel(LL_PWR_SMPS_OUTPUT_VOLTAGE_1V40);
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LL_PWR_SMPS_Enable();
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/* Select HSI as system clock source after Wake Up from Stop mode */
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LL_RCC_SetClkAfterWakeFromStop(LL_RCC_STOP_WAKEUPCLOCK_HSI);
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hsem_unlock(CFG_HW_RCC_SEMID);
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}
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#ifdef __cplusplus
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}
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#endif
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#endif /* ARDUINO_STEAM32_WB55RG */

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