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2 | 2 | ******************************************************************************
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3 | 3 | * @file stm32_hal_legacy.h
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4 | 4 | * @author MCD Application Team
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5 |
| - * @version V1.4.0 |
6 |
| - * @date 16-December-2016 |
7 | 5 | * @brief This file contains aliases definition for the STM32Cube HAL constants
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8 | 6 | * macros and functions maintained for legacy purpose.
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9 | 7 | ******************************************************************************
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10 | 8 | * @attention
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11 | 9 | *
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12 |
| - * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
| 10 | + * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
13 | 11 | *
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14 | 12 | * Redistribution and use in source and binary forms, with or without modification,
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15 | 13 | * are permitted provided that the following conditions are met:
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382 | 380 | /** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
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383 | 381 | * @{
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384 | 382 | */
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385 |
| -#if defined(STM32L4) || defined(STM32F7) |
| 383 | +#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) |
386 | 384 | #define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE
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387 | 385 | #define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE
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388 | 386 | #define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8
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946 | 944 | #define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
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947 | 945 | #define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */
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948 | 946 | #define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */
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949 |
| -#if defined(STM32F1) |
950 |
| -#else |
951 | 947 | #define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */
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952 | 948 | #define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */
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953 | 949 | #define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */
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954 |
| -#endif |
955 | 950 | #define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */
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956 | 951 | #define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */
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957 | 952 | #define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */
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980 | 975 | * @}
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981 | 976 | */
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982 | 977 |
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983 |
| -#if defined(STM32L4xx) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\ |
| 978 | +#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\ |
984 | 979 | defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
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985 | 980 | /** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
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986 | 981 | * @{
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1005 | 1000 | /**
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1006 | 1001 | * @}
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1007 | 1002 | */
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1008 |
| -#endif /* STM32L4xx || STM32F7*/ |
| 1003 | +#endif /* STM32L4 || STM32F7*/ |
1009 | 1004 |
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1010 | 1005 | /** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
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1011 | 1006 | * @{
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1190 | 1185 | * @{
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1191 | 1186 | */
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1192 | 1187 | #define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback
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| 1188 | +#define HAL_LTDC_Relaod HAL_LTDC_Reload |
| 1189 | +#define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig |
| 1190 | +#define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig |
1193 | 1191 | /**
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1194 | 1192 | * @}
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1195 | 1193 | */
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1625 | 1623 |
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1626 | 1624 | #define __HAL_I2C_RESET_CR2 I2C_RESET_CR2
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1627 | 1625 | #define __HAL_I2C_GENERATE_START I2C_GENERATE_START
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| 1626 | +#if defined(STM32F1) |
| 1627 | +#define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE |
| 1628 | +#else |
1628 | 1629 | #define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE
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| 1630 | +#endif /* STM32F1 */ |
1629 | 1631 | #define __HAL_I2C_RISE_TIME I2C_RISE_TIME
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1630 | 1632 | #define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD
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1631 | 1633 | #define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST
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2792 | 2794 | #define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1
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2793 | 2795 | #define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1
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2794 | 2796 | #define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1
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| 2797 | + |
| 2798 | +#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1 |
| 2799 | +#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2 |
| 2800 | +#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1 |
| 2801 | +#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2 |
| 2802 | +#define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2 |
| 2803 | +#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2 |
| 2804 | +#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1 |
| 2805 | + |
2795 | 2806 | /**
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2796 | 2807 | * @}
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2797 | 2808 | */
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2921 | 2932 | #define SDIO_IRQn SDMMC1_IRQn
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2922 | 2933 | #define SDIO_IRQHandler SDMMC1_IRQHandler
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2923 | 2934 | #endif
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| 2935 | + |
| 2936 | +#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) |
| 2937 | +#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef |
| 2938 | +#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef |
| 2939 | +#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef |
| 2940 | +#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef |
| 2941 | +#endif |
| 2942 | + |
2924 | 2943 | /**
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2925 | 2944 | * @}
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2926 | 2945 | */
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3109 | 3128 | * @{
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3110 | 3129 | */
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3111 | 3130 | #define __HAL_LTDC_LAYER LTDC_LAYER
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| 3131 | +#define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG |
3112 | 3132 | /**
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3113 | 3133 | * @}
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3114 | 3134 | */
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