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MitkoDyakovfpistm
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variant: L4: add generic L433C(B-C)(T-U) and L443CC(T-U)
Note: SRAM split into 2 blocks. Anyway SRAM2 is also mapped at the end of SRAM1 offering a contiguous address space with the SRAM1. Signed-off-by: Frederic Pillon <[email protected]> Co-authored-by: MitkoDyakov <[email protected]>
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README.md

+3
Original file line numberDiff line numberDiff line change
@@ -374,6 +374,9 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d
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| :----: | :-------: | ---- | :-----: | :---- |
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| :green_heart: | STM32L412K8<br>STM32L412KB<br>STM32L422KB | Generic Board | *2.0.0* | |
376376
| :green_heart: | STM32L432KB<br>STM32L432KC<br>STM32L442KC | Generic Board | *2.0.0* | |
377+
| :yellow_heart: | STM32L433CBT<br>STM32L433CCT | Generic Board | **2.1.0** | |
378+
| :yellow_heart: | STM32L433CBU<br>STM32L433CCU | Generic Board | **2.1.0** | |
379+
| :yellow_heart: | STM32L443CC<br>STM32L443CC | Generic Board | **2.1.0** | |
377380
| :green_heart: | STM32L433RC-P | Generic Board | *2.0.0* | |
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| :green_heart: | STM32L452RC<br>STM32L452RE<br>STM32L462RE | Generic Board | *2.0.0* | |
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| :green_heart: | STM32L452RE-P | Generic Board | *2.0.0* | |

boards.txt

+48
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@@ -4589,6 +4589,38 @@ GenL4.menu.pnum.GENERIC_L442KCUX.build.board=GENERIC_L442KCUX
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GenL4.menu.pnum.GENERIC_L442KCUX.build.product_line=STM32L442xx
45904590
GenL4.menu.pnum.GENERIC_L442KCUX.build.variant=STM32L4xx/L432K(B-C)U_L442KCU
45914591

4592+
# Generic L433CBTx
4593+
GenL4.menu.pnum.GENERIC_L433CBTX=Generic L433CBTx
4594+
GenL4.menu.pnum.GENERIC_L433CBTX.upload.maximum_size=131072
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GenL4.menu.pnum.GENERIC_L433CBTX.upload.maximum_data_size=65536
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GenL4.menu.pnum.GENERIC_L433CBTX.build.board=GENERIC_L433CBTX
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GenL4.menu.pnum.GENERIC_L433CBTX.build.product_line=STM32L433xx
4598+
GenL4.menu.pnum.GENERIC_L433CBTX.build.variant=STM32L4xx/L433C(B-C)(T-U)_L443CC(T-U)
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4600+
# Generic L433CCTx
4601+
GenL4.menu.pnum.GENERIC_L433CCTX=Generic L433CCTx
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GenL4.menu.pnum.GENERIC_L433CCTX.upload.maximum_size=262144
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GenL4.menu.pnum.GENERIC_L433CCTX.upload.maximum_data_size=65536
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GenL4.menu.pnum.GENERIC_L433CCTX.build.board=GENERIC_L433CCTX
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GenL4.menu.pnum.GENERIC_L433CCTX.build.product_line=STM32L433xx
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GenL4.menu.pnum.GENERIC_L433CCTX.build.variant=STM32L4xx/L433C(B-C)(T-U)_L443CC(T-U)
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4608+
# Generic L433CBUx
4609+
GenL4.menu.pnum.GENERIC_L433CBUX=Generic L433CBUx
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GenL4.menu.pnum.GENERIC_L433CBUX.upload.maximum_size=131072
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GenL4.menu.pnum.GENERIC_L433CBUX.upload.maximum_data_size=65536
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GenL4.menu.pnum.GENERIC_L433CBUX.build.board=GENERIC_L433CBUX
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GenL4.menu.pnum.GENERIC_L433CBUX.build.product_line=STM32L433xx
4614+
GenL4.menu.pnum.GENERIC_L433CBUX.build.variant=STM32L4xx/L433C(B-C)(T-U)_L443CC(T-U)
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# Generic L433CCUx
4617+
GenL4.menu.pnum.GENERIC_L433CCUX=Generic L433CCUx
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GenL4.menu.pnum.GENERIC_L433CCUX.upload.maximum_size=262144
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GenL4.menu.pnum.GENERIC_L433CCUX.upload.maximum_data_size=65536
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GenL4.menu.pnum.GENERIC_L433CCUX.build.board=GENERIC_L433CCUX
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GenL4.menu.pnum.GENERIC_L433CCUX.build.product_line=STM32L433xx
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GenL4.menu.pnum.GENERIC_L433CCUX.build.variant=STM32L4xx/L433C(B-C)(T-U)_L443CC(T-U)
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45924624
# Generic L433RCTxP
45934625
GenL4.menu.pnum.GENERIC_L433RCTXP=Generic L433RCTxP
45944626
GenL4.menu.pnum.GENERIC_L433RCTXP.upload.maximum_size=262144
@@ -4597,6 +4629,22 @@ GenL4.menu.pnum.GENERIC_L433RCTXP.build.board=GENERIC_L433RCTXP
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GenL4.menu.pnum.GENERIC_L433RCTXP.build.product_line=STM32L433xx
45984630
GenL4.menu.pnum.GENERIC_L433RCTXP.build.variant=STM32L4xx/L433RCTxP
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4632+
# Generic L443CCTx
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GenL4.menu.pnum.GENERIC_L443CCTX=Generic L443CCTx
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GenL4.menu.pnum.GENERIC_L443CCTX.upload.maximum_size=262144
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GenL4.menu.pnum.GENERIC_L443CCTX.upload.maximum_data_size=65536
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GenL4.menu.pnum.GENERIC_L443CCTX.build.board=GENERIC_L443CCTX
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GenL4.menu.pnum.GENERIC_L443CCTX.build.product_line=STM32L443xx
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GenL4.menu.pnum.GENERIC_L443CCTX.build.variant=STM32L4xx/L433C(B-C)(T-U)_L443CC(T-U)
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4640+
# Generic L443CCUx
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GenL4.menu.pnum.GENERIC_L443CCUX=Generic L443CCUx
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GenL4.menu.pnum.GENERIC_L443CCUX.upload.maximum_size=262144
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GenL4.menu.pnum.GENERIC_L443CCUX.upload.maximum_data_size=65536
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GenL4.menu.pnum.GENERIC_L443CCUX.build.board=GENERIC_L443CCUX
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GenL4.menu.pnum.GENERIC_L443CCUX.build.product_line=STM32L443xx
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GenL4.menu.pnum.GENERIC_L443CCUX.build.variant=STM32L4xx/L433C(B-C)(T-U)_L443CC(T-U)
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46004648
# Generic L452RCIx
46014649
GenL4.menu.pnum.GENERIC_L452RCIX=Generic L452RCIx
46024650
GenL4.menu.pnum.GENERIC_L452RCIX.upload.maximum_size=262144

variants/STM32L4xx/L433C(B-C)(T-U)_L443CC(T-U)/generic_clock.c

+51-2
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@@ -22,8 +22,57 @@
2222
*/
2323
WEAK void SystemClock_Config(void)
2424
{
25-
/* SystemClock_Config can be generated by STM32CubeMX */
26-
#warning "SystemClock_Config() is empty. Default clock at reset is used."
25+
RCC_OscInitTypeDef RCC_OscInitStruct = {};
26+
RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
27+
RCC_PeriphCLKInitTypeDef PeriphClkInit = {};
28+
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/** Configure the main internal regulator output voltage
30+
*/
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if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK) {
32+
Error_Handler();
33+
}
34+
/** Initializes the RCC Oscillators according to the specified parameters
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* in the RCC_OscInitTypeDef structure.
36+
*/
37+
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
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RCC_OscInitStruct.MSIState = RCC_MSI_ON;
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RCC_OscInitStruct.MSICalibrationValue = 0;
40+
RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
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RCC_OscInitStruct.PLL.PLLM = 1;
44+
RCC_OscInitStruct.PLL.PLLN = 40;
45+
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV7;
46+
RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
47+
RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
48+
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
49+
Error_Handler();
50+
}
51+
/** Initializes the CPU, AHB and APB buses clocks
52+
*/
53+
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
54+
| RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
55+
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
56+
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
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RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
59+
60+
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
61+
Error_Handler();
62+
}
63+
64+
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
65+
PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
66+
PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_MSI;
67+
PeriphClkInit.PLLSAI1.PLLSAI1M = 1;
68+
PeriphClkInit.PLLSAI1.PLLSAI1N = 24;
69+
PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
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PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
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PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
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PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
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if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) {
74+
Error_Handler();
75+
}
2776
}
2877

2978
#endif /* ARDUINO_GENERIC_* */
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@@ -0,0 +1,187 @@
1+
/*
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******************************************************************************
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**
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** @file : ldscript.ld
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**
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** @author : Auto-generated by STM32CubeIDE
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**
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** @brief : Linker script for STM32L433CCUx Device from STM32L4 series
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** 256Kbytes FLASH
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** 48Kbytes RAM
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** 16Kbytes RAM2
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**
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** Set heap size, stack size and stack location according
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** to application requirements.
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**
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** Set memory bank area and size if external memory is used
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**
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** Target : STMicroelectronics STM32
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**
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** Distribution: The file is distributed as is, without any warranty
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** of any kind.
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**
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******************************************************************************
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** @attention
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**
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** <h2><center>&copy; Copyright (c) 2021 STMicroelectronics.
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** All rights reserved.</center></h2>
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**
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** This software component is licensed by ST under BSD 3-Clause license,
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** the "License"; You may not use this file except in compliance with the
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** License. You may obtain a copy of the License at:
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** opensource.org/licenses/BSD-3-Clause
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**
34+
******************************************************************************
35+
*/
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37+
/* Entry Point */
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ENTRY(Reset_Handler)
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40+
/* Highest address of the user mode stack */
41+
_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
42+
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_Min_Heap_Size = 0x200; /* required amount of heap */
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_Min_Stack_Size = 0x400; /* required amount of stack */
45+
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/* Memories definition */
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MEMORY
48+
{
49+
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = LD_MAX_DATA_SIZE
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FLASH (rx) : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
51+
}
52+
53+
/* Sections */
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SECTIONS
55+
{
56+
/* The startup code into "FLASH" Rom type memory */
57+
.isr_vector :
58+
{
59+
. = ALIGN(4);
60+
KEEP(*(.isr_vector)) /* Startup code */
61+
. = ALIGN(4);
62+
} >FLASH
63+
64+
/* The program code and other data into "FLASH" Rom type memory */
65+
.text :
66+
{
67+
. = ALIGN(4);
68+
*(.text) /* .text sections (code) */
69+
*(.text*) /* .text* sections (code) */
70+
*(.glue_7) /* glue arm to thumb code */
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*(.glue_7t) /* glue thumb to arm code */
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*(.eh_frame)
73+
74+
KEEP (*(.init))
75+
KEEP (*(.fini))
76+
77+
. = ALIGN(4);
78+
_etext = .; /* define a global symbols at end of code */
79+
} >FLASH
80+
81+
/* Constant data into "FLASH" Rom type memory */
82+
.rodata :
83+
{
84+
. = ALIGN(4);
85+
*(.rodata) /* .rodata sections (constants, strings, etc.) */
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*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
87+
. = ALIGN(4);
88+
} >FLASH
89+
90+
.ARM.extab : {
91+
. = ALIGN(4);
92+
*(.ARM.extab* .gnu.linkonce.armextab.*)
93+
. = ALIGN(4);
94+
} >FLASH
95+
96+
.ARM : {
97+
. = ALIGN(4);
98+
__exidx_start = .;
99+
*(.ARM.exidx*)
100+
__exidx_end = .;
101+
. = ALIGN(4);
102+
} >FLASH
103+
104+
.preinit_array :
105+
{
106+
. = ALIGN(4);
107+
PROVIDE_HIDDEN (__preinit_array_start = .);
108+
KEEP (*(.preinit_array*))
109+
PROVIDE_HIDDEN (__preinit_array_end = .);
110+
. = ALIGN(4);
111+
} >FLASH
112+
113+
.init_array :
114+
{
115+
. = ALIGN(4);
116+
PROVIDE_HIDDEN (__init_array_start = .);
117+
KEEP (*(SORT(.init_array.*)))
118+
KEEP (*(.init_array*))
119+
PROVIDE_HIDDEN (__init_array_end = .);
120+
. = ALIGN(4);
121+
} >FLASH
122+
123+
.fini_array :
124+
{
125+
. = ALIGN(4);
126+
PROVIDE_HIDDEN (__fini_array_start = .);
127+
KEEP (*(SORT(.fini_array.*)))
128+
KEEP (*(.fini_array*))
129+
PROVIDE_HIDDEN (__fini_array_end = .);
130+
. = ALIGN(4);
131+
} >FLASH
132+
133+
/* Used by the startup to initialize data */
134+
_sidata = LOADADDR(.data);
135+
136+
/* Initialized data sections into "RAM" Ram type memory */
137+
.data :
138+
{
139+
. = ALIGN(4);
140+
_sdata = .; /* create a global symbol at data start */
141+
*(.data) /* .data sections */
142+
*(.data*) /* .data* sections */
143+
*(.RamFunc) /* .RamFunc sections */
144+
*(.RamFunc*) /* .RamFunc* sections */
145+
146+
. = ALIGN(4);
147+
_edata = .; /* define a global symbol at data end */
148+
149+
} >RAM AT> FLASH
150+
151+
/* Uninitialized data section into "RAM" Ram type memory */
152+
. = ALIGN(4);
153+
.bss :
154+
{
155+
/* This is used by the startup in order to initialize the .bss section */
156+
_sbss = .; /* define a global symbol at bss start */
157+
__bss_start__ = _sbss;
158+
*(.bss)
159+
*(.bss*)
160+
*(COMMON)
161+
162+
. = ALIGN(4);
163+
_ebss = .; /* define a global symbol at bss end */
164+
__bss_end__ = _ebss;
165+
} >RAM
166+
167+
/* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
168+
._user_heap_stack :
169+
{
170+
. = ALIGN(8);
171+
PROVIDE ( end = . );
172+
PROVIDE ( _end = . );
173+
. = . + _Min_Heap_Size;
174+
. = . + _Min_Stack_Size;
175+
. = ALIGN(8);
176+
} >RAM
177+
178+
/* Remove information from the compiler libraries */
179+
/DISCARD/ :
180+
{
181+
libc.a ( * )
182+
libm.a ( * )
183+
libgcc.a ( * )
184+
}
185+
186+
.ARM.attributes 0 : { *(.ARM.attributes) }
187+
}

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