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fpistmfpistm
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system(MP1) update STM32MP1xx HAL Drivers to v1.6.0
Included in STM32CubeMP1 FW 1.6.0 Signed-off-by: Frederic Pillon <[email protected]>
1 parent 3381c7f commit b01e483

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51 files changed

+2539
-1686
lines changed

Diff for: ‎system/Drivers/STM32MP1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h

+144-16
Original file line numberDiff line numberDiff line change
@@ -37,14 +37,16 @@ extern "C" {
3737
#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
3838
#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
3939
#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
40-
#if defined(STM32U5)
40+
#if defined(STM32U5) || defined(STM32H7) || defined(STM32MP1)
4141
#define CRYP_DATATYPE_32B CRYP_NO_SWAP
4242
#define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP
4343
#define CRYP_DATATYPE_8B CRYP_BYTE_SWAP
4444
#define CRYP_DATATYPE_1B CRYP_BIT_SWAP
45+
#if defined(STM32U5)
4546
#define CRYP_CCF_CLEAR CRYP_CLEAR_CCF
4647
#define CRYP_ERR_CLEAR CRYP_CLEAR_RWEIF
4748
#endif /* STM32U5 */
49+
#endif /* STM32U5 || STM32H7 || STM32MP1 */
4850
/**
4951
* @}
5052
*/
@@ -104,6 +106,12 @@ extern "C" {
104106
#if defined(STM32H7)
105107
#define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT
106108
#endif /* STM32H7 */
109+
110+
#if defined(STM32U5)
111+
#define ADC_SAMPLETIME_5CYCLE ADC_SAMPLETIME_5CYCLES
112+
#define ADC_SAMPLETIME_391CYCLES_5 ADC_SAMPLETIME_391CYCLES
113+
#define ADC4_SAMPLETIME_160CYCLES_5 ADC4_SAMPLETIME_814CYCLES_5
114+
#endif /* STM32U5 */
107115
/**
108116
* @}
109117
*/
@@ -411,6 +419,10 @@ extern "C" {
411419
#define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT
412420

413421
#endif /* STM32H7 */
422+
423+
#if defined(STM32U5)
424+
#define GPDMA1_REQUEST_DCMI GPDMA1_REQUEST_DCMI_PSSI
425+
#endif /* STM32U5 */
414426
/**
415427
* @}
416428
*/
@@ -658,6 +670,20 @@ extern "C" {
658670
#if defined(STM32U5)
659671
#define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ
660672
#endif /* STM32U5 */
673+
#if defined(STM32U5)
674+
#define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP
675+
#define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1
676+
#endif /* STM32U5 */
677+
/**
678+
* @}
679+
*/
680+
681+
/** @defgroup HAL_GTZC_Aliased_Defines HAL GTZC Aliased Defines maintained for legacy purpose
682+
* @{
683+
*/
684+
#if defined(STM32U5)
685+
#define GTZC_PERIPH_DCMI GTZC_PERIPH_DCMI_PSSI
686+
#endif /* STM32U5 */
661687
/**
662688
* @}
663689
*/
@@ -895,9 +921,19 @@ extern "C" {
895921
#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS
896922
#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS
897923

924+
925+
/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
926+
* @{
927+
*/
928+
#define HAL_LPTIM_ReadCompare HAL_LPTIM_ReadCapturedValue
929+
/**
930+
* @}
931+
*/
932+
898933
#if defined(STM32U5)
899934
#define LPTIM_ISR_CC1 LPTIM_ISR_CC1IF
900935
#define LPTIM_ISR_CC2 LPTIM_ISR_CC2IF
936+
#define LPTIM_CHANNEL_ALL 0x00000000U
901937
#endif /* STM32U5 */
902938
/**
903939
* @}
@@ -1050,8 +1086,8 @@ extern "C" {
10501086
#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
10511087

10521088
#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT
1053-
#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
1054-
#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
1089+
#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
1090+
#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
10551091
#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2
10561092

10571093
#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE
@@ -1062,15 +1098,22 @@ extern "C" {
10621098
#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
10631099
#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
10641100

1101+
#if defined(STM32F7)
1102+
#define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK
1103+
#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_IT_ENABLE_BITS_MASK
1104+
#endif /* STM32F7 */
1105+
10651106
#if defined(STM32H7)
10661107
#define RTC_TAMPCR_TAMPXE RTC_TAMPER_X
10671108
#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT
1109+
#endif /* STM32H7 */
10681110

1111+
#if defined(STM32F7) || defined(STM32H7)
10691112
#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1
10701113
#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2
10711114
#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3
1072-
#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMPALL
1073-
#endif /* STM32H7 */
1115+
#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP
1116+
#endif /* STM32F7 || STM32H7 */
10741117

10751118
/**
10761119
* @}
@@ -1237,6 +1280,10 @@ extern "C" {
12371280
#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2
12381281
#endif
12391282

1283+
#if defined(STM32U5) || defined(STM32MP2)
1284+
#define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS
1285+
#define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK
1286+
#endif
12401287
/**
12411288
* @}
12421289
*/
@@ -1667,6 +1714,79 @@ extern "C" {
16671714

16681715
#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL
16691716

1717+
#if defined (STM32U5)
1718+
#define PWR_SRAM1_PAGE1_STOP_RETENTION PWR_SRAM1_PAGE1_STOP
1719+
#define PWR_SRAM1_PAGE2_STOP_RETENTION PWR_SRAM1_PAGE2_STOP
1720+
#define PWR_SRAM1_PAGE3_STOP_RETENTION PWR_SRAM1_PAGE3_STOP
1721+
#define PWR_SRAM1_PAGE4_STOP_RETENTION PWR_SRAM1_PAGE4_STOP
1722+
#define PWR_SRAM1_PAGE5_STOP_RETENTION PWR_SRAM1_PAGE5_STOP
1723+
#define PWR_SRAM1_PAGE6_STOP_RETENTION PWR_SRAM1_PAGE6_STOP
1724+
#define PWR_SRAM1_PAGE7_STOP_RETENTION PWR_SRAM1_PAGE7_STOP
1725+
#define PWR_SRAM1_PAGE8_STOP_RETENTION PWR_SRAM1_PAGE8_STOP
1726+
#define PWR_SRAM1_PAGE9_STOP_RETENTION PWR_SRAM1_PAGE9_STOP
1727+
#define PWR_SRAM1_PAGE10_STOP_RETENTION PWR_SRAM1_PAGE10_STOP
1728+
#define PWR_SRAM1_PAGE11_STOP_RETENTION PWR_SRAM1_PAGE11_STOP
1729+
#define PWR_SRAM1_PAGE12_STOP_RETENTION PWR_SRAM1_PAGE12_STOP
1730+
#define PWR_SRAM1_FULL_STOP_RETENTION PWR_SRAM1_FULL_STOP
1731+
1732+
#define PWR_SRAM2_PAGE1_STOP_RETENTION PWR_SRAM2_PAGE1_STOP
1733+
#define PWR_SRAM2_PAGE2_STOP_RETENTION PWR_SRAM2_PAGE2_STOP
1734+
#define PWR_SRAM2_FULL_STOP_RETENTION PWR_SRAM2_FULL_STOP
1735+
1736+
#define PWR_SRAM3_PAGE1_STOP_RETENTION PWR_SRAM3_PAGE1_STOP
1737+
#define PWR_SRAM3_PAGE2_STOP_RETENTION PWR_SRAM3_PAGE2_STOP
1738+
#define PWR_SRAM3_PAGE3_STOP_RETENTION PWR_SRAM3_PAGE3_STOP
1739+
#define PWR_SRAM3_PAGE4_STOP_RETENTION PWR_SRAM3_PAGE4_STOP
1740+
#define PWR_SRAM3_PAGE5_STOP_RETENTION PWR_SRAM3_PAGE5_STOP
1741+
#define PWR_SRAM3_PAGE6_STOP_RETENTION PWR_SRAM3_PAGE6_STOP
1742+
#define PWR_SRAM3_PAGE7_STOP_RETENTION PWR_SRAM3_PAGE7_STOP
1743+
#define PWR_SRAM3_PAGE8_STOP_RETENTION PWR_SRAM3_PAGE8_STOP
1744+
#define PWR_SRAM3_PAGE9_STOP_RETENTION PWR_SRAM3_PAGE9_STOP
1745+
#define PWR_SRAM3_PAGE10_STOP_RETENTION PWR_SRAM3_PAGE10_STOP
1746+
#define PWR_SRAM3_PAGE11_STOP_RETENTION PWR_SRAM3_PAGE11_STOP
1747+
#define PWR_SRAM3_PAGE12_STOP_RETENTION PWR_SRAM3_PAGE12_STOP
1748+
#define PWR_SRAM3_PAGE13_STOP_RETENTION PWR_SRAM3_PAGE13_STOP
1749+
#define PWR_SRAM3_FULL_STOP_RETENTION PWR_SRAM3_FULL_STOP
1750+
1751+
#define PWR_SRAM4_FULL_STOP_RETENTION PWR_SRAM4_FULL_STOP
1752+
1753+
#define PWR_SRAM5_PAGE1_STOP_RETENTION PWR_SRAM5_PAGE1_STOP
1754+
#define PWR_SRAM5_PAGE2_STOP_RETENTION PWR_SRAM5_PAGE2_STOP
1755+
#define PWR_SRAM5_PAGE3_STOP_RETENTION PWR_SRAM5_PAGE3_STOP
1756+
#define PWR_SRAM5_PAGE4_STOP_RETENTION PWR_SRAM5_PAGE4_STOP
1757+
#define PWR_SRAM5_PAGE5_STOP_RETENTION PWR_SRAM5_PAGE5_STOP
1758+
#define PWR_SRAM5_PAGE6_STOP_RETENTION PWR_SRAM5_PAGE6_STOP
1759+
#define PWR_SRAM5_PAGE7_STOP_RETENTION PWR_SRAM5_PAGE7_STOP
1760+
#define PWR_SRAM5_PAGE8_STOP_RETENTION PWR_SRAM5_PAGE8_STOP
1761+
#define PWR_SRAM5_PAGE9_STOP_RETENTION PWR_SRAM5_PAGE9_STOP
1762+
#define PWR_SRAM5_PAGE10_STOP_RETENTION PWR_SRAM5_PAGE10_STOP
1763+
#define PWR_SRAM5_PAGE11_STOP_RETENTION PWR_SRAM5_PAGE11_STOP
1764+
#define PWR_SRAM5_PAGE12_STOP_RETENTION PWR_SRAM5_PAGE12_STOP
1765+
#define PWR_SRAM5_PAGE13_STOP_RETENTION PWR_SRAM5_PAGE13_STOP
1766+
#define PWR_SRAM5_FULL_STOP_RETENTION PWR_SRAM5_FULL_STOP
1767+
1768+
#define PWR_ICACHE_FULL_STOP_RETENTION PWR_ICACHE_FULL_STOP
1769+
#define PWR_DCACHE1_FULL_STOP_RETENTION PWR_DCACHE1_FULL_STOP
1770+
#define PWR_DCACHE2_FULL_STOP_RETENTION PWR_DCACHE2_FULL_STOP
1771+
#define PWR_DMA2DRAM_FULL_STOP_RETENTION PWR_DMA2DRAM_FULL_STOP
1772+
#define PWR_PERIPHRAM_FULL_STOP_RETENTION PWR_PERIPHRAM_FULL_STOP
1773+
#define PWR_PKA32RAM_FULL_STOP_RETENTION PWR_PKA32RAM_FULL_STOP
1774+
#define PWR_GRAPHICPRAM_FULL_STOP_RETENTION PWR_GRAPHICPRAM_FULL_STOP
1775+
#define PWR_DSIRAM_FULL_STOP_RETENTION PWR_DSIRAM_FULL_STOP
1776+
1777+
#define PWR_SRAM2_PAGE1_STANDBY_RETENTION PWR_SRAM2_PAGE1_STANDBY
1778+
#define PWR_SRAM2_PAGE2_STANDBY_RETENTION PWR_SRAM2_PAGE2_STANDBY
1779+
#define PWR_SRAM2_FULL_STANDBY_RETENTION PWR_SRAM2_FULL_STANDBY
1780+
1781+
#define PWR_SRAM1_FULL_RUN_RETENTION PWR_SRAM1_FULL_RUN
1782+
#define PWR_SRAM2_FULL_RUN_RETENTION PWR_SRAM2_FULL_RUN
1783+
#define PWR_SRAM3_FULL_RUN_RETENTION PWR_SRAM3_FULL_RUN
1784+
#define PWR_SRAM4_FULL_RUN_RETENTION PWR_SRAM4_FULL_RUN
1785+
#define PWR_SRAM5_FULL_RUN_RETENTION PWR_SRAM5_FULL_RUN
1786+
1787+
#define PWR_ALL_RAM_RUN_RETENTION_MASK PWR_ALL_RAM_RUN_MASK
1788+
#endif
1789+
16701790
/**
16711791
* @}
16721792
*/
@@ -3413,8 +3533,8 @@ extern "C" {
34133533
#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2
34143534
#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1
34153535
#if defined(STM32U5)
3416-
#define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL
3417-
#define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL
3536+
#define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL
3537+
#define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL
34183538
#define __HAL_RCC_AHB21_CLK_DISABLE __HAL_RCC_AHB2_1_CLK_DISABLE
34193539
#define __HAL_RCC_AHB22_CLK_DISABLE __HAL_RCC_AHB2_2_CLK_DISABLE
34203540
#define __HAL_RCC_AHB1_CLK_Disable_Clear __HAL_RCC_AHB1_CLK_ENABLE
@@ -3430,13 +3550,20 @@ extern "C" {
34303550
#define RCC_CLK48CLKSOURCE_PLL2 RCC_ICLK_CLKSOURCE_PLL2
34313551
#define RCC_CLK48CLKSOURCE_PLL1 RCC_ICLK_CLKSOURCE_PLL1
34323552
#define RCC_CLK48CLKSOURCE_MSIK RCC_ICLK_CLKSOURCE_MSIK
3433-
#define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
3434-
#define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
3435-
#define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
3436-
#define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
3437-
#define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
3438-
#define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
3439-
#endif
3553+
#define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
3554+
#define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
3555+
#define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
3556+
#define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
3557+
#define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
3558+
#define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
3559+
#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC12_CLK_SLEEP_ENABLE
3560+
#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC12_CLK_SLEEP_DISABLE
3561+
#define __HAL_RCC_GET_CLK48_SOURCE __HAL_RCC_GET_ICLK_SOURCE
3562+
#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE
3563+
#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE
3564+
#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG
3565+
#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE
3566+
#endif /* STM32U5 */
34403567

34413568
/**
34423569
* @}
@@ -3454,7 +3581,8 @@ extern "C" {
34543581
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
34553582
* @{
34563583
*/
3457-
#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5)
3584+
#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx)|| \
3585+
defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5)
34583586
#else
34593587
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
34603588
#endif
@@ -3518,7 +3646,7 @@ extern "C" {
35183646
#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
35193647
#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
35203648

3521-
#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32L1)
3649+
#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32L1)
35223650
#define eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE
35233651
#define eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE
35243652
#define eMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE

Diff for: ‎system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal.h

+3
Original file line numberDiff line numberDiff line change
@@ -751,6 +751,9 @@ void HAL_ResumeTick(void);
751751
uint32_t HAL_GetHalVersion(void);
752752
uint32_t HAL_GetREVID(void);
753753
uint32_t HAL_GetDEVID(void);
754+
uint32_t HAL_GetUIDw0(void);
755+
uint32_t HAL_GetUIDw1(void);
756+
uint32_t HAL_GetUIDw2(void);
754757
void HAL_SYSCFG_ETHInterfaceSelect(uint32_t SYSCFG_ETHInterface);
755758
void HAL_SYSCFG_AnalogSwitchConfig(uint32_t SYSCFG_AnalogSwitch , uint32_t SYSCFG_SwitchState );
756759
void HAL_SYSCFG_EnableBOOST(void);

Diff for: ‎system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_adc.h

+2-2
Original file line numberDiff line numberDiff line change
@@ -1752,8 +1752,8 @@ void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
17521752
* @{
17531753
*/
17541754
/* Peripheral Control functions ***********************************************/
1755-
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig);
1756-
HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig);
1755+
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *pConfig);
1756+
HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *pAnalogWDGConfig);
17571757

17581758
/**
17591759
* @}

Diff for: ‎system/Drivers/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_adc_ex.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -1082,7 +1082,7 @@ HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc);
10821082
HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc,
10831083
ADC_InjectionConfTypeDef *sConfigInjected);
10841084
#if defined(ADC_MULTIMODE_SUPPORT)
1085-
HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode);
1085+
HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *pmultimode);
10861086
#endif /* ADC_MULTIMODE_SUPPORT */
10871087
HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef *hadc);
10881088
HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef *hadc);

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