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alextrical
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variant(G4): add some missing generic
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36 files changed

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-57
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36 files changed

+4555
-57
lines changed

Diff for: ‎README.md

+39
Original file line numberDiff line numberDiff line change
@@ -402,18 +402,57 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d
402402

403403
| Status | Device(s) | Name | Release | Notes |
404404
| :----: | :-------: | ---- | :-----: | :---- |
405+
| :yellow_heart: | STM32G431C6<br>STM32G431C8<br>STM32G431CB | Generic Board | **2.4.0** | |
405406
| :green_heart: | STM32G431C6U<br>STM32G431C8U<br>STM32G431CBU | Generic Board | *2.0.0* | |
407+
| :yellow_heart: | STM32G431M6<br>STM32G431M8<br>STM32G431MB | Generic Board | **2.4.0** | |
408+
| :yellow_heart: | STM32G431V6<br>STM32G431V8<br>STM32G431VB | Generic Board | **2.4.0** | |
409+
| :yellow_heart: | STM32G441CB | Generic Board | **2.4.0** | |
406410
| :green_heart: | STM32G441CBU | Generic Board | *2.0.0* | |
411+
| :yellow_heart: | STM32G441MB | Generic Board | **2.4.0** | |
412+
| :yellow_heart: | STM32G441VB | Generic Board | **2.4.0** | |
407413
| :green_heart: | STM32G431K6<br>STM32G431K8<br>STM32G431KB | Generic Board | *2.0.0* | |
408414
| :green_heart: | STM32G441KB | Generic Board | *2.0.0* | |
409415
| :green_heart: | STM32G431R6<br>STM32G431R8<br>STM32G431RB | Generic Board | *2.0.0* | |
410416
| :green_heart: | STM32G441RB | Generic Board | *2.0.0* | |
417+
| :yellow_heart: | STM32G471CC<br>STM32G471CE | Generic Board | **2.4.0** | |
418+
| :yellow_heart: | STM32G471MC<br>STM32G471ME | Generic Board | **2.4.0** | |
419+
| :yellow_heart: | STM32G471QC<br>STM32G471QE | Generic Board | **2.4.0** | |
420+
| :yellow_heart: | STM32G471RC<br>STM32G471RE | Generic Board | **2.4.0** | |
421+
| :yellow_heart: | STM32G471VC<br>STM32G471VE | Generic Board | **2.4.0** | |
422+
| :yellow_heart: | STM32G473CB<br>STM32G473CC<br>STM32G473CE | Generic Board | **2.4.0** | |
423+
| :yellow_heart: | STM32G473MB<br>STM32G473MC<br>STM32G473ME | Generic Board | **2.4.0** | |
424+
| :yellow_heart: | STM32G473PB<br>STM32G473PC<br>STM32G473PE | Generic Board | **2.4.0** | |
425+
| :yellow_heart: | STM32G473QB<br>STM32G473QC<br>STM32G473QE | Generic Board | **2.4.0** | |
411426
| :green_heart: | STM32G473RB<br>STM32G473RC<br>STM32G473RE | Generic Board | *2.0.0* | |
427+
| :yellow_heart: | STM32G473VB<br>STM32G473VC<br>STM32G473VE | Generic Board | **2.4.0** | |
428+
| :yellow_heart: | STM32G474CB<br>STM32G474CC<br>STM32G474CE | Generic Board | **2.4.0** | |
429+
| :yellow_heart: | STM32G474MB<br>STM32G474MC<br>STM32G474ME | Generic Board | **2.4.0** | |
430+
| :yellow_heart: | STM32G474PB<br>STM32G474PC<br>STM32G474PE | Generic Board | **2.4.0** | |
431+
| :yellow_heart: | STM32G474QB<br>STM32G474QC<br>STM32G474QE | Generic Board | **2.4.0** | |
412432
| :green_heart: | STM32G474RB<br>STM32G474RC<br>STM32G474RE | Generic Board | *2.0.0* | |
433+
| :yellow_heart: | STM32G474VB<br>STM32G474VC<br>STM32G474VE | Generic Board | **2.4.0** | |
434+
| :yellow_heart: | STM32G483CE | Generic Board | **2.4.0** | |
435+
| :yellow_heart: | STM32G483ME | Generic Board | **2.4.0** | |
436+
| :yellow_heart: | STM32G483PE | Generic Board | **2.4.0** | |
437+
| :yellow_heart: | STM32G483QE | Generic Board | **2.4.0** | |
413438
| :green_heart: | STM32G483RE | Generic Board | *2.0.0* | |
439+
| :yellow_heart: | STM32G483VE | Generic Board | **2.4.0** | |
440+
| :yellow_heart: | STM32G484CE | Generic Board | **2.4.0** | |
441+
| :yellow_heart: | STM32G484ME | Generic Board | **2.4.0** | |
442+
| :yellow_heart: | STM32G484PE | Generic Board | **2.4.0** | |
443+
| :yellow_heart: | STM32G484QE | Generic Board | **2.4.0** | |
414444
| :green_heart: | STM32G484RE | Generic Board | *2.0.0* | |
445+
| :yellow_heart: | STM32G484VE | Generic Board | **2.4.0** | |
446+
| :yellow_heart: | STM32G491CC<br>STM32G491CE | Generic Board | **2.4.0** | |
447+
| :yellow_heart: | STM32G491KC<br>STM32G491KE | Generic Board | **2.4.0** | |
448+
| :yellow_heart: | STM32G491MC<br>STM32G491ME | Generic Board | **2.4.0** | |
415449
| :green_heart: | STM32G491RC<br>STM32G491RE | Generic Board | *2.3.0* | |
450+
| :yellow_heart: | STM32G491VC<br>STM32G491VE | Generic Board | **2.4.0** | |
451+
| :yellow_heart: | STM32G4A1CE | Generic Board | **2.4.0** | |
452+
| :yellow_heart: | STM32G4A1KE | Generic Board | **2.4.0** | |
453+
| :yellow_heart: | STM32G4A1ME | Generic Board | **2.4.0** | |
416454
| :green_heart: | STM32G4A1RE | Generic Board | *2.3.0* | |
455+
| :yellow_heart: | STM32G4A1VE | Generic Board | **2.4.0** | |
417456

418457
### Generic STM32H7 boards
419458

Diff for: ‎boards.txt

+742-23
Large diffs are not rendered by default.

Diff for: ‎variants/STM32G4xx/G431C(6-8-B)T_G441CBT/generic_clock.c

+37-2
Original file line numberDiff line numberDiff line change
@@ -21,8 +21,43 @@
2121
*/
2222
WEAK void SystemClock_Config(void)
2323
{
24-
/* SystemClock_Config can be generated by STM32CubeMX */
25-
#warning "SystemClock_Config() is empty. Default clock at reset is used."
24+
RCC_OscInitTypeDef RCC_OscInitStruct = {};
25+
RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
26+
27+
/** Configure the main internal regulator output voltage
28+
*/
29+
HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
30+
31+
/** Initializes the RCC Oscillators according to the specified parameters
32+
* in the RCC_OscInitTypeDef structure.
33+
*/
34+
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
35+
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
36+
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
37+
RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
38+
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
39+
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
40+
RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV4;
41+
RCC_OscInitStruct.PLL.PLLN = 75;
42+
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
43+
RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
44+
RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
45+
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
46+
Error_Handler();
47+
}
48+
49+
/** Initializes the CPU, AHB and APB buses clocks
50+
*/
51+
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
52+
| RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
53+
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
54+
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
55+
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
56+
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
57+
58+
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
59+
Error_Handler();
60+
}
2661
}
2762

2863
#endif /* ARDUINO_GENERIC_* */

Diff for: ‎variants/STM32G4xx/G431C(6-8-B)T_G441CBT/ldscript.ld

+185
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,185 @@
1+
/*
2+
******************************************************************************
3+
**
4+
** @file : LinkerScript.ld
5+
**
6+
** @author : Auto-generated by STM32CubeIDE
7+
**
8+
** @brief : Linker script for STM32G431C6Tx Device from STM32G4 series
9+
** 32Kbytes FLASH
10+
** 32Kbytes RAM
11+
**
12+
** Set heap size, stack size and stack location according
13+
** to application requirements.
14+
**
15+
** Set memory bank area and size if external memory is used
16+
**
17+
** Target : STMicroelectronics STM32
18+
**
19+
** Distribution: The file is distributed as is, without any warranty
20+
** of any kind.
21+
**
22+
******************************************************************************
23+
** @attention
24+
**
25+
** Copyright (c) 2022 STMicroelectronics.
26+
** All rights reserved.
27+
**
28+
** This software is licensed under terms that can be found in the LICENSE file
29+
** in the root directory of this software component.
30+
** If no LICENSE file comes with this software, it is provided AS-IS.
31+
**
32+
******************************************************************************
33+
*/
34+
35+
/* Entry Point */
36+
ENTRY(Reset_Handler)
37+
38+
/* Highest address of the user mode stack */
39+
_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
40+
41+
_Min_Heap_Size = 0x200; /* required amount of heap */
42+
_Min_Stack_Size = 0x400; /* required amount of stack */
43+
44+
/* Memories definition */
45+
MEMORY
46+
{
47+
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = LD_MAX_DATA_SIZE
48+
FLASH (rx) : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
49+
}
50+
51+
/* Sections */
52+
SECTIONS
53+
{
54+
/* The startup code into "FLASH" Rom type memory */
55+
.isr_vector :
56+
{
57+
. = ALIGN(4);
58+
KEEP(*(.isr_vector)) /* Startup code */
59+
. = ALIGN(4);
60+
} >FLASH
61+
62+
/* The program code and other data into "FLASH" Rom type memory */
63+
.text :
64+
{
65+
. = ALIGN(4);
66+
*(.text) /* .text sections (code) */
67+
*(.text*) /* .text* sections (code) */
68+
*(.glue_7) /* glue arm to thumb code */
69+
*(.glue_7t) /* glue thumb to arm code */
70+
*(.eh_frame)
71+
72+
KEEP (*(.init))
73+
KEEP (*(.fini))
74+
75+
. = ALIGN(4);
76+
_etext = .; /* define a global symbols at end of code */
77+
} >FLASH
78+
79+
/* Constant data into "FLASH" Rom type memory */
80+
.rodata :
81+
{
82+
. = ALIGN(4);
83+
*(.rodata) /* .rodata sections (constants, strings, etc.) */
84+
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
85+
. = ALIGN(4);
86+
} >FLASH
87+
88+
.ARM.extab : {
89+
. = ALIGN(4);
90+
*(.ARM.extab* .gnu.linkonce.armextab.*)
91+
. = ALIGN(4);
92+
} >FLASH
93+
94+
.ARM : {
95+
. = ALIGN(4);
96+
__exidx_start = .;
97+
*(.ARM.exidx*)
98+
__exidx_end = .;
99+
. = ALIGN(4);
100+
} >FLASH
101+
102+
.preinit_array :
103+
{
104+
. = ALIGN(4);
105+
PROVIDE_HIDDEN (__preinit_array_start = .);
106+
KEEP (*(.preinit_array*))
107+
PROVIDE_HIDDEN (__preinit_array_end = .);
108+
. = ALIGN(4);
109+
} >FLASH
110+
111+
.init_array :
112+
{
113+
. = ALIGN(4);
114+
PROVIDE_HIDDEN (__init_array_start = .);
115+
KEEP (*(SORT(.init_array.*)))
116+
KEEP (*(.init_array*))
117+
PROVIDE_HIDDEN (__init_array_end = .);
118+
. = ALIGN(4);
119+
} >FLASH
120+
121+
.fini_array :
122+
{
123+
. = ALIGN(4);
124+
PROVIDE_HIDDEN (__fini_array_start = .);
125+
KEEP (*(SORT(.fini_array.*)))
126+
KEEP (*(.fini_array*))
127+
PROVIDE_HIDDEN (__fini_array_end = .);
128+
. = ALIGN(4);
129+
} >FLASH
130+
131+
/* Used by the startup to initialize data */
132+
_sidata = LOADADDR(.data);
133+
134+
/* Initialized data sections into "RAM" Ram type memory */
135+
.data :
136+
{
137+
. = ALIGN(4);
138+
_sdata = .; /* create a global symbol at data start */
139+
*(.data) /* .data sections */
140+
*(.data*) /* .data* sections */
141+
*(.RamFunc) /* .RamFunc sections */
142+
*(.RamFunc*) /* .RamFunc* sections */
143+
144+
. = ALIGN(4);
145+
_edata = .; /* define a global symbol at data end */
146+
147+
} >RAM AT> FLASH
148+
149+
/* Uninitialized data section into "RAM" Ram type memory */
150+
. = ALIGN(4);
151+
.bss :
152+
{
153+
/* This is used by the startup in order to initialize the .bss section */
154+
_sbss = .; /* define a global symbol at bss start */
155+
__bss_start__ = _sbss;
156+
*(.bss)
157+
*(.bss*)
158+
*(COMMON)
159+
160+
. = ALIGN(4);
161+
_ebss = .; /* define a global symbol at bss end */
162+
__bss_end__ = _ebss;
163+
} >RAM
164+
165+
/* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
166+
._user_heap_stack :
167+
{
168+
. = ALIGN(8);
169+
PROVIDE ( end = . );
170+
PROVIDE ( _end = . );
171+
. = . + _Min_Heap_Size;
172+
. = . + _Min_Stack_Size;
173+
. = ALIGN(8);
174+
} >RAM
175+
176+
/* Remove information from the compiler libraries */
177+
/DISCARD/ :
178+
{
179+
libc.a ( * )
180+
libm.a ( * )
181+
libgcc.a ( * )
182+
}
183+
184+
.ARM.attributes 0 : { *(.ARM.attributes) }
185+
}

Diff for: ‎variants/STM32G4xx/G431M(6-8-B)T_G441MBT/generic_clock.c

+37-2
Original file line numberDiff line numberDiff line change
@@ -21,8 +21,43 @@
2121
*/
2222
WEAK void SystemClock_Config(void)
2323
{
24-
/* SystemClock_Config can be generated by STM32CubeMX */
25-
#warning "SystemClock_Config() is empty. Default clock at reset is used."
24+
RCC_OscInitTypeDef RCC_OscInitStruct = {};
25+
RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
26+
27+
/** Configure the main internal regulator output voltage
28+
*/
29+
HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
30+
31+
/** Initializes the RCC Oscillators according to the specified parameters
32+
* in the RCC_OscInitTypeDef structure.
33+
*/
34+
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
35+
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
36+
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
37+
RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
38+
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
39+
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
40+
RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV4;
41+
RCC_OscInitStruct.PLL.PLLN = 75;
42+
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
43+
RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
44+
RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
45+
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
46+
Error_Handler();
47+
}
48+
49+
/** Initializes the CPU, AHB and APB buses clocks
50+
*/
51+
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
52+
| RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
53+
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
54+
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
55+
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
56+
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
57+
58+
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
59+
Error_Handler();
60+
}
2661
}
2762

2863
#endif /* ARDUINO_GENERIC_* */

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