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committedMar 21, 2020
NUCLEO_F756ZG: Use HSE Bypass as PLL clock source
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‎variants/NUCLEO_F756ZG/variant.cpp

Lines changed: 6 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -151,14 +151,14 @@ extern "C" {
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/**
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* @brief System Clock Configuration
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* The system Clock is configured as follow :
154-
* System Clock source = PLL (HSI)
154+
* System Clock source = PLL (HSE)
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* SYSCLK(Hz) = 216000000
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* HCLK(Hz) = 216000000
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* AHB Prescaler = 1
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* APB1 Prescaler = 4
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* APB2 Prescaler = 2
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* HSE Frequency(Hz) = 16000000
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* PLL_M = 8
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* PLL_M = 4
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* PLL_N = 216
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* PLL_P = 2
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* PLL_Q = 9
@@ -182,12 +182,11 @@ WEAK void SystemClock_Config(void)
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__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
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/** Initializes the CPU, AHB and APB busses clocks
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*/
185-
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
186-
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
187-
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
185+
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
186+
RCC_OscInitStruct.HSEState = RCC_HSE_ON; //RCC_HSE_BYPASS;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
189-
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
190-
RCC_OscInitStruct.PLL.PLLM = 8;
188+
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
189+
RCC_OscInitStruct.PLL.PLLM = 4;
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RCC_OscInitStruct.PLL.PLLN = 216;
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RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
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RCC_OscInitStruct.PLL.PLLQ = 9;

‎variants/NUCLEO_F756ZG/variant.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -23,6 +23,8 @@
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extern "C" {
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#endif // __cplusplus
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26+
#define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
27+
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/*----------------------------------------------------------------------------
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* Pins
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*----------------------------------------------------------------------------*/

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