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variant: add STM32L433RC, STM32L433RB and STM32L443RC support (#2033)
* add STM32L433RC, STM32L433RB and STM32L443RC support Signed-off-by: Habibur Rahman <[email protected]> Co-authored-by: Frederic Pillon <[email protected]>
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Diff for: README.md

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Original file line numberDiff line numberDiff line change
@@ -641,6 +641,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d
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| :green_heart: | STM32L433CBT<br>STM32L433CCT | Generic Board | *2.1.0* | |
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| :green_heart: | STM32L433CBU<br>STM32L433CCU | Generic Board | *2.1.0* | |
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| :green_heart: | STM32L443CC<br>STM32L443CC | Generic Board | *2.1.0* | |
644+
| :yellow_heart: | STM32L433RC<br>STM32L443RC<br>STM32L433RB | Generic Board | **2.6.0** | |
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| :green_heart: | STM32L433RC-P | Generic Board | *2.0.0* | |
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| :green_heart: | STM32L452RC<br>STM32L452RE<br>STM32L462RE | Generic Board | *2.0.0* | |
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| :green_heart: | STM32L452RE | [Leafony AP03](https://docs.leafony.com/en/docs/leaf/processor/ap03) | *2.4.0* |

Diff for: boards.txt

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Original file line numberDiff line numberDiff line change
@@ -9239,6 +9239,78 @@ GenL4.menu.pnum.GENERIC_L433CCUX.build.board=GENERIC_L433CCUX
92399239
GenL4.menu.pnum.GENERIC_L433CCUX.build.product_line=STM32L433xx
92409240
GenL4.menu.pnum.GENERIC_L433CCUX.build.variant=STM32L4xx/L433C(B-C)(T-U)_L443CC(T-U)
92419241

9242+
# Generic L433RBIx
9243+
GenL4.menu.pnum.GENERIC_L433RBIX=Generic L433RBIx
9244+
GenL4.menu.pnum.GENERIC_L433RBIX.upload.maximum_size=131072
9245+
GenL4.menu.pnum.GENERIC_L433RBIX.upload.maximum_data_size=65536
9246+
GenL4.menu.pnum.GENERIC_L433RBIX.build.board=GENERIC_L433RBIX
9247+
GenL4.menu.pnum.GENERIC_L433RBIX.build.product_line=STM32L433xx
9248+
GenL4.menu.pnum.GENERIC_L433RBIX.build.variant=STM32L4xx/L433R(B-C)(I-T-Y)_L443RC(I-T-Y)
9249+
9250+
# Generic L433RCIx
9251+
GenL4.menu.pnum.GENERIC_L433RCIX=Generic L433RCIx
9252+
GenL4.menu.pnum.GENERIC_L433RCIX.upload.maximum_size=262144
9253+
GenL4.menu.pnum.GENERIC_L433RCIX.upload.maximum_data_size=65536
9254+
GenL4.menu.pnum.GENERIC_L433RCIX.build.board=GENERIC_L433RCIX
9255+
GenL4.menu.pnum.GENERIC_L433RCIX.build.product_line=STM32L433xx
9256+
GenL4.menu.pnum.GENERIC_L433RCIX.build.variant=STM32L4xx/L433R(B-C)(I-T-Y)_L443RC(I-T-Y)
9257+
9258+
# Generic L433RBTx
9259+
GenL4.menu.pnum.GENERIC_L433RBTX=Generic L433RBTx
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GenL4.menu.pnum.GENERIC_L433RBTX.upload.maximum_size=131072
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GenL4.menu.pnum.GENERIC_L433RBTX.upload.maximum_data_size=65536
9262+
GenL4.menu.pnum.GENERIC_L433RBTX.build.board=GENERIC_L433RBTX
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GenL4.menu.pnum.GENERIC_L433RBTX.build.product_line=STM32L433xx
9264+
GenL4.menu.pnum.GENERIC_L433RBTX.build.variant=STM32L4xx/L433R(B-C)(I-T-Y)_L443RC(I-T-Y)
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9266+
# Generic L433RCTx
9267+
GenL4.menu.pnum.GENERIC_L433RCTX=Generic L433RCTx
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GenL4.menu.pnum.GENERIC_L433RCTX.upload.maximum_size=262144
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GenL4.menu.pnum.GENERIC_L433RCTX.upload.maximum_data_size=65536
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GenL4.menu.pnum.GENERIC_L433RCTX.build.board=GENERIC_L433RCTX
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GenL4.menu.pnum.GENERIC_L433RCTX.build.product_line=STM32L433xx
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GenL4.menu.pnum.GENERIC_L433RCTX.build.variant=STM32L4xx/L433R(B-C)(I-T-Y)_L443RC(I-T-Y)
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# Generic L433RBYx
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GenL4.menu.pnum.GENERIC_L433RBYX=Generic L433RBYx
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GenL4.menu.pnum.GENERIC_L433RBYX.upload.maximum_size=131072
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GenL4.menu.pnum.GENERIC_L433RBYX.upload.maximum_data_size=65536
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GenL4.menu.pnum.GENERIC_L433RBYX.build.board=GENERIC_L433RBYX
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GenL4.menu.pnum.GENERIC_L433RBYX.build.product_line=STM32L433xx
9280+
GenL4.menu.pnum.GENERIC_L433RBYX.build.variant=STM32L4xx/L433R(B-C)(I-T-Y)_L443RC(I-T-Y)
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# Generic L433RCYx
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GenL4.menu.pnum.GENERIC_L433RCYX=Generic L433RCYx
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GenL4.menu.pnum.GENERIC_L433RCYX.upload.maximum_size=262144
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GenL4.menu.pnum.GENERIC_L433RCYX.upload.maximum_data_size=65536
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GenL4.menu.pnum.GENERIC_L433RCYX.build.board=GENERIC_L433RCYX
9287+
GenL4.menu.pnum.GENERIC_L433RCYX.build.product_line=STM32L433xx
9288+
GenL4.menu.pnum.GENERIC_L433RCYX.build.variant=STM32L4xx/L433R(B-C)(I-T-Y)_L443RC(I-T-Y)
9289+
9290+
# Generic L443RCIx
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GenL4.menu.pnum.GENERIC_L443RCIX=Generic L443RCIx
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GenL4.menu.pnum.GENERIC_L443RCIX.upload.maximum_size=262144
9293+
GenL4.menu.pnum.GENERIC_L443RCIX.upload.maximum_data_size=65536
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GenL4.menu.pnum.GENERIC_L443RCIX.build.board=GENERIC_L443RCIX
9295+
GenL4.menu.pnum.GENERIC_L443RCIX.build.product_line=STM32L443xx
9296+
GenL4.menu.pnum.GENERIC_L443RCIX.build.variant=STM32L4xx/L433R(B-C)(I-T-Y)_L443RC(I-T-Y)
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9298+
# Generic L443RCTx
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GenL4.menu.pnum.GENERIC_L443RCTX=Generic L443RCTx
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GenL4.menu.pnum.GENERIC_L443RCTX.upload.maximum_size=262144
9301+
GenL4.menu.pnum.GENERIC_L443RCTX.upload.maximum_data_size=65536
9302+
GenL4.menu.pnum.GENERIC_L443RCTX.build.board=GENERIC_L443RCTX
9303+
GenL4.menu.pnum.GENERIC_L443RCTX.build.product_line=STM32L443xx
9304+
GenL4.menu.pnum.GENERIC_L443RCTX.build.variant=STM32L4xx/L433R(B-C)(I-T-Y)_L443RC(I-T-Y)
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# Generic L443RCYx
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GenL4.menu.pnum.GENERIC_L443RCYX=Generic L443RCYx
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GenL4.menu.pnum.GENERIC_L443RCYX.upload.maximum_size=262144
9309+
GenL4.menu.pnum.GENERIC_L443RCYX.upload.maximum_data_size=65536
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GenL4.menu.pnum.GENERIC_L443RCYX.build.board=GENERIC_L443RCYX
9311+
GenL4.menu.pnum.GENERIC_L443RCYX.build.product_line=STM32L443xx
9312+
GenL4.menu.pnum.GENERIC_L443RCYX.build.variant=STM32L4xx/L433R(B-C)(I-T-Y)_L443RC(I-T-Y)
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# Generic L433RCTxP
92439315
GenL4.menu.pnum.GENERIC_L433RCTXP=Generic L433RCTxP
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GenL4.menu.pnum.GENERIC_L433RCTXP.upload.maximum_size=262144

Diff for: variants/STM32L4xx/L433R(B-C)(I-T-Y)_L443RC(I-T-Y)/generic_clock.c

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@@ -24,8 +24,53 @@
2424
*/
2525
WEAK void SystemClock_Config(void)
2626
{
27-
/* SystemClock_Config can be generated by STM32CubeMX */
28-
#warning "SystemClock_Config() is empty. Default clock at reset is used."
27+
RCC_OscInitTypeDef RCC_OscInitStruct = {};
28+
RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
29+
RCC_PeriphCLKInitTypeDef PeriphClkInit = {};
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/** Configure the main internal regulator output voltage
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*/
33+
if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK) {
34+
Error_Handler();
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}
36+
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/** Initializes the RCC Oscillators according to the specified parameters
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* in the RCC_OscInitTypeDef structure.
39+
*/
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_MSI;
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RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
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RCC_OscInitStruct.MSIState = RCC_MSI_ON;
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RCC_OscInitStruct.MSICalibrationValue = 0;
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RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
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RCC_OscInitStruct.PLL.PLLM = 1;
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RCC_OscInitStruct.PLL.PLLN = 40;
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RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV7;
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RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
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RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
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if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
53+
Error_Handler();
54+
}
55+
56+
/** Initializes the CPU, AHB and APB buses clocks
57+
*/
58+
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
59+
| RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
60+
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
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RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
63+
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
64+
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if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
66+
Error_Handler();
67+
}
68+
69+
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
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PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
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if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) {
72+
Error_Handler();
73+
}
2974
}
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#endif /* ARDUINO_GENERIC_* */
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@@ -0,0 +1,186 @@
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/*
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******************************************************************************
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**
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** @file : LinkerScript.ld
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**
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** @author : Auto-generated by STM32CubeIDE
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**
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** @brief : Linker script for STM32L433RCTx Device from STM32L4 series
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** 256Kbytes FLASH
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** 64Kbytes RAM
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** 16Kbytes RAM2
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**
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** Set heap size, stack size and stack location according
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** to application requirements.
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**
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** Set memory bank area and size if external memory is used
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**
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** Target : STMicroelectronics STM32
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**
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** Distribution: The file is distributed as is, without any warranty
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** of any kind.
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**
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******************************************************************************
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** @attention
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**
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** Copyright (c) 2023 STMicroelectronics.
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** All rights reserved.
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**
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** This software is licensed under terms that can be found in the LICENSE file
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** in the root directory of this software component.
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** If no LICENSE file comes with this software, it is provided AS-IS.
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**
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******************************************************************************
34+
*/
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36+
/* Entry Point */
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ENTRY(Reset_Handler)
38+
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/* Highest address of the user mode stack */
40+
_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
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_Min_Heap_Size = 0x200; /* required amount of heap */
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_Min_Stack_Size = 0x400; /* required amount of stack */
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/* Memories definition */
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MEMORY
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{
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RAM (xrw) : ORIGIN = 0x20000000, LENGTH = LD_MAX_DATA_SIZE
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FLASH (rx) : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
50+
}
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/* Sections */
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SECTIONS
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{
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/* The startup code into "FLASH" Rom type memory */
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.isr_vector :
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{
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. = ALIGN(4);
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KEEP(*(.isr_vector)) /* Startup code */
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. = ALIGN(4);
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} >FLASH
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/* The program code and other data into "FLASH" Rom type memory */
64+
.text :
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{
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. = ALIGN(4);
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*(.text) /* .text sections (code) */
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*(.text*) /* .text* sections (code) */
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*(.glue_7) /* glue arm to thumb code */
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*(.glue_7t) /* glue thumb to arm code */
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*(.eh_frame)
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KEEP (*(.init))
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KEEP (*(.fini))
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. = ALIGN(4);
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_etext = .; /* define a global symbols at end of code */
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} >FLASH
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/* Constant data into "FLASH" Rom type memory */
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.rodata :
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{
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. = ALIGN(4);
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*(.rodata) /* .rodata sections (constants, strings, etc.) */
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*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
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. = ALIGN(4);
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} >FLASH
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89+
.ARM.extab : {
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. = ALIGN(4);
91+
*(.ARM.extab* .gnu.linkonce.armextab.*)
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. = ALIGN(4);
93+
} >FLASH
94+
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.ARM : {
96+
. = ALIGN(4);
97+
__exidx_start = .;
98+
*(.ARM.exidx*)
99+
__exidx_end = .;
100+
. = ALIGN(4);
101+
} >FLASH
102+
103+
.preinit_array :
104+
{
105+
. = ALIGN(4);
106+
PROVIDE_HIDDEN (__preinit_array_start = .);
107+
KEEP (*(.preinit_array*))
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PROVIDE_HIDDEN (__preinit_array_end = .);
109+
. = ALIGN(4);
110+
} >FLASH
111+
112+
.init_array :
113+
{
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. = ALIGN(4);
115+
PROVIDE_HIDDEN (__init_array_start = .);
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KEEP (*(SORT(.init_array.*)))
117+
KEEP (*(.init_array*))
118+
PROVIDE_HIDDEN (__init_array_end = .);
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. = ALIGN(4);
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} >FLASH
121+
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.fini_array :
123+
{
124+
. = ALIGN(4);
125+
PROVIDE_HIDDEN (__fini_array_start = .);
126+
KEEP (*(SORT(.fini_array.*)))
127+
KEEP (*(.fini_array*))
128+
PROVIDE_HIDDEN (__fini_array_end = .);
129+
. = ALIGN(4);
130+
} >FLASH
131+
132+
/* Used by the startup to initialize data */
133+
_sidata = LOADADDR(.data);
134+
135+
/* Initialized data sections into "RAM" Ram type memory */
136+
.data :
137+
{
138+
. = ALIGN(4);
139+
_sdata = .; /* create a global symbol at data start */
140+
*(.data) /* .data sections */
141+
*(.data*) /* .data* sections */
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*(.RamFunc) /* .RamFunc sections */
143+
*(.RamFunc*) /* .RamFunc* sections */
144+
145+
. = ALIGN(4);
146+
_edata = .; /* define a global symbol at data end */
147+
148+
} >RAM AT> FLASH
149+
150+
/* Uninitialized data section into "RAM" Ram type memory */
151+
. = ALIGN(4);
152+
.bss :
153+
{
154+
/* This is used by the startup in order to initialize the .bss section */
155+
_sbss = .; /* define a global symbol at bss start */
156+
__bss_start__ = _sbss;
157+
*(.bss)
158+
*(.bss*)
159+
*(COMMON)
160+
161+
. = ALIGN(4);
162+
_ebss = .; /* define a global symbol at bss end */
163+
__bss_end__ = _ebss;
164+
} >RAM
165+
166+
/* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
167+
._user_heap_stack :
168+
{
169+
. = ALIGN(8);
170+
PROVIDE ( end = . );
171+
PROVIDE ( _end = . );
172+
. = . + _Min_Heap_Size;
173+
. = . + _Min_Stack_Size;
174+
. = ALIGN(8);
175+
} >RAM
176+
177+
/* Remove information from the compiler libraries */
178+
/DISCARD/ :
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{
180+
libc.a ( * )
181+
libm.a ( * )
182+
libgcc.a ( * )
183+
}
184+
185+
.ARM.attributes 0 : { *(.ARM.attributes) }
186+
}

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