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variant: G0: add generix G0B1R(B-C-E)T and G0C1R(C-E)T
Signed-off-by: Frederic Pillon <[email protected]>
1 parent efa7216 commit 9e0d196

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Diff for: README.md

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Original file line numberDiff line numberDiff line change
@@ -289,6 +289,8 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d
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| :green_heart: | STM32G041K6<br>STM32G041K8 | Generic Board | *2.0.0* | |
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| :green_heart: | STM32G071R6<br>STM32G071R8<br>STM32G071RB | Generic Board | *2.0.0* | |
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| :green_heart: | STM32G081RB | Generic Board | *2.0.0* | |
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| :yellow_heart: | STM32G0B1RB<br>STM32G0B1RC<br>STM32G0B1RE | Generic Board | **2.1.0** | |
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| :yellow_heart: | STM32G0C1RB<br>STM32G0C1RE | Generic Board | **2.1.0** | |
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### Generic STM32G4 boards
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Diff for: boards.txt

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@@ -3261,6 +3261,46 @@ GenG0.menu.pnum.GENERIC_G081RBTX.build.board=GENERIC_G081RBTX
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GenG0.menu.pnum.GENERIC_G081RBTX.build.product_line=STM32G081xx
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GenG0.menu.pnum.GENERIC_G081RBTX.build.variant=STM32G0xx/G071R(6-8)T_G071RB(I-T)_G081RB(I-T)
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# Generic G0B1RBTx
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GenG0.menu.pnum.GENERIC_G0B1RBTX=Generic G0B1RBTx
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GenG0.menu.pnum.GENERIC_G0B1RBTX.upload.maximum_size=131072
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GenG0.menu.pnum.GENERIC_G0B1RBTX.upload.maximum_data_size=147456
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GenG0.menu.pnum.GENERIC_G0B1RBTX.build.board=GENERIC_G0B1RBTX
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GenG0.menu.pnum.GENERIC_G0B1RBTX.build.product_line=STM32G0B1xx
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GenG0.menu.pnum.GENERIC_G0B1RBTX.build.variant=STM32G0xx/G0B1R(B-C-E)T_G0C1R(C-E)T
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# Generic G0B1RCTx
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GenG0.menu.pnum.GENERIC_G0B1RCTX=Generic G0B1RCTx
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GenG0.menu.pnum.GENERIC_G0B1RCTX.upload.maximum_size=262144
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GenG0.menu.pnum.GENERIC_G0B1RCTX.upload.maximum_data_size=147456
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GenG0.menu.pnum.GENERIC_G0B1RCTX.build.board=GENERIC_G0B1RCTX
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GenG0.menu.pnum.GENERIC_G0B1RCTX.build.product_line=STM32G0B1xx
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GenG0.menu.pnum.GENERIC_G0B1RCTX.build.variant=STM32G0xx/G0B1R(B-C-E)T_G0C1R(C-E)T
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# Generic G0B1RETx
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GenG0.menu.pnum.GENERIC_G0B1RETX=Generic G0B1RETx
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GenG0.menu.pnum.GENERIC_G0B1RETX.upload.maximum_size=524288
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GenG0.menu.pnum.GENERIC_G0B1RETX.upload.maximum_data_size=147456
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GenG0.menu.pnum.GENERIC_G0B1RETX.build.board=GENERIC_G0B1RETX
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GenG0.menu.pnum.GENERIC_G0B1RETX.build.product_line=STM32G0B1xx
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GenG0.menu.pnum.GENERIC_G0B1RETX.build.variant=STM32G0xx/G0B1R(B-C-E)T_G0C1R(C-E)T
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# Generic G0C1RCTx
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GenG0.menu.pnum.GENERIC_G0C1RCTX=Generic G0C1RCTx
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GenG0.menu.pnum.GENERIC_G0C1RCTX.upload.maximum_size=262144
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GenG0.menu.pnum.GENERIC_G0C1RCTX.upload.maximum_data_size=147456
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GenG0.menu.pnum.GENERIC_G0C1RCTX.build.board=GENERIC_G0C1RCTX
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GenG0.menu.pnum.GENERIC_G0C1RCTX.build.product_line=STM32G0C1xx
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GenG0.menu.pnum.GENERIC_G0C1RCTX.build.variant=STM32G0xx/G0B1R(B-C-E)T_G0C1R(C-E)T
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# Generic G0C1RETx
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GenG0.menu.pnum.GENERIC_G0C1RETX=Generic G0C1RETx
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GenG0.menu.pnum.GENERIC_G0C1RETX.upload.maximum_size=524288
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GenG0.menu.pnum.GENERIC_G0C1RETX.upload.maximum_data_size=147456
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GenG0.menu.pnum.GENERIC_G0C1RETX.build.board=GENERIC_G0C1RETX
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GenG0.menu.pnum.GENERIC_G0C1RETX.build.product_line=STM32G0C1xx
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GenG0.menu.pnum.GENERIC_G0C1RETX.build.variant=STM32G0xx/G0B1R(B-C-E)T_G0C1R(C-E)T
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# Upload menu
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GenG0.menu.upload_method.swdMethod=STM32CubeProgrammer (SWD)
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GenG0.menu.upload_method.swdMethod.upload.protocol=0

Diff for: variants/STM32G0xx/G0B1R(B-C-E)T_G0C1R(C-E)T/generic_clock.c

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@@ -22,8 +22,49 @@
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*/
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WEAK void SystemClock_Config(void)
2424
{
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/* SystemClock_Config can be generated by STM32CubeMX */
26-
#warning "SystemClock_Config() is empty. Default clock at reset is used."
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RCC_OscInitTypeDef RCC_OscInitStruct = {};
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RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
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RCC_PeriphCLKInitTypeDef PeriphClkInit = {};
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/** Configure the main internal regulator output voltage
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*/
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HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
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/** Initializes the RCC Oscillators according to the specified parameters
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* in the RCC_OscInitTypeDef structure.
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*/
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
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RCC_OscInitStruct.HSIState = RCC_HSI_ON;
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RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
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RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1;
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RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
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RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
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RCC_OscInitStruct.PLL.PLLN = 8;
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RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
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RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
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RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
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if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
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Error_Handler();
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}
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/** Initializes the CPU, AHB and APB buses clocks
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*/
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RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
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| RCC_CLOCKTYPE_PCLK1;
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
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RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
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if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
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Error_Handler();
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}
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/** Initializes the peripherals clocks
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*/
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PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
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PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
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if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) {
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Error_Handler();
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}
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}
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#endif /* ARDUINO_GENERIC_* */
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/**
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******************************************************************************
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* @file LinkerScript.ld
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* @author Auto-generated by STM32CubeIDE
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* @brief Linker script for STM32G0B1RETx Device from STM32G0 series
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* 512Kbytes FLASH
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* 144Kbytes RAM
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*
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* Set heap size, stack size and stack location according
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* to application requirements.
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*
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* Set memory bank area and size if external memory is used
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******************************************************************************
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* @attention
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*
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* <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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*/
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/* Entry Point */
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ENTRY(Reset_Handler)
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/* Highest address of the user mode stack */
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_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
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_Min_Heap_Size = 0x200; /* required amount of heap */
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_Min_Stack_Size = 0x400; /* required amount of stack */
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/* Memories definition */
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MEMORY
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{
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RAM (xrw) : ORIGIN = 0x20000000, LENGTH = LD_MAX_DATA_SIZE
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FLASH (rx) : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
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}
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/* Sections */
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SECTIONS
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{
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/* The startup code into "FLASH" Rom type memory */
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.isr_vector :
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{
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. = ALIGN(4);
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KEEP(*(.isr_vector)) /* Startup code */
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. = ALIGN(4);
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} >FLASH
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/* The program code and other data into "FLASH" Rom type memory */
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.text :
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{
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. = ALIGN(4);
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*(.text) /* .text sections (code) */
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*(.text*) /* .text* sections (code) */
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*(.glue_7) /* glue arm to thumb code */
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*(.glue_7t) /* glue thumb to arm code */
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*(.eh_frame)
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KEEP (*(.init))
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KEEP (*(.fini))
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. = ALIGN(4);
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_etext = .; /* define a global symbols at end of code */
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} >FLASH
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/* Constant data into "FLASH" Rom type memory */
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.rodata :
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{
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. = ALIGN(4);
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*(.rodata) /* .rodata sections (constants, strings, etc.) */
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*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
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. = ALIGN(4);
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} >FLASH
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.ARM.extab : {
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. = ALIGN(4);
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*(.ARM.extab* .gnu.linkonce.armextab.*)
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. = ALIGN(4);
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} >FLASH
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.ARM : {
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. = ALIGN(4);
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__exidx_start = .;
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*(.ARM.exidx*)
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__exidx_end = .;
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. = ALIGN(4);
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} >FLASH
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.preinit_array :
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{
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. = ALIGN(4);
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PROVIDE_HIDDEN (__preinit_array_start = .);
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KEEP (*(.preinit_array*))
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PROVIDE_HIDDEN (__preinit_array_end = .);
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. = ALIGN(4);
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} >FLASH
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.init_array :
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{
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. = ALIGN(4);
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PROVIDE_HIDDEN (__init_array_start = .);
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KEEP (*(SORT(.init_array.*)))
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KEEP (*(.init_array*))
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PROVIDE_HIDDEN (__init_array_end = .);
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. = ALIGN(4);
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} >FLASH
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.fini_array :
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{
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. = ALIGN(4);
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PROVIDE_HIDDEN (__fini_array_start = .);
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KEEP (*(SORT(.fini_array.*)))
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KEEP (*(.fini_array*))
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PROVIDE_HIDDEN (__fini_array_end = .);
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. = ALIGN(4);
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} >FLASH
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/* Used by the startup to initialize data */
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_sidata = LOADADDR(.data);
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/* Initialized data sections into "RAM" Ram type memory */
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.data :
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{
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. = ALIGN(4);
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_sdata = .; /* create a global symbol at data start */
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*(.data) /* .data sections */
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*(.data*) /* .data* sections */
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*(.RamFunc) /* .RamFunc sections */
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*(.RamFunc*) /* .RamFunc* sections */
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. = ALIGN(4);
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_edata = .; /* define a global symbol at data end */
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} >RAM AT> FLASH
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/* Uninitialized data section into "RAM" Ram type memory */
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. = ALIGN(4);
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.bss :
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{
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/* This is used by the startup in order to initialize the .bss section */
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_sbss = .; /* define a global symbol at bss start */
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__bss_start__ = _sbss;
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*(.bss)
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*(.bss*)
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*(COMMON)
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. = ALIGN(4);
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_ebss = .; /* define a global symbol at bss end */
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__bss_end__ = _ebss;
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} >RAM
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/* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
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._user_heap_stack :
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{
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. = ALIGN(8);
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PROVIDE ( end = . );
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PROVIDE ( _end = . );
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. = . + _Min_Heap_Size;
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. = . + _Min_Stack_Size;
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. = ALIGN(8);
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} >RAM
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/* Remove information from the compiler libraries */
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/DISCARD/ :
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{
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libc.a ( * )
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libm.a ( * )
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libgcc.a ( * )
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}
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.ARM.attributes 0 : { *(.ARM.attributes) }
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}

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