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dojyorindojyorin
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Fix degrade & variants with external OSC actively use it.
1 parent cc925bd commit 8dab285

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13 files changed

+56
-45
lines changed

13 files changed

+56
-45
lines changed

Diff for: ‎variants/STM32H5xx/H503CB(T-U)/generic_clock.c

+1-1
Original file line numberDiff line numberDiff line change
@@ -55,7 +55,7 @@ WEAK void SystemClock_Config(void)
5555

5656
/** Initializes the CPU, AHB and APB buses clocks
5757
*/
58-
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
58+
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK
5959
| RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2
6060
| RCC_CLOCKTYPE_PCLK3;
6161
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;

Diff for: ‎variants/STM32H5xx/H503KBU/generic_clock.c

+1-1
Original file line numberDiff line numberDiff line change
@@ -55,7 +55,7 @@ WEAK void SystemClock_Config(void)
5555

5656
/** Initializes the CPU, AHB and APB buses clocks
5757
*/
58-
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
58+
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK
5959
| RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2
6060
| RCC_CLOCKTYPE_PCLK3;
6161
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;

Diff for: ‎variants/STM32H5xx/H503RBT/generic_clock.c

+1-1
Original file line numberDiff line numberDiff line change
@@ -55,7 +55,7 @@ WEAK void SystemClock_Config(void)
5555

5656
/** Initializes the CPU, AHB and APB buses clocks
5757
*/
58-
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
58+
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK
5959
| RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2
6060
| RCC_CLOCKTYPE_PCLK3;
6161
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;

Diff for: ‎variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.cpp

+14-7
Original file line numberDiff line numberDiff line change
@@ -115,18 +115,25 @@ WEAK void SystemClock_Config(void)
115115

116116
while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
117117

118+
/** Configure LSE Drive Capability
119+
* Warning : Only applied when the LSE is disabled.
120+
*/
121+
HAL_PWR_EnableBkUpAccess();
122+
__HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
123+
118124
/** Initializes the RCC Oscillators according to the specified parameters
119125
* in the RCC_OscInitTypeDef structure.
120126
*/
121127
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_CSI | RCC_OSCILLATORTYPE_HSI48
122-
| RCC_OSCILLATORTYPE_LSI;
128+
| RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_LSE;
123129
RCC_OscInitStruct.CSIState = RCC_CSI_ON;
124130
RCC_OscInitStruct.CSICalibrationValue = RCC_CSICALIBRATION_DEFAULT;
125131
RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
126-
RCC_OscInitStruct.LSIState = RCC_LSI_ON;
132+
RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS_DIGITAL;
133+
RCC_OscInitStruct.LSEState = RCC_LSE_ON;
127134
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
128-
RCC_OscInitStruct.PLL.PLLSource = RCC_PLL1_SOURCE_CSI;
129-
RCC_OscInitStruct.PLL.PLLM = 1;
135+
RCC_OscInitStruct.PLL.PLLSource = RCC_PLL1_SOURCE_HSE;
136+
RCC_OscInitStruct.PLL.PLLM = 6;
130137
RCC_OscInitStruct.PLL.PLLN = 125;
131138
RCC_OscInitStruct.PLL.PLLP = 2;
132139
RCC_OscInitStruct.PLL.PLLQ = 10;
@@ -140,7 +147,7 @@ WEAK void SystemClock_Config(void)
140147

141148
/** Initializes the CPU, AHB and APB buses clocks
142149
*/
143-
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
150+
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK
144151
| RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2
145152
| RCC_CLOCKTYPE_PCLK3;
146153
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
@@ -161,8 +168,8 @@ WEAK void SystemClock_Config(void)
161168
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_LPUART1
162169
| RCC_PERIPHCLK_USB | RCC_PERIPHCLK_SPI1
163170
| RCC_PERIPHCLK_SPI2 | RCC_PERIPHCLK_SPI3;
164-
PeriphClkInitStruct.PLL2.PLL2Source = RCC_PLL2_SOURCE_CSI;
165-
PeriphClkInitStruct.PLL2.PLL2M = 1;
171+
PeriphClkInitStruct.PLL2.PLL2Source = RCC_PLL2_SOURCE_HSE;
172+
PeriphClkInitStruct.PLL2.PLL2M = 6;
166173
PeriphClkInitStruct.PLL2.PLL2N = 125;
167174
PeriphClkInitStruct.PLL2.PLL2P = 2;
168175
PeriphClkInitStruct.PLL2.PLL2Q = 15;

Diff for: ‎variants/STM32H5xx/H562R(G-I)T/generic_clock.c

+2-2
Original file line numberDiff line numberDiff line change
@@ -55,7 +55,7 @@ WEAK void SystemClock_Config(void)
5555

5656
/** Initializes the CPU, AHB and APB buses clocks
5757
*/
58-
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
58+
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK
5959
| RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2
6060
| RCC_CLOCKTYPE_PCLK3;
6161
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
@@ -93,7 +93,7 @@ WEAK void SystemClock_Config(void)
9393
PeriphClkInitStruct.PLL3.PLL3P = 2;
9494
PeriphClkInitStruct.PLL3.PLL3Q = 5;
9595
PeriphClkInitStruct.PLL3.PLL3R = 2;
96-
PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3_VCIRANGE_3;
96+
PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3_VCIRANGE_1;
9797
PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3_VCORANGE_WIDE;
9898
PeriphClkInitStruct.PLL3.PLL3FRACN = 0;
9999
PeriphClkInitStruct.PLL3.PLL3ClockOut = RCC_PLL3_DIVQ;

Diff for: ‎variants/STM32H5xx/H562R(G-I)T/variant_WEACT_H562RG.cpp

+6-2
Original file line numberDiff line numberDiff line change
@@ -134,7 +134,7 @@ WEAK void SystemClock_Config(void)
134134

135135
/** Initializes the CPU, AHB and APB buses clocks
136136
*/
137-
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
137+
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK
138138
| RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2
139139
| RCC_CLOCKTYPE_PCLK3;
140140
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
@@ -172,7 +172,7 @@ WEAK void SystemClock_Config(void)
172172
PeriphClkInitStruct.PLL3.PLL3P = 2;
173173
PeriphClkInitStruct.PLL3.PLL3Q = 5;
174174
PeriphClkInitStruct.PLL3.PLL3R = 2;
175-
PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3_VCIRANGE_3;
175+
PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3_VCIRANGE_1;
176176
PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3_VCORANGE_WIDE;
177177
PeriphClkInitStruct.PLL3.PLL3FRACN = 0;
178178
PeriphClkInitStruct.PLL3.PLL3ClockOut = RCC_PLL3_DIVQ;
@@ -187,6 +187,10 @@ WEAK void SystemClock_Config(void)
187187
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
188188
Error_Handler();
189189
}
190+
191+
/** Configure the programming delay
192+
*/
193+
__HAL_FLASH_SET_PROGRAM_DELAY(FLASH_PROGRAMMING_DELAY_2);
190194
}
191195

192196
#ifdef __cplusplus

Diff for: ‎variants/STM32H5xx/H562R(G-I)T/variant_WEACT_H562RG.h

-1
Original file line numberDiff line numberDiff line change
@@ -222,7 +222,6 @@ P1 P2
222222
#define HAL_SD_MODULE_ENABLED
223223
#endif
224224

225-
// Value of the HSE Bypass in Hz
226225
#define HSE_VALUE 8000000UL
227226

228227
// SD card slot Definitions

Diff for: ‎variants/STM32H5xx/H563IIKxQ_H573IIKxQ/generic_clock.c

+2-2
Original file line numberDiff line numberDiff line change
@@ -55,7 +55,7 @@ WEAK void SystemClock_Config(void)
5555

5656
/** Initializes the CPU, AHB and APB buses clocks
5757
*/
58-
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
58+
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK
5959
| RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2
6060
| RCC_CLOCKTYPE_PCLK3;
6161
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
@@ -94,7 +94,7 @@ WEAK void SystemClock_Config(void)
9494
PeriphClkInitStruct.PLL3.PLL3P = 2;
9595
PeriphClkInitStruct.PLL3.PLL3Q = 5;
9696
PeriphClkInitStruct.PLL3.PLL3R = 2;
97-
PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3_VCIRANGE_3;
97+
PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3_VCIRANGE_1;
9898
PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3_VCORANGE_WIDE;
9999
PeriphClkInitStruct.PLL3.PLL3FRACN = 0;
100100
PeriphClkInitStruct.PLL3.PLL3ClockOut = RCC_PLL3_DIVQ;

Diff for: ‎variants/STM32H5xx/H563IIKxQ_H573IIKxQ/variant_STM32H573I_DK.cpp

+22-18
Original file line numberDiff line numberDiff line change
@@ -205,18 +205,22 @@ WEAK void SystemClock_Config(void)
205205

206206
while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
207207

208+
/** Configure LSE Drive Capability
209+
* Warning : Only applied when the LSE is disabled.
210+
*/
211+
HAL_PWR_EnableBkUpAccess();
212+
__HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
213+
208214
/** Initializes the RCC Oscillators according to the specified parameters
209215
* in the RCC_OscInitTypeDef structure.
210216
*/
211217
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_CSI | RCC_OSCILLATORTYPE_HSI48
212-
| RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI;
218+
| RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_LSE;
213219
RCC_OscInitStruct.CSIState = RCC_CSI_ON;
214220
RCC_OscInitStruct.CSICalibrationValue = RCC_CSICALIBRATION_DEFAULT;
215221
RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
216222
RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS_DIGITAL;
217-
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
218-
RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1;
219-
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
223+
RCC_OscInitStruct.LSEState = RCC_LSE_ON;
220224
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
221225
RCC_OscInitStruct.PLL.PLLSource = RCC_PLL1_SOURCE_HSE;
222226
RCC_OscInitStruct.PLL.PLLM = 5;
@@ -233,7 +237,7 @@ WEAK void SystemClock_Config(void)
233237

234238
/** Initializes the CPU, AHB and APB buses clocks
235239
*/
236-
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
240+
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK
237241
| RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2
238242
| RCC_CLOCKTYPE_PCLK3;
239243
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
@@ -257,28 +261,28 @@ WEAK void SystemClock_Config(void)
257261
| RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2
258262
| RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_SPI4
259263
| RCC_PERIPHCLK_SPI5 | RCC_PERIPHCLK_SPI6;
260-
PeriphClkInitStruct.PLL2.PLL2Source = RCC_PLL2_SOURCE_CSI;
261-
PeriphClkInitStruct.PLL2.PLL2M = 1;
262-
PeriphClkInitStruct.PLL2.PLL2N = 32;
263-
PeriphClkInitStruct.PLL2.PLL2P = 1;
264-
PeriphClkInitStruct.PLL2.PLL2Q = 4;
265-
PeriphClkInitStruct.PLL2.PLL2R = 2;
264+
PeriphClkInitStruct.PLL2.PLL2Source = RCC_PLL2_SOURCE_HSE;
265+
PeriphClkInitStruct.PLL2.PLL2M = 5;
266+
PeriphClkInitStruct.PLL2.PLL2N = 100;
267+
PeriphClkInitStruct.PLL2.PLL2P = 2;
268+
PeriphClkInitStruct.PLL2.PLL2Q = 15;
269+
PeriphClkInitStruct.PLL2.PLL2R = 4;
266270
PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2_VCIRANGE_2;
267271
PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2_VCORANGE_WIDE;
268272
PeriphClkInitStruct.PLL2.PLL2FRACN = 0;
269273
PeriphClkInitStruct.PLL2.PLL2ClockOut = RCC_PLL2_DIVQ | RCC_PLL2_DIVR;
270-
PeriphClkInitStruct.PLL3.PLL3Source = RCC_PLL3_SOURCE_CSI;
271-
PeriphClkInitStruct.PLL3.PLL3M = 2;
272-
PeriphClkInitStruct.PLL3.PLL3N = 125;
274+
PeriphClkInitStruct.PLL3.PLL3Source = RCC_PLL3_SOURCE_HSE;
275+
PeriphClkInitStruct.PLL3.PLL3M = 5;
276+
PeriphClkInitStruct.PLL3.PLL3N = 50;
273277
PeriphClkInitStruct.PLL3.PLL3P = 2;
274278
PeriphClkInitStruct.PLL3.PLL3Q = 5;
275279
PeriphClkInitStruct.PLL3.PLL3R = 2;
276-
PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3_VCIRANGE_3;
280+
PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3_VCIRANGE_2;
277281
PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3_VCORANGE_WIDE;
278282
PeriphClkInitStruct.PLL3.PLL3FRACN = 0;
279-
PeriphClkInitStruct.PLL3.PLL3ClockOut = RCC_PLL3_DIVQ;
280-
PeriphClkInitStruct.Sai1ClockSelection = RCC_SAI1CLKSOURCE_PLL2P;
281-
PeriphClkInitStruct.Sai2ClockSelection = RCC_SAI2CLKSOURCE_PLL2P;
283+
PeriphClkInitStruct.PLL3.PLL3ClockOut = RCC_PLL3_DIVP | RCC_PLL3_DIVQ;
284+
PeriphClkInitStruct.Sai1ClockSelection = RCC_SAI1CLKSOURCE_PLL3P;
285+
PeriphClkInitStruct.Sai2ClockSelection = RCC_SAI2CLKSOURCE_PLL3P;
282286
PeriphClkInitStruct.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_PLL1Q;
283287
PeriphClkInitStruct.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_PLL2R;
284288
PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PLL2Q;

Diff for: ‎variants/STM32H5xx/H563IIKxQ_H573IIKxQ/variant_STM32H573I_DK.h

-3
Original file line numberDiff line numberDiff line change
@@ -312,9 +312,6 @@
312312
#define HAL_SD_MODULE_ENABLED
313313
#endif
314314

315-
// Value of the HSE Bypass in Hz
316-
#define HSE_VALUE 25000000UL
317-
318315
/*----------------------------------------------------------------------------
319316
* Arduino objects - C++ only
320317
*----------------------------------------------------------------------------*/

Diff for: ‎variants/STM32H5xx/H563R(G-I)T_H573RIT/generic_clock.c

+2-2
Original file line numberDiff line numberDiff line change
@@ -56,7 +56,7 @@ WEAK void SystemClock_Config(void)
5656

5757
/** Initializes the CPU, AHB and APB buses clocks
5858
*/
59-
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
59+
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK
6060
| RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2
6161
| RCC_CLOCKTYPE_PCLK3;
6262
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
@@ -94,7 +94,7 @@ WEAK void SystemClock_Config(void)
9494
PeriphClkInitStruct.PLL3.PLL3P = 2;
9595
PeriphClkInitStruct.PLL3.PLL3Q = 5;
9696
PeriphClkInitStruct.PLL3.PLL3R = 2;
97-
PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3_VCIRANGE_3;
97+
PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3_VCIRANGE_1;
9898
PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3_VCORANGE_WIDE;
9999
PeriphClkInitStruct.PLL3.PLL3FRACN = 0;
100100
PeriphClkInitStruct.PLL3.PLL3ClockOut = RCC_PLL3_DIVQ;

Diff for: ‎variants/STM32H5xx/H563Z(G-I)T_H573ZIT/generic_clock.c

+2-2
Original file line numberDiff line numberDiff line change
@@ -56,7 +56,7 @@ WEAK void SystemClock_Config(void)
5656

5757
/** Initializes the CPU, AHB and APB buses clocks
5858
*/
59-
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
59+
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK
6060
| RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2
6161
| RCC_CLOCKTYPE_PCLK3;
6262
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
@@ -95,7 +95,7 @@ WEAK void SystemClock_Config(void)
9595
PeriphClkInitStruct.PLL3.PLL3P = 2;
9696
PeriphClkInitStruct.PLL3.PLL3Q = 5;
9797
PeriphClkInitStruct.PLL3.PLL3R = 2;
98-
PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3_VCIRANGE_3;
98+
PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3_VCIRANGE_1;
9999
PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3_VCORANGE_WIDE;
100100
PeriphClkInitStruct.PLL3.PLL3FRACN = 0;
101101
PeriphClkInitStruct.PLL3.PLL3ClockOut = RCC_PLL3_DIVQ;

Diff for: ‎variants/STM32H5xx/H563Z(G-I)T_H573ZIT/variant_NUCLEO_H563ZI.cpp

+3-3
Original file line numberDiff line numberDiff line change
@@ -193,7 +193,7 @@ WEAK void SystemClock_Config(void)
193193
RCC_OscInitStruct.CSIState = RCC_CSI_ON;
194194
RCC_OscInitStruct.CSICalibrationValue = RCC_CSICALIBRATION_DEFAULT;
195195
RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
196-
RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
196+
RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS_DIGITAL;
197197
RCC_OscInitStruct.LSEState = RCC_LSE_ON;
198198
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
199199
RCC_OscInitStruct.PLL.PLLSource = RCC_PLL1_SOURCE_HSE;
@@ -211,7 +211,7 @@ WEAK void SystemClock_Config(void)
211211

212212
/** Initializes the CPU, AHB and APB buses clocks
213213
*/
214-
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
214+
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK
215215
| RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2
216216
| RCC_CLOCKTYPE_PCLK3;
217217
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
@@ -250,7 +250,7 @@ WEAK void SystemClock_Config(void)
250250
PeriphClkInitStruct.PLL3.PLL3P = 2;
251251
PeriphClkInitStruct.PLL3.PLL3Q = 5;
252252
PeriphClkInitStruct.PLL3.PLL3R = 2;
253-
PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3_VCIRANGE_3;
253+
PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3_VCIRANGE_1;
254254
PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3_VCORANGE_WIDE;
255255
PeriphClkInitStruct.PLL3.PLL3FRACN = 0;
256256
PeriphClkInitStruct.PLL3.PLL3ClockOut = RCC_PLL3_DIVQ;

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