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system(F3): update STM32F3xx CMSIS Drivers to v2.3.7
Included in STM32CubeF3 FW v1.11.4 Signed-off-by: Frederic Pillon <[email protected]>
1 parent 0be1cd6 commit 8cba517

39 files changed

+2192
-470
lines changed

Diff for: ‎system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f301x8.h

+22-21
Original file line numberDiff line numberDiff line change
@@ -12,13 +12,12 @@
1212
******************************************************************************
1313
* @attention
1414
*
15-
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
16-
* All rights reserved.</center></h2>
15+
* Copyright (c) 2016 STMicroelectronics.
16+
* All rights reserved.
1717
*
18-
* This software component is licensed by ST under BSD 3-Clause license,
19-
* the "License"; You may not use this file except in compliance with the
20-
* License. You may obtain a copy of the License at:
21-
* opensource.org/licenses/BSD-3-Clause
18+
* This software is licensed under terms that can be found in the LICENSE file
19+
* in the root directory of this software component.
20+
* If no LICENSE file comes with this software, it is provided AS-IS.
2221
*
2322
******************************************************************************
2423
*/
@@ -571,6 +570,10 @@ typedef struct
571570
__IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
572571
} WWDG_TypeDef;
573572

573+
/**
574+
* @}
575+
*/
576+
574577
/** @addtogroup Peripheral_memory_map
575578
* @{
576579
*/
@@ -746,7 +749,7 @@ typedef struct
746749
#define ADC5_V1_1 /*!< ADC IP version */
747750

748751
/*
749-
* @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
752+
* @brief Specific device feature definitions (not present on all devices in the STM32F3 series)
750753
*/
751754
/* Note: No specific macro feature on this device */
752755

@@ -883,7 +886,7 @@ typedef struct
883886

884887
#define ADC_CFGR_ALIGN_Pos (5U)
885888
#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */
886-
#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */
889+
#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */
887890

888891
#define ADC_CFGR_EXTSEL_Pos (6U)
889892
#define ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */
@@ -2241,7 +2244,7 @@ typedef struct
22412244
#define OPAMP2_CSR_TSTREF OPAMP2_CSR_TSTREF_Msk /*!< It enables the switch to put out the internal reference */
22422245
#define OPAMP2_CSR_OUTCAL_Pos (30U)
22432246
#define OPAMP2_CSR_OUTCAL_Msk (0x1UL << OPAMP2_CSR_OUTCAL_Pos) /*!< 0x40000000 */
2244-
#define OPAMP2_CSR_OUTCAL OPAMP2_CSR_OUTCAL_Msk /*!< OPAMP ouput status flag */
2247+
#define OPAMP2_CSR_OUTCAL OPAMP2_CSR_OUTCAL_Msk /*!< OPAMP output status flag */
22452248
#define OPAMP2_CSR_LOCK_Pos (31U)
22462249
#define OPAMP2_CSR_LOCK_Msk (0x1UL << OPAMP2_CSR_LOCK_Pos) /*!< 0x80000000 */
22472250
#define OPAMP2_CSR_LOCK OPAMP2_CSR_LOCK_Msk /*!< OPAMP lock */
@@ -2303,7 +2306,7 @@ typedef struct
23032306
#define OPAMP_CSR_TSTREF OPAMP_CSR_TSTREF_Msk /*!< It enables the switch to put out the internal reference */
23042307
#define OPAMP_CSR_OUTCAL_Pos (30U)
23052308
#define OPAMP_CSR_OUTCAL_Msk (0x1UL << OPAMP_CSR_OUTCAL_Pos) /*!< 0x40000000 */
2306-
#define OPAMP_CSR_OUTCAL OPAMP_CSR_OUTCAL_Msk /*!< OPAMP ouput status flag */
2309+
#define OPAMP_CSR_OUTCAL OPAMP_CSR_OUTCAL_Msk /*!< OPAMP output status flag */
23072310
#define OPAMP_CSR_LOCK_Pos (31U)
23082311
#define OPAMP_CSR_LOCK_Msk (0x1UL << OPAMP_CSR_LOCK_Pos) /*!< 0x80000000 */
23092312
#define OPAMP_CSR_LOCK OPAMP_CSR_LOCK_Msk /*!< OPAMP lock */
@@ -2356,7 +2359,7 @@ typedef struct
23562359
/******************************************************************************/
23572360

23582361
/*
2359-
* @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
2362+
* @brief Specific device feature definitions (not present on all devices in the STM32F3 series)
23602363
*/
23612364
/* Note: No specific macro feature on this device */
23622365

@@ -5348,7 +5351,7 @@ typedef struct
53485351
/* */
53495352
/******************************************************************************/
53505353
/*
5351-
* @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
5354+
* @brief Specific device feature definitions (not present on all devices in the STM32F3 series)
53525355
*/
53535356
#define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */
53545357
#define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */
@@ -6030,7 +6033,7 @@ typedef struct
60306033
/******************************************************************************/
60316034

60326035
/*
6033-
* @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
6036+
* @brief Specific device feature definitions (not present on all devices in the STM32F3 series)
60346037
*/
60356038
#define SPI_I2S_SUPPORT /*!< I2S support */
60366039
#define SPI_I2S_FULLDUPLEX_SUPPORT /*!< I2S Full-Duplex support */
@@ -7138,11 +7141,11 @@ typedef struct
71387141
#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
71397142

71407143
/******************* Bit definition for TIM16_OR register *********************/
7141-
#define TIM16_OR_TI1_RMP_Pos (6U)
7142-
#define TIM16_OR_TI1_RMP_Msk (0x3UL << TIM16_OR_TI1_RMP_Pos) /*!< 0x000000C0 */
7144+
#define TIM16_OR_TI1_RMP_Pos (0U)
7145+
#define TIM16_OR_TI1_RMP_Msk (0x3UL << TIM16_OR_TI1_RMP_Pos) /*!< 0x00000003 */
71437146
#define TIM16_OR_TI1_RMP TIM16_OR_TI1_RMP_Msk /*!<TI1_RMP[1:0] bits (TIM16 Input 1 remap) */
7144-
#define TIM16_OR_TI1_RMP_0 (0x1UL << TIM16_OR_TI1_RMP_Pos) /*!< 0x00000040 */
7145-
#define TIM16_OR_TI1_RMP_1 (0x2UL << TIM16_OR_TI1_RMP_Pos) /*!< 0x00000080 */
7147+
#define TIM16_OR_TI1_RMP_0 (0x1UL << TIM16_OR_TI1_RMP_Pos) /*!< 0x00000001 */
7148+
#define TIM16_OR_TI1_RMP_1 (0x2UL << TIM16_OR_TI1_RMP_Pos) /*!< 0x00000002 */
71467149

71477150
/******************* Bit definition for TIM1_OR register *********************/
71487151
#define TIM1_OR_ETR_RMP_Pos (0U)
@@ -7740,7 +7743,7 @@ typedef struct
77407743
/******************************************************************************/
77417744

77427745
/*
7743-
* @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
7746+
* @brief Specific device feature definitions (not present on all devices in the STM32F3 series)
77447747
*/
77457748

77467749
/* Support of 7 bits data length feature */
@@ -8612,8 +8615,6 @@ typedef struct
86128615
* @}
86138616
*/
86148617

8615-
/**
8618+
/**
86168619
* @}
86178620
*/
8618-
8619-
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Diff for: ‎system/Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302x8.h

+18-17
Original file line numberDiff line numberDiff line change
@@ -12,13 +12,12 @@
1212
******************************************************************************
1313
* @attention
1414
*
15-
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
16-
* All rights reserved.</center></h2>
15+
* Copyright (c) 2016 STMicroelectronics.
16+
* All rights reserved.
1717
*
18-
* This software component is licensed by ST under BSD 3-Clause license,
19-
* the "License"; You may not use this file except in compliance with the
20-
* License. You may obtain a copy of the License at:
21-
* opensource.org/licenses/BSD-3-Clause
18+
* This software is licensed under terms that can be found in the LICENSE file
19+
* in the root directory of this software component.
20+
* If no LICENSE file comes with this software, it is provided AS-IS.
2221
*
2322
******************************************************************************
2423
*/
@@ -675,6 +674,10 @@ typedef struct
675674
__IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
676675
} WWDG_TypeDef;
677676

677+
/**
678+
* @}
679+
*/
680+
678681
/** @addtogroup Peripheral_memory_map
679682
* @{
680683
*/
@@ -855,7 +858,7 @@ typedef struct
855858
#define ADC5_V1_1 /*!< ADC IP version */
856859

857860
/*
858-
* @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
861+
* @brief Specific device feature definitions (not present on all devices in the STM32F3 series)
859862
*/
860863
/* Note: No specific macro feature on this device */
861864

@@ -992,7 +995,7 @@ typedef struct
992995

993996
#define ADC_CFGR_ALIGN_Pos (5U)
994997
#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */
995-
#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */
998+
#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */
996999

9971000
#define ADC_CFGR_EXTSEL_Pos (6U)
9981001
#define ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */
@@ -2350,7 +2353,7 @@ typedef struct
23502353
#define OPAMP2_CSR_TSTREF OPAMP2_CSR_TSTREF_Msk /*!< It enables the switch to put out the internal reference */
23512354
#define OPAMP2_CSR_OUTCAL_Pos (30U)
23522355
#define OPAMP2_CSR_OUTCAL_Msk (0x1UL << OPAMP2_CSR_OUTCAL_Pos) /*!< 0x40000000 */
2353-
#define OPAMP2_CSR_OUTCAL OPAMP2_CSR_OUTCAL_Msk /*!< OPAMP ouput status flag */
2356+
#define OPAMP2_CSR_OUTCAL OPAMP2_CSR_OUTCAL_Msk /*!< OPAMP output status flag */
23542357
#define OPAMP2_CSR_LOCK_Pos (31U)
23552358
#define OPAMP2_CSR_LOCK_Msk (0x1UL << OPAMP2_CSR_LOCK_Pos) /*!< 0x80000000 */
23562359
#define OPAMP2_CSR_LOCK OPAMP2_CSR_LOCK_Msk /*!< OPAMP lock */
@@ -2412,7 +2415,7 @@ typedef struct
24122415
#define OPAMP_CSR_TSTREF OPAMP_CSR_TSTREF_Msk /*!< It enables the switch to put out the internal reference */
24132416
#define OPAMP_CSR_OUTCAL_Pos (30U)
24142417
#define OPAMP_CSR_OUTCAL_Msk (0x1UL << OPAMP_CSR_OUTCAL_Pos) /*!< 0x40000000 */
2415-
#define OPAMP_CSR_OUTCAL OPAMP_CSR_OUTCAL_Msk /*!< OPAMP ouput status flag */
2418+
#define OPAMP_CSR_OUTCAL OPAMP_CSR_OUTCAL_Msk /*!< OPAMP output status flag */
24162419
#define OPAMP_CSR_LOCK_Pos (31U)
24172420
#define OPAMP_CSR_LOCK_Msk (0x1UL << OPAMP_CSR_LOCK_Pos) /*!< 0x80000000 */
24182421
#define OPAMP_CSR_LOCK OPAMP_CSR_LOCK_Msk /*!< OPAMP lock */
@@ -5943,7 +5946,7 @@ typedef struct
59435946
/******************************************************************************/
59445947

59455948
/*
5946-
* @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
5949+
* @brief Specific device feature definitions (not present on all devices in the STM32F3 series)
59475950
*/
59485951
/* Note: No specific macro feature on this device */
59495952

@@ -8976,7 +8979,7 @@ typedef struct
89768979
/* */
89778980
/******************************************************************************/
89788981
/*
8979-
* @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
8982+
* @brief Specific device feature definitions (not present on all devices in the STM32F3 series)
89808983
*/
89818984
#define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */
89828985
#define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */
@@ -9658,7 +9661,7 @@ typedef struct
96589661
/******************************************************************************/
96599662

96609663
/*
9661-
* @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
9664+
* @brief Specific device feature definitions (not present on all devices in the STM32F3 series)
96629665
*/
96639666
#define SPI_I2S_SUPPORT /*!< I2S support */
96649667
#define SPI_I2S_FULLDUPLEX_SUPPORT /*!< I2S Full-Duplex support */
@@ -11371,7 +11374,7 @@ typedef struct
1137111374
/******************************************************************************/
1137211375

1137311376
/*
11374-
* @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
11377+
* @brief Specific device feature definitions (not present on all devices in the STM32F3 series)
1137511378
*/
1137611379

1137711380
/* Support of 7 bits data length feature */
@@ -12385,8 +12388,6 @@ typedef struct
1238512388
* @}
1238612389
*/
1238712390

12388-
/**
12391+
/**
1238912392
* @}
1239012393
*/
12391-
12392-
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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