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90 | 90 | #endif /* USE_HAL_DRIVER */
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91 | 91 |
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92 | 92 | /**
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93 |
| - * @brief CMSIS Device version number V4.3.2 |
| 93 | + * @brief CMSIS Device version number V4.3.3 |
94 | 94 | */
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95 | 95 | #define __STM32F1_CMSIS_VERSION_MAIN (0x04) /*!< [31:24] main version */
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96 | 96 | #define __STM32F1_CMSIS_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
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97 |
| -#define __STM32F1_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */ |
| 97 | +#define __STM32F1_CMSIS_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */ |
98 | 98 | #define __STM32F1_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
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99 | 99 | #define __STM32F1_CMSIS_VERSION ((__STM32F1_CMSIS_VERSION_MAIN << 24)\
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100 | 100 | |(__STM32F1_CMSIS_VERSION_SUB1 << 16)\
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@@ -191,6 +191,61 @@ typedef enum
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191 | 191 |
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192 | 192 | #define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
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193 | 193 |
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| 194 | +/* Use of CMSIS compiler intrinsics for register exclusive access */ |
| 195 | +/* Atomic 32-bit register access macro to set one or several bits */ |
| 196 | +#define ATOMIC_SET_BIT(REG, BIT) \ |
| 197 | + do { \ |
| 198 | + uint32_t val; \ |
| 199 | + do { \ |
| 200 | + val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT); \ |
| 201 | + } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \ |
| 202 | + } while(0) |
| 203 | + |
| 204 | +/* Atomic 32-bit register access macro to clear one or several bits */ |
| 205 | +#define ATOMIC_CLEAR_BIT(REG, BIT) \ |
| 206 | + do { \ |
| 207 | + uint32_t val; \ |
| 208 | + do { \ |
| 209 | + val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT); \ |
| 210 | + } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \ |
| 211 | + } while(0) |
| 212 | + |
| 213 | +/* Atomic 32-bit register access macro to clear and set one or several bits */ |
| 214 | +#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \ |
| 215 | + do { \ |
| 216 | + uint32_t val; \ |
| 217 | + do { \ |
| 218 | + val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \ |
| 219 | + } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \ |
| 220 | + } while(0) |
| 221 | + |
| 222 | +/* Atomic 16-bit register access macro to set one or several bits */ |
| 223 | +#define ATOMIC_SETH_BIT(REG, BIT) \ |
| 224 | + do { \ |
| 225 | + uint16_t val; \ |
| 226 | + do { \ |
| 227 | + val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT); \ |
| 228 | + } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \ |
| 229 | + } while(0) |
| 230 | + |
| 231 | +/* Atomic 16-bit register access macro to clear one or several bits */ |
| 232 | +#define ATOMIC_CLEARH_BIT(REG, BIT) \ |
| 233 | + do { \ |
| 234 | + uint16_t val; \ |
| 235 | + do { \ |
| 236 | + val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT); \ |
| 237 | + } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \ |
| 238 | + } while(0) |
| 239 | + |
| 240 | +/* Atomic 16-bit register access macro to clear and set one or several bits */ |
| 241 | +#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) \ |
| 242 | + do { \ |
| 243 | + uint16_t val; \ |
| 244 | + do { \ |
| 245 | + val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \ |
| 246 | + } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \ |
| 247 | + } while(0) |
| 248 | + |
194 | 249 |
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195 | 250 | /**
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196 | 251 | * @}
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