@@ -37,16 +37,12 @@ extern "C" {
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#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
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#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
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#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
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- #if defined(STM32U5 ) || defined( STM32H7 ) || defined(STM32MP1 )
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+ #if defined(STM32H7 ) || defined(STM32MP1 )
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#define CRYP_DATATYPE_32B CRYP_NO_SWAP
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#define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP
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#define CRYP_DATATYPE_8B CRYP_BYTE_SWAP
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#define CRYP_DATATYPE_1B CRYP_BIT_SWAP
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- #if defined(STM32U5 )
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- #define CRYP_CCF_CLEAR CRYP_CLEAR_CCF
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- #define CRYP_ERR_CLEAR CRYP_CLEAR_RWEIF
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- #endif /* STM32U5 */
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- #endif /* STM32U5 || STM32H7 || STM32MP1 */
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+ #endif /* STM32H7 || STM32MP1 */
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/**
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* @}
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*/
@@ -279,7 +275,7 @@ extern "C" {
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#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
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#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
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- #if defined(STM32G4 ) || defined(STM32L5 ) || defined( STM32H7 ) || defined (STM32U5 )
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+ #if defined(STM32G4 ) || defined(STM32H7 ) || defined (STM32U5 )
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#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL
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#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL
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#endif
@@ -476,7 +472,9 @@ extern "C" {
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#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE
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#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD
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#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD
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+ #if !defined(STM32F2 ) && !defined(STM32F4 ) && !defined(STM32F7 ) && !defined(STM32H7 )
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#define PAGESIZE FLASH_PAGE_SIZE
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+ #endif /* STM32F2 && STM32F4 && STM32F7 && STM32H7 */
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#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE
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#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD
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#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD
@@ -552,6 +550,16 @@ extern "C" {
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#define OB_SRAM134_RST_ERASE OB_SRAM_RST_ERASE
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#define OB_SRAM134_RST_NOT_ERASE OB_SRAM_RST_NOT_ERASE
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#endif /* STM32U5 */
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+ #if defined(STM32U0 )
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+ #define OB_USER_nRST_STOP OB_USER_NRST_STOP
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+ #define OB_USER_nRST_STDBY OB_USER_NRST_STDBY
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+ #define OB_USER_nRST_SHDW OB_USER_NRST_SHDW
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+ #define OB_USER_nBOOT_SEL OB_USER_NBOOT_SEL
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+ #define OB_USER_nBOOT0 OB_USER_NBOOT0
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+ #define OB_USER_nBOOT1 OB_USER_NBOOT1
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+ #define OB_nBOOT0_RESET OB_NBOOT0_RESET
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+ #define OB_nBOOT0_SET OB_NBOOT0_SET
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+ #endif /* STM32U0 */
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/**
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* @}
@@ -800,6 +808,21 @@ extern "C" {
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#define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP
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#define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1
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#endif /* STM32U5 */
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+
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+ #if defined(STM32WBA )
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+ #define GPIO_AF11_RF_ANTSW0 GPIO_AF11_RF
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+ #define GPIO_AF11_RF_ANTSW1 GPIO_AF11_RF
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+ #define GPIO_AF11_RF_ANTSW2 GPIO_AF11_RF
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+ #define GPIO_AF11_RF_IO1 GPIO_AF11_RF
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+ #define GPIO_AF11_RF_IO2 GPIO_AF11_RF
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+ #define GPIO_AF11_RF_IO3 GPIO_AF11_RF
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+ #define GPIO_AF11_RF_IO4 GPIO_AF11_RF
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+ #define GPIO_AF11_RF_IO5 GPIO_AF11_RF
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+ #define GPIO_AF11_RF_IO6 GPIO_AF11_RF
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+ #define GPIO_AF11_RF_IO7 GPIO_AF11_RF
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+ #define GPIO_AF11_RF_IO8 GPIO_AF11_RF
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+ #define GPIO_AF11_RF_IO9 GPIO_AF11_RF
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+ #endif /* STM32WBA */
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/**
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* @}
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*/
@@ -1243,10 +1266,10 @@ extern "C" {
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#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
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#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
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- #if defined(STM32H5 )
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+ #if defined(STM32H5 ) || defined( STM32H7RS )
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#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE
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#define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM
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- #endif /* STM32H5 */
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+ #endif /* STM32H5 || STM32H7RS */
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#if defined(STM32WBA )
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#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE
@@ -1258,10 +1281,10 @@ extern "C" {
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#define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL
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#endif /* STM32WBA */
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- #if defined(STM32H5 ) || defined(STM32WBA )
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+ #if defined(STM32H5 ) || defined(STM32WBA ) || defined( STM32H7RS )
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#define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE
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#define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL
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- #endif /* STM32H5 || STM32WBA */
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+ #endif /* STM32H5 || STM32WBA || STM32H7RS */
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#if defined(STM32F7 )
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#define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK
@@ -1599,6 +1622,8 @@ extern "C" {
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#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */
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#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */
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+ #define ETH_TxPacketConfig ETH_TxPacketConfigTypeDef /* Transmit Packet Configuration structure definition */
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+
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/**
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* @}
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*/
@@ -1809,7 +1834,7 @@ extern "C" {
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#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter
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#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
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- #define HAL_I2CFastModePlusConfig (SYSCFG_I2CFastModePlus , cmd ) ((cmd == ENABLE)? \
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+ #define HAL_I2CFastModePlusConfig (SYSCFG_I2CFastModePlus , cmd ) ((( cmd) == ENABLE)? \
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HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): \
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HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
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@@ -1991,12 +2016,12 @@ extern "C" {
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/** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose
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* @{
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*/
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- #if defined(STM32H5 ) || defined(STM32WBA )
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+ #if defined(STM32H5 ) || defined(STM32WBA ) || defined( STM32H7RS )
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#define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey
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#define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock
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#define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock
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#define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets
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- #endif /* STM32H5 || STM32WBA */
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+ #endif /* STM32H5 || STM32WBA || STM32H7RS */
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/**
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* @}
@@ -2311,8 +2336,8 @@ extern "C" {
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#define __HAL_COMP_EXTI_CLEAR_FLAG (__FLAG__ ) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
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((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
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__HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
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- # endif
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- # if defined(STM32F302xE ) || defined(STM32F302xC )
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+ #endif
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+ #if defined(STM32F302xE ) || defined(STM32F302xC )
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#define __HAL_COMP_EXTI_RISING_IT_ENABLE (__EXTILINE__ ) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
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((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
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((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
@@ -2345,8 +2370,8 @@ extern "C" {
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((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
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((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
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__HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
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- # endif
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- # if defined(STM32F303xE ) || defined(STM32F398xx ) || defined(STM32F303xC ) || defined(STM32F358xx )
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+ #endif
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+ #if defined(STM32F303xE ) || defined(STM32F398xx ) || defined(STM32F303xC ) || defined(STM32F358xx )
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#define __HAL_COMP_EXTI_RISING_IT_ENABLE (__EXTILINE__ ) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
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((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
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((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
@@ -2403,8 +2428,8 @@ extern "C" {
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((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \
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((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \
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__HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
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- # endif
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- # if defined(STM32F373xC ) || defined(STM32F378xx )
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+ #endif
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+ #if defined(STM32F373xC ) || defined(STM32F378xx )
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#define __HAL_COMP_EXTI_RISING_IT_ENABLE (__EXTILINE__ ) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
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__HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
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#define __HAL_COMP_EXTI_RISING_IT_DISABLE (__EXTILINE__ ) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
@@ -2421,7 +2446,7 @@ extern "C" {
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__HAL_COMP_COMP2_EXTI_GET_FLAG())
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#define __HAL_COMP_EXTI_CLEAR_FLAG (__FLAG__ ) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
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__HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
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- # endif
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+ #endif
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#else
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#define __HAL_COMP_EXTI_RISING_IT_ENABLE (__EXTILINE__ ) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
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__HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
@@ -2723,6 +2748,12 @@ extern "C" {
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#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
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#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
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#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
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+ #if defined(STM32C0 )
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+ #define __HAL_RCC_APB1_FORCE_RESET __HAL_RCC_APB1_GRP1_FORCE_RESET
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+ #define __HAL_RCC_APB1_RELEASE_RESET __HAL_RCC_APB1_GRP1_RELEASE_RESET
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+ #define __HAL_RCC_APB2_FORCE_RESET __HAL_RCC_APB1_GRP2_FORCE_RESET
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+ #define __HAL_RCC_APB2_RELEASE_RESET __HAL_RCC_APB1_GRP2_RELEASE_RESET
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+ #endif /* STM32C0 */
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#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
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#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
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#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
@@ -3646,8 +3677,12 @@ extern "C" {
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#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
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#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
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+ #if defined(STM32U0 )
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+ #define RCC_SYSCLKSOURCE_STATUS_PLLR RCC_SYSCLKSOURCE_STATUS_PLLCLK
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+ #endif
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+
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#if defined(STM32L4 ) || defined(STM32WB ) || defined(STM32G0 ) || defined(STM32G4 ) || defined(STM32L5 ) || \
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- defined(STM32WL ) || defined(STM32C0 )
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+ defined(STM32WL ) || defined(STM32C0 ) || defined( STM32H7RS ) || defined( STM32U0 )
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#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
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#else
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#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
@@ -3749,8 +3784,10 @@ extern "C" {
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#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE
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#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
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#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1
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+ #if !defined(STM32U0 )
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#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1
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#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1
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+ #endif
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#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1
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#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2
@@ -3894,9 +3931,9 @@ extern "C" {
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/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
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* @{
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*/
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- #if defined (STM32G0 ) || defined (STM32L5 ) || defined (STM32L412xx ) || defined (STM32L422xx ) || \
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- defined (STM32L4P5xx ) || defined (STM32L4Q5xx ) || defined (STM32G4 ) || defined (STM32WL ) || defined (STM32U5 ) || \
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- defined (STM32WBA ) || defined (STM32H5 ) || defined (STM32C0 )
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+ #if defined (STM32G0 ) || defined (STM32L5 ) || defined (STM32L412xx ) || defined (STM32L422xx ) || defined ( STM32L4P5xx ) || \
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+ defined (STM32L4Q5xx ) || defined (STM32G4 ) || defined (STM32WL ) || defined (STM32U5 ) || defined (STM32WBA ) || \
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+ defined (STM32H5 ) || defined (STM32C0 ) || defined (STM32H7RS ) || defined ( STM32U0 )
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#else
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#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
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#endif
@@ -3932,7 +3969,9 @@ extern "C" {
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#endif /* STM32F1 */
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#if defined (STM32F0 ) || defined (STM32F2 ) || defined (STM32F3 ) || defined (STM32F4 ) || defined (STM32F7 ) || \
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- defined (STM32L0 ) || defined (STM32L1 )
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+ defined (STM32H7 ) || \
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+ defined (STM32L0 ) || defined (STM32L1 ) || \
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+ defined (STM32WB )
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#define __HAL_RTC_TAMPER_GET_IT __HAL_RTC_TAMPER_GET_FLAG
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#endif
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@@ -4217,6 +4256,9 @@ extern "C" {
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#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE
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#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1
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+
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+ #define TIM_OCMODE_ASSYMETRIC_PWM1 TIM_OCMODE_ASYMMETRIC_PWM1
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+ #define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_OCMODE_ASYMMETRIC_PWM2
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/**
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* @}
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*/
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