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system(G4): update STM32G4xx CMSIS Drivers to v1.2.3
Included in STM32CubeG4 FW v1.5.2 Signed-off-by: Frederic Pillon <[email protected]>
1 parent fa5f52a commit 8779de8

28 files changed

+499
-480
lines changed

Diff for: ‎system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h

+7-21
Original file line numberDiff line numberDiff line change
@@ -699,8 +699,7 @@ typedef struct
699699

700700
typedef struct
701701
{
702-
__IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
703-
uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */
702+
uint32_t RESERVED[17]; /*!< Reserved, Address offset: 0x00 to 0x40 */
704703
__IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */
705704
__IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */
706705
} SAI_TypeDef;
@@ -1216,7 +1215,7 @@ typedef struct
12161215
/******************************************************************************/
12171216

12181217
/*
1219-
* @brief Specific device feature definitions (not present on all devices in the STM32G4 serie)
1218+
* @brief Specific device feature definitions (not present on all devices in the STM32G4 series)
12201219
*/
12211220
#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */
12221221

@@ -1362,7 +1361,7 @@ typedef struct
13621361
#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */
13631362
#define ADC_CFGR_ALIGN_Pos (15U)
13641363
#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00008000 */
1365-
#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */
1364+
#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */
13661365
#define ADC_CFGR_DISCEN_Pos (16U)
13671366
#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */
13681367
#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */
@@ -4063,7 +4062,7 @@ typedef struct
40634062
/***************** Bit definition for FDCAN_ENDN register *******************/
40644063
#define FDCAN_ENDN_ETV_Pos (0U)
40654064
#define FDCAN_ENDN_ETV_Msk (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos) /*!< 0xFFFFFFFF */
4066-
#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endiannes Test Value */
4065+
#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endianness Test Value */
40674066

40684067
/***************** Bit definition for FDCAN_DBTP register *******************/
40694068
#define FDCAN_DBTP_DSJW_Pos (0U)
@@ -6372,7 +6371,7 @@ typedef struct
63726371
#define OPAMP_CSR_TRIMOFFSETN OPAMP_CSR_TRIMOFFSETN_Msk /*!< Offset trimming value (NMOS) */
63736372
#define OPAMP_CSR_OUTCAL_Pos (30U)
63746373
#define OPAMP_CSR_OUTCAL_Msk (0x1UL << OPAMP_CSR_OUTCAL_Pos) /*!< 0x40000000 */
6375-
#define OPAMP_CSR_OUTCAL OPAMP_CSR_OUTCAL_Msk /*!< OPAMP ouput status flag */
6374+
#define OPAMP_CSR_OUTCAL OPAMP_CSR_OUTCAL_Msk /*!< OPAMP output status flag */
63766375
#define OPAMP_CSR_LOCK_Pos (31U)
63776376
#define OPAMP_CSR_LOCK_Msk (0x1UL << OPAMP_CSR_LOCK_Pos) /*!< 0x80000000 */
63786377
#define OPAMP_CSR_LOCK OPAMP_CSR_LOCK_Msk /*!< OPAMP control/status register lock */
@@ -7225,7 +7224,7 @@ typedef struct
72257224
/* */
72267225
/******************************************************************************/
72277226
/*
7228-
* @brief Specific device feature definitions (not present on all devices in the STM32G4 serie)
7227+
* @brief Specific device feature definitions (not present on all devices in the STM32G4 series)
72297228
*/
72307229

72317230
#define RCC_HSI48_SUPPORT
@@ -9050,19 +9049,6 @@ typedef struct
90509049
/* Serial Audio Interface */
90519050
/* */
90529051
/******************************************************************************/
9053-
/******************** Bit definition for SAI_GCR register *******************/
9054-
#define SAI_GCR_SYNCIN_Pos (0U)
9055-
#define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */
9056-
#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
9057-
#define SAI_GCR_SYNCIN_0 (0x1UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000001 */
9058-
#define SAI_GCR_SYNCIN_1 (0x2UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000002 */
9059-
9060-
#define SAI_GCR_SYNCOUT_Pos (4U)
9061-
#define SAI_GCR_SYNCOUT_Msk (0x3UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000030 */
9062-
#define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
9063-
#define SAI_GCR_SYNCOUT_0 (0x1UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000010 */
9064-
#define SAI_GCR_SYNCOUT_1 (0x2UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000020 */
9065-
90669052
/******************* Bit definition for SAI_xCR1 register *******************/
90679053
#define SAI_xCR1_MODE_Pos (0U)
90689054
#define SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */
@@ -9403,7 +9389,7 @@ typedef struct
94039389
/* */
94049390
/******************************************************************************/
94059391
/*
9406-
* @brief Specific device feature definitions (not present on all devices in the STM32G4 serie)
9392+
* @brief Specific device feature definitions (not present on all devices in the STM32G4 series)
94079393
*/
94089394
#define SPI_I2S_SUPPORT /*!< I2S support */
94099395

Diff for: ‎system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g441xx.h

+7-21
Original file line numberDiff line numberDiff line change
@@ -700,8 +700,7 @@ typedef struct
700700

701701
typedef struct
702702
{
703-
__IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
704-
uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */
703+
uint32_t RESERVED[17]; /*!< Reserved, Address offset: 0x00 to 0x40 */
705704
__IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */
706705
__IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */
707706
} SAI_TypeDef;
@@ -1250,7 +1249,7 @@ typedef struct
12501249
/******************************************************************************/
12511250

12521251
/*
1253-
* @brief Specific device feature definitions (not present on all devices in the STM32G4 serie)
1252+
* @brief Specific device feature definitions (not present on all devices in the STM32G4 series)
12541253
*/
12551254
#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */
12561255

@@ -1396,7 +1395,7 @@ typedef struct
13961395
#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */
13971396
#define ADC_CFGR_ALIGN_Pos (15U)
13981397
#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00008000 */
1399-
#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */
1398+
#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */
14001399
#define ADC_CFGR_DISCEN_Pos (16U)
14011400
#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */
14021401
#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */
@@ -4284,7 +4283,7 @@ typedef struct
42844283
/***************** Bit definition for FDCAN_ENDN register *******************/
42854284
#define FDCAN_ENDN_ETV_Pos (0U)
42864285
#define FDCAN_ENDN_ETV_Msk (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos) /*!< 0xFFFFFFFF */
4287-
#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endiannes Test Value */
4286+
#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endianness Test Value */
42884287

42894288
/***************** Bit definition for FDCAN_DBTP register *******************/
42904289
#define FDCAN_DBTP_DSJW_Pos (0U)
@@ -6593,7 +6592,7 @@ typedef struct
65936592
#define OPAMP_CSR_TRIMOFFSETN OPAMP_CSR_TRIMOFFSETN_Msk /*!< Offset trimming value (NMOS) */
65946593
#define OPAMP_CSR_OUTCAL_Pos (30U)
65956594
#define OPAMP_CSR_OUTCAL_Msk (0x1UL << OPAMP_CSR_OUTCAL_Pos) /*!< 0x40000000 */
6596-
#define OPAMP_CSR_OUTCAL OPAMP_CSR_OUTCAL_Msk /*!< OPAMP ouput status flag */
6595+
#define OPAMP_CSR_OUTCAL OPAMP_CSR_OUTCAL_Msk /*!< OPAMP output status flag */
65976596
#define OPAMP_CSR_LOCK_Pos (31U)
65986597
#define OPAMP_CSR_LOCK_Msk (0x1UL << OPAMP_CSR_LOCK_Pos) /*!< 0x80000000 */
65996598
#define OPAMP_CSR_LOCK OPAMP_CSR_LOCK_Msk /*!< OPAMP control/status register lock */
@@ -7446,7 +7445,7 @@ typedef struct
74467445
/* */
74477446
/******************************************************************************/
74487447
/*
7449-
* @brief Specific device feature definitions (not present on all devices in the STM32G4 serie)
7448+
* @brief Specific device feature definitions (not present on all devices in the STM32G4 series)
74507449
*/
74517450

74527451
#define RCC_HSI48_SUPPORT
@@ -9280,19 +9279,6 @@ typedef struct
92809279
/* Serial Audio Interface */
92819280
/* */
92829281
/******************************************************************************/
9283-
/******************** Bit definition for SAI_GCR register *******************/
9284-
#define SAI_GCR_SYNCIN_Pos (0U)
9285-
#define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */
9286-
#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
9287-
#define SAI_GCR_SYNCIN_0 (0x1UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000001 */
9288-
#define SAI_GCR_SYNCIN_1 (0x2UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000002 */
9289-
9290-
#define SAI_GCR_SYNCOUT_Pos (4U)
9291-
#define SAI_GCR_SYNCOUT_Msk (0x3UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000030 */
9292-
#define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
9293-
#define SAI_GCR_SYNCOUT_0 (0x1UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000010 */
9294-
#define SAI_GCR_SYNCOUT_1 (0x2UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000020 */
9295-
92969282
/******************* Bit definition for SAI_xCR1 register *******************/
92979283
#define SAI_xCR1_MODE_Pos (0U)
92989284
#define SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */
@@ -9633,7 +9619,7 @@ typedef struct
96339619
/* */
96349620
/******************************************************************************/
96359621
/*
9636-
* @brief Specific device feature definitions (not present on all devices in the STM32G4 serie)
9622+
* @brief Specific device feature definitions (not present on all devices in the STM32G4 series)
96379623
*/
96389624
#define SPI_I2S_SUPPORT /*!< I2S support */
96399625

Diff for: ‎system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g471xx.h

+7-21
Original file line numberDiff line numberDiff line change
@@ -757,8 +757,7 @@ typedef struct
757757

758758
typedef struct
759759
{
760-
__IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
761-
uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */
760+
uint32_t RESERVED[17]; /*!< Reserved, Address offset: 0x00 to 0x40 */
762761
__IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */
763762
__IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */
764763
} SAI_TypeDef;
@@ -1307,7 +1306,7 @@ typedef struct
13071306
/******************************************************************************/
13081307

13091308
/*
1310-
* @brief Specific device feature definitions (not present on all devices in the STM32G4 serie)
1309+
* @brief Specific device feature definitions (not present on all devices in the STM32G4 series)
13111310
*/
13121311
#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */
13131312

@@ -1453,7 +1452,7 @@ typedef struct
14531452
#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */
14541453
#define ADC_CFGR_ALIGN_Pos (15U)
14551454
#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00008000 */
1456-
#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */
1455+
#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */
14571456
#define ADC_CFGR_DISCEN_Pos (16U)
14581457
#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */
14591458
#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */
@@ -4245,7 +4244,7 @@ typedef struct
42454244
/***************** Bit definition for FDCAN_ENDN register *******************/
42464245
#define FDCAN_ENDN_ETV_Pos (0U)
42474246
#define FDCAN_ENDN_ETV_Msk (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos) /*!< 0xFFFFFFFF */
4248-
#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endiannes Test Value */
4247+
#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endianness Test Value */
42494248

42504249
/***************** Bit definition for FDCAN_DBTP register *******************/
42514250
#define FDCAN_DBTP_DSJW_Pos (0U)
@@ -6607,7 +6606,7 @@ typedef struct
66076606
#define OPAMP_CSR_TRIMOFFSETN OPAMP_CSR_TRIMOFFSETN_Msk /*!< Offset trimming value (NMOS) */
66086607
#define OPAMP_CSR_OUTCAL_Pos (30U)
66096608
#define OPAMP_CSR_OUTCAL_Msk (0x1UL << OPAMP_CSR_OUTCAL_Pos) /*!< 0x40000000 */
6610-
#define OPAMP_CSR_OUTCAL OPAMP_CSR_OUTCAL_Msk /*!< OPAMP ouput status flag */
6609+
#define OPAMP_CSR_OUTCAL OPAMP_CSR_OUTCAL_Msk /*!< OPAMP output status flag */
66116610
#define OPAMP_CSR_LOCK_Pos (31U)
66126611
#define OPAMP_CSR_LOCK_Msk (0x1UL << OPAMP_CSR_LOCK_Pos) /*!< 0x80000000 */
66136612
#define OPAMP_CSR_LOCK OPAMP_CSR_LOCK_Msk /*!< OPAMP control/status register lock */
@@ -7735,7 +7734,7 @@ typedef struct
77357734
/* */
77367735
/******************************************************************************/
77377736
/*
7738-
* @brief Specific device feature definitions (not present on all devices in the STM32G4 serie)
7737+
* @brief Specific device feature definitions (not present on all devices in the STM32G4 series)
77397738
*/
77407739

77417740
#define RCC_HSI48_SUPPORT
@@ -9714,19 +9713,6 @@ typedef struct
97149713
/* Serial Audio Interface */
97159714
/* */
97169715
/******************************************************************************/
9717-
/******************** Bit definition for SAI_GCR register *******************/
9718-
#define SAI_GCR_SYNCIN_Pos (0U)
9719-
#define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */
9720-
#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
9721-
#define SAI_GCR_SYNCIN_0 (0x1UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000001 */
9722-
#define SAI_GCR_SYNCIN_1 (0x2UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000002 */
9723-
9724-
#define SAI_GCR_SYNCOUT_Pos (4U)
9725-
#define SAI_GCR_SYNCOUT_Msk (0x3UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000030 */
9726-
#define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
9727-
#define SAI_GCR_SYNCOUT_0 (0x1UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000010 */
9728-
#define SAI_GCR_SYNCOUT_1 (0x2UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000020 */
9729-
97309716
/******************* Bit definition for SAI_xCR1 register *******************/
97319717
#define SAI_xCR1_MODE_Pos (0U)
97329718
#define SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */
@@ -10067,7 +10053,7 @@ typedef struct
1006710053
/* */
1006810054
/******************************************************************************/
1006910055
/*
10070-
* @brief Specific device feature definitions (not present on all devices in the STM32G4 serie)
10056+
* @brief Specific device feature definitions (not present on all devices in the STM32G4 series)
1007110057
*/
1007210058
#define SPI_I2S_SUPPORT /*!< I2S support */
1007310059

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