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fpistmfpistm
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Merge pull request #1761 from TDhaouST/update_F7_Serie
Update f7xx HAL drivers and CMSIS
2 parents 251b502 + 9b1b030 commit 82ccde0

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113 files changed

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Diff for: ‎libraries/SrcWrapper/src/HAL/stm32yyxx_hal_eth.c

+1
Original file line numberDiff line numberDiff line change
@@ -10,6 +10,7 @@
1010
#include "Legacy/stm32f4xx_hal_eth.c"
1111
#include "stm32f4xx_hal_eth.c"
1212
#elif STM32F7xx
13+
#include "Legacy/stm32f7xx_hal_eth.c"
1314
#include "stm32f7xx_hal_eth.c"
1415
#elif STM32H7xx
1516
#include "Legacy/stm32h7xx_hal_eth.c"

Diff for: ‎system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f745xx.h

+30-24
Original file line numberDiff line numberDiff line change
@@ -15153,33 +15153,36 @@ typedef struct
1515315153
/******************************************************************************/
1515415154

1515515155
/* Bit definition for Ethernet PTP Time Stamp Contol Register */
15156+
#define ETH_PTPTSCR_TSPFFMAE_Pos (18U)
15157+
#define ETH_PTPTSCR_TSPFFMAE_Msk (0x1UL << ETH_PTPTSCR_TSPFFMAE_Pos) /*!< 0x00008000 */
15158+
#define ETH_PTPTSCR_TSPFFMAE ETH_PTPTSCR_TSPFFMAE_Msk /* Time stamp PTP frame filtering MAC address enable */
1515615159
#define ETH_PTPTSCR_TSCNT_Pos (16U)
1515715160
#define ETH_PTPTSCR_TSCNT_Msk (0x3UL << ETH_PTPTSCR_TSCNT_Pos) /*!< 0x00030000 */
1515815161
#define ETH_PTPTSCR_TSCNT ETH_PTPTSCR_TSCNT_Msk /* Time stamp clock node type */
15159-
#define ETH_PTPTSSR_TSSMRME_Pos (15U)
15160-
#define ETH_PTPTSSR_TSSMRME_Msk (0x1UL << ETH_PTPTSSR_TSSMRME_Pos) /*!< 0x00008000 */
15161-
#define ETH_PTPTSSR_TSSMRME ETH_PTPTSSR_TSSMRME_Msk /* Time stamp snapshot for message relevant to master enable */
15162-
#define ETH_PTPTSSR_TSSEME_Pos (14U)
15163-
#define ETH_PTPTSSR_TSSEME_Msk (0x1UL << ETH_PTPTSSR_TSSEME_Pos) /*!< 0x00004000 */
15164-
#define ETH_PTPTSSR_TSSEME ETH_PTPTSSR_TSSEME_Msk /* Time stamp snapshot for event message enable */
15165-
#define ETH_PTPTSSR_TSSIPV4FE_Pos (13U)
15166-
#define ETH_PTPTSSR_TSSIPV4FE_Msk (0x1UL << ETH_PTPTSSR_TSSIPV4FE_Pos) /*!< 0x00002000 */
15167-
#define ETH_PTPTSSR_TSSIPV4FE ETH_PTPTSSR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */
15168-
#define ETH_PTPTSSR_TSSIPV6FE_Pos (12U)
15169-
#define ETH_PTPTSSR_TSSIPV6FE_Msk (0x1UL << ETH_PTPTSSR_TSSIPV6FE_Pos) /*!< 0x00001000 */
15170-
#define ETH_PTPTSSR_TSSIPV6FE ETH_PTPTSSR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */
15171-
#define ETH_PTPTSSR_TSSPTPOEFE_Pos (11U)
15172-
#define ETH_PTPTSSR_TSSPTPOEFE_Msk (0x1UL << ETH_PTPTSSR_TSSPTPOEFE_Pos) /*!< 0x00000800 */
15173-
#define ETH_PTPTSSR_TSSPTPOEFE ETH_PTPTSSR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */
15174-
#define ETH_PTPTSSR_TSPTPPSV2E_Pos (10U)
15175-
#define ETH_PTPTSSR_TSPTPPSV2E_Msk (0x1UL << ETH_PTPTSSR_TSPTPPSV2E_Pos) /*!< 0x00000400 */
15176-
#define ETH_PTPTSSR_TSPTPPSV2E ETH_PTPTSSR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */
15177-
#define ETH_PTPTSSR_TSSSR_Pos (9U)
15178-
#define ETH_PTPTSSR_TSSSR_Msk (0x1UL << ETH_PTPTSSR_TSSSR_Pos) /*!< 0x00000200 */
15179-
#define ETH_PTPTSSR_TSSSR ETH_PTPTSSR_TSSSR_Msk /* Time stamp Sub-seconds rollover */
15180-
#define ETH_PTPTSSR_TSSARFE_Pos (8U)
15181-
#define ETH_PTPTSSR_TSSARFE_Msk (0x1UL << ETH_PTPTSSR_TSSARFE_Pos) /*!< 0x00000100 */
15182-
#define ETH_PTPTSSR_TSSARFE ETH_PTPTSSR_TSSARFE_Msk /* Time stamp snapshot for all received frames enable */
15162+
#define ETH_PTPTSCR_TSSMRME_Pos (15U)
15163+
#define ETH_PTPTSCR_TSSMRME_Msk (0x1UL << ETH_PTPTSCR_TSSMRME_Pos) /*!< 0x00008000 */
15164+
#define ETH_PTPTSCR_TSSMRME ETH_PTPTSCR_TSSMRME_Msk /* Time stamp snapshot for message relevant to master enable */
15165+
#define ETH_PTPTSCR_TSSEME_Pos (14U)
15166+
#define ETH_PTPTSCR_TSSEME_Msk (0x1UL << ETH_PTPTSCR_TSSEME_Pos) /*!< 0x00004000 */
15167+
#define ETH_PTPTSCR_TSSEME ETH_PTPTSCR_TSSEME_Msk /* Time stamp snapshot for event message enable */
15168+
#define ETH_PTPTSCR_TSSIPV4FE_Pos (13U)
15169+
#define ETH_PTPTSCR_TSSIPV4FE_Msk (0x1UL << ETH_PTPTSCR_TSSIPV4FE_Pos) /*!< 0x00002000 */
15170+
#define ETH_PTPTSCR_TSSIPV4FE ETH_PTPTSCR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */
15171+
#define ETH_PTPTSCR_TSSIPV6FE_Pos (12U)
15172+
#define ETH_PTPTSCR_TSSIPV6FE_Msk (0x1UL << ETH_PTPTSCR_TSSIPV6FE_Pos) /*!< 0x00001000 */
15173+
#define ETH_PTPTSCR_TSSIPV6FE ETH_PTPTSCR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */
15174+
#define ETH_PTPTSCR_TSSPTPOEFE_Pos (11U)
15175+
#define ETH_PTPTSCR_TSSPTPOEFE_Msk (0x1UL << ETH_PTPTSCR_TSSPTPOEFE_Pos) /*!< 0x00000800 */
15176+
#define ETH_PTPTSCR_TSSPTPOEFE ETH_PTPTSCR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */
15177+
#define ETH_PTPTSCR_TSPTPPSV2E_Pos (10U)
15178+
#define ETH_PTPTSCR_TSPTPPSV2E_Msk (0x1UL << ETH_PTPTSCR_TSPTPPSV2E_Pos) /*!< 0x00000400 */
15179+
#define ETH_PTPTSCR_TSPTPPSV2E ETH_PTPTSCR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */
15180+
#define ETH_PTPTSCR_TSSSR_Pos (9U)
15181+
#define ETH_PTPTSCR_TSSSR_Msk (0x1UL << ETH_PTPTSCR_TSSSR_Pos) /*!< 0x00000200 */
15182+
#define ETH_PTPTSCR_TSSSR ETH_PTPTSCR_TSSSR_Msk /* Time stamp Sub-seconds rollover */
15183+
#define ETH_PTPTSCR_TSSARFE_Pos (8U)
15184+
#define ETH_PTPTSCR_TSSARFE_Msk (0x1UL << ETH_PTPTSCR_TSSARFE_Pos) /*!< 0x00000100 */
15185+
#define ETH_PTPTSCR_TSSARFE ETH_PTPTSCR_TSSARFE_Msk /* Time stamp snapshot for all received frames enable */
1518315186

1518415187
#define ETH_PTPTSCR_TSARU_Pos (5U)
1518515188
#define ETH_PTPTSCR_TSARU_Msk (0x1UL << ETH_PTPTSCR_TSARU_Pos) /*!< 0x00000020 */
@@ -15264,6 +15267,9 @@ typedef struct
1526415267
/******************************************************************************/
1526515268

1526615269
/* Bit definition for Ethernet DMA Bus Mode Register */
15270+
#define ETH_DMABMR_MB_Pos (26U)
15271+
#define ETH_DMABMR_MB_Msk (0x1UL << ETH_DMABMR_MB_Pos) /*!< 0x04000000 */
15272+
#define ETH_DMABMR_MB ETH_DMABMR_MB_Msk /* Mixed Burst */
1526715273
#define ETH_DMABMR_AAB_Pos (25U)
1526815274
#define ETH_DMABMR_AAB_Msk (0x1UL << ETH_DMABMR_AAB_Pos) /*!< 0x02000000 */
1526915275
#define ETH_DMABMR_AAB ETH_DMABMR_AAB_Msk /* Address-Aligned beats */

Diff for: ‎system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h

+30-24
Original file line numberDiff line numberDiff line change
@@ -15501,33 +15501,36 @@ typedef struct
1550115501
/******************************************************************************/
1550215502

1550315503
/* Bit definition for Ethernet PTP Time Stamp Contol Register */
15504+
#define ETH_PTPTSCR_TSPFFMAE_Pos (18U)
15505+
#define ETH_PTPTSCR_TSPFFMAE_Msk (0x1UL << ETH_PTPTSCR_TSPFFMAE_Pos) /*!< 0x00008000 */
15506+
#define ETH_PTPTSCR_TSPFFMAE ETH_PTPTSCR_TSPFFMAE_Msk /* Time stamp PTP frame filtering MAC address enable */
1550415507
#define ETH_PTPTSCR_TSCNT_Pos (16U)
1550515508
#define ETH_PTPTSCR_TSCNT_Msk (0x3UL << ETH_PTPTSCR_TSCNT_Pos) /*!< 0x00030000 */
1550615509
#define ETH_PTPTSCR_TSCNT ETH_PTPTSCR_TSCNT_Msk /* Time stamp clock node type */
15507-
#define ETH_PTPTSSR_TSSMRME_Pos (15U)
15508-
#define ETH_PTPTSSR_TSSMRME_Msk (0x1UL << ETH_PTPTSSR_TSSMRME_Pos) /*!< 0x00008000 */
15509-
#define ETH_PTPTSSR_TSSMRME ETH_PTPTSSR_TSSMRME_Msk /* Time stamp snapshot for message relevant to master enable */
15510-
#define ETH_PTPTSSR_TSSEME_Pos (14U)
15511-
#define ETH_PTPTSSR_TSSEME_Msk (0x1UL << ETH_PTPTSSR_TSSEME_Pos) /*!< 0x00004000 */
15512-
#define ETH_PTPTSSR_TSSEME ETH_PTPTSSR_TSSEME_Msk /* Time stamp snapshot for event message enable */
15513-
#define ETH_PTPTSSR_TSSIPV4FE_Pos (13U)
15514-
#define ETH_PTPTSSR_TSSIPV4FE_Msk (0x1UL << ETH_PTPTSSR_TSSIPV4FE_Pos) /*!< 0x00002000 */
15515-
#define ETH_PTPTSSR_TSSIPV4FE ETH_PTPTSSR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */
15516-
#define ETH_PTPTSSR_TSSIPV6FE_Pos (12U)
15517-
#define ETH_PTPTSSR_TSSIPV6FE_Msk (0x1UL << ETH_PTPTSSR_TSSIPV6FE_Pos) /*!< 0x00001000 */
15518-
#define ETH_PTPTSSR_TSSIPV6FE ETH_PTPTSSR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */
15519-
#define ETH_PTPTSSR_TSSPTPOEFE_Pos (11U)
15520-
#define ETH_PTPTSSR_TSSPTPOEFE_Msk (0x1UL << ETH_PTPTSSR_TSSPTPOEFE_Pos) /*!< 0x00000800 */
15521-
#define ETH_PTPTSSR_TSSPTPOEFE ETH_PTPTSSR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */
15522-
#define ETH_PTPTSSR_TSPTPPSV2E_Pos (10U)
15523-
#define ETH_PTPTSSR_TSPTPPSV2E_Msk (0x1UL << ETH_PTPTSSR_TSPTPPSV2E_Pos) /*!< 0x00000400 */
15524-
#define ETH_PTPTSSR_TSPTPPSV2E ETH_PTPTSSR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */
15525-
#define ETH_PTPTSSR_TSSSR_Pos (9U)
15526-
#define ETH_PTPTSSR_TSSSR_Msk (0x1UL << ETH_PTPTSSR_TSSSR_Pos) /*!< 0x00000200 */
15527-
#define ETH_PTPTSSR_TSSSR ETH_PTPTSSR_TSSSR_Msk /* Time stamp Sub-seconds rollover */
15528-
#define ETH_PTPTSSR_TSSARFE_Pos (8U)
15529-
#define ETH_PTPTSSR_TSSARFE_Msk (0x1UL << ETH_PTPTSSR_TSSARFE_Pos) /*!< 0x00000100 */
15530-
#define ETH_PTPTSSR_TSSARFE ETH_PTPTSSR_TSSARFE_Msk /* Time stamp snapshot for all received frames enable */
15510+
#define ETH_PTPTSCR_TSSMRME_Pos (15U)
15511+
#define ETH_PTPTSCR_TSSMRME_Msk (0x1UL << ETH_PTPTSCR_TSSMRME_Pos) /*!< 0x00008000 */
15512+
#define ETH_PTPTSCR_TSSMRME ETH_PTPTSCR_TSSMRME_Msk /* Time stamp snapshot for message relevant to master enable */
15513+
#define ETH_PTPTSCR_TSSEME_Pos (14U)
15514+
#define ETH_PTPTSCR_TSSEME_Msk (0x1UL << ETH_PTPTSCR_TSSEME_Pos) /*!< 0x00004000 */
15515+
#define ETH_PTPTSCR_TSSEME ETH_PTPTSCR_TSSEME_Msk /* Time stamp snapshot for event message enable */
15516+
#define ETH_PTPTSCR_TSSIPV4FE_Pos (13U)
15517+
#define ETH_PTPTSCR_TSSIPV4FE_Msk (0x1UL << ETH_PTPTSCR_TSSIPV4FE_Pos) /*!< 0x00002000 */
15518+
#define ETH_PTPTSCR_TSSIPV4FE ETH_PTPTSCR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */
15519+
#define ETH_PTPTSCR_TSSIPV6FE_Pos (12U)
15520+
#define ETH_PTPTSCR_TSSIPV6FE_Msk (0x1UL << ETH_PTPTSCR_TSSIPV6FE_Pos) /*!< 0x00001000 */
15521+
#define ETH_PTPTSCR_TSSIPV6FE ETH_PTPTSCR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */
15522+
#define ETH_PTPTSCR_TSSPTPOEFE_Pos (11U)
15523+
#define ETH_PTPTSCR_TSSPTPOEFE_Msk (0x1UL << ETH_PTPTSCR_TSSPTPOEFE_Pos) /*!< 0x00000800 */
15524+
#define ETH_PTPTSCR_TSSPTPOEFE ETH_PTPTSCR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */
15525+
#define ETH_PTPTSCR_TSPTPPSV2E_Pos (10U)
15526+
#define ETH_PTPTSCR_TSPTPPSV2E_Msk (0x1UL << ETH_PTPTSCR_TSPTPPSV2E_Pos) /*!< 0x00000400 */
15527+
#define ETH_PTPTSCR_TSPTPPSV2E ETH_PTPTSCR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */
15528+
#define ETH_PTPTSCR_TSSSR_Pos (9U)
15529+
#define ETH_PTPTSCR_TSSSR_Msk (0x1UL << ETH_PTPTSCR_TSSSR_Pos) /*!< 0x00000200 */
15530+
#define ETH_PTPTSCR_TSSSR ETH_PTPTSCR_TSSSR_Msk /* Time stamp Sub-seconds rollover */
15531+
#define ETH_PTPTSCR_TSSARFE_Pos (8U)
15532+
#define ETH_PTPTSCR_TSSARFE_Msk (0x1UL << ETH_PTPTSCR_TSSARFE_Pos) /*!< 0x00000100 */
15533+
#define ETH_PTPTSCR_TSSARFE ETH_PTPTSCR_TSSARFE_Msk /* Time stamp snapshot for all received frames enable */
1553115534

1553215535
#define ETH_PTPTSCR_TSARU_Pos (5U)
1553315536
#define ETH_PTPTSCR_TSARU_Msk (0x1UL << ETH_PTPTSCR_TSARU_Pos) /*!< 0x00000020 */
@@ -15612,6 +15615,9 @@ typedef struct
1561215615
/******************************************************************************/
1561315616

1561415617
/* Bit definition for Ethernet DMA Bus Mode Register */
15618+
#define ETH_DMABMR_MB_Pos (26U)
15619+
#define ETH_DMABMR_MB_Msk (0x1UL << ETH_DMABMR_MB_Pos) /*!< 0x04000000 */
15620+
#define ETH_DMABMR_MB ETH_DMABMR_MB_Msk /* Mixed Burst */
1561515621
#define ETH_DMABMR_AAB_Pos (25U)
1561615622
#define ETH_DMABMR_AAB_Msk (0x1UL << ETH_DMABMR_AAB_Pos) /*!< 0x02000000 */
1561715623
#define ETH_DMABMR_AAB ETH_DMABMR_AAB_Msk /* Address-Aligned beats */

Diff for: ‎system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f750xx.h

+30-24
Original file line numberDiff line numberDiff line change
@@ -15794,33 +15794,36 @@ typedef struct
1579415794
/******************************************************************************/
1579515795

1579615796
/* Bit definition for Ethernet PTP Time Stamp Contol Register */
15797+
#define ETH_PTPTSCR_TSPFFMAE_Pos (18U)
15798+
#define ETH_PTPTSCR_TSPFFMAE_Msk (0x1UL << ETH_PTPTSCR_TSPFFMAE_Pos) /*!< 0x00008000 */
15799+
#define ETH_PTPTSCR_TSPFFMAE ETH_PTPTSCR_TSPFFMAE_Msk /* Time stamp PTP frame filtering MAC address enable */
1579715800
#define ETH_PTPTSCR_TSCNT_Pos (16U)
1579815801
#define ETH_PTPTSCR_TSCNT_Msk (0x3UL << ETH_PTPTSCR_TSCNT_Pos) /*!< 0x00030000 */
1579915802
#define ETH_PTPTSCR_TSCNT ETH_PTPTSCR_TSCNT_Msk /* Time stamp clock node type */
15800-
#define ETH_PTPTSSR_TSSMRME_Pos (15U)
15801-
#define ETH_PTPTSSR_TSSMRME_Msk (0x1UL << ETH_PTPTSSR_TSSMRME_Pos) /*!< 0x00008000 */
15802-
#define ETH_PTPTSSR_TSSMRME ETH_PTPTSSR_TSSMRME_Msk /* Time stamp snapshot for message relevant to master enable */
15803-
#define ETH_PTPTSSR_TSSEME_Pos (14U)
15804-
#define ETH_PTPTSSR_TSSEME_Msk (0x1UL << ETH_PTPTSSR_TSSEME_Pos) /*!< 0x00004000 */
15805-
#define ETH_PTPTSSR_TSSEME ETH_PTPTSSR_TSSEME_Msk /* Time stamp snapshot for event message enable */
15806-
#define ETH_PTPTSSR_TSSIPV4FE_Pos (13U)
15807-
#define ETH_PTPTSSR_TSSIPV4FE_Msk (0x1UL << ETH_PTPTSSR_TSSIPV4FE_Pos) /*!< 0x00002000 */
15808-
#define ETH_PTPTSSR_TSSIPV4FE ETH_PTPTSSR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */
15809-
#define ETH_PTPTSSR_TSSIPV6FE_Pos (12U)
15810-
#define ETH_PTPTSSR_TSSIPV6FE_Msk (0x1UL << ETH_PTPTSSR_TSSIPV6FE_Pos) /*!< 0x00001000 */
15811-
#define ETH_PTPTSSR_TSSIPV6FE ETH_PTPTSSR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */
15812-
#define ETH_PTPTSSR_TSSPTPOEFE_Pos (11U)
15813-
#define ETH_PTPTSSR_TSSPTPOEFE_Msk (0x1UL << ETH_PTPTSSR_TSSPTPOEFE_Pos) /*!< 0x00000800 */
15814-
#define ETH_PTPTSSR_TSSPTPOEFE ETH_PTPTSSR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */
15815-
#define ETH_PTPTSSR_TSPTPPSV2E_Pos (10U)
15816-
#define ETH_PTPTSSR_TSPTPPSV2E_Msk (0x1UL << ETH_PTPTSSR_TSPTPPSV2E_Pos) /*!< 0x00000400 */
15817-
#define ETH_PTPTSSR_TSPTPPSV2E ETH_PTPTSSR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */
15818-
#define ETH_PTPTSSR_TSSSR_Pos (9U)
15819-
#define ETH_PTPTSSR_TSSSR_Msk (0x1UL << ETH_PTPTSSR_TSSSR_Pos) /*!< 0x00000200 */
15820-
#define ETH_PTPTSSR_TSSSR ETH_PTPTSSR_TSSSR_Msk /* Time stamp Sub-seconds rollover */
15821-
#define ETH_PTPTSSR_TSSARFE_Pos (8U)
15822-
#define ETH_PTPTSSR_TSSARFE_Msk (0x1UL << ETH_PTPTSSR_TSSARFE_Pos) /*!< 0x00000100 */
15823-
#define ETH_PTPTSSR_TSSARFE ETH_PTPTSSR_TSSARFE_Msk /* Time stamp snapshot for all received frames enable */
15803+
#define ETH_PTPTSCR_TSSMRME_Pos (15U)
15804+
#define ETH_PTPTSCR_TSSMRME_Msk (0x1UL << ETH_PTPTSCR_TSSMRME_Pos) /*!< 0x00008000 */
15805+
#define ETH_PTPTSCR_TSSMRME ETH_PTPTSCR_TSSMRME_Msk /* Time stamp snapshot for message relevant to master enable */
15806+
#define ETH_PTPTSCR_TSSEME_Pos (14U)
15807+
#define ETH_PTPTSCR_TSSEME_Msk (0x1UL << ETH_PTPTSCR_TSSEME_Pos) /*!< 0x00004000 */
15808+
#define ETH_PTPTSCR_TSSEME ETH_PTPTSCR_TSSEME_Msk /* Time stamp snapshot for event message enable */
15809+
#define ETH_PTPTSCR_TSSIPV4FE_Pos (13U)
15810+
#define ETH_PTPTSCR_TSSIPV4FE_Msk (0x1UL << ETH_PTPTSCR_TSSIPV4FE_Pos) /*!< 0x00002000 */
15811+
#define ETH_PTPTSCR_TSSIPV4FE ETH_PTPTSCR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */
15812+
#define ETH_PTPTSCR_TSSIPV6FE_Pos (12U)
15813+
#define ETH_PTPTSCR_TSSIPV6FE_Msk (0x1UL << ETH_PTPTSCR_TSSIPV6FE_Pos) /*!< 0x00001000 */
15814+
#define ETH_PTPTSCR_TSSIPV6FE ETH_PTPTSCR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */
15815+
#define ETH_PTPTSCR_TSSPTPOEFE_Pos (11U)
15816+
#define ETH_PTPTSCR_TSSPTPOEFE_Msk (0x1UL << ETH_PTPTSCR_TSSPTPOEFE_Pos) /*!< 0x00000800 */
15817+
#define ETH_PTPTSCR_TSSPTPOEFE ETH_PTPTSCR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */
15818+
#define ETH_PTPTSCR_TSPTPPSV2E_Pos (10U)
15819+
#define ETH_PTPTSCR_TSPTPPSV2E_Msk (0x1UL << ETH_PTPTSCR_TSPTPPSV2E_Pos) /*!< 0x00000400 */
15820+
#define ETH_PTPTSCR_TSPTPPSV2E ETH_PTPTSCR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */
15821+
#define ETH_PTPTSCR_TSSSR_Pos (9U)
15822+
#define ETH_PTPTSCR_TSSSR_Msk (0x1UL << ETH_PTPTSCR_TSSSR_Pos) /*!< 0x00000200 */
15823+
#define ETH_PTPTSCR_TSSSR ETH_PTPTSCR_TSSSR_Msk /* Time stamp Sub-seconds rollover */
15824+
#define ETH_PTPTSCR_TSSARFE_Pos (8U)
15825+
#define ETH_PTPTSCR_TSSARFE_Msk (0x1UL << ETH_PTPTSCR_TSSARFE_Pos) /*!< 0x00000100 */
15826+
#define ETH_PTPTSCR_TSSARFE ETH_PTPTSCR_TSSARFE_Msk /* Time stamp snapshot for all received frames enable */
1582415827

1582515828
#define ETH_PTPTSCR_TSARU_Pos (5U)
1582615829
#define ETH_PTPTSCR_TSARU_Msk (0x1UL << ETH_PTPTSCR_TSARU_Pos) /*!< 0x00000020 */
@@ -15905,6 +15908,9 @@ typedef struct
1590515908
/******************************************************************************/
1590615909

1590715910
/* Bit definition for Ethernet DMA Bus Mode Register */
15911+
#define ETH_DMABMR_MB_Pos (26U)
15912+
#define ETH_DMABMR_MB_Msk (0x1UL << ETH_DMABMR_MB_Pos) /*!< 0x04000000 */
15913+
#define ETH_DMABMR_MB ETH_DMABMR_MB_Msk /* Mixed Burst */
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#define ETH_DMABMR_AAB_Pos (25U)
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#define ETH_DMABMR_AAB_Msk (0x1UL << ETH_DMABMR_AAB_Pos) /*!< 0x02000000 */
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#define ETH_DMABMR_AAB ETH_DMABMR_AAB_Msk /* Address-Aligned beats */

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