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TDhaouSTfpistm
TDhaouST
authored and
fpistm
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system(F4) update STM32F4xx HAL Drivers to v1.8.1
Included in STM32CubeF4 FW v1.27.1 Signed-off-by: TLIG Dhaou <[email protected]>
1 parent 6162582 commit 7e8ffbf

10 files changed

+406
-265
lines changed

Diff for: ‎system/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h

+54-22
Original file line numberDiff line numberDiff line change
@@ -37,14 +37,16 @@ extern "C" {
3737
#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
3838
#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
3939
#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
40-
#if defined(STM32U5)
40+
#if defined(STM32U5) || defined(STM32H7) || defined(STM32MP1)
4141
#define CRYP_DATATYPE_32B CRYP_NO_SWAP
4242
#define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP
4343
#define CRYP_DATATYPE_8B CRYP_BYTE_SWAP
4444
#define CRYP_DATATYPE_1B CRYP_BIT_SWAP
45+
#if defined(STM32U5)
4546
#define CRYP_CCF_CLEAR CRYP_CLEAR_CCF
4647
#define CRYP_ERR_CLEAR CRYP_CLEAR_RWEIF
4748
#endif /* STM32U5 */
49+
#endif /* STM32U5 || STM32H7 || STM32MP1 */
4850
/**
4951
* @}
5052
*/
@@ -110,6 +112,7 @@ extern "C" {
110112
#define ADC_SAMPLETIME_391CYCLES_5 ADC_SAMPLETIME_391CYCLES
111113
#define ADC4_SAMPLETIME_160CYCLES_5 ADC4_SAMPLETIME_814CYCLES_5
112114
#endif /* STM32U5 */
115+
113116
/**
114117
* @}
115118
*/
@@ -231,8 +234,11 @@ extern "C" {
231234
/** @defgroup CRC_Aliases CRC API aliases
232235
* @{
233236
*/
237+
#if defined(STM32C0)
238+
#else
234239
#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */
235240
#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */
241+
#endif
236242
/**
237243
* @}
238244
*/
@@ -499,7 +505,7 @@ extern "C" {
499505
#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0
500506
#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1
501507
#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2
502-
#if defined(STM32G0)
508+
#if defined(STM32G0) || defined(STM32C0)
503509
#define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE
504510
#define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH
505511
#else
@@ -568,7 +574,6 @@ extern "C" {
568574
#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD
569575
#endif /* STM32G4 */
570576

571-
572577
/**
573578
* @}
574579
*/
@@ -668,6 +673,10 @@ extern "C" {
668673
#if defined(STM32U5)
669674
#define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ
670675
#endif /* STM32U5 */
676+
#if defined(STM32U5)
677+
#define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP
678+
#define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1
679+
#endif /* STM32U5 */
671680
/**
672681
* @}
673682
*/
@@ -1080,8 +1089,8 @@ extern "C" {
10801089
#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
10811090

10821091
#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT
1083-
#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
1084-
#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
1092+
#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
1093+
#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
10851094
#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2
10861095

10871096
#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE
@@ -1092,15 +1101,22 @@ extern "C" {
10921101
#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
10931102
#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
10941103

1104+
#if defined(STM32F7)
1105+
#define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK
1106+
#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_IT_ENABLE_BITS_MASK
1107+
#endif /* STM32F7 */
1108+
10951109
#if defined(STM32H7)
10961110
#define RTC_TAMPCR_TAMPXE RTC_TAMPER_X
10971111
#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT
1112+
#endif /* STM32H7 */
10981113

1114+
#if defined(STM32F7) || defined(STM32H7)
10991115
#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1
11001116
#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2
11011117
#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3
1102-
#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMPALL
1103-
#endif /* STM32H7 */
1118+
#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP
1119+
#endif /* STM32F7 || STM32H7 */
11041120

11051121
/**
11061122
* @}
@@ -3407,7 +3423,7 @@ extern "C" {
34073423
#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
34083424
#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
34093425

3410-
#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL)
3426+
#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL) || defined(STM32C0)
34113427
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
34123428
#else
34133429
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
@@ -3520,8 +3536,8 @@ extern "C" {
35203536
#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2
35213537
#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1
35223538
#if defined(STM32U5)
3523-
#define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL
3524-
#define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL
3539+
#define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL
3540+
#define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL
35253541
#define __HAL_RCC_AHB21_CLK_DISABLE __HAL_RCC_AHB2_1_CLK_DISABLE
35263542
#define __HAL_RCC_AHB22_CLK_DISABLE __HAL_RCC_AHB2_2_CLK_DISABLE
35273543
#define __HAL_RCC_AHB1_CLK_Disable_Clear __HAL_RCC_AHB1_CLK_ENABLE
@@ -3537,15 +3553,20 @@ extern "C" {
35373553
#define RCC_CLK48CLKSOURCE_PLL2 RCC_ICLK_CLKSOURCE_PLL2
35383554
#define RCC_CLK48CLKSOURCE_PLL1 RCC_ICLK_CLKSOURCE_PLL1
35393555
#define RCC_CLK48CLKSOURCE_MSIK RCC_ICLK_CLKSOURCE_MSIK
3540-
#define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
3541-
#define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
3542-
#define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
3543-
#define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
3544-
#define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
3545-
#define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
3546-
#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC12_CLK_SLEEP_ENABLE
3547-
#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC12_CLK_SLEEP_DISABLE
3548-
#endif
3556+
#define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
3557+
#define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
3558+
#define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
3559+
#define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
3560+
#define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
3561+
#define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
3562+
#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC12_CLK_SLEEP_ENABLE
3563+
#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC12_CLK_SLEEP_DISABLE
3564+
#define __HAL_RCC_GET_CLK48_SOURCE __HAL_RCC_GET_ICLK_SOURCE
3565+
#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE
3566+
#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE
3567+
#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG
3568+
#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE
3569+
#endif /* STM32U5 */
35493570

35503571
/**
35513572
* @}
@@ -3563,7 +3584,9 @@ extern "C" {
35633584
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
35643585
* @{
35653586
*/
3566-
#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5)
3587+
#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx)|| \
3588+
defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \
3589+
defined (STM32C0)
35673590
#else
35683591
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
35693592
#endif
@@ -3616,7 +3639,6 @@ extern "C" {
36163639
#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE
36173640
#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE
36183641

3619-
36203642
/**
36213643
* @}
36223644
*/
@@ -3628,7 +3650,7 @@ extern "C" {
36283650
#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
36293651
#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
36303652

3631-
#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32L1)
3653+
#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32L1)
36323654
#define eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE
36333655
#define eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE
36343656
#define eMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE
@@ -3965,6 +3987,16 @@ extern "C" {
39653987
* @}
39663988
*/
39673989

3990+
/** @defgroup HAL_Generic_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
3991+
* @{
3992+
*/
3993+
#if defined (STM32F7)
3994+
#define ART_ACCLERATOR_ENABLE ART_ACCELERATOR_ENABLE
3995+
#endif /* STM32F7 */
3996+
/**
3997+
* @}
3998+
*/
3999+
39684000
/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
39694001
* @{
39704002
*/

Diff for: ‎system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_conf_template.h

+2-3
Original file line numberDiff line numberDiff line change
@@ -209,8 +209,8 @@
209209
#define MAC_ADDR5 0U
210210

211211
/* Definition of the Ethernet driver buffers size and count */
212-
#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
213-
#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
212+
#define ETH_RX_BUF_SIZE 1528U /* ETH Max buffer size for receive */
213+
#define ETH_TX_BUF_SIZE 1528U /* ETH Max buffer size for transmit */
214214
#define ETH_RXBUFNB 4U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
215215
#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
216216

@@ -497,4 +497,3 @@
497497
#endif /* __STM32F4xx_HAL_CONF_H */
498498

499499

500-

Diff for: ‎system/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h

-1
Original file line numberDiff line numberDiff line change
@@ -404,4 +404,3 @@ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
404404

405405
#endif /* __STM32F4xx_HAL_CORTEX_H */
406406

407-

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