@@ -34,7 +34,7 @@ extern "C" {
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#define NOT_AN_INTERRUPT NC // -1
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#define DEND PEND
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- #define NUM_DIGITAL_PINS DEND
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+ #define NUM_DIGITAL_PINS ((uint32_t) DEND)
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#define NUM_ANALOG_INPUTS (AEND-A0)
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// Convert a digital pin number Dxx to a PinName PX_n
@@ -62,9 +62,34 @@ uint32_t pinNametoDigitalPin(PinName p);
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pin_in_pinmap(digitalPinToPinName(p), PinMap_SPI_SSEL))
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- #define digitalPinToPort (p ) (get_GPIO_Port(digitalPinToPinName(p)))
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+ #define digitalPinToPort (p ) (get_GPIO_Port(STM_PORT( digitalPinToPinName(p) )))
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#define digitalPinToBitMask (p ) (STM_GPIO_PIN(digitalPinToPinName(p)))
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+ #define analogInPinToBit (p ) (STM_PIN(digitalPinToPinName(p)))
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+ #define portOutputRegister (P ) (&(P->ODR))
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+ #define portInputRegister (P ) (&(P->IDR))
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+
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+ #define portSetRegister (P ) (&(P->BSRR))
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+ #if defined(STM32F2xx ) || defined(STM32F4xx ) || defined(STM32F7xx )
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+ // For those series reset are in the high part so << 16U needed
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+ #define portClearRegister (P ) (&(P->BSRR))
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+ #else
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+ #define portClearRegister (P ) (&(P->BRR))
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+ #endif
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+
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+
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+ #if defined(STM32F1xx )
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+ // Config registers split in 2 registers:
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+ // CRL: pin 0..7
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+ // CRH: pin 8..15
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+ // Return only CRL
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+ #define portModeRegister (P ) (&(P->CRL))
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+ #else
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+ #define portModeRegister (P ) (&(P->MODER))
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+ #endif
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+ #define portConfigRegister (P ) (portModeRegister(P))
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+
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+
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#define digitalPinIsValid (p ) (digitalPinToPinName(p) != NC)
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// As some pin could be duplicated in digitalPin[]
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