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system(WB) update STM32WBxx HAL Drivers to v1.14.1
Included in STM32CubeWB FW v1.18.0 Signed-off-by: Frederic Pillon <[email protected]>
1 parent 0c9cc73 commit 73b834c

21 files changed

+343
-280
lines changed

Diff for: ‎system/Drivers/STM32WBxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h

+6-3
Original file line numberDiff line numberDiff line change
@@ -3643,7 +3643,8 @@ extern "C" {
36433643
#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
36443644

36453645
#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \
3646-
defined(STM32WL) || defined(STM32C0)
3646+
defined(STM32WL) || defined(STM32C0)
3647+
36473648
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
36483649
#else
36493650
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
@@ -3892,7 +3893,8 @@ extern "C" {
38923893
*/
38933894
#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \
38943895
defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \
3895-
defined (STM32WBA) || defined (STM32H5) || defined (STM32C0)
3896+
defined (STM32WBA) || defined (STM32H5) || \
3897+
defined (STM32C0)
38963898
#else
38973899
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
38983900
#endif
@@ -3929,7 +3931,8 @@ extern "C" {
39293931

39303932
#if defined (STM32F0) || defined (STM32F2) || defined (STM32F3) || defined (STM32F4) || defined (STM32F7) || \
39313933
defined (STM32H7) || \
3932-
defined (STM32L0) || defined (STM32L1)
3934+
defined (STM32L0) || defined (STM32L1) || \
3935+
defined (STM32WB)
39333936
#define __HAL_RTC_TAMPER_GET_IT __HAL_RTC_TAMPER_GET_FLAG
39343937
#endif
39353938

Diff for: ‎system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_i2c.h

-2
Original file line numberDiff line numberDiff line change
@@ -118,8 +118,6 @@ typedef enum
118118
HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception
119119
process is ongoing */
120120
HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */
121-
HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */
122-
HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */
123121

124122
} HAL_I2C_StateTypeDef;
125123

Diff for: ‎system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_lptim.h

+2-2
Original file line numberDiff line numberDiff line change
@@ -657,9 +657,9 @@ void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim);
657657

658658
/* Callbacks Register/UnRegister functions ***********************************/
659659
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
660-
HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID,
660+
HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *hlptim, HAL_LPTIM_CallbackIDTypeDef CallbackID,
661661
pLPTIM_CallbackTypeDef pCallback);
662-
HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID);
662+
HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlptim, HAL_LPTIM_CallbackIDTypeDef CallbackID);
663663
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
664664
/**
665665
* @}

Diff for: ‎system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_rtc_ex.h

-8
Original file line numberDiff line numberDiff line change
@@ -794,14 +794,6 @@ typedef struct
794794
*
795795
* @retval None
796796
*/
797-
#if defined(RTC_TAMPER1_SUPPORT) && defined(RTC_TAMPER3_SUPPORT)
798-
#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) == RTC_IT_TAMP1) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 3U)) != 0U) ? 1U : 0U) : \
799-
((__INTERRUPT__) == RTC_IT_TAMP2) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 5U)) != 0U) ? 1U : 0U) : \
800-
((__INTERRUPT__) == RTC_IT_TAMP3) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 7U)) != 0U) ? 1U : 0U))
801-
#else
802-
#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__)\
803-
== RTC_IT_TAMP1) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 3U)) != 0U) ? 1U : 0U))
804-
#endif /* RTC_TAMPER1_SUPPORT || RTC_TAMPER3_SUPPORT */
805797

806798
/**************************************************************************************************/
807799

Diff for: ‎system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_smbus.h

-2
Original file line numberDiff line numberDiff line change
@@ -100,8 +100,6 @@ typedef struct
100100
#define HAL_SMBUS_STATE_MASTER_BUSY_RX (0x00000022U) /*!< Master Data Reception process is ongoing */
101101
#define HAL_SMBUS_STATE_SLAVE_BUSY_TX (0x00000032U) /*!< Slave Data Transmission process is ongoing */
102102
#define HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U) /*!< Slave Data Reception process is ongoing */
103-
#define HAL_SMBUS_STATE_TIMEOUT (0x00000003U) /*!< Timeout state */
104-
#define HAL_SMBUS_STATE_ERROR (0x00000004U) /*!< Reception process is ongoing */
105103
#define HAL_SMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */
106104
/**
107105
* @}

Diff for: ‎system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_tim.h

+20-20
Original file line numberDiff line numberDiff line change
@@ -402,29 +402,28 @@ typedef struct
402402
*/
403403
typedef enum
404404
{
405-
HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */
406-
, HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */
407-
, HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */
408-
, HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */
409-
, HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */
410-
, HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */
411-
, HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */
412-
, HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */
413-
, HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */
414-
, HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */
415-
, HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */
416-
, HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */
417-
, HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */
418-
, HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */
405+
HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */
406+
, HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */
407+
, HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */
408+
, HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */
409+
, HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */
410+
, HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */
411+
, HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */
412+
, HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */
413+
, HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */
414+
, HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */
415+
, HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */
416+
, HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */
417+
, HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */
418+
, HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */
419419
, HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */
420420
, HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */
421421
, HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */
422422
, HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */
423-
424423
, HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */
425424
, HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */
426425
, HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */
427-
, HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */
426+
, HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */
428427
, HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */
429428
, HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */
430429
, HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */
@@ -1866,8 +1865,9 @@ mode.
18661865
#define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
18671866
((__CHANNEL__) == TIM_CHANNEL_2))
18681867

1869-
#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) \
1870-
((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : ((__PERIOD__) > 0U))
1868+
#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? \
1869+
(((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : \
1870+
((__PERIOD__) > 0U))
18711871

18721872
#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
18731873
((__CHANNEL__) == TIM_CHANNEL_2) || \
@@ -1920,7 +1920,6 @@ mode.
19201920

19211921
#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL)
19221922

1923-
19241923
#define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \
19251924
((__STATE__) == TIM_BREAK_DISABLE))
19261925

@@ -2317,7 +2316,8 @@ HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_S
23172316
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig);
23182317
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig);
23192318
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
2320-
uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength);
2319+
uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
2320+
uint32_t BurstLength);
23212321
HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
23222322
uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
23232323
uint32_t BurstLength, uint32_t DataLength);

Diff for: ‎system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_i2c.h

+8-1
Original file line numberDiff line numberDiff line change
@@ -2133,11 +2133,18 @@ __STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(const I2C_TypeDef *I2Cx)
21332133
__STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize,
21342134
uint32_t TransferSize, uint32_t EndMode, uint32_t Request)
21352135
{
2136+
/* Declaration of tmp to prevent undefined behavior of volatile usage */
2137+
uint32_t tmp = ((uint32_t)(((uint32_t)SlaveAddr & I2C_CR2_SADD) | \
2138+
((uint32_t)SlaveAddrSize & I2C_CR2_ADD10) | \
2139+
(((uint32_t)TransferSize << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
2140+
(uint32_t)EndMode | (uint32_t)Request) & (~0x80000000U));
2141+
2142+
/* update CR2 register */
21362143
MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 |
21372144
(I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) |
21382145
I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD |
21392146
I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R,
2140-
SlaveAddr | SlaveAddrSize | (TransferSize << I2C_CR2_NBYTES_Pos) | EndMode | Request);
2147+
tmp);
21412148
}
21422149

21432150
/**

Diff for: ‎system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_tim.h

+24-28
Original file line numberDiff line numberDiff line change
@@ -664,10 +664,10 @@ typedef struct
664664
/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
665665
* @{
666666
*/
667-
#define LL_TIM_COUNTERMODE_UP 0x00000000U /*!<Counter used as upcounter */
667+
#define LL_TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as upcounter */
668668
#define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */
669669
#define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */
670-
#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
670+
#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
671671
#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */
672672
/**
673673
* @}
@@ -1132,6 +1132,15 @@ typedef struct
11321132
* @}
11331133
*/
11341134

1135+
/** Legacy definitions for compatibility purpose
1136+
@cond 0
1137+
*/
1138+
#define LL_TIM_ReArmBRK(_PARAM_)
1139+
#define LL_TIM_ReArmBRK2(_PARAM_)
1140+
/**
1141+
@endcond
1142+
*/
1143+
11351144
/** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
11361145
* @{
11371146
*/
@@ -1278,8 +1287,8 @@ typedef struct
12781287
/** @defgroup TIM_LL_EC_OCREF_CLR_INT OCREF clear input selection
12791288
* @{
12801289
*/
1281-
#define LL_TIM_OCREF_CLR_INT_OCREF_CLR 0x00000000U /*!< OCREF_CLR_INT is connected to the OCREF_CLR input */
1282-
#define LL_TIM_OCREF_CLR_INT_ETR TIM_SMCR_OCCS /*!< OCREF_CLR_INT is connected to ETRF */
1290+
#define LL_TIM_OCREF_CLR_INT_OCREF_CLR 0x00000000U /*!< OCREF_CLR_INT is connected to the OCREF_CLR input */
1291+
#define LL_TIM_OCREF_CLR_INT_ETR TIM_SMCR_OCCS /*!< OCREF_CLR_INT is connected to ETRF */
12831292
/**
12841293
* @}
12851294
*/
@@ -1878,6 +1887,17 @@ __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
18781887
CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
18791888
}
18801889

1890+
/**
1891+
* @brief Indicates whether the capture/compare control bits (CCxE, CCxNE and OCxM) preload is enabled.
1892+
* @rmtoll CR2 CCPC LL_TIM_CC_IsEnabledPreload
1893+
* @param TIMx Timer instance
1894+
* @retval State of bit (1 or 0).
1895+
*/
1896+
__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef *TIMx)
1897+
{
1898+
return ((READ_BIT(TIMx->CR2, TIM_CR2_CCPC) == (TIM_CR2_CCPC)) ? 1UL : 0UL);
1899+
}
1900+
18811901
/**
18821902
* @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
18831903
* @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
@@ -3532,18 +3552,6 @@ __STATIC_INLINE void LL_TIM_DisarmBRK(TIM_TypeDef *TIMx)
35323552
SET_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM);
35333553
}
35343554

3535-
/**
3536-
* @brief Re-arm the break input (when it operates in bidirectional mode).
3537-
* @note The Break input is automatically armed as soon as MOE bit is set.
3538-
* @rmtoll BDTR BKDSRM LL_TIM_ReArmBRK
3539-
* @param TIMx Timer instance
3540-
* @retval None
3541-
*/
3542-
__STATIC_INLINE void LL_TIM_ReArmBRK(TIM_TypeDef *TIMx)
3543-
{
3544-
CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM);
3545-
}
3546-
35473555
/**
35483556
* @brief Enable the break 2 function.
35493557
* @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
@@ -3633,18 +3641,6 @@ __STATIC_INLINE void LL_TIM_DisarmBRK2(TIM_TypeDef *TIMx)
36333641
SET_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM);
36343642
}
36353643

3636-
/**
3637-
* @brief Re-arm the break 2 input (when it operates in bidirectional mode).
3638-
* @note The Break 2 input is automatically armed as soon as MOE bit is set.
3639-
* @rmtoll BDTR BK2DSRM LL_TIM_ReArmBRK2
3640-
* @param TIMx Timer instance
3641-
* @retval None
3642-
*/
3643-
__STATIC_INLINE void LL_TIM_ReArmBRK2(TIM_TypeDef *TIMx)
3644-
{
3645-
CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM);
3646-
}
3647-
36483644
/**
36493645
* @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
36503646
* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not

Diff for: ‎system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_usb.h

+11-11
Original file line numberDiff line numberDiff line change
@@ -53,26 +53,26 @@ typedef enum
5353
*/
5454
typedef struct
5555
{
56-
uint32_t dev_endpoints; /*!< Device Endpoints number.
56+
uint8_t dev_endpoints; /*!< Device Endpoints number.
5757
This parameter depends on the used USB core.
5858
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
5959

60-
uint32_t speed; /*!< USB Core speed.
61-
This parameter can be any value of @ref PCD_Speed/HCD_Speed
62-
(HCD_SPEED_xxx, HCD_SPEED_xxx) */
60+
uint8_t speed; /*!< USB Core speed.
61+
This parameter can be any value of @ref PCD_Speed/HCD_Speed
62+
(HCD_SPEED_xxx, HCD_SPEED_xxx) */
6363

64-
uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */
64+
uint8_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */
6565

66-
uint32_t phy_itface; /*!< Select the used PHY interface.
67-
This parameter can be any value of @ref PCD_PHY_Module/HCD_PHY_Module */
66+
uint8_t phy_itface; /*!< Select the used PHY interface.
67+
This parameter can be any value of @ref PCD_PHY_Module/HCD_PHY_Module */
6868

69-
uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */
69+
uint8_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */
7070

71-
uint32_t low_power_enable; /*!< Enable or disable the low Power Mode. */
71+
uint8_t low_power_enable; /*!< Enable or disable the low Power Mode. */
7272

73-
uint32_t lpm_enable; /*!< Enable or disable Link Power Management. */
73+
uint8_t lpm_enable; /*!< Enable or disable Link Power Management. */
7474

75-
uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */
75+
uint8_t battery_charging_enable; /*!< Enable or disable Battery charging. */
7676
} USB_CfgTypeDef;
7777

7878
typedef struct

Diff for: ‎system/Drivers/STM32WBxx_HAL_Driver/License.md renamed to ‎system/Drivers/STM32WBxx_HAL_Driver/LICENSE.md

File renamed without changes.

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