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system(WB) update STM32WBxx HAL Drivers to v1.13.0
Included in STM32CubeWB FW v1.16.0 Signed-off-by: Frederic Pillon <[email protected]>
1 parent 3ac4049 commit 6e3f991

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51 files changed

+2445
-1740
lines changed

Diff for: ‎system/Drivers/STM32WBxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h

+353-51
Large diffs are not rendered by default.

Diff for: ‎system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal.h

+2-2
Original file line numberDiff line numberDiff line change
@@ -534,13 +534,13 @@ typedef enum
534534
(((__INTERRUPT__) & SYSCFG_IT_FPU_IDC) == SYSCFG_IT_FPU_IDC) || \
535535
(((__INTERRUPT__) & SYSCFG_IT_FPU_IXC) == SYSCFG_IT_FPU_IXC))
536536

537-
#if defined(STM32WB15xx)
537+
#if defined(STM32WB15xx) || defined(STM32WB10xx)
538538
#define IS_SYSCFG_SRAM2WRP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0xFFFFFFFFU))
539539
#define IS_SYSCFG_SRAM2WRP2_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0x0000000FU))
540540
#else
541541
#define IS_SYSCFG_SRAM2WRP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0xFFFFFFFFU))
542542
#define IS_SYSCFG_SRAM2WRP2_PAGE(__PAGE__) IS_SYSCFG_SRAM2WRP_PAGE(__PAGE__)
543-
#endif /* STM32WB15xx */
543+
#endif /* STM32WB15xx || STM32WB10xx */
544544

545545
#if defined(VREFBUF)
546546
#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \

Diff for: ‎system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_cortex.h

+11-11
Original file line numberDiff line numberDiff line change
@@ -48,27 +48,27 @@ extern "C" {
4848
*/
4949
typedef struct
5050
{
51-
uint8_t Enable; /*!< Specifies the status of the region.
51+
uint8_t Enable; /*!< Specifies the status of the region.
5252
This parameter can be a value of @ref CORTEX_MPU_Region_Enable */
53-
uint8_t Number; /*!< Specifies the number of the region to protect.
53+
uint8_t Number; /*!< Specifies the number of the region to protect.
5454
This parameter can be a value of @ref CORTEX_MPU_Region_Number */
5555
uint32_t BaseAddress; /*!< Specifies the base address of the region to protect.
5656
*/
57-
uint8_t Size; /*!< Specifies the size of the region to protect.
57+
uint8_t Size; /*!< Specifies the size of the region to protect.
5858
This parameter can be a value of @ref CORTEX_MPU_Region_Size */
59-
uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable.
59+
uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable.
6060
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
6161
uint8_t TypeExtField; /*!< Specifies the TEX field level.
6262
This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */
63-
uint8_t AccessPermission; /*!< Specifies the region access permission type.
63+
uint8_t AccessPermission; /*!< Specifies the region access permission type.
6464
This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */
65-
uint8_t DisableExec; /*!< Specifies the instruction access status.
65+
uint8_t DisableExec; /*!< Specifies the instruction access status.
6666
This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */
67-
uint8_t IsShareable; /*!< Specifies the shareability status of the protected region.
67+
uint8_t IsShareable; /*!< Specifies the shareability status of the protected region.
6868
This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */
69-
uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected.
69+
uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected.
7070
This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */
71-
uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region.
71+
uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region.
7272
This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */
7373
} MPU_Region_InitTypeDef;
7474
/**
@@ -213,8 +213,8 @@ typedef struct
213213
/**
214214
* @}
215215
*/
216-
217-
/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
216+
217+
/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
218218
* @{
219219
*/
220220
#define MPU_REGION_NO_ACCESS ((uint8_t)0x00)

Diff for: ‎system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_dma.h

+84-82
Large diffs are not rendered by default.

Diff for: ‎system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_flash.h

+68-52
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Diff for: ‎system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_flash_ex.h

-1
Original file line numberDiff line numberDiff line change
@@ -49,7 +49,6 @@ extern "C" {
4949
* @}
5050
*/
5151

52-
5352
/** @defgroup FLASHEx_ECC_CPUID FLASHEx ECC CPU Identification
5453
* @{
5554
*/

Diff for: ‎system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_gpio.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -242,7 +242,7 @@ typedef enum
242242
(((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00u))
243243

244244
#define IS_GPIO_COMMON_PIN(__RESETMASK__, __SETMASK__) \
245-
(((uint32_t)(__RESETMASK__) & (uint32_t)(__SETMASK__)) == 0x00u)
245+
(((uint32_t)(__RESETMASK__) & (uint32_t)(__SETMASK__)) == 0x00u)
246246

247247

248248
#define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\

Diff for: ‎system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_gpio_ex.h

+17-17
Original file line numberDiff line numberDiff line change
@@ -76,28 +76,28 @@ extern "C" {
7676
/**
7777
* @brief AF 1 selection
7878
*/
79-
#define GPIO_AF1_TIM1 ((uint8_t)0x01) /*!< TIM1 Alternate Function mapping */
80-
#define GPIO_AF1_TIM2 ((uint8_t)0x01) /*!< TIM2 Alternate Function mapping */
81-
#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /*!< LPTIM1 Alternate Function mapping */
79+
#define GPIO_AF1_TIM1 ((uint8_t)0x01) /*!< TIM1 Alternate Function mapping */
80+
#define GPIO_AF1_TIM2 ((uint8_t)0x01) /*!< TIM2 Alternate Function mapping */
81+
#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /*!< LPTIM1 Alternate Function mapping */
8282

8383
/**
8484
* @brief AF 2 selection
8585
*/
86-
#define GPIO_AF2_TIM2 ((uint8_t)0x02) /*!< TIM2 Alternate Function mapping */
87-
#define GPIO_AF2_TIM1 ((uint8_t)0x02) /*!< TIM1 Alternate Function mapping */
86+
#define GPIO_AF2_TIM2 ((uint8_t)0x02) /*!< TIM2 Alternate Function mapping */
87+
#define GPIO_AF2_TIM1 ((uint8_t)0x02) /*!< TIM1 Alternate Function mapping */
8888

8989
/**
9090
* @brief AF 3 selection
9191
*/
92-
#define GPIO_AF3_SAI1 ((uint8_t)0x03) /*!< SAI1_CK1 Alternate Function mapping */
92+
#define GPIO_AF3_SAI1 ((uint8_t)0x03) /*!< SAI1_CK1 Alternate Function mapping */
9393
#define GPIO_AF3_SPI2 ((uint8_t)0x03) /*!< SPI2 Alternate Function mapping */
9494
#define GPIO_AF3_TIM1 ((uint8_t)0x03) /*!< TIM1 Alternate Function mapping */
9595

9696
/**
9797
* @brief AF 4 selection
9898
*/
9999
#define GPIO_AF4_I2C1 ((uint8_t)0x04) /*!< I2C1 Alternate Function mapping */
100-
#define GPIO_AF4_I2C3 ((uint8_t)0x04) /*!< I2C3 Alternate Function mapping */
100+
#define GPIO_AF4_I2C3 ((uint8_t)0x04) /*!< I2C3 Alternate Function mapping */
101101

102102
/**
103103
* @brief AF 5 selection
@@ -135,13 +135,13 @@ extern "C" {
135135
/**
136136
* @brief AF 7 selection
137137
*/
138-
#define GPIO_AF7_USART1 ((uint8_t)0x07) /*!< USART1 Alternate Function mapping */
138+
#define GPIO_AF7_USART1 ((uint8_t)0x07) /*!< USART1 Alternate Function mapping */
139139

140140
/**
141141
* @brief AF 8 selection
142142
*/
143-
#define GPIO_AF8_LPUART1 ((uint8_t)0x08) /*!< LPUART1 Alternate Function mapping */
144-
#define GPIO_AF8_IR ((uint8_t)0x08) /*!< IR Alternate Function mapping */
143+
#define GPIO_AF8_LPUART1 ((uint8_t)0x08) /*!< LPUART1 Alternate Function mapping */
144+
#define GPIO_AF8_IR ((uint8_t)0x08) /*!< IR Alternate Function mapping */
145145

146146
/**
147147
* @brief AF 9 selection
@@ -187,7 +187,7 @@ extern "C" {
187187

188188
#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0f)
189189

190-
#endif
190+
#endif /* STM32WB55xx || STM32WB5Mxx */
191191

192192

193193
#if defined (STM32WB50xx)
@@ -285,12 +285,12 @@ extern "C" {
285285
/**
286286
* @brief AF 15 selection
287287
*/
288-
#define GPIO_AF15_EVENTOUT ((uint8_t)0x0f) /*!< EVENTOUT Alternate Function mapping */
288+
#define GPIO_AF15_EVENTOUT ((uint8_t)0x0f) /*!< EVENTOUT Alternate Function mapping */
289289

290290
#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0F)\
291291
&& ((AF) != (uint8_t)0x09) && ((AF) != (uint8_t)0x0A) && ((AF) != (uint8_t)0x0B) && ((AF) != (uint8_t)0x0D))
292292

293-
#endif
293+
#endif /* STM32WB50xx */
294294

295295

296296
#if defined (STM32WB35xx)
@@ -413,7 +413,7 @@ extern "C" {
413413

414414
#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0F) && ((AF) != (uint8_t)0x0B) && ((AF) != (uint8_t)0x0D))
415415

416-
#endif
416+
#endif /* STM32WB35xx */
417417

418418
#if defined (STM32WB30xx)
419419
/**
@@ -520,7 +520,7 @@ extern "C" {
520520
#define IS_GPIO_AF(AF) (((AF) <= (uint8_t)0x0F)\
521521
&& ((AF) != (uint8_t)0x0A) && ((AF) != (uint8_t)0x0B) && ((AF) != (uint8_t)0x0D))
522522

523-
#endif
523+
#endif /* STM32WB30xx */
524524

525525
#if defined (STM32WB15xx) || defined (STM32WB10xx) || defined (STM32WB1Mxx)
526526
/**
@@ -625,7 +625,7 @@ extern "C" {
625625
#define GPIO_AF15_EVENTOUT ((uint8_t)0x0f) /*!< EVENTOUT Alternate Function mapping */
626626

627627
#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0f)
628-
#endif
628+
#endif /* STM32WB15xx || STM32WB10xx || STM32WB1Mxx */
629629

630630
/**
631631
* @}
@@ -654,7 +654,7 @@ extern "C" {
654654
((__GPIOx__) == (GPIOB))? 1uL :\
655655
((__GPIOx__) == (GPIOC))? 2uL :\
656656
((__GPIOx__) == (GPIOE))? 4uL : 7uL)
657-
#endif
657+
#endif /* STM32WB55xx || STM32WB5Mxx */
658658
/**
659659
* @}
660660
*/

Diff for: ‎system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_i2c.h

+8-3
Original file line numberDiff line numberDiff line change
@@ -203,10 +203,13 @@ typedef struct __I2C_HandleTypeDef
203203
HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
204204
/*!< I2C transfer IRQ handler function pointer */
205205

206+
#if defined(HAL_DMA_MODULE_ENABLED)
206207
DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */
207208

208209
DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */
209210

211+
#endif /*HAL_DMA_MODULE_ENABLED*/
212+
210213
HAL_LockTypeDef Lock; /*!< I2C locking object */
211214

212215
__IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */
@@ -661,6 +664,7 @@ HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
661664
HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
662665
HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
663666

667+
#if defined(HAL_DMA_MODULE_ENABLED)
664668
/******* Non-Blocking mode: DMA */
665669
HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
666670
uint16_t Size);
@@ -681,6 +685,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_
681685
uint32_t XferOptions);
682686
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
683687
uint32_t XferOptions);
688+
#endif /*HAL_DMA_MODULE_ENABLED*/
684689
/**
685690
* @}
686691
*/
@@ -709,9 +714,9 @@ void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
709714
* @{
710715
*/
711716
/* Peripheral State, Mode and Error functions *********************************/
712-
HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
713-
HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);
714-
uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
717+
HAL_I2C_StateTypeDef HAL_I2C_GetState(const I2C_HandleTypeDef *hi2c);
718+
HAL_I2C_ModeTypeDef HAL_I2C_GetMode(const I2C_HandleTypeDef *hi2c);
719+
uint32_t HAL_I2C_GetError(const I2C_HandleTypeDef *hi2c);
715720

716721
/**
717722
* @}

Diff for: ‎system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_ipcc.h

+18-14
Original file line numberDiff line numberDiff line change
@@ -22,7 +22,7 @@
2222

2323
#ifdef __cplusplus
2424
extern "C" {
25-
#endif
25+
#endif /* __cplusplus */
2626

2727
/* Includes ------------------------------------------------------------------*/
2828
#include "stm32wbxx_hal_def.h"
@@ -199,8 +199,8 @@ typedef void ChannelCb(IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CH
199199

200200
/* Initialization and de-initialization functions *******************************/
201201
/** @defgroup IPCC_Exported_Functions_Group1 Initialization and deinitialization functions
202-
* @{
203-
*/
202+
* @{
203+
*/
204204
HAL_StatusTypeDef HAL_IPCC_Init(IPCC_HandleTypeDef *hipcc);
205205
HAL_StatusTypeDef HAL_IPCC_DeInit(IPCC_HandleTypeDef *hipcc);
206206
void HAL_IPCC_MspInit(IPCC_HandleTypeDef *hipcc);
@@ -210,29 +210,33 @@ void HAL_IPCC_MspDeInit(IPCC_HandleTypeDef *hipcc);
210210
*/
211211

212212
/** @defgroup IPCC_Exported_Functions_Group2 Communication functions
213-
* @{
214-
*/
213+
* @{
214+
*/
215215
/* IO operation functions *****************************************************/
216-
HAL_StatusTypeDef HAL_IPCC_ActivateNotification(IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir, ChannelCb cb);
217-
HAL_StatusTypeDef HAL_IPCC_DeActivateNotification(IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir);
218-
IPCC_CHANNELStatusTypeDef HAL_IPCC_GetChannelStatus(IPCC_HandleTypeDef const *const hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir);
219-
HAL_StatusTypeDef HAL_IPCC_NotifyCPU(IPCC_HandleTypeDef const *const hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir);
216+
HAL_StatusTypeDef HAL_IPCC_ActivateNotification(IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex,
217+
IPCC_CHANNELDirTypeDef ChannelDir, ChannelCb cb);
218+
HAL_StatusTypeDef HAL_IPCC_DeActivateNotification(IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex,
219+
IPCC_CHANNELDirTypeDef ChannelDir);
220+
IPCC_CHANNELStatusTypeDef HAL_IPCC_GetChannelStatus(IPCC_HandleTypeDef const *const hipcc,
221+
uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir);
222+
HAL_StatusTypeDef HAL_IPCC_NotifyCPU(IPCC_HandleTypeDef const *const hipcc, uint32_t ChannelIndex,
223+
IPCC_CHANNELDirTypeDef ChannelDir);
220224
/**
221225
* @}
222226
*/
223227

224228
/** @defgroup IPCC_Exported_Functions_Group3 Peripheral State and Error functions
225-
* @{
226-
*/
229+
* @{
230+
*/
227231
/* Peripheral State and Error functions ****************************************/
228232
HAL_IPCC_StateTypeDef HAL_IPCC_GetState(IPCC_HandleTypeDef const *const hipcc);
229233
/**
230234
* @}
231235
*/
232236

233237
/** @defgroup IPCC_IRQ_Handler_and_Callbacks Peripheral IRQ Handler and Callbacks
234-
* @{
235-
*/
238+
* @{
239+
*/
236240
/* IRQHandler and Callbacks used in non blocking modes ************************/
237241
void HAL_IPCC_TX_IRQHandler(IPCC_HandleTypeDef *const hipcc);
238242
void HAL_IPCC_RX_IRQHandler(IPCC_HandleTypeDef *const hipcc);
@@ -257,7 +261,7 @@ void HAL_IPCC_RxCallback(IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_
257261

258262
#ifdef __cplusplus
259263
}
260-
#endif
264+
#endif /* __cplusplus */
261265

262266
#endif /* STM32WBxx_HAL_IPCC_H */
263267

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