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Merge pull request #84 from fpistm/F1_AF
Full Alternate function management for F1 series
2 parents 25c5adc + 48c42bd commit 644ea7a

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5 files changed

+734
-257
lines changed

5 files changed

+734
-257
lines changed

‎cores/arduino/stm32/PinAF_STM32F1.h

+304-49
Original file line numberDiff line numberDiff line change
@@ -56,6 +56,8 @@ static inline void pinF1_DisconnectDebug(PinName pin)
5656
if ((pin == PA_15) || (pin == PB_3) || (pin == PB_4)) {
5757
__HAL_AFIO_REMAP_SWJ_NOJTAG(); // JTAG-DP Disabled and SW-DP enabled
5858
}
59+
#else
60+
UNUSED(pin);
5961
#endif /* STM32F1_FORCE_DEBUG */
6062
}
6163

@@ -64,55 +66,308 @@ static inline void pin_SetF1AFPin(uint32_t afnum)
6466
// Enable AFIO clock
6567
__HAL_RCC_AFIO_CLK_ENABLE();
6668

67-
if (afnum > 0) {
68-
switch (afnum) {
69-
case 1: // Remap SPI1
70-
__HAL_AFIO_REMAP_SPI1_ENABLE();
71-
break;
72-
case 2: // Remap I2C1
73-
__HAL_AFIO_REMAP_I2C1_ENABLE();
74-
break;
75-
case 3: // Remap USART1
76-
__HAL_AFIO_REMAP_USART1_ENABLE();
77-
break;
78-
case 4: // Remap USART2
79-
__HAL_AFIO_REMAP_USART2_ENABLE();
80-
break;
81-
case 5: // Partial Remap USART3
82-
__HAL_AFIO_REMAP_USART3_PARTIAL();
83-
break;
84-
case 6: // Partial Remap TIM1
85-
__HAL_AFIO_REMAP_TIM1_PARTIAL();
86-
break;
87-
case 7: // Partial Remap TIM3
88-
__HAL_AFIO_REMAP_TIM3_PARTIAL();
89-
break;
90-
case 8: // Full Remap TIM2
91-
__HAL_AFIO_REMAP_TIM2_ENABLE();
92-
break;
93-
case 9: // Full Remap TIM3
94-
__HAL_AFIO_REMAP_TIM3_ENABLE();
95-
break;
96-
#if defined(AFIO_MAPR_CAN_REMAP_REMAP1)
97-
case 10: // CAN_RX mapped to PB8, CAN_TX mapped to PB9
98-
__HAL_AFIO_REMAP_CAN1_2();
99-
break;
100-
case 11: // CAN_RX mapped to PB8, CAN_TX mapped to PB9
101-
__HAL_AFIO_REMAP_CAN1_3();
102-
break;
103-
#endif
104-
case 12: // Full Remap USART3
105-
__HAL_AFIO_REMAP_USART3_ENABLE();
106-
break;
107-
case 13: // Full Remap TIM1
108-
__HAL_AFIO_REMAP_TIM1_ENABLE();
109-
break;
110-
case 14: // Full Remap TIM4
111-
__HAL_AFIO_REMAP_TIM4_ENABLE();
112-
break;
113-
default:
114-
break;
115-
}
69+
switch (afnum) {
70+
case AFIO_SPI1_ENABLE:
71+
__HAL_AFIO_REMAP_SPI1_ENABLE();
72+
break;
73+
case AFIO_SPI1_DISABLE:
74+
__HAL_AFIO_REMAP_SPI1_DISABLE();
75+
break;
76+
case AFIO_I2C1_ENABLE:
77+
__HAL_AFIO_REMAP_I2C1_ENABLE();
78+
break;
79+
case AFIO_I2C1_DISABLE:
80+
__HAL_AFIO_REMAP_I2C1_DISABLE();
81+
break;
82+
case AFIO_USART1_ENABLE:
83+
__HAL_AFIO_REMAP_USART1_ENABLE();
84+
break;
85+
case AFIO_USART1_DISABLE:
86+
__HAL_AFIO_REMAP_USART1_DISABLE();
87+
break;
88+
case AFIO_USART2_ENABLE:
89+
__HAL_AFIO_REMAP_USART2_ENABLE();
90+
break;
91+
case AFIO_USART2_DISABLE:
92+
__HAL_AFIO_REMAP_USART2_DISABLE();
93+
break;
94+
case AFIO_USART3_ENABLE:
95+
__HAL_AFIO_REMAP_USART3_ENABLE();
96+
break;
97+
case AFIO_USART3_PARTIAL:
98+
__HAL_AFIO_REMAP_USART3_PARTIAL();
99+
break;
100+
case AFIO_USART3_DISABLE:
101+
__HAL_AFIO_REMAP_USART3_DISABLE();
102+
break;
103+
case AFIO_TIM1_ENABLE:
104+
__HAL_AFIO_REMAP_TIM1_ENABLE();
105+
break;
106+
case AFIO_TIM1_PARTIAL:
107+
__HAL_AFIO_REMAP_TIM1_PARTIAL();
108+
break;
109+
case AFIO_TIM1_DISABLE:
110+
__HAL_AFIO_REMAP_TIM1_DISABLE();
111+
break;
112+
case AFIO_TIM2_ENABLE:
113+
__HAL_AFIO_REMAP_TIM2_ENABLE();
114+
break;
115+
case AFIO_TIM2_PARTIAL_2:
116+
__HAL_AFIO_REMAP_TIM2_PARTIAL_2();
117+
break;
118+
case AFIO_TIM2_PARTIAL_1:
119+
__HAL_AFIO_REMAP_TIM2_PARTIAL_1();
120+
break;
121+
case AFIO_TIM2_DISABLE:
122+
__HAL_AFIO_REMAP_TIM2_DISABLE();
123+
break;
124+
case AFIO_TIM3_ENABLE:
125+
__HAL_AFIO_REMAP_TIM3_ENABLE();
126+
break;
127+
case AFIO_TIM3_PARTIAL:
128+
__HAL_AFIO_REMAP_TIM3_PARTIAL();
129+
break;
130+
case AFIO_TIM3_DISABLE:
131+
__HAL_AFIO_REMAP_TIM3_DISABLE();
132+
break;
133+
case AFIO_TIM4_ENABLE:
134+
__HAL_AFIO_REMAP_TIM4_ENABLE();
135+
break;
136+
case AFIO_TIM4_DISABLE:
137+
__HAL_AFIO_REMAP_TIM4_DISABLE();
138+
break;
139+
#if defined(AFIO_MAPR_CAN_REMAP1)
140+
case AFIO_CAN1_1:
141+
__HAL_AFIO_REMAP_CAN1_1();
142+
break;
143+
case AFIO_CAN1_2:
144+
__HAL_AFIO_REMAP_CAN1_2();
145+
break;
146+
case AFIO_CAN1_3:
147+
__HAL_AFIO_REMAP_CAN1_3();
148+
break;
149+
#endif
150+
case AFIO_PD01_ENABLE:
151+
__HAL_AFIO_REMAP_PD01_ENABLE();
152+
break;
153+
case AFIO_PD01_DISABLE:
154+
__HAL_AFIO_REMAP_PD01_DISABLE();
155+
break;
156+
#if defined(AFIO_MAPR_TIM5CH4_IREMAP)
157+
case AFIO_TIM5CH4_ENABLE:
158+
__HAL_AFIO_REMAP_TIM5CH4_ENABLE();
159+
break;
160+
case AFIO_TIM5CH4_DISABLE:
161+
__HAL_AFIO_REMAP_TIM5CH4_DISABLE();
162+
break;
163+
#endif
164+
#if defined(AFIO_MAPR_ETH_REMAP)
165+
case AFIO_ETH_ENABLE:
166+
__HAL_AFIO_REMAP_ETH_ENABLE();
167+
break;
168+
case AFIO_ETH_DISABLE:
169+
__HAL_AFIO_REMAP_ETH_DISABLE();
170+
break;
171+
#endif
172+
#if defined(AFIO_MAPR_CAN2_REMAP)
173+
case AFIO_CAN2_ENABLE:
174+
__HAL_AFIO_REMAP_CAN2_ENABLE();
175+
break;
176+
case AFIO_CAN2_DISABLE:
177+
__HAL_AFIO_REMAP_CAN2_DISABLE();
178+
break;
179+
#endif
180+
#if defined(AFIO_MAPR_MII_RMII_SEL)
181+
case AFIO_ETH_RMII:
182+
__HAL_AFIO_ETH_RMII();
183+
break;
184+
case AFIO_ETH_MII:
185+
__HAL_AFIO_ETH_MII();
186+
break;
187+
#endif
188+
#if defined(AFIO_MAPR_ADC1_ETRGINJ_REMAP)
189+
case AFIO_ADC1_ETRGINJ_ENABLE:
190+
__HAL_AFIO_REMAP_ADC1_ETRGINJ_ENABLE();
191+
break;
192+
case AFIO_ADC1_ETRGINJ_DISABLE:
193+
__HAL_AFIO_REMAP_ADC1_ETRGINJ_DISABLE();
194+
break;
195+
#endif
196+
#if defined(AFIO_MAPR_ADC1_ETRGREG_REMAP)
197+
case AFIO_ADC1_ETRGREG_ENABLE:
198+
__HAL_AFIO_REMAP_ADC1_ETRGREG_ENABLE();
199+
break;
200+
case AFIO_ADC1_ETRGREG_DISABLE:
201+
__HAL_AFIO_REMAP_ADC1_ETRGREG_DISABLE();
202+
break;
203+
#endif
204+
#if defined(AFIO_MAPR_ADC2_ETRGINJ_REMAP)
205+
case AFIO_ADC2_ETRGINJ_ENABLE:
206+
__HAL_AFIO_REMAP_ADC2_ETRGINJ_ENABLE();
207+
break;
208+
case AFIO_ADC2_ETRGINJ_DISABLE:
209+
__HAL_AFIO_REMAP_ADC2_ETRGINJ_DISABLE();
210+
break;
211+
#endif
212+
#if defined(AFIO_MAPR_ADC2_ETRGREG_REMAP)
213+
case AFIO_ADC2_ETRGREG_ENABLE:
214+
__HAL_AFIO_REMAP_ADC2_ETRGREG_ENABLE();
215+
break;
216+
case AFIO_ADC2_ETRGREG_DISABLE:
217+
__HAL_AFIO_REMAP_ADC2_ETRGREG_DISABLE();
218+
break;
219+
#endif
220+
case AFIO_SWJ_ENABLE:
221+
__HAL_AFIO_REMAP_SWJ_ENABLE();
222+
break;
223+
case AFIO_SWJ_NONJTRST:
224+
__HAL_AFIO_REMAP_SWJ_NONJTRST();
225+
break;
226+
case AFIO_SWJ_NOJTAG:
227+
__HAL_AFIO_REMAP_SWJ_NOJTAG();
228+
break;
229+
case AFIO_SWJ_DISABLE:
230+
__HAL_AFIO_REMAP_SWJ_DISABLE();
231+
break;
232+
#if defined(AFIO_MAPR_SPI3_REMAP)
233+
case AFIO_SPI3_ENABLE:
234+
__HAL_AFIO_REMAP_SPI3_ENABLE();
235+
break;
236+
case AFIO_SPI3_DISABLE:
237+
__HAL_AFIO_REMAP_SPI3_DISABLE();
238+
break;
239+
#endif
240+
#if defined(AFIO_MAPR_TIM2ITR1_IREMAP)
241+
case AFIO_TIM2ITR1_TO_USB:
242+
__HAL_AFIO_TIM2ITR1_TO_USB();
243+
break;
244+
case AFIO_TIM2ITR1_TO_ETH:
245+
__HAL_AFIO_TIM2ITR1_TO_ETH();
246+
break;
247+
#endif
248+
#if defined(AFIO_MAPR_PTP_PPS_REMAP)
249+
case AFIO_ETH_PTP_PPS_ENABLE:
250+
__HAL_AFIO_ETH_PTP_PPS_ENABLE();
251+
break;
252+
case AFIO_ETH_PTP_PPS_DISABLE:
253+
__HAL_AFIO_ETH_PTP_PPS_DISABLE();
254+
break;
255+
#endif
256+
#if defined(AFIO_MAPR2_TIM9_REMAP)
257+
case AFIO_TIM9_ENABLE:
258+
__HAL_AFIO_REMAP_TIM9_ENABLE();
259+
break;
260+
case AFIO_TIM9_DISABLE:
261+
__HAL_AFIO_REMAP_TIM9_DISABLE();
262+
break;
263+
#endif
264+
#if defined(AFIO_MAPR2_TIM10_REMAP)
265+
case AFIO_TIM10_ENABLE:
266+
__HAL_AFIO_REMAP_TIM10_ENABLE();
267+
break;
268+
case AFIO_TIM10_DISABLE:
269+
__HAL_AFIO_REMAP_TIM10_DISABLE();
270+
break;
271+
#endif
272+
#if defined(AFIO_MAPR2_TIM11_REMAP)
273+
case AFIO_TIM11_ENABLE:
274+
__HAL_AFIO_REMAP_TIM11_ENABLE();
275+
break;
276+
case AFIO_TIM11_DISABLE:
277+
__HAL_AFIO_REMAP_TIM11_DISABLE();
278+
break;
279+
#endif
280+
#if defined(AFIO_MAPR2_TIM13_REMAP)
281+
case AFIO_TIM13_ENABLE:
282+
__HAL_AFIO_REMAP_TIM13_ENABLE();
283+
break;
284+
case AFIO_TIM13_DISABLE:
285+
__HAL_AFIO_REMAP_TIM13_DISABLE();
286+
break;
287+
#endif
288+
#if defined(AFIO_MAPR2_TIM14_REMAP)
289+
case AFIO_TIM14_ENABLE:
290+
__HAL_AFIO_REMAP_TIM14_ENABLE();
291+
break;
292+
case AFIO_TIM14_DISABLE:
293+
__HAL_AFIO_REMAP_TIM14_DISABLE();
294+
break;
295+
#endif
296+
#if defined(AFIO_MAPR2_FSMC_NADV_REMAP)
297+
case AFIO_FSMCNADV_DISCONNECTED:
298+
__HAL_AFIO_FSMCNADV_DISCONNECTED();
299+
break;
300+
case AFIO_FSMCNADV_CONNECTED:
301+
__HAL_AFIO_FSMCNADV_CONNECTED();
302+
break;
303+
#endif
304+
#if defined(AFIO_MAPR2_TIM15_REMAP)
305+
case AFIO_TIM15_ENABLE:
306+
__HAL_AFIO_REMAP_TIM15_ENABLE();
307+
break;
308+
case AFIO_TIM15_DISABLE:
309+
__HAL_AFIO_REMAP_TIM15_DISABLE();
310+
break;
311+
#endif
312+
#if defined(AFIO_MAPR2_TIM16_REMAP)
313+
case AFIO_TIM16_ENABLE:
314+
__HAL_AFIO_REMAP_TIM16_ENABLE();
315+
break;
316+
case AFIO_TIM16_DISABLE:
317+
__HAL_AFIO_REMAP_TIM16_DISABLE();
318+
break;
319+
#endif
320+
#if defined(AFIO_MAPR2_TIM17_REMAP)
321+
case AFIO_TIM17_ENABLE:
322+
__HAL_AFIO_REMAP_TIM17_ENABLE();
323+
break;
324+
case AFIO_TIM17_DISABLE:
325+
__HAL_AFIO_REMAP_TIM17_DISABLE();
326+
break;
327+
#endif
328+
#if defined(AFIO_MAPR2_CEC_REMAP)
329+
case AFIO_CEC_ENABLE:
330+
__HAL_AFIO_REMAP_CEC_ENABLE();
331+
break;
332+
case AFIO_CEC_DISABLE:
333+
__HAL_AFIO_REMAP_CEC_DISABLE();
334+
break;
335+
#endif
336+
#if defined(AFIO_MAPR2_TIM1_DMA_REMAP)
337+
case AFIO_TIM1DMA_ENABLE:
338+
__HAL_AFIO_REMAP_TIM1DMA_ENABLE();
339+
break;
340+
case AFIO_TIM1DMA_DISABLE:
341+
__HAL_AFIO_REMAP_TIM1DMA_DISABLE();
342+
break;
343+
#endif
344+
#if defined(AFIO_MAPR2_TIM67_DAC_DMA_REMAP)
345+
case AFIO_TIM67DACDMA_ENABLE:
346+
__HAL_AFIO_REMAP_TIM67DACDMA_ENABLE();
347+
break;
348+
case AFIO_TIM67DACDMA_DISABLE:
349+
__HAL_AFIO_REMAP_TIM67DACDMA_DISABLE();
350+
break;
351+
#endif
352+
#if defined(AFIO_MAPR2_TIM12_REMAP)
353+
case AFIO_TIM12_ENABLE:
354+
__HAL_AFIO_REMAP_TIM12_ENABLE();
355+
break;
356+
case AFIO_TIM12_DISABLE:
357+
__HAL_AFIO_REMAP_TIM12_DISABLE();
358+
break;
359+
#endif
360+
#if defined(AFIO_MAPR2_MISC_REMAP)
361+
case AFIO_MISC_ENABLE:
362+
__HAL_AFIO_REMAP_MISC_ENABLE();
363+
break;
364+
case AFIO_MISC_DISABLE:
365+
__HAL_AFIO_REMAP_MISC_DISABLE();
366+
break;
367+
#endif
368+
default:
369+
case AFIO_NONE:
370+
break;
116371
}
117372
}
118373

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