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[G4] Update STM32G4xx CMSIS Drivers to v1.1.1
Included in STM32CubeG4 FW v1.2.0 Signed-off-by: Frederic Pillon <[email protected]>
1 parent 7dcdc8a commit 5f1c8f1

15 files changed

+2254
-488
lines changed

Diff for: ‎system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h

+27-30
Original file line numberDiff line numberDiff line change
@@ -8847,19 +8847,19 @@ typedef struct
88478847
#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk
88488848

88498849
/******************** Bits definition for TAMP_FLTCR register ***************/
8850-
#define TAMP_FLTCR_TAMPFREQ_0 ((uint32_t)0x00000001)
8851-
#define TAMP_FLTCR_TAMPFREQ_1 ((uint32_t)0x00000002)
8852-
#define TAMP_FLTCR_TAMPFREQ_2 ((uint32_t)0x00000004)
8850+
#define TAMP_FLTCR_TAMPFREQ_0 (0x00000001UL)
8851+
#define TAMP_FLTCR_TAMPFREQ_1 (0x00000002UL)
8852+
#define TAMP_FLTCR_TAMPFREQ_2 (0x00000004UL)
88538853
#define TAMP_FLTCR_TAMPFREQ_Pos (0U)
88548854
#define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */
88558855
#define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk
8856-
#define TAMP_FLTCR_TAMPFLT_0 ((uint32_t)0x00000008)
8857-
#define TAMP_FLTCR_TAMPFLT_1 ((uint32_t)0x00000010)
8856+
#define TAMP_FLTCR_TAMPFLT_0 (0x00000008UL)
8857+
#define TAMP_FLTCR_TAMPFLT_1 (0x00000010UL)
88588858
#define TAMP_FLTCR_TAMPFLT_Pos (3U)
88598859
#define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */
88608860
#define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk
8861-
#define TAMP_FLTCR_TAMPPRCH_0 ((uint32_t)0x00000020)
8862-
#define TAMP_FLTCR_TAMPPRCH_1 ((uint32_t)0x00000040)
8861+
#define TAMP_FLTCR_TAMPPRCH_0 (0x00000020UL)
8862+
#define TAMP_FLTCR_TAMPPRCH_1 (0x00000040UL)
88638863
#define TAMP_FLTCR_TAMPPRCH_Pos (5U)
88648864
#define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */
88658865
#define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk
@@ -9903,35 +9903,35 @@ typedef struct
99039903

99049904
/****************** Bit definition for SYSCFG_SWPR register ****************/
99059905
#define SYSCFG_SWPR_PAGE0_Pos (0U)
9906-
#define SYSCFG_SWPR_PAGE0_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE0_Pos) /*!< 0x00000001 */
9907-
#define SYSCFG_SWPR_PAGE0 (uint32_t)(SYSCFG_SWPR_PAGE0_Msk) /*!< CCMSRAM Write protection page 0 */
9906+
#define SYSCFG_SWPR_PAGE0_Msk (0x1UL << SYSCFG_SWPR_PAGE0_Pos) /*!< 0x00000001 */
9907+
#define SYSCFG_SWPR_PAGE0 (SYSCFG_SWPR_PAGE0_Msk) /*!< CCMSRAM Write protection page 0 */
99089908
#define SYSCFG_SWPR_PAGE1_Pos (1U)
9909-
#define SYSCFG_SWPR_PAGE1_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE1_Pos) /*!< 0x00000002 */
9910-
#define SYSCFG_SWPR_PAGE1 (uint32_t)(SYSCFG_SWPR_PAGE1_Msk) /*!< CCMSRAM Write protection page 1 */
9909+
#define SYSCFG_SWPR_PAGE1_Msk (0x1UL << SYSCFG_SWPR_PAGE1_Pos) /*!< 0x00000002 */
9910+
#define SYSCFG_SWPR_PAGE1 (SYSCFG_SWPR_PAGE1_Msk) /*!< CCMSRAM Write protection page 1 */
99119911
#define SYSCFG_SWPR_PAGE2_Pos (2U)
9912-
#define SYSCFG_SWPR_PAGE2_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE2_Pos) /*!< 0x00000004 */
9913-
#define SYSCFG_SWPR_PAGE2 (uint32_t)(SYSCFG_SWPR_PAGE2_Msk) /*!< CCMSRAM Write protection page 2 */
9912+
#define SYSCFG_SWPR_PAGE2_Msk (0x1UL << SYSCFG_SWPR_PAGE2_Pos) /*!< 0x00000004 */
9913+
#define SYSCFG_SWPR_PAGE2 (SYSCFG_SWPR_PAGE2_Msk) /*!< CCMSRAM Write protection page 2 */
99149914
#define SYSCFG_SWPR_PAGE3_Pos (3U)
9915-
#define SYSCFG_SWPR_PAGE3_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE3_Pos) /*!< 0x00000008 */
9916-
#define SYSCFG_SWPR_PAGE3 (uint32_t)(SYSCFG_SWPR_PAGE3_Msk) /*!< CCMSRAM Write protection page 3 */
9915+
#define SYSCFG_SWPR_PAGE3_Msk (0x1UL << SYSCFG_SWPR_PAGE3_Pos) /*!< 0x00000008 */
9916+
#define SYSCFG_SWPR_PAGE3 (SYSCFG_SWPR_PAGE3_Msk) /*!< CCMSRAM Write protection page 3 */
99179917
#define SYSCFG_SWPR_PAGE4_Pos (4U)
9918-
#define SYSCFG_SWPR_PAGE4_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE4_Pos) /*!< 0x00000010 */
9919-
#define SYSCFG_SWPR_PAGE4 (uint32_t)(SYSCFG_SWPR_PAGE4_Msk) /*!< CCMSRAM Write protection page 4 */
9918+
#define SYSCFG_SWPR_PAGE4_Msk (0x1UL << SYSCFG_SWPR_PAGE4_Pos) /*!< 0x00000010 */
9919+
#define SYSCFG_SWPR_PAGE4 (SYSCFG_SWPR_PAGE4_Msk) /*!< CCMSRAM Write protection page 4 */
99209920
#define SYSCFG_SWPR_PAGE5_Pos (5U)
9921-
#define SYSCFG_SWPR_PAGE5_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE5_Pos) /*!< 0x00000020 */
9922-
#define SYSCFG_SWPR_PAGE5 (uint32_t)(SYSCFG_SWPR_PAGE5_Msk) /*!< CCMSRAM Write protection page 5 */
9921+
#define SYSCFG_SWPR_PAGE5_Msk (0x1UL << SYSCFG_SWPR_PAGE5_Pos) /*!< 0x00000020 */
9922+
#define SYSCFG_SWPR_PAGE5 (SYSCFG_SWPR_PAGE5_Msk) /*!< CCMSRAM Write protection page 5 */
99239923
#define SYSCFG_SWPR_PAGE6_Pos (6U)
9924-
#define SYSCFG_SWPR_PAGE6_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE6_Pos) /*!< 0x00000040 */
9925-
#define SYSCFG_SWPR_PAGE6 (uint32_t)(SYSCFG_SWPR_PAGE6_Msk) /*!< CCMSRAM Write protection page 6 */
9924+
#define SYSCFG_SWPR_PAGE6_Msk (0x1UL << SYSCFG_SWPR_PAGE6_Pos) /*!< 0x00000040 */
9925+
#define SYSCFG_SWPR_PAGE6 (SYSCFG_SWPR_PAGE6_Msk) /*!< CCMSRAM Write protection page 6 */
99269926
#define SYSCFG_SWPR_PAGE7_Pos (7U)
9927-
#define SYSCFG_SWPR_PAGE7_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE7_Pos) /*!< 0x00000080 */
9928-
#define SYSCFG_SWPR_PAGE7 (uint32_t)(SYSCFG_SWPR_PAGE7_Msk) /*!< CCMSRAM Write protection page 7 */
9927+
#define SYSCFG_SWPR_PAGE7_Msk (0x1UL << SYSCFG_SWPR_PAGE7_Pos) /*!< 0x00000080 */
9928+
#define SYSCFG_SWPR_PAGE7 (SYSCFG_SWPR_PAGE7_Msk) /*!< CCMSRAM Write protection page 7 */
99299929
#define SYSCFG_SWPR_PAGE8_Pos (8U)
9930-
#define SYSCFG_SWPR_PAGE8_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE8_Pos) /*!< 0x00000100 */
9931-
#define SYSCFG_SWPR_PAGE8 (uint32_t)(SYSCFG_SWPR_PAGE8_Msk) /*!< CCMSRAM Write protection page 8 */
9930+
#define SYSCFG_SWPR_PAGE8_Msk (0x1UL << SYSCFG_SWPR_PAGE8_Pos) /*!< 0x00000100 */
9931+
#define SYSCFG_SWPR_PAGE8 (SYSCFG_SWPR_PAGE8_Msk) /*!< CCMSRAM Write protection page 8 */
99329932
#define SYSCFG_SWPR_PAGE9_Pos (9U)
9933-
#define SYSCFG_SWPR_PAGE9_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE9_Pos) /*!< 0x00000200 */
9934-
#define SYSCFG_SWPR_PAGE9 (uint32_t)(SYSCFG_SWPR_PAGE9_Msk) /*!< CCMSRAM Write protection page 9 */
9933+
#define SYSCFG_SWPR_PAGE9_Msk (0x1UL << SYSCFG_SWPR_PAGE9_Pos) /*!< 0x00000200 */
9934+
#define SYSCFG_SWPR_PAGE9 (SYSCFG_SWPR_PAGE9_Msk) /*!< CCMSRAM Write protection page 9 */
99359935
/****************** Bit definition for SYSCFG_SKR register ****************/
99369936
#define SYSCFG_SKR_KEY_Pos (0U)
99379937
#define SYSCFG_SKR_KEY_Msk (0xFFUL << SYSCFG_SKR_KEY_Pos) /*!< 0x000000FF */
@@ -12978,9 +12978,6 @@ typedef struct
1297812978
((INSTANCE) == TIM16) || \
1297912979
((INSTANCE) == TIM17))
1298012980

12981-
/****************** TIM Instances : supporting synchronization ****************/
12982-
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
12983-
1298412981
/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
1298512982
#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
1298612983
((INSTANCE) == TIM8))

Diff for: ‎system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g441xx.h

+27-30
Original file line numberDiff line numberDiff line change
@@ -9078,19 +9078,19 @@ typedef struct
90789078
#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk
90799079

90809080
/******************** Bits definition for TAMP_FLTCR register ***************/
9081-
#define TAMP_FLTCR_TAMPFREQ_0 ((uint32_t)0x00000001)
9082-
#define TAMP_FLTCR_TAMPFREQ_1 ((uint32_t)0x00000002)
9083-
#define TAMP_FLTCR_TAMPFREQ_2 ((uint32_t)0x00000004)
9081+
#define TAMP_FLTCR_TAMPFREQ_0 (0x00000001UL)
9082+
#define TAMP_FLTCR_TAMPFREQ_1 (0x00000002UL)
9083+
#define TAMP_FLTCR_TAMPFREQ_2 (0x00000004UL)
90849084
#define TAMP_FLTCR_TAMPFREQ_Pos (0U)
90859085
#define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */
90869086
#define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk
9087-
#define TAMP_FLTCR_TAMPFLT_0 ((uint32_t)0x00000008)
9088-
#define TAMP_FLTCR_TAMPFLT_1 ((uint32_t)0x00000010)
9087+
#define TAMP_FLTCR_TAMPFLT_0 (0x00000008UL)
9088+
#define TAMP_FLTCR_TAMPFLT_1 (0x00000010UL)
90899089
#define TAMP_FLTCR_TAMPFLT_Pos (3U)
90909090
#define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */
90919091
#define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk
9092-
#define TAMP_FLTCR_TAMPPRCH_0 ((uint32_t)0x00000020)
9093-
#define TAMP_FLTCR_TAMPPRCH_1 ((uint32_t)0x00000040)
9092+
#define TAMP_FLTCR_TAMPPRCH_0 (0x00000020UL)
9093+
#define TAMP_FLTCR_TAMPPRCH_1 (0x00000040UL)
90949094
#define TAMP_FLTCR_TAMPPRCH_Pos (5U)
90959095
#define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */
90969096
#define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk
@@ -10134,35 +10134,35 @@ typedef struct
1013410134

1013510135
/****************** Bit definition for SYSCFG_SWPR register ****************/
1013610136
#define SYSCFG_SWPR_PAGE0_Pos (0U)
10137-
#define SYSCFG_SWPR_PAGE0_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE0_Pos) /*!< 0x00000001 */
10138-
#define SYSCFG_SWPR_PAGE0 (uint32_t)(SYSCFG_SWPR_PAGE0_Msk) /*!< CCMSRAM Write protection page 0 */
10137+
#define SYSCFG_SWPR_PAGE0_Msk (0x1UL << SYSCFG_SWPR_PAGE0_Pos) /*!< 0x00000001 */
10138+
#define SYSCFG_SWPR_PAGE0 (SYSCFG_SWPR_PAGE0_Msk) /*!< CCMSRAM Write protection page 0 */
1013910139
#define SYSCFG_SWPR_PAGE1_Pos (1U)
10140-
#define SYSCFG_SWPR_PAGE1_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE1_Pos) /*!< 0x00000002 */
10141-
#define SYSCFG_SWPR_PAGE1 (uint32_t)(SYSCFG_SWPR_PAGE1_Msk) /*!< CCMSRAM Write protection page 1 */
10140+
#define SYSCFG_SWPR_PAGE1_Msk (0x1UL << SYSCFG_SWPR_PAGE1_Pos) /*!< 0x00000002 */
10141+
#define SYSCFG_SWPR_PAGE1 (SYSCFG_SWPR_PAGE1_Msk) /*!< CCMSRAM Write protection page 1 */
1014210142
#define SYSCFG_SWPR_PAGE2_Pos (2U)
10143-
#define SYSCFG_SWPR_PAGE2_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE2_Pos) /*!< 0x00000004 */
10144-
#define SYSCFG_SWPR_PAGE2 (uint32_t)(SYSCFG_SWPR_PAGE2_Msk) /*!< CCMSRAM Write protection page 2 */
10143+
#define SYSCFG_SWPR_PAGE2_Msk (0x1UL << SYSCFG_SWPR_PAGE2_Pos) /*!< 0x00000004 */
10144+
#define SYSCFG_SWPR_PAGE2 (SYSCFG_SWPR_PAGE2_Msk) /*!< CCMSRAM Write protection page 2 */
1014510145
#define SYSCFG_SWPR_PAGE3_Pos (3U)
10146-
#define SYSCFG_SWPR_PAGE3_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE3_Pos) /*!< 0x00000008 */
10147-
#define SYSCFG_SWPR_PAGE3 (uint32_t)(SYSCFG_SWPR_PAGE3_Msk) /*!< CCMSRAM Write protection page 3 */
10146+
#define SYSCFG_SWPR_PAGE3_Msk (0x1UL << SYSCFG_SWPR_PAGE3_Pos) /*!< 0x00000008 */
10147+
#define SYSCFG_SWPR_PAGE3 (SYSCFG_SWPR_PAGE3_Msk) /*!< CCMSRAM Write protection page 3 */
1014810148
#define SYSCFG_SWPR_PAGE4_Pos (4U)
10149-
#define SYSCFG_SWPR_PAGE4_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE4_Pos) /*!< 0x00000010 */
10150-
#define SYSCFG_SWPR_PAGE4 (uint32_t)(SYSCFG_SWPR_PAGE4_Msk) /*!< CCMSRAM Write protection page 4 */
10149+
#define SYSCFG_SWPR_PAGE4_Msk (0x1UL << SYSCFG_SWPR_PAGE4_Pos) /*!< 0x00000010 */
10150+
#define SYSCFG_SWPR_PAGE4 (SYSCFG_SWPR_PAGE4_Msk) /*!< CCMSRAM Write protection page 4 */
1015110151
#define SYSCFG_SWPR_PAGE5_Pos (5U)
10152-
#define SYSCFG_SWPR_PAGE5_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE5_Pos) /*!< 0x00000020 */
10153-
#define SYSCFG_SWPR_PAGE5 (uint32_t)(SYSCFG_SWPR_PAGE5_Msk) /*!< CCMSRAM Write protection page 5 */
10152+
#define SYSCFG_SWPR_PAGE5_Msk (0x1UL << SYSCFG_SWPR_PAGE5_Pos) /*!< 0x00000020 */
10153+
#define SYSCFG_SWPR_PAGE5 (SYSCFG_SWPR_PAGE5_Msk) /*!< CCMSRAM Write protection page 5 */
1015410154
#define SYSCFG_SWPR_PAGE6_Pos (6U)
10155-
#define SYSCFG_SWPR_PAGE6_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE6_Pos) /*!< 0x00000040 */
10156-
#define SYSCFG_SWPR_PAGE6 (uint32_t)(SYSCFG_SWPR_PAGE6_Msk) /*!< CCMSRAM Write protection page 6 */
10155+
#define SYSCFG_SWPR_PAGE6_Msk (0x1UL << SYSCFG_SWPR_PAGE6_Pos) /*!< 0x00000040 */
10156+
#define SYSCFG_SWPR_PAGE6 (SYSCFG_SWPR_PAGE6_Msk) /*!< CCMSRAM Write protection page 6 */
1015710157
#define SYSCFG_SWPR_PAGE7_Pos (7U)
10158-
#define SYSCFG_SWPR_PAGE7_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE7_Pos) /*!< 0x00000080 */
10159-
#define SYSCFG_SWPR_PAGE7 (uint32_t)(SYSCFG_SWPR_PAGE7_Msk) /*!< CCMSRAM Write protection page 7 */
10158+
#define SYSCFG_SWPR_PAGE7_Msk (0x1UL << SYSCFG_SWPR_PAGE7_Pos) /*!< 0x00000080 */
10159+
#define SYSCFG_SWPR_PAGE7 (SYSCFG_SWPR_PAGE7_Msk) /*!< CCMSRAM Write protection page 7 */
1016010160
#define SYSCFG_SWPR_PAGE8_Pos (8U)
10161-
#define SYSCFG_SWPR_PAGE8_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE8_Pos) /*!< 0x00000100 */
10162-
#define SYSCFG_SWPR_PAGE8 (uint32_t)(SYSCFG_SWPR_PAGE8_Msk) /*!< CCMSRAM Write protection page 8 */
10161+
#define SYSCFG_SWPR_PAGE8_Msk (0x1UL << SYSCFG_SWPR_PAGE8_Pos) /*!< 0x00000100 */
10162+
#define SYSCFG_SWPR_PAGE8 (SYSCFG_SWPR_PAGE8_Msk) /*!< CCMSRAM Write protection page 8 */
1016310163
#define SYSCFG_SWPR_PAGE9_Pos (9U)
10164-
#define SYSCFG_SWPR_PAGE9_Msk (uint32_t)(0x1UL << SYSCFG_SWPR_PAGE9_Pos) /*!< 0x00000200 */
10165-
#define SYSCFG_SWPR_PAGE9 (uint32_t)(SYSCFG_SWPR_PAGE9_Msk) /*!< CCMSRAM Write protection page 9 */
10164+
#define SYSCFG_SWPR_PAGE9_Msk (0x1UL << SYSCFG_SWPR_PAGE9_Pos) /*!< 0x00000200 */
10165+
#define SYSCFG_SWPR_PAGE9 (SYSCFG_SWPR_PAGE9_Msk) /*!< CCMSRAM Write protection page 9 */
1016610166
/****************** Bit definition for SYSCFG_SKR register ****************/
1016710167
#define SYSCFG_SKR_KEY_Pos (0U)
1016810168
#define SYSCFG_SKR_KEY_Msk (0xFFUL << SYSCFG_SKR_KEY_Pos) /*!< 0x000000FF */
@@ -13211,9 +13211,6 @@ typedef struct
1321113211
((INSTANCE) == TIM16) || \
1321213212
((INSTANCE) == TIM17))
1321313213

13214-
/****************** TIM Instances : supporting synchronization ****************/
13215-
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
13216-
1321713214
/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
1321813215
#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
1321913216
((INSTANCE) == TIM8))

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