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variant(g4): register Generic G474CEUx board
* UFQFN48 (U) boards were missing from selection, only LQFP48 were available (T) * Copy missing linkerscript from G474CET * Copy missing SystemClock_Config and readjust for HSI16 into PLL150 and HSI48 CRS (for USB FS Device)
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Diff for: ‎boards.txt

+9
Original file line numberDiff line numberDiff line change
@@ -8101,6 +8101,15 @@ GenG4.menu.pnum.GENERIC_G474CETX.build.product_line=STM32G474xx
81018101
GenG4.menu.pnum.GENERIC_G474CETX.build.variant=STM32G4xx/G473C(B-C-E)T_G474C(B-C-E)T_G483CET_G484CET
81028102
GenG4.menu.pnum.GENERIC_G474CETX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G474.svd
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# Generic G474CEUx
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GenG4.menu.pnum.GENERIC_G474CEUX=Generic G474CEUx
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GenG4.menu.pnum.GENERIC_G474CEUX.upload.maximum_size=524288
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GenG4.menu.pnum.GENERIC_G474CEUX.upload.maximum_data_size=131072
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GenG4.menu.pnum.GENERIC_G474CEUX.build.board=GENERIC_G474CEUX
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GenG4.menu.pnum.GENERIC_G474CEUX.build.product_line=STM32G474xx
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GenG4.menu.pnum.GENERIC_G474CEUX.build.variant=STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU
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GenG4.menu.pnum.GENERIC_G474CEUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G474.svd
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81048113
# Generic G474MBTx
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GenG4.menu.pnum.GENERIC_G474MBTX=Generic G474MBTx
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GenG4.menu.pnum.GENERIC_G474MBTX.upload.maximum_size=131072

Diff for: ‎variants/STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU/generic_clock.c

+59-2
Original file line numberDiff line numberDiff line change
@@ -23,8 +23,65 @@
2323
*/
2424
WEAK void SystemClock_Config(void)
2525
{
26-
/* SystemClock_Config can be generated by STM32CubeMX */
27-
#warning "SystemClock_Config() is empty. Default clock at reset is used."
26+
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
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RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
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#ifdef USBCON
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RCC_CRSInitTypeDef pInit = {0};
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RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
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#endif
32+
33+
/* Configure the main internal regulator output voltage */
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HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
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/* Initializes the RCC Oscillators */
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
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RCC_OscInitStruct.HSIState = RCC_HSI_ON;
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RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
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RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
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RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV4;
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RCC_OscInitStruct.PLL.PLLN = 75;
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RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
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RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
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RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
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if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
49+
Error_Handler();
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}
51+
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/* Initializes the CPU, AHB and APB buses clocks */
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RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
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| RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
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RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
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RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
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if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
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Error_Handler();
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}
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#ifdef USBCON
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/* Enable the SYSCFG APB clock */
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__HAL_RCC_CRS_CLK_ENABLE();
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/* Configures CRS */
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pInit.Prescaler = RCC_CRS_SYNC_DIV1;
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pInit.Source = RCC_CRS_SYNC_SOURCE_USB;
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pInit.Polarity = RCC_CRS_SYNC_POLARITY_RISING;
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pInit.ReloadValue = __HAL_RCC_CRS_RELOADVALUE_CALCULATE(48000000,1000);
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pInit.ErrorLimitValue = 34;
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pInit.HSI48CalibrationValue = 32;
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HAL_RCCEx_CRSConfig(&pInit);
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/* Initializes the peripherals clocks */
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PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
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PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
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if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) {
82+
Error_Handler();
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}
84+
#endif
2885
}
2986

3087
#endif /* ARDUINO_GENERIC_* */

Diff for: ‎variants/STM32G4xx/G473C(B-C-E)U_G474C(B-C-E)U_G483CEU_G484CEU/ldscript.ld

+185
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,185 @@
1+
/*
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******************************************************************************
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**
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** @file : LinkerScript.ld
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**
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** @author : Auto-generated by STM32CubeIDE
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**
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** @brief : Linker script for STM32G473CBUx Device from STM32G4 series
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** 128Kbytes FLASH
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** 128Kbytes RAM
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**
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** Set heap size, stack size and stack location according
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** to application requirements.
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**
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** Set memory bank area and size if external memory is used
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**
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** Target : STMicroelectronics STM32
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**
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** Distribution: The file is distributed as is, without any warranty
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** of any kind.
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**
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******************************************************************************
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** @attention
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**
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** Copyright (c) 2022 STMicroelectronics.
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** All rights reserved.
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**
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** This software is licensed under terms that can be found in the LICENSE file
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** in the root directory of this software component.
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** If no LICENSE file comes with this software, it is provided AS-IS.
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**
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******************************************************************************
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*/
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/* Entry Point */
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ENTRY(Reset_Handler)
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/* Highest address of the user mode stack */
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_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
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_Min_Heap_Size = 0x200; /* required amount of heap */
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_Min_Stack_Size = 0x400; /* required amount of stack */
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/* Memories definition */
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MEMORY
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{
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RAM (xrw) : ORIGIN = 0x20000000, LENGTH = LD_MAX_DATA_SIZE
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FLASH (rx) : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
49+
}
50+
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/* Sections */
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SECTIONS
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{
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/* The startup code into "FLASH" Rom type memory */
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.isr_vector :
56+
{
57+
. = ALIGN(4);
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KEEP(*(.isr_vector)) /* Startup code */
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. = ALIGN(4);
60+
} >FLASH
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/* The program code and other data into "FLASH" Rom type memory */
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.text :
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{
65+
. = ALIGN(4);
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*(.text) /* .text sections (code) */
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*(.text*) /* .text* sections (code) */
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*(.glue_7) /* glue arm to thumb code */
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*(.glue_7t) /* glue thumb to arm code */
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*(.eh_frame)
71+
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KEEP (*(.init))
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KEEP (*(.fini))
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. = ALIGN(4);
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_etext = .; /* define a global symbols at end of code */
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} >FLASH
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79+
/* Constant data into "FLASH" Rom type memory */
80+
.rodata :
81+
{
82+
. = ALIGN(4);
83+
*(.rodata) /* .rodata sections (constants, strings, etc.) */
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*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
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. = ALIGN(4);
86+
} >FLASH
87+
88+
.ARM.extab (READONLY) : {
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. = ALIGN(4);
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*(.ARM.extab* .gnu.linkonce.armextab.*)
91+
. = ALIGN(4);
92+
} >FLASH
93+
94+
.ARM (READONLY) : {
95+
. = ALIGN(4);
96+
__exidx_start = .;
97+
*(.ARM.exidx*)
98+
__exidx_end = .;
99+
. = ALIGN(4);
100+
} >FLASH
101+
102+
.preinit_array (READONLY) :
103+
{
104+
. = ALIGN(4);
105+
PROVIDE_HIDDEN (__preinit_array_start = .);
106+
KEEP (*(.preinit_array*))
107+
PROVIDE_HIDDEN (__preinit_array_end = .);
108+
. = ALIGN(4);
109+
} >FLASH
110+
111+
.init_array (READONLY) :
112+
{
113+
. = ALIGN(4);
114+
PROVIDE_HIDDEN (__init_array_start = .);
115+
KEEP (*(SORT(.init_array.*)))
116+
KEEP (*(.init_array*))
117+
PROVIDE_HIDDEN (__init_array_end = .);
118+
. = ALIGN(4);
119+
} >FLASH
120+
121+
.fini_array (READONLY) :
122+
{
123+
. = ALIGN(4);
124+
PROVIDE_HIDDEN (__fini_array_start = .);
125+
KEEP (*(SORT(.fini_array.*)))
126+
KEEP (*(.fini_array*))
127+
PROVIDE_HIDDEN (__fini_array_end = .);
128+
. = ALIGN(4);
129+
} >FLASH
130+
131+
/* Used by the startup to initialize data */
132+
_sidata = LOADADDR(.data);
133+
134+
/* Initialized data sections into "RAM" Ram type memory */
135+
.data :
136+
{
137+
. = ALIGN(4);
138+
_sdata = .; /* create a global symbol at data start */
139+
*(.data) /* .data sections */
140+
*(.data*) /* .data* sections */
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*(.RamFunc) /* .RamFunc sections */
142+
*(.RamFunc*) /* .RamFunc* sections */
143+
144+
. = ALIGN(4);
145+
_edata = .; /* define a global symbol at data end */
146+
147+
} >RAM AT> FLASH
148+
149+
/* Uninitialized data section into "RAM" Ram type memory */
150+
. = ALIGN(4);
151+
.bss :
152+
{
153+
/* This is used by the startup in order to initialize the .bss section */
154+
_sbss = .; /* define a global symbol at bss start */
155+
__bss_start__ = _sbss;
156+
*(.bss)
157+
*(.bss*)
158+
*(COMMON)
159+
160+
. = ALIGN(4);
161+
_ebss = .; /* define a global symbol at bss end */
162+
__bss_end__ = _ebss;
163+
} >RAM
164+
165+
/* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
166+
._user_heap_stack :
167+
{
168+
. = ALIGN(8);
169+
PROVIDE ( end = . );
170+
PROVIDE ( _end = . );
171+
. = . + _Min_Heap_Size;
172+
. = . + _Min_Stack_Size;
173+
. = ALIGN(8);
174+
} >RAM
175+
176+
/* Remove information from the compiler libraries */
177+
/DISCARD/ :
178+
{
179+
libc.a ( * )
180+
libm.a ( * )
181+
libgcc.a ( * )
182+
}
183+
184+
.ARM.attributes 0 : { *(.ARM.attributes) }
185+
}

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