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fpistmfpistm
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Merge pull request #205 from fpistm/Driver_update
Update HAL and CMSIS Drivers to the latest version
2 parents 4892d54 + 8726db2 commit 5a9caf5

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‎system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f723xx.h

+34-13
Original file line numberDiff line numberDiff line change
@@ -14634,16 +14634,22 @@ typedef struct
1463414634
#define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
1463514635
#define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */
1463614636

14637-
/******************** Bit definition for USBPHYC_PLL register ********************/
14638-
#define USB_HS_PHYC_PLL_PLLEN_Pos (0U)
14639-
#define USB_HS_PHYC_PLL_PLLEN_Msk (0x1U << USB_HS_PHYC_PLL_PLLEN_Pos) /*!< 0x00000001 */
14640-
#define USB_HS_PHYC_PLL_PLLEN USB_HS_PHYC_PLL_PLLEN_Msk /*!< Enable PLL */
14641-
#define USB_HS_PHYC_PLL_PLLSEL_Pos (2U)
14642-
#define USB_HS_PHYC_PLL_PLLSEL_Msk (0x5U << USB_HS_PHYC_PLL_PLLSEL_Pos) /*!< 0x00000014 */
14643-
#define USB_HS_PHYC_PLL_PLLSEL USB_HS_PHYC_PLL_PLLSEL_Msk /*!< Controls PHY frequency operation selection */
14644-
#define USB_HS_PHYC_PLL_PLLSEL_1 (0x0U << USB_HS_PHYC_PLL_PLLSEL_Pos) /*!< 0x00000002 */
14645-
#define USB_HS_PHYC_PLL_PLLSEL_2 (0x1U << USB_HS_PHYC_PLL_PLLSEL_Pos) /*!< 0x00000004 */
14646-
#define USB_HS_PHYC_PLL_PLLSEL_3 (0x2U << USB_HS_PHYC_PLL_PLLSEL_Pos) /*!< 0x00000008 */
14637+
/******************** Bit definition for USBPHYC_PLL1 register ********************/
14638+
#define USB_HS_PHYC_PLL1_PLLEN_Pos (0U)
14639+
#define USB_HS_PHYC_PLL1_PLLEN_Msk (0x1U << USB_HS_PHYC_PLL1_PLLEN_Pos) /*!< 0x00000001 */
14640+
#define USB_HS_PHYC_PLL1_PLLEN USB_HS_PHYC_PLL1_PLLEN_Msk /*!< Enable PLL */
14641+
#define USB_HS_PHYC_PLL1_PLLSEL_Pos (1U)
14642+
#define USB_HS_PHYC_PLL1_PLLSEL_Msk (0x7U << USB_HS_PHYC_PLL1_PLLSEL_Pos) /*!< 0x0000000E */
14643+
#define USB_HS_PHYC_PLL1_PLLSEL USB_HS_PHYC_PLL1_PLLSEL_Msk /*!< Controls PHY frequency operation selection */
14644+
#define USB_HS_PHYC_PLL1_PLLSEL_1 (0x1U << USB_HS_PHYC_PLL1_PLLSEL_Pos) /*!< 0x00000002 */
14645+
#define USB_HS_PHYC_PLL1_PLLSEL_2 (0x2U << USB_HS_PHYC_PLL1_PLLSEL_Pos) /*!< 0x00000004 */
14646+
#define USB_HS_PHYC_PLL1_PLLSEL_3 (0x4U << USB_HS_PHYC_PLL1_PLLSEL_Pos) /*!< 0x00000008 */
14647+
14648+
#define USB_HS_PHYC_PLL1_PLLSEL_12MHZ 0x00000000U /*!< PHY PLL1 input clock frequency 12 MHz */
14649+
#define USB_HS_PHYC_PLL1_PLLSEL_12_5MHZ USB_HS_PHYC_PLL1_PLLSEL_1 /*!< PHY PLL1 input clock frequency 12.5 MHz */
14650+
#define USB_HS_PHYC_PLL1_PLLSEL_16MHZ (uint32_t)(USB_HS_PHYC_PLL1_PLLSEL_1 | USB_HS_PHYC_PLL1_PLLSEL_2) /*!< PHY PLL1 input clock frequency 16 MHz */
14651+
#define USB_HS_PHYC_PLL1_PLLSEL_24MHZ USB_HS_PHYC_PLL1_PLLSEL_3 /*!< PHY PLL1 input clock frequency 24 MHz */
14652+
#define USB_HS_PHYC_PLL1_PLLSEL_25MHZ (uint32_t)(USB_HS_PHYC_PLL1_PLLSEL_2 | USB_HS_PHYC_PLL1_PLLSEL_3) /*!< PHY PLL1 input clock frequency 25 MHz */
1464714653

1464814654
/******************** Bit definition for USBPHYC_LDO register ********************/
1464914655
#define USB_HS_PHYC_LDO_USED_Pos (0U)
@@ -14652,9 +14658,24 @@ typedef struct
1465214658
#define USB_HS_PHYC_LDO_STATUS_Pos (1U)
1465314659
#define USB_HS_PHYC_LDO_STATUS_Msk (0x1U << USB_HS_PHYC_LDO_STATUS_Pos) /*!< 0x00000002 */
1465414660
#define USB_HS_PHYC_LDO_STATUS USB_HS_PHYC_LDO_STATUS_Msk /*!< Monitors the status of the PHY's LDO. */
14655-
#define USB_HS_PHYC_LDO_ENABLE_Pos (2U)
14656-
#define USB_HS_PHYC_LDO_ENABLE_Msk (0x1U << USB_HS_PHYC_LDO_ENABLE_Pos) /*!< 0x00000004 */
14657-
#define USB_HS_PHYC_LDO_ENABLE USB_HS_PHYC_LDO_ENABLE_Msk /*!< Controls disable of the High Speed PHY's LDO */
14661+
#define USB_HS_PHYC_LDO_DISABLE_Pos (2U)
14662+
#define USB_HS_PHYC_LDO_DISABLE_Msk (0x1U << USB_HS_PHYC_LDO_DISABLE_Pos) /*!< 0x00000004 */
14663+
#define USB_HS_PHYC_LDO_DISABLE USB_HS_PHYC_LDO_DISABLE_Msk /*!< Controls disable of the High Speed PHY's LDO */
14664+
14665+
/* Legacy */
14666+
#define USB_HS_PHYC_PLL_PLLEN_Pos USB_HS_PHYC_PLL1_PLLEN_Pos
14667+
#define USB_HS_PHYC_PLL_PLLEN_Msk USB_HS_PHYC_PLL1_PLLEN_Msk
14668+
#define USB_HS_PHYC_PLL_PLLEN USB_HS_PHYC_PLL1_PLLEN
14669+
#define USB_HS_PHYC_PLL_PLLSEL_Pos USB_HS_PHYC_PLL1_PLLSEL_Pos
14670+
#define USB_HS_PHYC_PLL_PLLSEL_Msk USB_HS_PHYC_PLL1_PLLSEL_Msk
14671+
#define USB_HS_PHYC_PLL_PLLSEL USB_HS_PHYC_PLL1_PLLSEL
14672+
#define USB_HS_PHYC_PLL_PLLSEL_1 USB_HS_PHYC_PLL1_PLLSEL_1
14673+
#define USB_HS_PHYC_PLL_PLLSEL_2 USB_HS_PHYC_PLL1_PLLSEL_2
14674+
#define USB_HS_PHYC_PLL_PLLSEL_3 USB_HS_PHYC_PLL1_PLLSEL_3
14675+
14676+
#define USB_HS_PHYC_LDO_ENABLE_Pos USB_HS_PHYC_LDO_DISABLE_Pos
14677+
#define USB_HS_PHYC_LDO_ENABLE_Msk USB_HS_PHYC_LDO_DISABLE_Msk
14678+
#define USB_HS_PHYC_LDO_ENABLE USB_HS_PHYC_LDO_DISABLE
1465814679

1465914680

1466014681

‎system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f733xx.h

+34-13
Original file line numberDiff line numberDiff line change
@@ -14857,16 +14857,22 @@ typedef struct
1485714857
#define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
1485814858
#define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */
1485914859

14860-
/******************** Bit definition for USBPHYC_PLL register ********************/
14861-
#define USB_HS_PHYC_PLL_PLLEN_Pos (0U)
14862-
#define USB_HS_PHYC_PLL_PLLEN_Msk (0x1U << USB_HS_PHYC_PLL_PLLEN_Pos) /*!< 0x00000001 */
14863-
#define USB_HS_PHYC_PLL_PLLEN USB_HS_PHYC_PLL_PLLEN_Msk /*!< Enable PLL */
14864-
#define USB_HS_PHYC_PLL_PLLSEL_Pos (2U)
14865-
#define USB_HS_PHYC_PLL_PLLSEL_Msk (0x5U << USB_HS_PHYC_PLL_PLLSEL_Pos) /*!< 0x00000014 */
14866-
#define USB_HS_PHYC_PLL_PLLSEL USB_HS_PHYC_PLL_PLLSEL_Msk /*!< Controls PHY frequency operation selection */
14867-
#define USB_HS_PHYC_PLL_PLLSEL_1 (0x0U << USB_HS_PHYC_PLL_PLLSEL_Pos) /*!< 0x00000002 */
14868-
#define USB_HS_PHYC_PLL_PLLSEL_2 (0x1U << USB_HS_PHYC_PLL_PLLSEL_Pos) /*!< 0x00000004 */
14869-
#define USB_HS_PHYC_PLL_PLLSEL_3 (0x2U << USB_HS_PHYC_PLL_PLLSEL_Pos) /*!< 0x00000008 */
14860+
/******************** Bit definition for USBPHYC_PLL1 register ********************/
14861+
#define USB_HS_PHYC_PLL1_PLLEN_Pos (0U)
14862+
#define USB_HS_PHYC_PLL1_PLLEN_Msk (0x1U << USB_HS_PHYC_PLL1_PLLEN_Pos) /*!< 0x00000001 */
14863+
#define USB_HS_PHYC_PLL1_PLLEN USB_HS_PHYC_PLL1_PLLEN_Msk /*!< Enable PLL */
14864+
#define USB_HS_PHYC_PLL1_PLLSEL_Pos (1U)
14865+
#define USB_HS_PHYC_PLL1_PLLSEL_Msk (0x7U << USB_HS_PHYC_PLL1_PLLSEL_Pos) /*!< 0x0000000E */
14866+
#define USB_HS_PHYC_PLL1_PLLSEL USB_HS_PHYC_PLL1_PLLSEL_Msk /*!< Controls PHY frequency operation selection */
14867+
#define USB_HS_PHYC_PLL1_PLLSEL_1 (0x1U << USB_HS_PHYC_PLL1_PLLSEL_Pos) /*!< 0x00000002 */
14868+
#define USB_HS_PHYC_PLL1_PLLSEL_2 (0x2U << USB_HS_PHYC_PLL1_PLLSEL_Pos) /*!< 0x00000004 */
14869+
#define USB_HS_PHYC_PLL1_PLLSEL_3 (0x4U << USB_HS_PHYC_PLL1_PLLSEL_Pos) /*!< 0x00000008 */
14870+
14871+
#define USB_HS_PHYC_PLL1_PLLSEL_12MHZ 0x00000000U /*!< PHY PLL1 input clock frequency 12 MHz */
14872+
#define USB_HS_PHYC_PLL1_PLLSEL_12_5MHZ USB_HS_PHYC_PLL1_PLLSEL_1 /*!< PHY PLL1 input clock frequency 12.5 MHz */
14873+
#define USB_HS_PHYC_PLL1_PLLSEL_16MHZ (uint32_t)(USB_HS_PHYC_PLL1_PLLSEL_1 | USB_HS_PHYC_PLL1_PLLSEL_2) /*!< PHY PLL1 input clock frequency 16 MHz */
14874+
#define USB_HS_PHYC_PLL1_PLLSEL_24MHZ USB_HS_PHYC_PLL1_PLLSEL_3 /*!< PHY PLL1 input clock frequency 24 MHz */
14875+
#define USB_HS_PHYC_PLL1_PLLSEL_25MHZ (uint32_t)(USB_HS_PHYC_PLL1_PLLSEL_2 | USB_HS_PHYC_PLL1_PLLSEL_3) /*!< PHY PLL1 input clock frequency 25 MHz */
1487014876

1487114877
/******************** Bit definition for USBPHYC_LDO register ********************/
1487214878
#define USB_HS_PHYC_LDO_USED_Pos (0U)
@@ -14875,9 +14881,24 @@ typedef struct
1487514881
#define USB_HS_PHYC_LDO_STATUS_Pos (1U)
1487614882
#define USB_HS_PHYC_LDO_STATUS_Msk (0x1U << USB_HS_PHYC_LDO_STATUS_Pos) /*!< 0x00000002 */
1487714883
#define USB_HS_PHYC_LDO_STATUS USB_HS_PHYC_LDO_STATUS_Msk /*!< Monitors the status of the PHY's LDO. */
14878-
#define USB_HS_PHYC_LDO_ENABLE_Pos (2U)
14879-
#define USB_HS_PHYC_LDO_ENABLE_Msk (0x1U << USB_HS_PHYC_LDO_ENABLE_Pos) /*!< 0x00000004 */
14880-
#define USB_HS_PHYC_LDO_ENABLE USB_HS_PHYC_LDO_ENABLE_Msk /*!< Controls disable of the High Speed PHY's LDO */
14884+
#define USB_HS_PHYC_LDO_DISABLE_Pos (2U)
14885+
#define USB_HS_PHYC_LDO_DISABLE_Msk (0x1U << USB_HS_PHYC_LDO_DISABLE_Pos) /*!< 0x00000004 */
14886+
#define USB_HS_PHYC_LDO_DISABLE USB_HS_PHYC_LDO_DISABLE_Msk /*!< Controls disable of the High Speed PHY's LDO */
14887+
14888+
/* Legacy */
14889+
#define USB_HS_PHYC_PLL_PLLEN_Pos USB_HS_PHYC_PLL1_PLLEN_Pos
14890+
#define USB_HS_PHYC_PLL_PLLEN_Msk USB_HS_PHYC_PLL1_PLLEN_Msk
14891+
#define USB_HS_PHYC_PLL_PLLEN USB_HS_PHYC_PLL1_PLLEN
14892+
#define USB_HS_PHYC_PLL_PLLSEL_Pos USB_HS_PHYC_PLL1_PLLSEL_Pos
14893+
#define USB_HS_PHYC_PLL_PLLSEL_Msk USB_HS_PHYC_PLL1_PLLSEL_Msk
14894+
#define USB_HS_PHYC_PLL_PLLSEL USB_HS_PHYC_PLL1_PLLSEL
14895+
#define USB_HS_PHYC_PLL_PLLSEL_1 USB_HS_PHYC_PLL1_PLLSEL_1
14896+
#define USB_HS_PHYC_PLL_PLLSEL_2 USB_HS_PHYC_PLL1_PLLSEL_2
14897+
#define USB_HS_PHYC_PLL_PLLSEL_3 USB_HS_PHYC_PLL1_PLLSEL_3
14898+
14899+
#define USB_HS_PHYC_LDO_ENABLE_Pos USB_HS_PHYC_LDO_DISABLE_Pos
14900+
#define USB_HS_PHYC_LDO_ENABLE_Msk USB_HS_PHYC_LDO_DISABLE_Msk
14901+
#define USB_HS_PHYC_LDO_ENABLE USB_HS_PHYC_LDO_DISABLE
1488114902

1488214903

1488314904

‎system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h

+2-2
Original file line numberDiff line numberDiff line change
@@ -109,11 +109,11 @@
109109
#endif /* USE_HAL_DRIVER */
110110

111111
/**
112-
* @brief CMSIS Device version number V1.2.1
112+
* @brief CMSIS Device version number V1.2.2
113113
*/
114114
#define __STM32F7_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
115115
#define __STM32F7_CMSIS_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
116-
#define __STM32F7_CMSIS_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
116+
#define __STM32F7_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
117117
#define __STM32F7_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
118118
#define __STM32F7_CMSIS_VERSION ((__STM32F7_CMSIS_VERSION_MAIN << 24)\
119119
|(__STM32F7_CMSIS_VERSION_SUB1 << 16)\

‎system/Drivers/CMSIS/Device/ST/STM32F7xx/Release_Notes.html

+5-2
Large diffs are not rendered by default.

‎system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l100xb.h

+25-3
Original file line numberDiff line numberDiff line change
@@ -423,10 +423,12 @@ typedef struct
423423
typedef struct
424424
{
425425
__IO uint32_t ICR; /*!< RI input capture register, Address offset: 0x00 */
426-
__IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */
427-
__IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */
426+
__IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */
427+
__IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */
428428
__IO uint32_t HYSCR1; /*!< RI hysteresis control register, Address offset: 0x0C */
429-
__IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */
429+
__IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */
430+
__IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */
431+
uint32_t RESERVED1; /*!< Reserved, Address offset: 0x18 */
430432
} RI_TypeDef;
431433

432434
/**
@@ -5584,6 +5586,26 @@ typedef struct
55845586
#define RI_HYSCR2_PD_14 (0x4000U << RI_HYSCR2_PD_Pos) /*!< 0x40000000 */
55855587
#define RI_HYSCR2_PD_15 (0x8000U << RI_HYSCR2_PD_Pos) /*!< 0x80000000 */
55865588

5589+
/******************** Bit definition for RI_HYSCR3 register ********************/
5590+
#define RI_HYSCR3_PE_Pos (0U)
5591+
#define RI_HYSCR3_PE_Msk (0xFFFFU << RI_HYSCR3_PE_Pos) /*!< 0x0000FFFF */
5592+
#define RI_HYSCR3_PE RI_HYSCR3_PE_Msk /*!< PE[15:0] Port E Hysteresis selection */
5593+
#define RI_HYSCR3_PE_0 (0x0001U << RI_HYSCR3_PE_Pos) /*!< 0x00000001 */
5594+
#define RI_HYSCR3_PE_1 (0x0002U << RI_HYSCR3_PE_Pos) /*!< 0x00000002 */
5595+
#define RI_HYSCR3_PE_2 (0x0004U << RI_HYSCR3_PE_Pos) /*!< 0x00000004 */
5596+
#define RI_HYSCR3_PE_3 (0x0008U << RI_HYSCR3_PE_Pos) /*!< 0x00000008 */
5597+
#define RI_HYSCR3_PE_4 (0x0010U << RI_HYSCR3_PE_Pos) /*!< 0x00000010 */
5598+
#define RI_HYSCR3_PE_5 (0x0020U << RI_HYSCR3_PE_Pos) /*!< 0x00000020 */
5599+
#define RI_HYSCR3_PE_6 (0x0040U << RI_HYSCR3_PE_Pos) /*!< 0x00000040 */
5600+
#define RI_HYSCR3_PE_7 (0x0080U << RI_HYSCR3_PE_Pos) /*!< 0x00000080 */
5601+
#define RI_HYSCR3_PE_8 (0x0100U << RI_HYSCR3_PE_Pos) /*!< 0x00000100 */
5602+
#define RI_HYSCR3_PE_9 (0x0200U << RI_HYSCR3_PE_Pos) /*!< 0x00000200 */
5603+
#define RI_HYSCR3_PE_10 (0x0400U << RI_HYSCR3_PE_Pos) /*!< 0x00000400 */
5604+
#define RI_HYSCR3_PE_11 (0x0800U << RI_HYSCR3_PE_Pos) /*!< 0x00000800 */
5605+
#define RI_HYSCR3_PE_12 (0x1000U << RI_HYSCR3_PE_Pos) /*!< 0x00001000 */
5606+
#define RI_HYSCR3_PE_13 (0x2000U << RI_HYSCR3_PE_Pos) /*!< 0x00002000 */
5607+
#define RI_HYSCR3_PE_14 (0x4000U << RI_HYSCR3_PE_Pos) /*!< 0x00004000 */
5608+
#define RI_HYSCR3_PE_15 (0x8000U << RI_HYSCR3_PE_Pos) /*!< 0x00008000 */
55875609

55885610
/******************************************************************************/
55895611
/* */

‎system/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l100xba.h

+25-3
Original file line numberDiff line numberDiff line change
@@ -423,10 +423,12 @@ typedef struct
423423
typedef struct
424424
{
425425
__IO uint32_t ICR; /*!< RI input capture register, Address offset: 0x00 */
426-
__IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */
427-
__IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */
426+
__IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */
427+
__IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */
428428
__IO uint32_t HYSCR1; /*!< RI hysteresis control register, Address offset: 0x0C */
429-
__IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */
429+
__IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */
430+
__IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */
431+
uint32_t RESERVED1; /*!< Reserved, Address offset: 0x18 */
430432
} RI_TypeDef;
431433

432434
/**
@@ -5732,6 +5734,26 @@ typedef struct
57325734
#define RI_HYSCR2_PD_14 (0x4000U << RI_HYSCR2_PD_Pos) /*!< 0x40000000 */
57335735
#define RI_HYSCR2_PD_15 (0x8000U << RI_HYSCR2_PD_Pos) /*!< 0x80000000 */
57345736

5737+
/******************** Bit definition for RI_HYSCR3 register ********************/
5738+
#define RI_HYSCR3_PE_Pos (0U)
5739+
#define RI_HYSCR3_PE_Msk (0xFFFFU << RI_HYSCR3_PE_Pos) /*!< 0x0000FFFF */
5740+
#define RI_HYSCR3_PE RI_HYSCR3_PE_Msk /*!< PE[15:0] Port E Hysteresis selection */
5741+
#define RI_HYSCR3_PE_0 (0x0001U << RI_HYSCR3_PE_Pos) /*!< 0x00000001 */
5742+
#define RI_HYSCR3_PE_1 (0x0002U << RI_HYSCR3_PE_Pos) /*!< 0x00000002 */
5743+
#define RI_HYSCR3_PE_2 (0x0004U << RI_HYSCR3_PE_Pos) /*!< 0x00000004 */
5744+
#define RI_HYSCR3_PE_3 (0x0008U << RI_HYSCR3_PE_Pos) /*!< 0x00000008 */
5745+
#define RI_HYSCR3_PE_4 (0x0010U << RI_HYSCR3_PE_Pos) /*!< 0x00000010 */
5746+
#define RI_HYSCR3_PE_5 (0x0020U << RI_HYSCR3_PE_Pos) /*!< 0x00000020 */
5747+
#define RI_HYSCR3_PE_6 (0x0040U << RI_HYSCR3_PE_Pos) /*!< 0x00000040 */
5748+
#define RI_HYSCR3_PE_7 (0x0080U << RI_HYSCR3_PE_Pos) /*!< 0x00000080 */
5749+
#define RI_HYSCR3_PE_8 (0x0100U << RI_HYSCR3_PE_Pos) /*!< 0x00000100 */
5750+
#define RI_HYSCR3_PE_9 (0x0200U << RI_HYSCR3_PE_Pos) /*!< 0x00000200 */
5751+
#define RI_HYSCR3_PE_10 (0x0400U << RI_HYSCR3_PE_Pos) /*!< 0x00000400 */
5752+
#define RI_HYSCR3_PE_11 (0x0800U << RI_HYSCR3_PE_Pos) /*!< 0x00000800 */
5753+
#define RI_HYSCR3_PE_12 (0x1000U << RI_HYSCR3_PE_Pos) /*!< 0x00001000 */
5754+
#define RI_HYSCR3_PE_13 (0x2000U << RI_HYSCR3_PE_Pos) /*!< 0x00002000 */
5755+
#define RI_HYSCR3_PE_14 (0x4000U << RI_HYSCR3_PE_Pos) /*!< 0x00004000 */
5756+
#define RI_HYSCR3_PE_15 (0x8000U << RI_HYSCR3_PE_Pos) /*!< 0x00008000 */
57355757

57365758
/******************************************************************************/
57375759
/* */

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