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fpistmmrguen
fpistm
and
mrguen
committedAug 27, 2019
Core Board F401RC
Fixes #594 Co-authored-by: Thierry GUENNOU <[email protected]> Signed-off-by: Frederic.Pillon <[email protected]>
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‎README.md

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@@ -113,6 +113,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d
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| :yellow_heart: | BlackPill F401CC | **1.7.0** | |
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| :green_heart: | [Black F407VET6](https://stm32-base.org/boards/STM32F407VET6-STM32-F4VE-V2.0) | *1.4.0* | VG/ZE/ZG in *1.5.0* |
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| :green_heart: | [Blue F407VET6 Mini](https://stm32-base.org/boards/STM32F407VET6-VCC-GND-Small) | *1.4.0* | |
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| :yellow_heart: | Core Board F401RC | **1.7.0** | |
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| :green_heart: | [DIYMROE STM32F407VGT](https://stm32-base.org/boards/STM32F407VGT6-diymore) | *1.5.0* | |
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| :green_heart: | FK407M1 | *1.5.0* | |
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‎boards.txt

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@@ -905,6 +905,14 @@ GenF4.menu.pnum.BLACKPILL_F401CC.build.board=BLACKPILL_F401CC
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GenF4.menu.pnum.BLACKPILL_F401CC.build.product_line=STM32F401xC
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GenF4.menu.pnum.BLACKPILL_F401CC.build.variant=PILL_F401XX
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# Core board F401RCT6
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GenF4.menu.pnum.CoreBoard_F401RC=Core board F401RCT6
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GenF4.menu.pnum.CoreBoard_F401RC.upload.maximum_size=262144
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GenF4.menu.pnum.CoreBoard_F401RC.upload.maximum_data_size=65536
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GenF4.menu.pnum.CoreBoard_F401RC.build.board=CoreBoard_F401RC
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GenF4.menu.pnum.CoreBoard_F401RC.build.product_line=STM32F401xC
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GenF4.menu.pnum.CoreBoard_F401RC.build.variant=CoreBoard_F401RC
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# Upload menu
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GenF4.menu.upload_method.swdMethod=STM32CubeProgrammer (SWD)
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GenF4.menu.upload_method.swdMethod.upload.protocol=0

‎variants/CoreBoard_F401RC/PeripheralPins.c

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/*
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*******************************************************************************
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* Copyright (c) 2019, STMicroelectronics
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* All rights reserved.
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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*******************************************************************************
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* Automatically generated from STM32F401R(B-C)Tx.xml
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*/
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#include "Arduino.h"
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#include "PeripheralPins.h"
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/* =====
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* Note: Commented lines are alternative possibilities which are not used per default.
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* If you change them, you will have to know what you do
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* =====
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*/
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//*** ADC ***
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#ifdef HAL_ADC_MODULE_ENABLED
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WEAK const PinMap PinMap_ADC[] = {
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{PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0
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{PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1
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{PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2
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{PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3
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{PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4
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{PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5
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{PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6
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{PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7
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{PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8
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{PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9
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{PC_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10
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{PC_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11
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{PC_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12
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{PC_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13
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{PC_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14
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{PC_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15
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{NC, NP, 0}
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};
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#endif
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//*** No DAC ***
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//*** I2C ***
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#ifdef HAL_I2C_MODULE_ENABLED
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WEAK const PinMap PinMap_I2C_SDA[] = {
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{PB_3, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C2)},
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{PB_4, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C3)},
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{PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
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{PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
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{PC_9, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
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{NC, NP, 0}
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};
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#endif
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#ifdef HAL_I2C_MODULE_ENABLED
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WEAK const PinMap PinMap_I2C_SCL[] = {
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{PA_8, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
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{PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
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{PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
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{PB_10, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
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{NC, NP, 0}
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};
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#endif
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//*** PWM ***
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#ifdef HAL_TIM_MODULE_ENABLED
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WEAK const PinMap PinMap_PWM[] = {
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{PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
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// {PA_0, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1
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// {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2
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{PA_1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2
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// {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3
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// {PA_2, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3
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{PA_2, TIM9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1
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{PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4
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// {PA_3, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4
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// {PA_3, TIM9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2
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{PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
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{PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
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{PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
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// {PA_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
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{PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1
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{PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2
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{PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3
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// {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4
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{PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
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// {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
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{PB_0, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
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{PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
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// {PB_1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
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{PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2
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{PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
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{PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
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{PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1
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{PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2
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// {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3
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{PB_8, TIM10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1
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// {PB_9, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4
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{PB_9, TIM11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1
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{PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3
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{PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
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{PB_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
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{PB_15, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
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{PC_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
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{PC_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
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{PC_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
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{PC_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
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{NC, NP, 0}
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};
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#endif
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//*** SERIAL ***
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#ifdef HAL_UART_MODULE_ENABLED
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WEAK const PinMap PinMap_UART_TX[] = {
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{PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
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{PA_9, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
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// {PA_11, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
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{PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
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{PC_6, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
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{NC, NP, 0}
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};
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#endif
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#ifdef HAL_UART_MODULE_ENABLED
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WEAK const PinMap PinMap_UART_RX[] = {
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{PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
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{PA_10, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
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// {PA_12, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
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{PB_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
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{PC_7, USART6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
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{NC, NP, 0}
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};
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#endif
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#ifdef HAL_UART_MODULE_ENABLED
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WEAK const PinMap PinMap_UART_RTS[] = {
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{PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
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// {PA_12, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
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{NC, NP, 0}
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};
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#endif
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#ifdef HAL_UART_MODULE_ENABLED
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WEAK const PinMap PinMap_UART_CTS[] = {
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{PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
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// {PA_11, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
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{NC, NP, 0}
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};
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#endif
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//*** SPI ***
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#ifdef HAL_SPI_MODULE_ENABLED
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WEAK const PinMap PinMap_SPI_MOSI[] = {
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{PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
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// {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
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{PB_5, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
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{PB_15, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
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{PC_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
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{PC_12, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
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{NC, NP, 0}
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};
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#endif
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#ifdef HAL_SPI_MODULE_ENABLED
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WEAK const PinMap PinMap_SPI_MISO[] = {
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{PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
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// {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
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{PB_4, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
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{PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
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{PC_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
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{PC_11, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
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{NC, NP, 0}
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};
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#endif
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#ifdef HAL_SPI_MODULE_ENABLED
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WEAK const PinMap PinMap_SPI_SCLK[] = {
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{PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
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// {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
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{PB_3, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
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{PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
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{PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
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{PC_10, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
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{NC, NP, 0}
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};
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#endif
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#ifdef HAL_SPI_MODULE_ENABLED
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WEAK const PinMap PinMap_SPI_SSEL[] = {
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{PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
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// {PA_4, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
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// {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
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{PA_15, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
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{PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
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{PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
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{NC, NP, 0}
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};
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#endif
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//*** No CAN ***
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//*** No ETHERNET ***
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//*** No QUADSPI ***
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//*** USB ***
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#ifdef HAL_PCD_MODULE_ENABLED
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WEAK const PinMap PinMap_USB_OTG_FS[] = {
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// {PA_8, USB_OTG_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_FS)}, // USB_OTG_FS_SOF
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// {PA_9, USB_OTG_FS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_OTG_FS_VBUS
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{PA_10, USB_OTG_FS, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF10_OTG_FS)}, // USB_OTG_FS_ID
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{PA_11, USB_OTG_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_FS)}, // USB_OTG_FS_DM
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{PA_12, USB_OTG_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_FS)}, // USB_OTG_FS_DP
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{NC, NP, 0}
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};
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#endif
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//*** No USB_OTG_HS ***
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//*** SD ***
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#ifdef HAL_SD_MODULE_ENABLED
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WEAK const PinMap PinMap_SD[] = {
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{PB_8, SDIO, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDIO)}, // SDIO_D4
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{PB_9, SDIO, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDIO)}, // SDIO_D5
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{PC_6, SDIO, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDIO)}, // SDIO_D6
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{PC_7, SDIO, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDIO)}, // SDIO_D7
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{PC_8, SDIO, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDIO)}, // SDIO_D0
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{PC_9, SDIO, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDIO)}, // SDIO_D1
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{PC_10, SDIO, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDIO)}, // SDIO_D2
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{PC_11, SDIO, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDIO)}, // SDIO_D3
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{PC_12, SDIO, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDIO)}, // SDIO_CK
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{PD_2, SDIO, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDIO)}, // SDIO_CMD
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{NC, NP, 0}
246+
};
247+
#endif

‎variants/CoreBoard_F401RC/PinNamesVar.h

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1+
/* SYS_WKUP */
2+
#ifdef PWR_WAKEUP_PIN1
3+
SYS_WKUP1 = PA_0,
4+
#endif
5+
#ifdef PWR_WAKEUP_PIN2
6+
SYS_WKUP2 = NC,
7+
#endif
8+
#ifdef PWR_WAKEUP_PIN3
9+
SYS_WKUP3 = NC,
10+
#endif
11+
#ifdef PWR_WAKEUP_PIN4
12+
SYS_WKUP4 = NC,
13+
#endif
14+
#ifdef PWR_WAKEUP_PIN5
15+
SYS_WKUP5 = NC,
16+
#endif
17+
#ifdef PWR_WAKEUP_PIN6
18+
SYS_WKUP6 = NC,
19+
#endif
20+
#ifdef PWR_WAKEUP_PIN7
21+
SYS_WKUP7 = NC,
22+
#endif
23+
#ifdef PWR_WAKEUP_PIN8
24+
SYS_WKUP8 = NC,
25+
#endif
26+
/* USB */
27+
#ifdef USBCON
28+
USB_OTG_FS_SOF = PA_8,
29+
USB_OTG_FS_VBUS = PA_9,
30+
USB_OTG_FS_ID = PA_10,
31+
USB_OTG_FS_DM = PA_11,
32+
USB_OTG_FS_DP = PA_12,
33+
#endif

‎variants/CoreBoard_F401RC/ldscript.ld

Lines changed: 200 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,200 @@
1+
/*
2+
******************************************************************************
3+
**
4+
** File : LinkerScript.ld
5+
**
6+
** Author : Auto-generated by STM32CubeIDE
7+
**
8+
** Abstract : Linker script for STM32F401RCTx Device from STM32F4 series
9+
** 256Kbytes FLASH
10+
** 64Kbytes RAM
11+
**
12+
** Set heap size, stack size and stack location according
13+
** to application requirements.
14+
**
15+
** Set memory bank area and size if external memory is used.
16+
**
17+
** Target : STMicroelectronics STM32
18+
**
19+
** Distribution: The file is distributed as is without any warranty
20+
** of any kind.
21+
**
22+
*****************************************************************************
23+
** @attention
24+
**
25+
** <h2><center>&copy; COPYRIGHT(c) 2019 STMicroelectronics</center></h2>
26+
**
27+
** Redistribution and use in source and binary forms, with or without modification,
28+
** are permitted provided that the following conditions are met:
29+
** 1. Redistributions of source code must retain the above copyright notice,
30+
** this list of conditions and the following disclaimer.
31+
** 2. Redistributions in binary form must reproduce the above copyright notice,
32+
** this list of conditions and the following disclaimer in the documentation
33+
** and/or other materials provided with the distribution.
34+
** 3. Neither the name of STMicroelectronics nor the names of its contributors
35+
** may be used to endorse or promote products derived from this software
36+
** without specific prior written permission.
37+
**
38+
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
39+
** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
40+
** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
41+
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
42+
** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
43+
** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
44+
** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
45+
** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
46+
** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
47+
** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
48+
**
49+
*****************************************************************************
50+
*/
51+
52+
/* Entry Point */
53+
ENTRY(Reset_Handler)
54+
55+
/* Highest address of the user mode stack */
56+
_estack = 0x20010000; /* end of "RAM" Ram type memory */
57+
58+
_Min_Heap_Size = 0x200; /* required amount of heap */
59+
_Min_Stack_Size = 0x400; /* required amount of stack */
60+
61+
/* Memories definition */
62+
MEMORY
63+
{
64+
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K
65+
FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 256K
66+
}
67+
68+
/* Sections */
69+
SECTIONS
70+
{
71+
/* The startup code into "FLASH" Rom type memory */
72+
.isr_vector :
73+
{
74+
. = ALIGN(4);
75+
KEEP(*(.isr_vector)) /* Startup code */
76+
. = ALIGN(4);
77+
} >FLASH
78+
79+
/* The program code and other data into "FLASH" Rom type memory */
80+
.text :
81+
{
82+
. = ALIGN(4);
83+
*(.text) /* .text sections (code) */
84+
*(.text*) /* .text* sections (code) */
85+
*(.glue_7) /* glue arm to thumb code */
86+
*(.glue_7t) /* glue thumb to arm code */
87+
*(.eh_frame)
88+
89+
KEEP (*(.init))
90+
KEEP (*(.fini))
91+
92+
. = ALIGN(4);
93+
_etext = .; /* define a global symbols at end of code */
94+
} >FLASH
95+
96+
/* Constant data into "FLASH" Rom type memory */
97+
.rodata :
98+
{
99+
. = ALIGN(4);
100+
*(.rodata) /* .rodata sections (constants, strings, etc.) */
101+
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
102+
. = ALIGN(4);
103+
} >FLASH
104+
105+
.ARM.extab : {
106+
. = ALIGN(4);
107+
*(.ARM.extab* .gnu.linkonce.armextab.*)
108+
. = ALIGN(4);
109+
} >FLASH
110+
111+
.ARM : {
112+
. = ALIGN(4);
113+
__exidx_start = .;
114+
*(.ARM.exidx*)
115+
__exidx_end = .;
116+
. = ALIGN(4);
117+
} >FLASH
118+
119+
.preinit_array :
120+
{
121+
. = ALIGN(4);
122+
PROVIDE_HIDDEN (__preinit_array_start = .);
123+
KEEP (*(.preinit_array*))
124+
PROVIDE_HIDDEN (__preinit_array_end = .);
125+
. = ALIGN(4);
126+
} >FLASH
127+
128+
.init_array :
129+
{
130+
. = ALIGN(4);
131+
PROVIDE_HIDDEN (__init_array_start = .);
132+
KEEP (*(SORT(.init_array.*)))
133+
KEEP (*(.init_array*))
134+
PROVIDE_HIDDEN (__init_array_end = .);
135+
. = ALIGN(4);
136+
} >FLASH
137+
138+
.fini_array :
139+
{
140+
. = ALIGN(4);
141+
PROVIDE_HIDDEN (__fini_array_start = .);
142+
KEEP (*(SORT(.fini_array.*)))
143+
KEEP (*(.fini_array*))
144+
PROVIDE_HIDDEN (__fini_array_end = .);
145+
. = ALIGN(4);
146+
} >FLASH
147+
148+
/* Used by the startup to initialize data */
149+
_sidata = LOADADDR(.data);
150+
151+
/* Initialized data sections into "RAM" Ram type memory */
152+
.data :
153+
{
154+
. = ALIGN(4);
155+
_sdata = .; /* create a global symbol at data start */
156+
*(.data) /* .data sections */
157+
*(.data*) /* .data* sections */
158+
159+
. = ALIGN(4);
160+
_edata = .; /* define a global symbol at data end */
161+
162+
} >RAM AT> FLASH
163+
164+
/* Uninitialized data section into "RAM" Ram type memory */
165+
. = ALIGN(4);
166+
.bss :
167+
{
168+
/* This is used by the startup in order to initialize the .bss secion */
169+
_sbss = .; /* define a global symbol at bss start */
170+
__bss_start__ = _sbss;
171+
*(.bss)
172+
*(.bss*)
173+
*(COMMON)
174+
175+
. = ALIGN(4);
176+
_ebss = .; /* define a global symbol at bss end */
177+
__bss_end__ = _ebss;
178+
} >RAM
179+
180+
/* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
181+
._user_heap_stack :
182+
{
183+
. = ALIGN(8);
184+
PROVIDE ( end = . );
185+
PROVIDE ( _end = . );
186+
. = . + _Min_Heap_Size;
187+
. = . + _Min_Stack_Size;
188+
. = ALIGN(8);
189+
} >RAM
190+
191+
/* Remove information from the compiler libraries */
192+
/DISCARD/ :
193+
{
194+
libc.a ( * )
195+
libm.a ( * )
196+
libgcc.a ( * )
197+
}
198+
199+
.ARM.attributes 0 : { *(.ARM.attributes) }
200+
}

‎variants/CoreBoard_F401RC/variant.cpp

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1+
/*
2+
*******************************************************************************
3+
* Copyright (c) 2017, STMicroelectronics
4+
* All rights reserved.
5+
*
6+
* Redistribution and use in source and binary forms, with or without
7+
* modification, are permitted provided that the following conditions are met:
8+
*
9+
* 1. Redistributions of source code must retain the above copyright notice,
10+
* this list of conditions and the following disclaimer.
11+
* 2. Redistributions in binary form must reproduce the above copyright notice,
12+
* this list of conditions and the following disclaimer in the documentation
13+
* and/or other materials provided with the distribution.
14+
* 3. Neither the name of STMicroelectronics nor the names of its contributors
15+
* may be used to endorse or promote products derived from this software
16+
* without specific prior written permission.
17+
*
18+
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19+
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20+
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
21+
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
22+
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23+
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
24+
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
25+
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
26+
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27+
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28+
*******************************************************************************
29+
*/
30+
31+
#include "pins_arduino.h"
32+
33+
#ifdef __cplusplus
34+
extern "C" {
35+
#endif
36+
37+
const PinName digitalPin[] = {
38+
PA_9, //D0 - USART RX
39+
PA_10, //D1 - USART TX
40+
PC_6, //D2
41+
PC_7, //D3
42+
PC_8, //D4
43+
PC_9, //D5
44+
PC_10, //D6
45+
PC_11, //D7
46+
PC_12, //D8
47+
PC_13, //D9
48+
PA_15, //D10 - SS
49+
PB_5, //D11 - MOSI
50+
PB_4, //D12 - MISO
51+
PB_3, //D13 - SCK
52+
PB_8, //D14 - SDA
53+
PB_9, //D15 - SCL
54+
PB_6, //D16
55+
PB_7, //D17
56+
PB_10, //D18
57+
PB_12, //D19
58+
PB_13, //D20
59+
PB_14, //D21
60+
PB_15, //D22
61+
PA_8, //D23
62+
PA_0, //D24/A0
63+
PA_1, //D25/A1
64+
PA_2, //D26/A2
65+
PA_3, //D27/A3
66+
PA_4, //D28/A4
67+
PA_5, //D29/A5
68+
PA_6, //D30/A6
69+
PA_7, //D31/A7
70+
PB_0, //D32/A8
71+
PB_1, //D33/A9
72+
PC_0, //D34/A10
73+
PC_1, //D35/A11
74+
PC_2, //D36/A12
75+
PC_3, //D37/A13
76+
PC_4, //D38/A14
77+
PC_5, //D39/A15
78+
PB_2, //D40/BOOT1
79+
PD_2, //D41/USB CONNECT
80+
PA_11, //D42/USB DM
81+
PA_12, //D43/USB DP
82+
PA_13, //D44/SWDIO
83+
PA_14 //D45/SWDCLK
84+
};
85+
86+
#ifdef __cplusplus
87+
}
88+
#endif
89+
90+
// ----------------------------------------------------------------------------
91+
92+
#ifdef __cplusplus
93+
extern "C" {
94+
#endif
95+
96+
/**
97+
* @brief System Clock Configuration
98+
* @param None
99+
* @retval None
100+
*/
101+
WEAK void SystemClock_Config(void)
102+
{
103+
RCC_OscInitTypeDef RCC_OscInitStruct;
104+
RCC_ClkInitTypeDef RCC_ClkInitStruct;
105+
106+
/* Configure the main internal regulator output voltage */
107+
__HAL_RCC_PWR_CLK_ENABLE();
108+
109+
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
110+
111+
/* Initializes the CPU, AHB and APB busses clocks */
112+
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
113+
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
114+
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
115+
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
116+
RCC_OscInitStruct.PLL.PLLM = 4;
117+
RCC_OscInitStruct.PLL.PLLN = 168;
118+
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4;
119+
RCC_OscInitStruct.PLL.PLLQ = 7;
120+
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
121+
_Error_Handler(__FILE__, __LINE__);
122+
}
123+
124+
/* Initializes the CPU, AHB and APB busses clocks */
125+
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
126+
| RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
127+
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
128+
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
129+
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
130+
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
131+
132+
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
133+
_Error_Handler(__FILE__, __LINE__);
134+
}
135+
}
136+
137+
#ifdef __cplusplus
138+
}
139+
#endif

‎variants/CoreBoard_F401RC/variant.h

Lines changed: 140 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,140 @@
1+
/*
2+
*******************************************************************************
3+
* Copyright (c) 2017, STMicroelectronics
4+
* All rights reserved.
5+
*
6+
* Redistribution and use in source and binary forms, with or without
7+
* modification, are permitted provided that the following conditions are met:
8+
*
9+
* 1. Redistributions of source code must retain the above copyright notice,
10+
* this list of conditions and the following disclaimer.
11+
* 2. Redistributions in binary form must reproduce the above copyright notice,
12+
* this list of conditions and the following disclaimer in the documentation
13+
* and/or other materials provided with the distribution.
14+
* 3. Neither the name of STMicroelectronics nor the names of its contributors
15+
* may be used to endorse or promote products derived from this software
16+
* without specific prior written permission.
17+
*
18+
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19+
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20+
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
21+
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
22+
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23+
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
24+
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
25+
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
26+
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27+
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28+
*******************************************************************************
29+
*/
30+
31+
#ifndef _VARIANT_ARDUINO_STM32_
32+
#define _VARIANT_ARDUINO_STM32_
33+
34+
#ifdef __cplusplus
35+
extern "C" {
36+
#endif // __cplusplus
37+
38+
/*----------------------------------------------------------------------------
39+
* Pins
40+
*----------------------------------------------------------------------------*/
41+
42+
#define PA9 0 // USART RX
43+
#define PA10 1 // USART TX
44+
#define PC6 2
45+
#define PC7 3
46+
#define PC8 4
47+
#define PC9 5
48+
#define PC10 6
49+
#define PC11 7
50+
#define PC12 8
51+
#define PC13 9
52+
#define PA15 10 // SS
53+
#define PB5 11 // MOSI
54+
#define PB4 12 // MISO
55+
#define PB3 13 // SCK
56+
#define PB8 14 // SDA
57+
#define PB9 15 // SCL
58+
#define PB6 16
59+
#define PB7 17
60+
#define PB10 18
61+
#define PB12 19
62+
#define PB13 20
63+
#define PB14 21
64+
#define PB15 22
65+
#define PA8 23
66+
#define PA0 24 // A0
67+
#define PA1 25 // A1
68+
#define PA2 26 // A2
69+
#define PA3 27 // A3
70+
#define PA4 28 // A4
71+
#define PA5 29 // A5
72+
#define PA6 30 // A6
73+
#define PA7 31 // A7
74+
#define PB0 32 // A8
75+
#define PB1 33 // A9
76+
#define PC0 34 // A10
77+
#define PC1 35 // A11
78+
#define PC2 36 // A12
79+
#define PC3 37 // A13
80+
#define PC4 38 // A14
81+
#define PC5 39 // A15
82+
#define PB2 40 // BOOT1
83+
#define PD2 41 // USB CONNECT
84+
#define PA11 42 // USB DM
85+
#define PA12 43 // USB DP
86+
#define PA13 44 // SWDIO
87+
#define PA14 45 // SWDCLK
88+
89+
// This must be a literal
90+
#define NUM_DIGITAL_PINS 46
91+
// This must be a literal with a value less than or equal to to MAX_ANALOG_INPUTS
92+
#define NUM_ANALOG_INPUTS 16
93+
#define NUM_ANALOG_FIRST 24
94+
95+
// On-board LED pin number
96+
#define LED_BUILTIN PB10
97+
98+
// Timer Definitions
99+
#define TIMER_TONE TIM10
100+
#define TIMER_SERVO TIM11
101+
102+
// UART Definitions
103+
#define SERIAL_UART_INSTANCE 1
104+
105+
// Default pin used for 'Serial' instance (ex: ST-Link)
106+
// Mandatory for Firmata
107+
#define PIN_SERIAL_RX PA10
108+
#define PIN_SERIAL_TX PA9
109+
110+
// USB
111+
#define USB_DISC_PIN PD2
112+
113+
#ifdef __cplusplus
114+
} // extern "C"
115+
#endif
116+
/*----------------------------------------------------------------------------
117+
* Arduino objects - C++ only
118+
*----------------------------------------------------------------------------*/
119+
120+
#ifdef __cplusplus
121+
// These serial port names are intended to allow libraries and architecture-neutral
122+
// sketches to automatically default to the correct port name for a particular type
123+
// of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN,
124+
// the first hardware serial port whose RX/TX pins are not dedicated to another use.
125+
//
126+
// SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor
127+
//
128+
// SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial
129+
//
130+
// SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library
131+
//
132+
// SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins.
133+
//
134+
// SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX
135+
// pins are NOT connected to anything by default.
136+
#define SERIAL_PORT_MONITOR Serial
137+
#define SERIAL_PORT_HARDWARE Serial1
138+
#endif
139+
140+
#endif /* _VARIANT_ARDUINO_STM32_ */

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