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fpistmfpistm
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Merge pull request #2394 from fpistm/STM32CubeF7_update
chore(f7): update to latest STM32CubeF7 v1.17.2
2 parents 483c954 + 111c046 commit 4fa3322

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Diff for: ‎system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f722xx.h

+5-5
Original file line numberDiff line numberDiff line change
@@ -6588,7 +6588,7 @@ typedef struct
65886588
#define FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk /*!<Write burst enable */
65896589
#define FMC_BCR1_CCLKEN_Pos (20U)
65906590
#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
6591-
#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
6591+
#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continuous clock enable */
65926592
#define FMC_BCR1_WFDIS_Pos (21U)
65936593
#define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
65946594
#define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
@@ -7491,7 +7491,7 @@ typedef struct
74917491
#define FMC_SDRTR_COUNT FMC_SDRTR_COUNT_Msk /*!<COUNT[12:0] bits (Refresh timer count) */
74927492
#define FMC_SDRTR_REIE_Pos (14U)
74937493
#define FMC_SDRTR_REIE_Msk (0x1UL << FMC_SDRTR_REIE_Pos) /*!< 0x00004000 */
7494-
#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interupt enable */
7494+
#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interrupt enable */
74957495

74967496
/****************** Bit definition for FMC_SDSR register ******************/
74977497
#define FMC_SDSR_RE_Pos (0U)
@@ -11413,7 +11413,7 @@ typedef struct
1141311413
#define SDMMC_DCOUNT_DATACOUNT_Msk (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
1141411414
#define SDMMC_DCOUNT_DATACOUNT SDMMC_DCOUNT_DATACOUNT_Msk /*!<Data count value */
1141511415

11416-
/****************** Bit definition for SDMMC_STA registe ********************/
11416+
/****************** Bit definition for SDMMC_STA register ********************/
1141711417
#define SDMMC_STA_CCRCFAIL_Pos (0U)
1141811418
#define SDMMC_STA_CCRCFAIL_Msk (0x1UL << SDMMC_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
1141911419
#define SDMMC_STA_CCRCFAIL SDMMC_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
@@ -12750,7 +12750,7 @@ typedef struct
1275012750
#define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
1275112751
#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
1275212752

12753-
/******************* Bit definition for TIM_OR regiter *********************/
12753+
/******************* Bit definition for TIM_OR register *********************/
1275412754
#define TIM_OR_TI4_RMP_Pos (6U)
1275512755
#define TIM_OR_TI4_RMP_Msk (0x3UL << TIM_OR_TI4_RMP_Pos) /*!< 0x000000C0 */
1275612756
#define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
@@ -13007,7 +13007,7 @@ typedef struct
1300713007
/* */
1300813008
/******************************************************************************/
1300913009
/*
13010-
* @brief Specific device feature definitions (not present on all devices in the STM32F7 serie)
13010+
* @brief Specific device feature definitions (not present on all devices in the STM32F7 series)
1301113011
*/
1301213012
/* Support of TCBGT feature : Supported from USART IP version c7amba_sci3 v1.3 */
1301313013
#define USART_TCBGT_SUPPORT

Diff for: ‎system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f723xx.h

+5-5
Original file line numberDiff line numberDiff line change
@@ -6604,7 +6604,7 @@ typedef struct
66046604
#define FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk /*!<Write burst enable */
66056605
#define FMC_BCR1_CCLKEN_Pos (20U)
66066606
#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
6607-
#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
6607+
#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continuous clock enable */
66086608
#define FMC_BCR1_WFDIS_Pos (21U)
66096609
#define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
66106610
#define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
@@ -7507,7 +7507,7 @@ typedef struct
75077507
#define FMC_SDRTR_COUNT FMC_SDRTR_COUNT_Msk /*!<COUNT[12:0] bits (Refresh timer count) */
75087508
#define FMC_SDRTR_REIE_Pos (14U)
75097509
#define FMC_SDRTR_REIE_Msk (0x1UL << FMC_SDRTR_REIE_Pos) /*!< 0x00004000 */
7510-
#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interupt enable */
7510+
#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interrupt enable */
75117511

75127512
/****************** Bit definition for FMC_SDSR register ******************/
75137513
#define FMC_SDSR_RE_Pos (0U)
@@ -11435,7 +11435,7 @@ typedef struct
1143511435
#define SDMMC_DCOUNT_DATACOUNT_Msk (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
1143611436
#define SDMMC_DCOUNT_DATACOUNT SDMMC_DCOUNT_DATACOUNT_Msk /*!<Data count value */
1143711437

11438-
/****************** Bit definition for SDMMC_STA registe ********************/
11438+
/****************** Bit definition for SDMMC_STA register ********************/
1143911439
#define SDMMC_STA_CCRCFAIL_Pos (0U)
1144011440
#define SDMMC_STA_CCRCFAIL_Msk (0x1UL << SDMMC_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
1144111441
#define SDMMC_STA_CCRCFAIL SDMMC_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
@@ -12772,7 +12772,7 @@ typedef struct
1277212772
#define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
1277312773
#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
1277412774

12775-
/******************* Bit definition for TIM_OR regiter *********************/
12775+
/******************* Bit definition for TIM_OR register *********************/
1277612776
#define TIM_OR_TI4_RMP_Pos (6U)
1277712777
#define TIM_OR_TI4_RMP_Msk (0x3UL << TIM_OR_TI4_RMP_Pos) /*!< 0x000000C0 */
1277812778
#define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
@@ -13029,7 +13029,7 @@ typedef struct
1302913029
/* */
1303013030
/******************************************************************************/
1303113031
/*
13032-
* @brief Specific device feature definitions (not present on all devices in the STM32F7 serie)
13032+
* @brief Specific device feature definitions (not present on all devices in the STM32F7 series)
1303313033
*/
1303413034
/* Support of TCBGT feature : Supported from USART IP version c7amba_sci3 v1.3 */
1303513035
#define USART_TCBGT_SUPPORT

Diff for: ‎system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f730xx.h

+5-5
Original file line numberDiff line numberDiff line change
@@ -6818,7 +6818,7 @@ typedef struct
68186818
#define FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk /*!<Write burst enable */
68196819
#define FMC_BCR1_CCLKEN_Pos (20U)
68206820
#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
6821-
#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
6821+
#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continuous clock enable */
68226822
#define FMC_BCR1_WFDIS_Pos (21U)
68236823
#define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
68246824
#define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
@@ -7721,7 +7721,7 @@ typedef struct
77217721
#define FMC_SDRTR_COUNT FMC_SDRTR_COUNT_Msk /*!<COUNT[12:0] bits (Refresh timer count) */
77227722
#define FMC_SDRTR_REIE_Pos (14U)
77237723
#define FMC_SDRTR_REIE_Msk (0x1UL << FMC_SDRTR_REIE_Pos) /*!< 0x00004000 */
7724-
#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interupt enable */
7724+
#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interrupt enable */
77257725

77267726
/****************** Bit definition for FMC_SDSR register ******************/
77277727
#define FMC_SDSR_RE_Pos (0U)
@@ -11658,7 +11658,7 @@ typedef struct
1165811658
#define SDMMC_DCOUNT_DATACOUNT_Msk (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
1165911659
#define SDMMC_DCOUNT_DATACOUNT SDMMC_DCOUNT_DATACOUNT_Msk /*!<Data count value */
1166011660

11661-
/****************** Bit definition for SDMMC_STA registe ********************/
11661+
/****************** Bit definition for SDMMC_STA register ********************/
1166211662
#define SDMMC_STA_CCRCFAIL_Pos (0U)
1166311663
#define SDMMC_STA_CCRCFAIL_Msk (0x1UL << SDMMC_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
1166411664
#define SDMMC_STA_CCRCFAIL SDMMC_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
@@ -12995,7 +12995,7 @@ typedef struct
1299512995
#define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
1299612996
#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
1299712997

12998-
/******************* Bit definition for TIM_OR regiter *********************/
12998+
/******************* Bit definition for TIM_OR register *********************/
1299912999
#define TIM_OR_TI4_RMP_Pos (6U)
1300013000
#define TIM_OR_TI4_RMP_Msk (0x3UL << TIM_OR_TI4_RMP_Pos) /*!< 0x000000C0 */
1300113001
#define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
@@ -13252,7 +13252,7 @@ typedef struct
1325213252
/* */
1325313253
/******************************************************************************/
1325413254
/*
13255-
* @brief Specific device feature definitions (not present on all devices in the STM32F7 serie)
13255+
* @brief Specific device feature definitions (not present on all devices in the STM32F7 series)
1325613256
*/
1325713257
/* Support of TCBGT feature : Supported from USART IP version c7amba_sci3 v1.3 */
1325813258
#define USART_TCBGT_SUPPORT

Diff for: ‎system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f732xx.h

+5-5
Original file line numberDiff line numberDiff line change
@@ -6802,7 +6802,7 @@ typedef struct
68026802
#define FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk /*!<Write burst enable */
68036803
#define FMC_BCR1_CCLKEN_Pos (20U)
68046804
#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
6805-
#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
6805+
#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continuous clock enable */
68066806
#define FMC_BCR1_WFDIS_Pos (21U)
68076807
#define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
68086808
#define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
@@ -7705,7 +7705,7 @@ typedef struct
77057705
#define FMC_SDRTR_COUNT FMC_SDRTR_COUNT_Msk /*!<COUNT[12:0] bits (Refresh timer count) */
77067706
#define FMC_SDRTR_REIE_Pos (14U)
77077707
#define FMC_SDRTR_REIE_Msk (0x1UL << FMC_SDRTR_REIE_Pos) /*!< 0x00004000 */
7708-
#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interupt enable */
7708+
#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interrupt enable */
77097709

77107710
/****************** Bit definition for FMC_SDSR register ******************/
77117711
#define FMC_SDSR_RE_Pos (0U)
@@ -11636,7 +11636,7 @@ typedef struct
1163611636
#define SDMMC_DCOUNT_DATACOUNT_Msk (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
1163711637
#define SDMMC_DCOUNT_DATACOUNT SDMMC_DCOUNT_DATACOUNT_Msk /*!<Data count value */
1163811638

11639-
/****************** Bit definition for SDMMC_STA registe ********************/
11639+
/****************** Bit definition for SDMMC_STA register ********************/
1164011640
#define SDMMC_STA_CCRCFAIL_Pos (0U)
1164111641
#define SDMMC_STA_CCRCFAIL_Msk (0x1UL << SDMMC_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
1164211642
#define SDMMC_STA_CCRCFAIL SDMMC_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
@@ -12973,7 +12973,7 @@ typedef struct
1297312973
#define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
1297412974
#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
1297512975

12976-
/******************* Bit definition for TIM_OR regiter *********************/
12976+
/******************* Bit definition for TIM_OR register *********************/
1297712977
#define TIM_OR_TI4_RMP_Pos (6U)
1297812978
#define TIM_OR_TI4_RMP_Msk (0x3UL << TIM_OR_TI4_RMP_Pos) /*!< 0x000000C0 */
1297912979
#define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
@@ -13230,7 +13230,7 @@ typedef struct
1323013230
/* */
1323113231
/******************************************************************************/
1323213232
/*
13233-
* @brief Specific device feature definitions (not present on all devices in the STM32F7 serie)
13233+
* @brief Specific device feature definitions (not present on all devices in the STM32F7 series)
1323413234
*/
1323513235
/* Support of TCBGT feature : Supported from USART IP version c7amba_sci3 v1.3 */
1323613236
#define USART_TCBGT_SUPPORT

Diff for: ‎system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f733xx.h

+5-5
Original file line numberDiff line numberDiff line change
@@ -6818,7 +6818,7 @@ typedef struct
68186818
#define FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk /*!<Write burst enable */
68196819
#define FMC_BCR1_CCLKEN_Pos (20U)
68206820
#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
6821-
#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
6821+
#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continuous clock enable */
68226822
#define FMC_BCR1_WFDIS_Pos (21U)
68236823
#define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
68246824
#define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
@@ -7721,7 +7721,7 @@ typedef struct
77217721
#define FMC_SDRTR_COUNT FMC_SDRTR_COUNT_Msk /*!<COUNT[12:0] bits (Refresh timer count) */
77227722
#define FMC_SDRTR_REIE_Pos (14U)
77237723
#define FMC_SDRTR_REIE_Msk (0x1UL << FMC_SDRTR_REIE_Pos) /*!< 0x00004000 */
7724-
#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interupt enable */
7724+
#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interrupt enable */
77257725

77267726
/****************** Bit definition for FMC_SDSR register ******************/
77277727
#define FMC_SDSR_RE_Pos (0U)
@@ -11658,7 +11658,7 @@ typedef struct
1165811658
#define SDMMC_DCOUNT_DATACOUNT_Msk (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
1165911659
#define SDMMC_DCOUNT_DATACOUNT SDMMC_DCOUNT_DATACOUNT_Msk /*!<Data count value */
1166011660

11661-
/****************** Bit definition for SDMMC_STA registe ********************/
11661+
/****************** Bit definition for SDMMC_STA register ********************/
1166211662
#define SDMMC_STA_CCRCFAIL_Pos (0U)
1166311663
#define SDMMC_STA_CCRCFAIL_Msk (0x1UL << SDMMC_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
1166411664
#define SDMMC_STA_CCRCFAIL SDMMC_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
@@ -12995,7 +12995,7 @@ typedef struct
1299512995
#define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
1299612996
#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
1299712997

12998-
/******************* Bit definition for TIM_OR regiter *********************/
12998+
/******************* Bit definition for TIM_OR register *********************/
1299912999
#define TIM_OR_TI4_RMP_Pos (6U)
1300013000
#define TIM_OR_TI4_RMP_Msk (0x3UL << TIM_OR_TI4_RMP_Pos) /*!< 0x000000C0 */
1300113001
#define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
@@ -13252,7 +13252,7 @@ typedef struct
1325213252
/* */
1325313253
/******************************************************************************/
1325413254
/*
13255-
* @brief Specific device feature definitions (not present on all devices in the STM32F7 serie)
13255+
* @brief Specific device feature definitions (not present on all devices in the STM32F7 series)
1325613256
*/
1325713257
/* Support of TCBGT feature : Supported from USART IP version c7amba_sci3 v1.3 */
1325813258
#define USART_TCBGT_SUPPORT

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