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Updated STM32L4xx CMSIS to v1.4.1
Included in STM32CubeL4 FW V1.10.0 Signed-off-by: Frederic.Pillon <[email protected]>
1 parent 3f1e7e3 commit 48e6615

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9 files changed

+166
-802
lines changed

9 files changed

+166
-802
lines changed

‎system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4r5xx.h

+27-367
Large diffs are not rendered by default.

‎system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4r7xx.h

+27-16
Original file line numberDiff line numberDiff line change
@@ -13533,9 +13533,6 @@ typedef struct
1353313533
#define RNG_CR_CED_Pos (5U)
1353413534
#define RNG_CR_CED_Msk (0x1U << RNG_CR_CED_Pos) /*!< 0x00000020 */
1353513535
#define RNG_CR_CED RNG_CR_CED_Msk
13536-
#define RNG_CR_BYP_Pos (6U)
13537-
#define RNG_CR_BYP_Msk (0x1U << RNG_CR_BYP_Pos) /*!< 0x00000040 */
13538-
#define RNG_CR_BYP RNG_CR_BYP_Msk
1353913536

1354013537
/******************** Bits definition for RNG_SR register *******************/
1354113538
#define RNG_SR_DRDY_Pos (0U)
@@ -14889,12 +14886,12 @@ typedef struct
1488914886
#define SDMMC_STA_DABORT_Pos (11U)
1489014887
#define SDMMC_STA_DABORT_Msk (0x1U << SDMMC_STA_DABORT_Pos) /*!< 0x00000800 */
1489114888
#define SDMMC_STA_DABORT SDMMC_STA_DABORT_Msk /*!<Data transfer aborted by CMD12 */
14892-
#define SDMMC_STA_CPSMACT_Pos (12U)
14893-
#define SDMMC_STA_CPSMACT_Msk (0x1U << SDMMC_STA_CPSMACT_Pos) /*!< 0x00001000 */
14894-
#define SDMMC_STA_CPSMACT SDMMC_STA_CPSMACT_Msk /*!<Data path state machine active */
14895-
#define SDMMC_STA_DPSMACT_Pos (13U)
14896-
#define SDMMC_STA_DPSMACT_Msk (0x1U << SDMMC_STA_DPSMACT_Pos) /*!< 0x00002000 */
14897-
#define SDMMC_STA_DPSMACT SDMMC_STA_DPSMACT_Msk /*!<Command path state machine active */
14889+
#define SDMMC_STA_DPSMACT_Pos (12U)
14890+
#define SDMMC_STA_DPSMACT_Msk (0x1U << SDMMC_STA_CPSMACT_Pos) /*!< 0x00001000 */
14891+
#define SDMMC_STA_DPSMACT SDMMC_STA_CPSMACT_Msk /*!<Data path state machine active */
14892+
#define SDMMC_STA_CPSMACT_Pos (13U)
14893+
#define SDMMC_STA_CPSMACT_Msk (0x1U << SDMMC_STA_DPSMACT_Pos) /*!< 0x00002000 */
14894+
#define SDMMC_STA_CPSMACT SDMMC_STA_DPSMACT_Msk /*!<Command path state machine active */
1489814895
#define SDMMC_STA_TXFIFOHE_Pos (14U)
1489914896
#define SDMMC_STA_TXFIFOHE_Msk (0x1U << SDMMC_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
1490014897
#define SDMMC_STA_TXFIFOHE SDMMC_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
@@ -15052,13 +15049,27 @@ typedef struct
1505215049
#define SDMMC_MASK_TXFIFOEIE_Pos (18U)
1505315050
#define SDMMC_MASK_TXFIFOEIE_Msk (0x1U << SDMMC_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
1505415051
#define SDMMC_MASK_TXFIFOEIE SDMMC_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */
15055-
#define SDMMC_MASK_BUSYD0ENDIE ((uint32_t)0x00200000) /*!<BUSYD0ENDIE interrupt Enable */
15056-
#define SDMMC_MASK_SDMMCITIE ((uint32_t)0x00400000) /*!<SDMMC Mode Interrupt Received interrupt Enable */
15057-
#define SDMMC_MASK_ACKFAILIE ((uint32_t)0x00800000) /*!<Acknowledgment Fail Interrupt Enable */
15058-
#define SDMMC_MASK_ACKTIMEOUTIE ((uint32_t)0x01000000) /*!<Acknowledgment timeout Interrupt Enable */
15059-
#define SDMMC_MASK_VSWENDIE ((uint32_t)0x02000000) /*!<Voltage switch critical timing section completion Interrupt Enable */
15060-
#define SDMMC_MASK_CKSTOPIE ((uint32_t)0x04000000) /*!<Voltage Switch clock stopped Interrupt Enable */
15061-
#define SDMMC_MASK_IDMABTCIE ((uint32_t)0x10000000) /*!<IDMA buffer transfer complete Interrupt Enable */
15052+
#define SDMMC_MASK_BUSYD0ENDIE_Pos (21U)
15053+
#define SDMMC_MASK_BUSYD0ENDIE_Msk (0x1U << SDMMC_MASK_BUSYD0ENDIE_Pos) /*!< 0x00200000 */
15054+
#define SDMMC_MASK_BUSYD0ENDIE SDMMC_MASK_BUSYD0ENDIE_Msk /*!<BUSYD0END interrupt Enable */
15055+
#define SDMMC_MASK_SDIOITIE_Pos (22U)
15056+
#define SDMMC_MASK_SDIOITIE_Msk (0x1U << SDMMC_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
15057+
#define SDMMC_MASK_SDIOITIE SDMMC_MASK_SDIOITIE_Msk /*!<SDIO Mode Interrupt Received interrupt Enable */
15058+
#define SDMMC_MASK_ACKFAILIE_Pos (23U)
15059+
#define SDMMC_MASK_ACKFAILIE_Msk (0x1U << SDMMC_MASK_ACKFAILIE_Pos) /*!< 0x00800000 */
15060+
#define SDMMC_MASK_ACKFAILIE SDMMC_MASK_ACKFAILIE_Msk /*!<Acknowledgment Fail Interrupt Enable */
15061+
#define SDMMC_MASK_ACKTIMEOUTIE_Pos (24U)
15062+
#define SDMMC_MASK_ACKTIMEOUTIE_Msk (0x1U << SDMMC_MASK_ACKTIMEOUTIE_Pos) /*!< 0x01000000 */
15063+
#define SDMMC_MASK_ACKTIMEOUTIE SDMMC_MASK_ACKTIMEOUTIE_Msk /*!<Acknowledgment timeout Interrupt Enable */
15064+
#define SDMMC_MASK_VSWENDIE_Pos (25U)
15065+
#define SDMMC_MASK_VSWENDIE_Msk (0x1U << SDMMC_MASK_VSWENDIE_Pos) /*!< 0x02000000 */
15066+
#define SDMMC_MASK_VSWENDIE SDMMC_MASK_VSWENDIE_Msk /*!<Voltage switch critical timing section completion Interrupt Enable */
15067+
#define SDMMC_MASK_CKSTOPIE_Pos (26U)
15068+
#define SDMMC_MASK_CKSTOPIE_Msk (0x1U << SDMMC_MASK_CKSTOPIE_Pos) /*!< 0x03000000 */
15069+
#define SDMMC_MASK_CKSTOPIE SDMMC_MASK_CKSTOPIE_Msk /*!<Voltage Switch clock stopped Interrupt Enable */
15070+
#define SDMMC_MASK_IDMABTCIE_Pos (28U)
15071+
#define SDMMC_MASK_IDMABTCIE_Msk (0x1U << SDMMC_MASK_IDMABTCIE_Pos) /*!< 0x10000000 */
15072+
#define SDMMC_MASK_IDMABTCIE SDMMC_MASK_IDMABTCIE_Msk /*!<IDMA buffer transfer complete Interrupt Enable */
1506215073

1506315074
/***************** Bit definition for SDMMC_FIFOCNT register *****************/
1506415075
#define SDMMC_FIFOCNT_FIFOCOUNT_Pos (0U)

‎system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4r9xx.h

+27-16
Original file line numberDiff line numberDiff line change
@@ -16665,9 +16665,6 @@ typedef struct
1666516665
#define RNG_CR_CED_Pos (5U)
1666616666
#define RNG_CR_CED_Msk (0x1U << RNG_CR_CED_Pos) /*!< 0x00000020 */
1666716667
#define RNG_CR_CED RNG_CR_CED_Msk
16668-
#define RNG_CR_BYP_Pos (6U)
16669-
#define RNG_CR_BYP_Msk (0x1U << RNG_CR_BYP_Pos) /*!< 0x00000040 */
16670-
#define RNG_CR_BYP RNG_CR_BYP_Msk
1667116668

1667216669
/******************** Bits definition for RNG_SR register *******************/
1667316670
#define RNG_SR_DRDY_Pos (0U)
@@ -18021,12 +18018,12 @@ typedef struct
1802118018
#define SDMMC_STA_DABORT_Pos (11U)
1802218019
#define SDMMC_STA_DABORT_Msk (0x1U << SDMMC_STA_DABORT_Pos) /*!< 0x00000800 */
1802318020
#define SDMMC_STA_DABORT SDMMC_STA_DABORT_Msk /*!<Data transfer aborted by CMD12 */
18024-
#define SDMMC_STA_CPSMACT_Pos (12U)
18025-
#define SDMMC_STA_CPSMACT_Msk (0x1U << SDMMC_STA_CPSMACT_Pos) /*!< 0x00001000 */
18026-
#define SDMMC_STA_CPSMACT SDMMC_STA_CPSMACT_Msk /*!<Data path state machine active */
18027-
#define SDMMC_STA_DPSMACT_Pos (13U)
18028-
#define SDMMC_STA_DPSMACT_Msk (0x1U << SDMMC_STA_DPSMACT_Pos) /*!< 0x00002000 */
18029-
#define SDMMC_STA_DPSMACT SDMMC_STA_DPSMACT_Msk /*!<Command path state machine active */
18021+
#define SDMMC_STA_DPSMACT_Pos (12U)
18022+
#define SDMMC_STA_DPSMACT_Msk (0x1U << SDMMC_STA_CPSMACT_Pos) /*!< 0x00001000 */
18023+
#define SDMMC_STA_DPSMACT SDMMC_STA_CPSMACT_Msk /*!<Data path state machine active */
18024+
#define SDMMC_STA_CPSMACT_Pos (13U)
18025+
#define SDMMC_STA_CPSMACT_Msk (0x1U << SDMMC_STA_DPSMACT_Pos) /*!< 0x00002000 */
18026+
#define SDMMC_STA_CPSMACT SDMMC_STA_DPSMACT_Msk /*!<Command path state machine active */
1803018027
#define SDMMC_STA_TXFIFOHE_Pos (14U)
1803118028
#define SDMMC_STA_TXFIFOHE_Msk (0x1U << SDMMC_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
1803218029
#define SDMMC_STA_TXFIFOHE SDMMC_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
@@ -18184,13 +18181,27 @@ typedef struct
1818418181
#define SDMMC_MASK_TXFIFOEIE_Pos (18U)
1818518182
#define SDMMC_MASK_TXFIFOEIE_Msk (0x1U << SDMMC_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
1818618183
#define SDMMC_MASK_TXFIFOEIE SDMMC_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */
18187-
#define SDMMC_MASK_BUSYD0ENDIE ((uint32_t)0x00200000) /*!<BUSYD0ENDIE interrupt Enable */
18188-
#define SDMMC_MASK_SDMMCITIE ((uint32_t)0x00400000) /*!<SDMMC Mode Interrupt Received interrupt Enable */
18189-
#define SDMMC_MASK_ACKFAILIE ((uint32_t)0x00800000) /*!<Acknowledgment Fail Interrupt Enable */
18190-
#define SDMMC_MASK_ACKTIMEOUTIE ((uint32_t)0x01000000) /*!<Acknowledgment timeout Interrupt Enable */
18191-
#define SDMMC_MASK_VSWENDIE ((uint32_t)0x02000000) /*!<Voltage switch critical timing section completion Interrupt Enable */
18192-
#define SDMMC_MASK_CKSTOPIE ((uint32_t)0x04000000) /*!<Voltage Switch clock stopped Interrupt Enable */
18193-
#define SDMMC_MASK_IDMABTCIE ((uint32_t)0x10000000) /*!<IDMA buffer transfer complete Interrupt Enable */
18184+
#define SDMMC_MASK_BUSYD0ENDIE_Pos (21U)
18185+
#define SDMMC_MASK_BUSYD0ENDIE_Msk (0x1U << SDMMC_MASK_BUSYD0ENDIE_Pos) /*!< 0x00200000 */
18186+
#define SDMMC_MASK_BUSYD0ENDIE SDMMC_MASK_BUSYD0ENDIE_Msk /*!<BUSYD0END interrupt Enable */
18187+
#define SDMMC_MASK_SDIOITIE_Pos (22U)
18188+
#define SDMMC_MASK_SDIOITIE_Msk (0x1U << SDMMC_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
18189+
#define SDMMC_MASK_SDIOITIE SDMMC_MASK_SDIOITIE_Msk /*!<SDIO Mode Interrupt Received interrupt Enable */
18190+
#define SDMMC_MASK_ACKFAILIE_Pos (23U)
18191+
#define SDMMC_MASK_ACKFAILIE_Msk (0x1U << SDMMC_MASK_ACKFAILIE_Pos) /*!< 0x00800000 */
18192+
#define SDMMC_MASK_ACKFAILIE SDMMC_MASK_ACKFAILIE_Msk /*!<Acknowledgment Fail Interrupt Enable */
18193+
#define SDMMC_MASK_ACKTIMEOUTIE_Pos (24U)
18194+
#define SDMMC_MASK_ACKTIMEOUTIE_Msk (0x1U << SDMMC_MASK_ACKTIMEOUTIE_Pos) /*!< 0x01000000 */
18195+
#define SDMMC_MASK_ACKTIMEOUTIE SDMMC_MASK_ACKTIMEOUTIE_Msk /*!<Acknowledgment timeout Interrupt Enable */
18196+
#define SDMMC_MASK_VSWENDIE_Pos (25U)
18197+
#define SDMMC_MASK_VSWENDIE_Msk (0x1U << SDMMC_MASK_VSWENDIE_Pos) /*!< 0x02000000 */
18198+
#define SDMMC_MASK_VSWENDIE SDMMC_MASK_VSWENDIE_Msk /*!<Voltage switch critical timing section completion Interrupt Enable */
18199+
#define SDMMC_MASK_CKSTOPIE_Pos (26U)
18200+
#define SDMMC_MASK_CKSTOPIE_Msk (0x1U << SDMMC_MASK_CKSTOPIE_Pos) /*!< 0x03000000 */
18201+
#define SDMMC_MASK_CKSTOPIE SDMMC_MASK_CKSTOPIE_Msk /*!<Voltage Switch clock stopped Interrupt Enable */
18202+
#define SDMMC_MASK_IDMABTCIE_Pos (28U)
18203+
#define SDMMC_MASK_IDMABTCIE_Msk (0x1U << SDMMC_MASK_IDMABTCIE_Pos) /*!< 0x10000000 */
18204+
#define SDMMC_MASK_IDMABTCIE SDMMC_MASK_IDMABTCIE_Msk /*!<IDMA buffer transfer complete Interrupt Enable */
1819418205

1819518206
/***************** Bit definition for SDMMC_FIFOCNT register *****************/
1819618207
#define SDMMC_FIFOCNT_FIFOCOUNT_Pos (0U)

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