@@ -1168,7 +1168,7 @@ typedef struct
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/******************************************************************************/
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/*
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- * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie )
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+ * @brief Specific device feature definitions (not present on all devices in the STM32L4 series )
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*/
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/* Note: No specific macro feature on this device */
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@@ -5812,7 +5812,7 @@ typedef struct
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/* */
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/******************************************************************************/
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/*
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- * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie )
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+ * @brief Specific device feature definitions (not present on all devices in the STM32L4 series )
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*/
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#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */
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@@ -9164,7 +9164,7 @@ typedef struct
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/* */
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/******************************************************************************/
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/*
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- * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie )
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+ * @brief Specific device feature definitions (not present on all devices in the STM32L4 series )
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*/
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#define RCC_PLLSAI1_SUPPORT
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#define RCC_PLLP_SUPPORT
@@ -11450,9 +11450,6 @@ typedef struct
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#define SDMMC_STA_DATAEND_Pos (8U)
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#define SDMMC_STA_DATAEND_Msk (0x1UL << SDMMC_STA_DATAEND_Pos) /*!< 0x00000100 */
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#define SDMMC_STA_DATAEND SDMMC_STA_DATAEND_Msk /*!<Data end (data counter, SDIDCOUNT, is zero) */
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- #define SDMMC_STA_STBITERR_Pos (9U)
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- #define SDMMC_STA_STBITERR_Msk (0x1UL << SDMMC_STA_STBITERR_Pos) /*!< 0x00000200 */
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- #define SDMMC_STA_STBITERR SDMMC_STA_STBITERR_Msk /*!<Start bit not detected on all data signals in wide bus mode */
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#define SDMMC_STA_DBCKEND_Pos (10U)
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#define SDMMC_STA_DBCKEND_Msk (0x1UL << SDMMC_STA_DBCKEND_Pos) /*!< 0x00000400 */
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#define SDMMC_STA_DBCKEND SDMMC_STA_DBCKEND_Msk /*!<Data block sent/received (CRC check passed) */
@@ -11493,6 +11490,11 @@ typedef struct
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#define SDMMC_STA_SDIOIT_Msk (0x1UL << SDMMC_STA_SDIOIT_Pos) /*!< 0x00400000 */
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#define SDMMC_STA_SDIOIT SDMMC_STA_SDIOIT_Msk /*!<SDIO interrupt received */
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+ /* Legacy Defines */
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+ #define SDMMC_STA_STBITERR_Pos (9U)
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+ #define SDMMC_STA_STBITERR_Msk (0x1UL << SDMMC_STA_STBITERR_Pos) /*!< 0x00000200 */
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+ #define SDMMC_STA_STBITERR SDMMC_STA_STBITERR_Msk /*!<Start bit not detected on all data signals in wide bus mode */
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+
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/******************* Bit definition for SDMMC_ICR register *******************/
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#define SDMMC_ICR_CCRCFAILC_Pos (0U)
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#define SDMMC_ICR_CCRCFAILC_Msk (0x1UL << SDMMC_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
@@ -13964,7 +13966,7 @@ typedef struct
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/******************************************************************************/
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/*
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- * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie )
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+ * @brief Specific device feature definitions (not present on all devices in the STM32L4 series )
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*/
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#define USART_TCBGT_SUPPORT
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