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Initial support for Nucleo-F439ZI
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‎README.md

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@@ -97,6 +97,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d
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| :green_heart: | STM32F412ZG | [Nucleo F412ZG](http://www.st.com/en/evaluation-tools/nucleo-f412zg.html) | *2.6.0* | |
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| :green_heart: | STM32F413ZH | [Nucleo F413ZH](http://www.st.com/en/evaluation-tools/nucleo-f413zh.html) | *2.4.0* | |
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| :green_heart: | STM32F429ZI | [Nucleo F429ZI](http://www.st.com/en/evaluation-tools/nucleo-f429zi.html) | *0.1.0* | |
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| :yellow_heart: | STM32F439ZI | [Nucleo F439ZI](http://www.st.com/en/evaluation-tools/nucleo-f439zi.html) | *2.9.0* | |
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| :green_heart: | STM32F446ZE | [Nucleo F446ZE](http://www.st.com/en/evaluation-tools/nucleo-f446ze.html) | *2.7.0* | |
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| :green_heart: | STM32F722ZE | [Nucleo F722ZE](http://www.st.com/en/evaluation-tools/nucleo-f722ze.html) | *2.4.0* | |
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| :green_heart: | STM32F767ZI | [Nucleo F767ZI](http://www.st.com/en/evaluation-tools/nucleo-f767zi.html) | *1.4.0* | |

‎variants/STM32F4xx/F427Z(G-I)T_F429ZET_F429Z(G-I)(T-Y)_F437Z(G-I)T_F439Z(G-I)(T-Y)/ldscript.ld

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******************************************************************************
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* @file LinkerScript.ld
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* @author Auto-generated by STM32CubeIDE
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* @brief Linker script for STM32F429ZITx Device from STM32F4 series
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* @brief Linker script for STM32F429ZITx/STM32F439ZITx Device from STM32F4 series
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* 2048Kbytes FLASH
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* 64Kbytes CCMRAM
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* 192Kbytes RAM

‎variants/STM32F4xx/F427Z(G-I)T_F429ZET_F429Z(G-I)(T-Y)_F437Z(G-I)T_F439Z(G-I)(T-Y)/variant_NUCLEO_F439ZI.cpp

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/*
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*******************************************************************************
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* Copyright (c) 2011-2021, STMicroelectronics
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* All rights reserved.
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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*******************************************************************************
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*/
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#if defined(ARDUINO_NUCLEO_F439ZI)
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#include "pins_arduino.h"
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// Pin number
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// Match Table 17. NUCLEO-F439ZI pin assignments
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// from UM1974 STM32 Nucleo-144 board
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const PinName digitalPin[] = {
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PG_9, //D0
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PG_14, //D1
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PF_15, //D2
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PE_13, //D3
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PF_14, //D4
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PE_11, //D5
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PE_9, //D6
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PF_13, //D7
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PF_12, //D8
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PD_15, //D9
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PD_14, //D10
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PA_7, //D11/A10
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PA_6, //D12/A11
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PA_5, //D13/A12
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PB_9, //D14
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PB_8, //D15
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PC_6, //D16
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PB_15, //D17
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PB_13, //D18
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PB_12, //D19
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PA_15, //D20
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PC_7, //D21
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PB_5, //D22
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PB_3, //D23
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PA_4, //D24/A13
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PB_4, //D25
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PB_6, //D26
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PB_2, //D27
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PD_13, //D28
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PD_12, //D29
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PD_11, //D30
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PE_2, //D31
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PA_0, //D32/A14
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PB_0, //D33/A18 - LED_GREEN
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PE_0, //D34
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PB_11, //D35
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PB_10, //D36
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PE_15, //D37
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PE_14, //D38
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PE_12, //D39
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PE_10, //D40
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PE_7, //D41
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PE_8, //D42
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PC_8, //D43
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PC_9, //D44
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PC_10, //D45
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PC_11, //D46
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PC_12, //D47
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PD_2, //D48
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PG_2, //D49
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PG_3, //D50
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PD_7, //D51
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PD_6, //D52
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PD_5, //D53
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PD_4, //D54
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PD_3, //D55
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PE_2, //D56
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PE_4, //D57
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PE_5, //D58
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PE_6, //D59
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PE_3, //D60
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PF_8, //D61/A15
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PF_7, //D62/A16
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PF_9, //D63/A17
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PG_1, //D64
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PG_0, //D65
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PD_1, //D66
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PD_0, //D67
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PF_0, //D68
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PF_1, //D69
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PF_2, //D70
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PA_7, //D71
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NC, //D72
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PB_7, //D73 - LED_BLUE
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PB_14, //D74 - LED_RED
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PC_13, //D75 - USER_BTN
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PD_9, //D76 - Serial Rx
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PD_8, //D77 - Serial Tx
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PA_3, //D78/A0
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PC_0, //D79/A1
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PC_3, //D80/A2
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PF_3, //D81/A3
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PF_5, //D82/A4
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PF_10, //D83/A5
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PB_1, //D84/A6
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PC_2, //D85/A7
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PF_4, //D86/A8
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PF_6, //D87/A9
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PA_1, //D88/A19
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PA_2, //D89/A20
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PA_8, //D90
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PA_9, //D91
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PA_10, //D92
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PA_11, //D93
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PA_12, //D94
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PA_13, //D95
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PA_14, //D96
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PC_1, //D97/A21
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PC_4, //D98/A22
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PC_5, //D99/A23
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PC_14, //D100
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PC_15, //D101
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PD_10, //D102
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PE_1, //D103
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PF_11, //D104
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PG_4, //D105
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PG_5, //D106
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PG_6, //D107
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PG_7, //D108
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PG_8, //D109
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PG_10, //D110
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PG_11, //D111
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PG_12, //D112
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PG_13, //D113
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PG_15, //D114
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PH_0, //D115
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PH_1 //D116
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};
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// Analog (Ax) pin number array
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const uint32_t analogInputPin[] = {
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78, //A0
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79, //A1
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80, //A2
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81, //A3
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82, //A4
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83, //A5
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84, //A6
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85, //A7
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86, //A8
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87, //A9
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11, //A10
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12, //A11
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13, //A12
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24, //A13
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32, //A14
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61, //A15
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62, //A16
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63, //A17
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33, //A18
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88, //A19
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89, //A20
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97, //A21
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98, //A22
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99 //A23
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};
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// ----------------------------------------------------------------------------
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief System Clock Configuration
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* The system Clock is configured as follow :
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* System Clock source = PLL (HSE)
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* SYSCLK(Hz) = 168000000
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* HCLK(Hz) = 168000000
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* AHB Prescaler = 1
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* APB1 Prescaler = 4
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* APB2 Prescaler = 2
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* HSE Frequency(Hz) = 8000000
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* PLL_M = 8
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* PLL_N = 336
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* PLL_P = 2
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* PLL_Q = 7
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* VDD(V) = 3.3
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* Main regulator output voltage = Scale1 mode
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* Flash Latency(WS) = 5
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* @param None
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* @retval None
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*/
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WEAK void SystemClock_Config(void)
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{
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RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
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RCC_OscInitTypeDef RCC_OscInitStruct = {};
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/* Enable Power Control clock */
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__HAL_RCC_PWR_CLK_ENABLE();
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/* The voltage scaling allows optimizing the power consumption when the device is
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clocked below the maximum system frequency, to update the voltage scaling value
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regarding system frequency refer to product datasheet. */
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__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
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/* Enable HSE Oscillator and activate PLL with HSE as source */
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
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RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
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RCC_OscInitStruct.PLL.PLLM = 8;
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RCC_OscInitStruct.PLL.PLLN = 336;
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RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
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RCC_OscInitStruct.PLL.PLLQ = 7;
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HAL_RCC_OscConfig(&RCC_OscInitStruct);
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HAL_PWREx_EnableOverDrive();
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/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2
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clocks dividers */
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RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK |
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RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
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RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
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RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
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HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5);
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/* Ensure CCM RAM clock is enabled */
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__HAL_RCC_CCMDATARAMEN_CLK_ENABLE();
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}
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#ifdef __cplusplus
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}
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#endif
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#endif /* ARDUINO_NUCLEO_F439ZI */

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