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system(C0): update STM32C0xx CMSIS Drivers to v1.3.0
Included in STM32CubeC0 FW v1.3.0 Signed-off-by: Frederic Pillon <[email protected]>
1 parent 25a4757 commit 2d39155

12 files changed

+23158
-22
lines changed

Diff for: ‎system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c011xx.h

+5-6
Original file line numberDiff line numberDiff line change
@@ -570,6 +570,11 @@ typedef struct
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#define UID_BASE (0x1FFF7550UL) /*!< Unique device ID register base address */
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#define FLASHSIZE_BASE (0x1FFF75A0UL) /*!< Flash size data register base address */
572572

573+
/*!< Bootloader Firmware */
574+
575+
/************ Bootloader Exit Secure Memory Firmware *************/
576+
#define BL_EXIT_SEC_MEM_BASE (0x1FFF1600UL)
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573578
/**
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* @}
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*/
@@ -3797,12 +3802,6 @@ typedef struct
37973802
/******************************************************************************/
37983803

37993804
/******************** Bit definition for RCC_CR register *****************/
3800-
#define RCC_CR_SYSDIV_Pos (2U)
3801-
#define RCC_CR_SYSDIV_Msk (0x7UL << RCC_CR_SYSDIV_Pos) /*!< 0x0000001C */
3802-
#define RCC_CR_SYSDIV RCC_CR_SYSDIV_Msk /*!< Clock division factor for system clock */
3803-
#define RCC_CR_SYSDIV_0 (0x1UL << RCC_CR_SYSDIV_Pos) /*!< 0x00000004 */
3804-
#define RCC_CR_SYSDIV_1 (0x2UL << RCC_CR_SYSDIV_Pos) /*!< 0x00000008 */
3805-
#define RCC_CR_SYSDIV_2 (0x4UL << RCC_CR_SYSDIV_Pos) /*!< 0x00000010 */
38063805
#define RCC_CR_HSIKERDIV_Pos (5U)
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#define RCC_CR_HSIKERDIV_Msk (0x7UL << RCC_CR_HSIKERDIV_Pos) /*!< 0x000000E0 */
38083807
#define RCC_CR_HSIKERDIV RCC_CR_HSIKERDIV_Msk /*!< HSI48 clock division factor for HSI kernel clocks inputs */

Diff for: ‎system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c031xx.h

+5-6
Original file line numberDiff line numberDiff line change
@@ -573,6 +573,11 @@ typedef struct
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#define UID_BASE (0x1FFF7550UL) /*!< Unique device ID register base address */
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#define FLASHSIZE_BASE (0x1FFF75A0UL) /*!< Flash size data register base address */
575575

576+
/*!< Bootloader Firmware */
577+
578+
/************ Bootloader Exit Secure Memory Firmware *************/
579+
#define BL_EXIT_SEC_MEM_BASE (0x1FFF1600UL)
580+
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/**
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* @}
578583
*/
@@ -3951,12 +3956,6 @@ typedef struct
39513956
/******************************************************************************/
39523957

39533958
/******************** Bit definition for RCC_CR register *****************/
3954-
#define RCC_CR_SYSDIV_Pos (2U)
3955-
#define RCC_CR_SYSDIV_Msk (0x7UL << RCC_CR_SYSDIV_Pos) /*!< 0x0000001C */
3956-
#define RCC_CR_SYSDIV RCC_CR_SYSDIV_Msk /*!< Clock division factor for system clock */
3957-
#define RCC_CR_SYSDIV_0 (0x1UL << RCC_CR_SYSDIV_Pos) /*!< 0x00000004 */
3958-
#define RCC_CR_SYSDIV_1 (0x2UL << RCC_CR_SYSDIV_Pos) /*!< 0x00000008 */
3959-
#define RCC_CR_SYSDIV_2 (0x4UL << RCC_CR_SYSDIV_Pos) /*!< 0x00000010 */
39603959
#define RCC_CR_HSIKERDIV_Pos (5U)
39613960
#define RCC_CR_HSIKERDIV_Msk (0x7UL << RCC_CR_HSIKERDIV_Pos) /*!< 0x000000E0 */
39623961
#define RCC_CR_HSIKERDIV RCC_CR_HSIKERDIV_Msk /*!< HSI48 clock division factor for HSI kernel clocks inputs */

Diff for: ‎system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c051xx.h

+7,036
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Diff for: ‎system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c071xx.h

+5
Original file line numberDiff line numberDiff line change
@@ -640,6 +640,11 @@ typedef struct
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#define UID_BASE (0x1FFF7550UL) /*!< Unique device ID register base address */
641641
#define FLASHSIZE_BASE (0x1FFF75A0UL) /*!< Flash size data register base address */
642642

643+
/*!< Bootloader Firmware */
644+
645+
/************ Bootloader Exit Secure Memory Firmware *************/
646+
#define BL_EXIT_SEC_MEM_BASE (0x1FFF6000UL)
647+
643648
/**
644649
* @}
645650
*/

Diff for: ‎system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c091xx.h

+7,276
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Diff for: ‎system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c092xx.h

+7,950
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Diff for: ‎system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c0xx.h

+13-2
Original file line numberDiff line numberDiff line change
@@ -56,10 +56,15 @@
5656
application
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*/
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59-
#if !defined (STM32C011xx) && !defined (STM32C031xx) && !defined (STM32C071xx)
59+
#if !defined (STM32C011xx) && !defined (STM32C031xx) \
60+
&& !defined (STM32C051xx) && !defined (STM32C071xx) \
61+
&& !defined (STM32C091xx) && !defined (STM32C092xx)
6062
/* #define STM32C011xx */ /*!< STM32C011xx Devices */
6163
/* #define STM32C031xx */ /*!< STM32C031xx Devices */
64+
/* #define STM32C051xx */ /*!< STM32C051xx Devices */
6265
/* #define STM32C071xx */ /*!< STM32C071xx Devices */
66+
/* #define STM32C091xx */ /*!< STM32C091xx Devices */
67+
/* #define STM32C092xx */ /*!< STM32C092xx Devices */
6368
#endif
6469

6570
/* Tip: To avoid modifying this file each time you need to switch between these
@@ -78,7 +83,7 @@
7883
* @brief CMSIS Device version number V1.0.0
7984
*/
8085
#define __STM32C0_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */
81-
#define __STM32C0_CMSIS_VERSION_SUB1 (0x02U) /*!< [23:16] sub1 version */
86+
#define __STM32C0_CMSIS_VERSION_SUB1 (0x03U) /*!< [23:16] sub1 version */
8287
#define __STM32C0_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
8388
#define __STM32C0_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
8489
#define __STM32C0_CMSIS_VERSION ((__STM32C0_CMSIS_VERSION_MAIN << 24)\
@@ -98,8 +103,14 @@
98103
#include "stm32c011xx.h"
99104
#elif defined(STM32C031xx)
100105
#include "stm32c031xx.h"
106+
#elif defined(STM32C051xx)
107+
#include "stm32c051xx.h"
101108
#elif defined(STM32C071xx)
102109
#include "stm32c071xx.h"
110+
#elif defined(STM32C091xx)
111+
#include "stm32c091xx.h"
112+
#elif defined(STM32C092xx)
113+
#include "stm32c092xx.h"
103114
#else
104115
#error "Please select first the target STM32C0xx device used in your application (in stm32c0xx.h file)"
105116
#endif

Diff for: ‎system/Drivers/CMSIS/Device/ST/STM32C0xx/Release_Notes.html

+48-7
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@@ -43,19 +43,60 @@ <h1 id="release-notes-for-stm32c0xx-cmsis">Release Notes for
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<section id="update-history" class="col-sm-12 col-lg-8">
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<h1><strong>Update History</strong></h1>
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<div class="collapse">
46-
<input type="checkbox" id="collapse-section3" checked aria-hidden="true">
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<label for="collapse-section3" checked aria-hidden="true"><strong>V1.2.0
48-
/ 05-June-2024</strong></label>
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<input type="checkbox" id="collapse-section4" checked aria-hidden="true">
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<label for="collapse-section4" checked aria-hidden="true"><strong>V1.3.0
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/ 30-October-2024</strong></label>
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<div>
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<h2 id="main-changes">Main Changes</h2>
5151
<ul>
52+
<li>Official release of STM32C0xx CMSIS drivers to support
53+
<strong>STM32C051xx</strong> and <strong>STM32C091/92xx</strong>
54+
devices</li>
55+
<li>General updates to fix known defects and enhance implementation</li>
56+
<li>Align version of bit and registers definition with the STM32C0
57+
reference manual</li>
58+
</ul>
59+
<h2 id="contents">Contents</h2>
60+
<ul>
61+
<li><strong>Support of STM32C051xx and STM32C091/92xx devices</strong>:
62+
<ul>
63+
<li>Add “stm32c051xx.h” , “stm32c091xx.h”, and “stm32c092xx.h”
64+
files</li>
65+
<li>Add startup files “startup_stm32c051xx.s”, “startup_stm32c091xx.s”
66+
and “startup_stm32c092xx.s” for EWARM, STM32CubeIDE and MDK-ARM
67+
toolchains</li>
68+
<li>Add STM32C051xx and STM32C091/92xx devices linker files for EWARM
69+
and STM32CubeIDE toolchains</li>
70+
</ul></li>
71+
<li><strong>Registers and bit field definitions updates</strong> :
72+
<ul>
73+
<li>Add BL_EXIT_SEC_MEM_BASE Bootloader Exit Secure Memory Firmware
74+
addresses</li>
75+
<li>Remove RCC_CR_SYSDIV bit definition from C031xx and C011xx CMSIS
76+
files as undefined</li>
77+
</ul></li>
78+
</ul>
79+
<h2 id="supported-devices">Supported Devices</h2>
80+
<ul>
81+
<li>STM32C011xx, STM32C031xx, <strong>STM32C051xx</strong>, STM32C071xx
82+
and <strong>STM32C091/92xx</strong> devices</li>
83+
</ul>
84+
</div>
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</div>
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<div class="collapse">
87+
<input type="checkbox" id="collapse-section3" aria-hidden="true">
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<label for="collapse-section3" aria-hidden="true"><strong>V1.2.0 /
89+
05-June-2024</strong></label>
90+
<div>
91+
<h2 id="main-changes-1">Main Changes</h2>
92+
<ul>
5293
<li>First official release of STM32C0xx CMSIS drivers to support
5394
<strong>STM32C071xx</strong> devices</li>
5495
<li>General updates to fix known defects and enhance implementation</li>
5596
<li>Align version of bit and registers definition with the STM32C0
5697
reference manual</li>
5798
</ul>
58-
<h2 id="contents">Contents</h2>
99+
<h2 id="contents-1">Contents</h2>
59100
<ul>
60101
<li><strong>Support of STM32C071xx devices</strong>:
61102
<ul>
@@ -102,7 +143,7 @@ <h2 id="contents">Contents</h2>
102143
</ul></li>
103144
</ul></li>
104145
</ul>
105-
<h2 id="supported-devices">Supported Devices</h2>
146+
<h2 id="supported-devices-1">Supported Devices</h2>
106147
<ul>
107148
<li>STM32C011xx, STM32C031xx and STM32C071xx devices</li>
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</ul>
@@ -112,14 +153,14 @@ <h2 id="supported-devices">Supported Devices</h2>
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<input type="checkbox" id="collapse-section2" aria-hidden="true">
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<label for="collapse-section2" aria-hidden="true"><strong>V1.1.0 /
114155
07-June-2023</strong></label>
115-
<h2 id="main-changes-1">Main Changes</h2>
156+
<h2 id="main-changes-2">Main Changes</h2>
116157
<p>Align flash register address with STM32C0 reference manual</p>
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</div>
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<div class="collapse">
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<input type="checkbox" id="collapse-section1" aria-hidden="true">
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<label for="collapse-section1" aria-hidden="true"><strong>V1.0.0 /
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09-February-2022</strong></label>
122-
<h2 id="main-changes-2">Main Changes</h2>
163+
<h2 id="main-changes-3">Main Changes</h2>
123164
<p>First official release version of bits and registers definition
124165
aligned with STM32C0 reference manual</p>
125166
</div>

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