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ABOSTMfpistm
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system(U5): HAL RCC should restore PWR clock after clock configuration
Internal ticket 112307 Signed-off-by: Alexandre Bourdiol <[email protected]>
1 parent 497ea5a commit 29d4caa

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+24
-6
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+24
-6
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system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rcc.c

+24-6
Original file line numberDiff line numberDiff line change
@@ -1154,6 +1154,8 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *pRCC_OscInitStruct)
11541154

11551155
if ((pRCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
11561156
{
1157+
FlagStatus pwrclkchanged = RESET;
1158+
11571159
/* Check if the PLL is used as system clock or not */
11581160
if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
11591161
{
@@ -1182,8 +1184,12 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *pRCC_OscInitStruct)
11821184
}
11831185
}
11841186

1185-
/* Enable PWR CLK */
1186-
__HAL_RCC_PWR_CLK_ENABLE();
1187+
/* Requires to enable write access to Backup Domain of necessary */
1188+
if (__HAL_RCC_PWR_IS_CLK_DISABLED())
1189+
{
1190+
__HAL_RCC_PWR_CLK_ENABLE();
1191+
pwrclkchanged = SET;
1192+
}
11871193

11881194
/*Disable EPOD to configure PLL1MBOOST*/
11891195
if (READ_BIT(PWR->VOSR, PWR_VOSR_BOOSTEN) == PWR_VOSR_BOOSTEN)
@@ -1223,8 +1229,11 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *pRCC_OscInitStruct)
12231229
SET_BIT(PWR->VOSR, PWR_VOSR_BOOSTEN);
12241230
}
12251231

1226-
/*Disable PWR clk */
1227-
__HAL_RCC_PWR_CLK_DISABLE();
1232+
/* Restore clock configuration if changed */
1233+
if (pwrclkchanged == SET)
1234+
{
1235+
__HAL_RCC_PWR_CLK_DISABLE();
1236+
}
12281237

12291238
/* Enable PLL System Clock output */
12301239
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVR);
@@ -1343,11 +1352,16 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *const pRCC_Clk
13431352
if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
13441353
{
13451354
assert_param(IS_RCC_SYSCLKSOURCE(pRCC_ClkInitStruct->SYSCLKSource));
1355+
FlagStatus pwrclkchanged = RESET;
13461356

13471357
/* PLL is selected as System Clock Source */
13481358
if (pRCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
13491359
{
1350-
__HAL_RCC_PWR_CLK_ENABLE();
1360+
if (__HAL_RCC_PWR_IS_CLK_DISABLED())
1361+
{
1362+
__HAL_RCC_PWR_CLK_ENABLE();
1363+
pwrclkchanged = SET;
1364+
}
13511365
tickstart = HAL_GetTick();
13521366
/* Check if EPOD is enabled */
13531367
if (READ_BIT(PWR->VOSR, PWR_VOSR_BOOSTEN) != 0U)
@@ -1362,7 +1376,11 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *const pRCC_Clk
13621376
}
13631377
}
13641378

1365-
__HAL_RCC_PWR_CLK_DISABLE();
1379+
/* Restore clock configuration if changed */
1380+
if (pwrclkchanged == SET)
1381+
{
1382+
__HAL_RCC_PWR_CLK_DISABLE();
1383+
}
13661384

13671385
/* Check the PLL ready flag */
13681386
if (READ_BIT(RCC->CR, RCC_CR_PLL1RDY) == 0U)

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