@@ -1154,6 +1154,8 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *pRCC_OscInitStruct)
1154
1154
1155
1155
if ((pRCC_OscInitStruct -> PLL .PLLState ) != RCC_PLL_NONE )
1156
1156
{
1157
+ FlagStatus pwrclkchanged = RESET ;
1158
+
1157
1159
/* Check if the PLL is used as system clock or not */
1158
1160
if (__HAL_RCC_GET_SYSCLK_SOURCE () != RCC_SYSCLKSOURCE_STATUS_PLLCLK )
1159
1161
{
@@ -1182,8 +1184,12 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *pRCC_OscInitStruct)
1182
1184
}
1183
1185
}
1184
1186
1185
- /* Enable PWR CLK */
1186
- __HAL_RCC_PWR_CLK_ENABLE ();
1187
+ /* Requires to enable write access to Backup Domain of necessary */
1188
+ if (__HAL_RCC_PWR_IS_CLK_DISABLED ())
1189
+ {
1190
+ __HAL_RCC_PWR_CLK_ENABLE ();
1191
+ pwrclkchanged = SET ;
1192
+ }
1187
1193
1188
1194
/*Disable EPOD to configure PLL1MBOOST*/
1189
1195
if (READ_BIT (PWR -> VOSR , PWR_VOSR_BOOSTEN ) == PWR_VOSR_BOOSTEN )
@@ -1223,8 +1229,11 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *pRCC_OscInitStruct)
1223
1229
SET_BIT (PWR -> VOSR , PWR_VOSR_BOOSTEN );
1224
1230
}
1225
1231
1226
- /*Disable PWR clk */
1227
- __HAL_RCC_PWR_CLK_DISABLE ();
1232
+ /* Restore clock configuration if changed */
1233
+ if (pwrclkchanged == SET )
1234
+ {
1235
+ __HAL_RCC_PWR_CLK_DISABLE ();
1236
+ }
1228
1237
1229
1238
/* Enable PLL System Clock output */
1230
1239
__HAL_RCC_PLLCLKOUT_ENABLE (RCC_PLL1_DIVR );
@@ -1343,11 +1352,16 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *const pRCC_Clk
1343
1352
if (((pRCC_ClkInitStruct -> ClockType ) & RCC_CLOCKTYPE_SYSCLK ) == RCC_CLOCKTYPE_SYSCLK )
1344
1353
{
1345
1354
assert_param (IS_RCC_SYSCLKSOURCE (pRCC_ClkInitStruct -> SYSCLKSource ));
1355
+ FlagStatus pwrclkchanged = RESET ;
1346
1356
1347
1357
/* PLL is selected as System Clock Source */
1348
1358
if (pRCC_ClkInitStruct -> SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK )
1349
1359
{
1350
- __HAL_RCC_PWR_CLK_ENABLE ();
1360
+ if (__HAL_RCC_PWR_IS_CLK_DISABLED ())
1361
+ {
1362
+ __HAL_RCC_PWR_CLK_ENABLE ();
1363
+ pwrclkchanged = SET ;
1364
+ }
1351
1365
tickstart = HAL_GetTick ();
1352
1366
/* Check if EPOD is enabled */
1353
1367
if (READ_BIT (PWR -> VOSR , PWR_VOSR_BOOSTEN ) != 0U )
@@ -1362,7 +1376,11 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *const pRCC_Clk
1362
1376
}
1363
1377
}
1364
1378
1365
- __HAL_RCC_PWR_CLK_DISABLE ();
1379
+ /* Restore clock configuration if changed */
1380
+ if (pwrclkchanged == SET )
1381
+ {
1382
+ __HAL_RCC_PWR_CLK_DISABLE ();
1383
+ }
1366
1384
1367
1385
/* Check the PLL ready flag */
1368
1386
if (READ_BIT (RCC -> CR , RCC_CR_PLL1RDY ) == 0U )
0 commit comments