@@ -214,6 +214,11 @@ extern "C" {
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#endif
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#endif
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+
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+ #if defined(STM32U5 )
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+ #define __HAL_COMP_COMP1_EXTI_CLEAR_RASING_FLAG __HAL_COMP_COMP1_EXTI_CLEAR_RISING_FLAG
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+ #endif
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+
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/**
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* @}
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*/
@@ -268,7 +273,7 @@ extern "C" {
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#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
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#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
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- #if defined(STM32G4 ) || defined(STM32H7 ) || defined (STM32U5 )
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+ #if defined(STM32G4 ) || defined(STM32L5 ) || defined( STM32H7 ) || defined (STM32U5 )
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#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL
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#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL
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#endif
@@ -530,6 +535,9 @@ extern "C" {
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#define OB_USER_nBOOT0 OB_USER_NBOOT0
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#define OB_nBOOT0_RESET OB_NBOOT0_RESET
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#define OB_nBOOT0_SET OB_NBOOT0_SET
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+ #define OB_USER_SRAM134_RST OB_USER_SRAM_RST
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+ #define OB_SRAM134_RST_ERASE OB_SRAM_RST_ERASE
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+ #define OB_SRAM134_RST_NOT_ERASE OB_SRAM_RST_NOT_ERASE
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#endif /* STM32U5 */
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/**
@@ -672,8 +680,6 @@ extern "C" {
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#if defined(STM32U5 )
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#define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ
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- #endif /* STM32U5 */
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- #if defined(STM32U5 )
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#define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP
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#define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1
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#endif /* STM32U5 */
@@ -686,7 +692,9 @@ extern "C" {
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*/
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#if defined(STM32U5 )
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#define GTZC_PERIPH_DCMI GTZC_PERIPH_DCMI_PSSI
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+ #define GTZC_PERIPH_LTDC GTZC_PERIPH_LTDCUSB
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#endif /* STM32U5 */
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+
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/**
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* @}
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*/
@@ -1005,7 +1013,7 @@ extern "C" {
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#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
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#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
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- #if defined(STM32L1 ) || defined(STM32L4 ) || defined(STM32L5 ) || defined(STM32H7 ) || defined(STM32G4 )
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+ #if defined(STM32L1 ) || defined(STM32L4 ) || defined(STM32L5 ) || defined(STM32H7 ) || defined(STM32G4 ) || defined( STM32U5 )
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#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID
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#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID
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#endif
@@ -2959,6 +2967,11 @@ extern "C" {
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#define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED
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#define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED
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+ #define RCC_SPI4CLKSOURCE_D2PCLK1 RCC_SPI4CLKSOURCE_D2PCLK2
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+ #define RCC_SPI5CLKSOURCE_D2PCLK1 RCC_SPI5CLKSOURCE_D2PCLK2
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+ #define RCC_SPI45CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_D2PCLK2
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+ #define RCC_SPI45CLKSOURCE_CDPCLK1 RCC_SPI45CLKSOURCE_CDPCLK2
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+ #define RCC_SPI45CLKSOURCE_PCLK1 RCC_SPI45CLKSOURCE_PCLK2
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#endif
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#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
@@ -3586,7 +3599,7 @@ extern "C" {
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*/
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#if defined (STM32G0 ) || defined (STM32L5 ) || defined (STM32L412xx ) || defined (STM32L422xx ) || defined (STM32L4P5xx )|| \
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defined (STM32L4Q5xx ) || defined (STM32G4 ) || defined (STM32WL ) || defined (STM32U5 ) || \
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- defined (STM32WB_GEN2 ) || defined ( STM32WBA ) || defined ( STM32C0 )
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+ defined (STM32C0 )
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#else
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#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
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#endif
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