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| 1 | +/* |
| 2 | + ******************************************************************************* |
| 3 | + * Copyright (c) 2022, STMicroelectronics |
| 4 | + * All rights reserved. |
| 5 | + * |
| 6 | + * This software component is licensed by ST under BSD 3-Clause license, |
| 7 | + * the "License"; You may not use this file except in compliance with the |
| 8 | + * License. You may obtain a copy of the License at: |
| 9 | + * opensource.org/licenses/BSD-3-Clause |
| 10 | + * |
| 11 | + ******************************************************************************* |
| 12 | + */ |
| 13 | +#if defined(ARDUINO_NUCLEO_WB15CC) |
| 14 | +#include "pins_arduino.h" |
| 15 | +#include "lock_resource.h" |
| 16 | + |
| 17 | +// Pin number |
| 18 | +const PinName digitalPin[] = { |
| 19 | + PB_7, |
| 20 | + PB_6, |
| 21 | + PB_0, |
| 22 | + PA_12, |
| 23 | + PB_1, |
| 24 | + PA_11, |
| 25 | + PA_8, |
| 26 | + PE_4, |
| 27 | + PB_5, |
| 28 | + PA_15, |
| 29 | + PB_2, |
| 30 | + PA_7, |
| 31 | + PB_4, |
| 32 | + PA_5, |
| 33 | + PB_9, |
| 34 | + PB_8, |
| 35 | + PA_4, |
| 36 | + PA_6, |
| 37 | + PA_1, |
| 38 | + PA_0, |
| 39 | + PA_2, |
| 40 | + PA_3, |
| 41 | + // ST Morpho |
| 42 | + // CN7 Left Side |
| 43 | + PH_3, |
| 44 | + PA_13, |
| 45 | + PA_14, |
| 46 | + PC_14, |
| 47 | + PC_15, |
| 48 | + // CN10 Right side |
| 49 | + PA_9, |
| 50 | + PA_10, |
| 51 | + PB_3, |
| 52 | +}; |
| 53 | + |
| 54 | +// Analog (Ax) pin number array |
| 55 | +const uint32_t analogInputPin[] = { |
| 56 | + 16, // A0 |
| 57 | + 17, // A1 |
| 58 | + 18, // A2 |
| 59 | + 19, // A3 |
| 60 | + 20, // A4 |
| 61 | + 21, // A5 |
| 62 | + 6, // A6 |
| 63 | + 11, // A7 |
| 64 | + 13, // A8 |
| 65 | + 27 // A9 |
| 66 | +}; |
| 67 | + |
| 68 | +// ---------------------------------------------------------------------------- |
| 69 | +#ifdef __cplusplus |
| 70 | +extern "C" { |
| 71 | +#endif |
| 72 | + |
| 73 | +/** |
| 74 | + * @brief System Clock Configuration |
| 75 | + * @param None |
| 76 | + * @retval None |
| 77 | + */ |
| 78 | +WEAK void SystemClock_Config(void) |
| 79 | +{ |
| 80 | + RCC_OscInitTypeDef RCC_OscInitStruct = {}; |
| 81 | + RCC_ClkInitTypeDef RCC_ClkInitStruct = {}; |
| 82 | + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {}; |
| 83 | + |
| 84 | + /* This prevents concurrent access to RCC registers by CPU2 (M0+) */ |
| 85 | + hsem_lock(CFG_HW_RCC_SEMID, HSEM_LOCK_DEFAULT_RETRY); |
| 86 | + |
| 87 | + /** Configure LSE Drive Capability |
| 88 | + */ |
| 89 | + HAL_PWR_EnableBkUpAccess(); |
| 90 | + __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_MEDIUMHIGH); |
| 91 | + |
| 92 | + /** Initializes the RCC Oscillators according to the specified parameters |
| 93 | + * in the RCC_OscInitTypeDef structure. |
| 94 | + */ |
| 95 | + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSI1 |
| 96 | + | RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_LSE; |
| 97 | + RCC_OscInitStruct.HSEState = RCC_HSE_ON; |
| 98 | + RCC_OscInitStruct.LSEState = RCC_LSE_ON; |
| 99 | + RCC_OscInitStruct.HSIState = RCC_HSI_ON; |
| 100 | + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; |
| 101 | + RCC_OscInitStruct.LSIState = RCC_LSI_ON; |
| 102 | + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; |
| 103 | + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; |
| 104 | + RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV2; |
| 105 | + RCC_OscInitStruct.PLL.PLLN = 6; |
| 106 | + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; |
| 107 | + RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV3; |
| 108 | + RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2; |
| 109 | + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { |
| 110 | + Error_Handler(); |
| 111 | + } |
| 112 | + |
| 113 | + /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers |
| 114 | + */ |
| 115 | + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4 | RCC_CLOCKTYPE_HCLK2 |
| 116 | + | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK |
| 117 | + | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; |
| 118 | + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; |
| 119 | + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; |
| 120 | + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; |
| 121 | + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; |
| 122 | + RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV1; |
| 123 | + RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1; |
| 124 | + |
| 125 | + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) { |
| 126 | + Error_Handler(); |
| 127 | + } |
| 128 | + |
| 129 | + /** Initializes the peripherals clock |
| 130 | + */ |
| 131 | + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SMPS | RCC_PERIPHCLK_RFWAKEUP; |
| 132 | + PeriphClkInitStruct.RFWakeUpClockSelection = RCC_RFWKPCLKSOURCE_LSE; |
| 133 | + PeriphClkInitStruct.SmpsClockSelection = RCC_SMPSCLKSOURCE_HSE; |
| 134 | + PeriphClkInitStruct.SmpsDivSelection = RCC_SMPSCLKDIV_RANGE0; |
| 135 | + |
| 136 | + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { |
| 137 | + Error_Handler(); |
| 138 | + } |
| 139 | + |
| 140 | + LL_PWR_SMPS_SetStartupCurrent(LL_PWR_SMPS_STARTUP_CURRENT_80MA); |
| 141 | + LL_PWR_SMPS_SetOutputVoltageLevel(LL_PWR_SMPS_OUTPUT_VOLTAGE_1V40); |
| 142 | + LL_PWR_SMPS_Enable(); |
| 143 | + |
| 144 | + /* Select HSI as system clock source after Wake Up from Stop mode */ |
| 145 | + LL_RCC_SetClkAfterWakeFromStop(LL_RCC_STOP_WAKEUPCLOCK_HSI); |
| 146 | + |
| 147 | + hsem_unlock(CFG_HW_RCC_SEMID); |
| 148 | +} |
| 149 | + |
| 150 | +#ifdef __cplusplus |
| 151 | +} |
| 152 | +#endif |
| 153 | +#endif /* ARDUINO_NUCLEO_WB15CC */ |
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