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system(F4) update STM32F4xx HAL Drivers to v1.8.0
Included in STM32CubeF4 FW v1.27.0 Signed-off-by: Alexandre Bourdiol <[email protected]>
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‎system/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h

+149-7
Original file line numberDiff line numberDiff line change
@@ -7,13 +7,12 @@
77
******************************************************************************
88
* @attention
99
*
10-
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
11-
* All rights reserved.</center></h2>
10+
* Copyright (c) 2021 STMicroelectronics.
11+
* All rights reserved.
1212
*
13-
* This software component is licensed by ST under BSD 3-Clause license,
14-
* the "License"; You may not use this file except in compliance with the
15-
* License. You may obtain a copy of the License at:
16-
* opensource.org/licenses/BSD-3-Clause
13+
* This software is licensed under terms that can be found in the LICENSE file
14+
* in the root directory of this software component.
15+
* If no LICENSE file comes with this software, it is provided AS-IS.
1716
*
1817
******************************************************************************
1918
*/
@@ -105,6 +104,12 @@ extern "C" {
105104
#if defined(STM32H7)
106105
#define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT
107106
#endif /* STM32H7 */
107+
108+
#if defined(STM32U5)
109+
#define ADC_SAMPLETIME_5CYCLE ADC_SAMPLETIME_5CYCLES
110+
#define ADC_SAMPLETIME_391CYCLES_5 ADC_SAMPLETIME_391CYCLES
111+
#define ADC4_SAMPLETIME_160CYCLES_5 ADC4_SAMPLETIME_814CYCLES_5
112+
#endif /* STM32U5 */
108113
/**
109114
* @}
110115
*/
@@ -214,10 +219,20 @@ extern "C" {
214219
* @{
215220
*/
216221
#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
222+
#if defined(STM32U5)
223+
#define MPU_DEVICE_nGnRnE MPU_DEVICE_NGNRNE
224+
#define MPU_DEVICE_nGnRE MPU_DEVICE_NGNRE
225+
#define MPU_DEVICE_nGRE MPU_DEVICE_NGRE
226+
#endif /* STM32U5 */
217227
/**
218228
* @}
219229
*/
220230

231+
/** @defgroup CRC_Aliases CRC API aliases
232+
* @{
233+
*/
234+
#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */
235+
#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */
221236
/**
222237
* @}
223238
*/
@@ -252,6 +267,13 @@ extern "C" {
252267
#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL
253268
#endif
254269

270+
#if defined(STM32U5)
271+
#define DAC_TRIGGER_STOP_LPTIM1_OUT DAC_TRIGGER_STOP_LPTIM1_CH1
272+
#define DAC_TRIGGER_STOP_LPTIM3_OUT DAC_TRIGGER_STOP_LPTIM3_CH1
273+
#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1
274+
#define DAC_TRIGGER_LPTIM3_OUT DAC_TRIGGER_LPTIM3_CH1
275+
#endif
276+
255277
#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4)
256278
#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID
257279
#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID
@@ -394,6 +416,10 @@ extern "C" {
394416
#define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT
395417

396418
#endif /* STM32H7 */
419+
420+
#if defined(STM32U5)
421+
#define GPDMA1_REQUEST_DCMI GPDMA1_REQUEST_DCMI_PSSI
422+
#endif /* STM32U5 */
397423
/**
398424
* @}
399425
*/
@@ -542,6 +568,7 @@ extern "C" {
542568
#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD
543569
#endif /* STM32G4 */
544570

571+
545572
/**
546573
* @}
547574
*/
@@ -637,6 +664,20 @@ extern "C" {
637664
#endif /* STM32F0 || STM32F3 || STM32F1 */
638665

639666
#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1
667+
668+
#if defined(STM32U5)
669+
#define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ
670+
#endif /* STM32U5 */
671+
/**
672+
* @}
673+
*/
674+
675+
/** @defgroup HAL_GTZC_Aliased_Defines HAL GTZC Aliased Defines maintained for legacy purpose
676+
* @{
677+
*/
678+
#if defined(STM32U5)
679+
#define GTZC_PERIPH_DCMI GTZC_PERIPH_DCMI_PSSI
680+
#endif /* STM32U5 */
640681
/**
641682
* @}
642683
*/
@@ -874,9 +915,19 @@ extern "C" {
874915
#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS
875916
#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS
876917

918+
919+
/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
920+
* @{
921+
*/
922+
#define HAL_LPTIM_ReadCompare HAL_LPTIM_ReadCapturedValue
923+
/**
924+
* @}
925+
*/
926+
877927
#if defined(STM32U5)
878928
#define LPTIM_ISR_CC1 LPTIM_ISR_CC1IF
879929
#define LPTIM_ISR_CC2 LPTIM_ISR_CC2IF
930+
#define LPTIM_CHANNEL_ALL 0x00000000U
880931
#endif /* STM32U5 */
881932
/**
882933
* @}
@@ -1216,6 +1267,10 @@ extern "C" {
12161267
#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2
12171268
#endif
12181269

1270+
#if defined(STM32U5) || defined(STM32MP2)
1271+
#define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS
1272+
#define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK
1273+
#endif
12191274
/**
12201275
* @}
12211276
*/
@@ -1646,6 +1701,79 @@ extern "C" {
16461701

16471702
#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL
16481703

1704+
#if defined (STM32U5)
1705+
#define PWR_SRAM1_PAGE1_STOP_RETENTION PWR_SRAM1_PAGE1_STOP
1706+
#define PWR_SRAM1_PAGE2_STOP_RETENTION PWR_SRAM1_PAGE2_STOP
1707+
#define PWR_SRAM1_PAGE3_STOP_RETENTION PWR_SRAM1_PAGE3_STOP
1708+
#define PWR_SRAM1_PAGE4_STOP_RETENTION PWR_SRAM1_PAGE4_STOP
1709+
#define PWR_SRAM1_PAGE5_STOP_RETENTION PWR_SRAM1_PAGE5_STOP
1710+
#define PWR_SRAM1_PAGE6_STOP_RETENTION PWR_SRAM1_PAGE6_STOP
1711+
#define PWR_SRAM1_PAGE7_STOP_RETENTION PWR_SRAM1_PAGE7_STOP
1712+
#define PWR_SRAM1_PAGE8_STOP_RETENTION PWR_SRAM1_PAGE8_STOP
1713+
#define PWR_SRAM1_PAGE9_STOP_RETENTION PWR_SRAM1_PAGE9_STOP
1714+
#define PWR_SRAM1_PAGE10_STOP_RETENTION PWR_SRAM1_PAGE10_STOP
1715+
#define PWR_SRAM1_PAGE11_STOP_RETENTION PWR_SRAM1_PAGE11_STOP
1716+
#define PWR_SRAM1_PAGE12_STOP_RETENTION PWR_SRAM1_PAGE12_STOP
1717+
#define PWR_SRAM1_FULL_STOP_RETENTION PWR_SRAM1_FULL_STOP
1718+
1719+
#define PWR_SRAM2_PAGE1_STOP_RETENTION PWR_SRAM2_PAGE1_STOP
1720+
#define PWR_SRAM2_PAGE2_STOP_RETENTION PWR_SRAM2_PAGE2_STOP
1721+
#define PWR_SRAM2_FULL_STOP_RETENTION PWR_SRAM2_FULL_STOP
1722+
1723+
#define PWR_SRAM3_PAGE1_STOP_RETENTION PWR_SRAM3_PAGE1_STOP
1724+
#define PWR_SRAM3_PAGE2_STOP_RETENTION PWR_SRAM3_PAGE2_STOP
1725+
#define PWR_SRAM3_PAGE3_STOP_RETENTION PWR_SRAM3_PAGE3_STOP
1726+
#define PWR_SRAM3_PAGE4_STOP_RETENTION PWR_SRAM3_PAGE4_STOP
1727+
#define PWR_SRAM3_PAGE5_STOP_RETENTION PWR_SRAM3_PAGE5_STOP
1728+
#define PWR_SRAM3_PAGE6_STOP_RETENTION PWR_SRAM3_PAGE6_STOP
1729+
#define PWR_SRAM3_PAGE7_STOP_RETENTION PWR_SRAM3_PAGE7_STOP
1730+
#define PWR_SRAM3_PAGE8_STOP_RETENTION PWR_SRAM3_PAGE8_STOP
1731+
#define PWR_SRAM3_PAGE9_STOP_RETENTION PWR_SRAM3_PAGE9_STOP
1732+
#define PWR_SRAM3_PAGE10_STOP_RETENTION PWR_SRAM3_PAGE10_STOP
1733+
#define PWR_SRAM3_PAGE11_STOP_RETENTION PWR_SRAM3_PAGE11_STOP
1734+
#define PWR_SRAM3_PAGE12_STOP_RETENTION PWR_SRAM3_PAGE12_STOP
1735+
#define PWR_SRAM3_PAGE13_STOP_RETENTION PWR_SRAM3_PAGE13_STOP
1736+
#define PWR_SRAM3_FULL_STOP_RETENTION PWR_SRAM3_FULL_STOP
1737+
1738+
#define PWR_SRAM4_FULL_STOP_RETENTION PWR_SRAM4_FULL_STOP
1739+
1740+
#define PWR_SRAM5_PAGE1_STOP_RETENTION PWR_SRAM5_PAGE1_STOP
1741+
#define PWR_SRAM5_PAGE2_STOP_RETENTION PWR_SRAM5_PAGE2_STOP
1742+
#define PWR_SRAM5_PAGE3_STOP_RETENTION PWR_SRAM5_PAGE3_STOP
1743+
#define PWR_SRAM5_PAGE4_STOP_RETENTION PWR_SRAM5_PAGE4_STOP
1744+
#define PWR_SRAM5_PAGE5_STOP_RETENTION PWR_SRAM5_PAGE5_STOP
1745+
#define PWR_SRAM5_PAGE6_STOP_RETENTION PWR_SRAM5_PAGE6_STOP
1746+
#define PWR_SRAM5_PAGE7_STOP_RETENTION PWR_SRAM5_PAGE7_STOP
1747+
#define PWR_SRAM5_PAGE8_STOP_RETENTION PWR_SRAM5_PAGE8_STOP
1748+
#define PWR_SRAM5_PAGE9_STOP_RETENTION PWR_SRAM5_PAGE9_STOP
1749+
#define PWR_SRAM5_PAGE10_STOP_RETENTION PWR_SRAM5_PAGE10_STOP
1750+
#define PWR_SRAM5_PAGE11_STOP_RETENTION PWR_SRAM5_PAGE11_STOP
1751+
#define PWR_SRAM5_PAGE12_STOP_RETENTION PWR_SRAM5_PAGE12_STOP
1752+
#define PWR_SRAM5_PAGE13_STOP_RETENTION PWR_SRAM5_PAGE13_STOP
1753+
#define PWR_SRAM5_FULL_STOP_RETENTION PWR_SRAM5_FULL_STOP
1754+
1755+
#define PWR_ICACHE_FULL_STOP_RETENTION PWR_ICACHE_FULL_STOP
1756+
#define PWR_DCACHE1_FULL_STOP_RETENTION PWR_DCACHE1_FULL_STOP
1757+
#define PWR_DCACHE2_FULL_STOP_RETENTION PWR_DCACHE2_FULL_STOP
1758+
#define PWR_DMA2DRAM_FULL_STOP_RETENTION PWR_DMA2DRAM_FULL_STOP
1759+
#define PWR_PERIPHRAM_FULL_STOP_RETENTION PWR_PERIPHRAM_FULL_STOP
1760+
#define PWR_PKA32RAM_FULL_STOP_RETENTION PWR_PKA32RAM_FULL_STOP
1761+
#define PWR_GRAPHICPRAM_FULL_STOP_RETENTION PWR_GRAPHICPRAM_FULL_STOP
1762+
#define PWR_DSIRAM_FULL_STOP_RETENTION PWR_DSIRAM_FULL_STOP
1763+
1764+
#define PWR_SRAM2_PAGE1_STANDBY_RETENTION PWR_SRAM2_PAGE1_STANDBY
1765+
#define PWR_SRAM2_PAGE2_STANDBY_RETENTION PWR_SRAM2_PAGE2_STANDBY
1766+
#define PWR_SRAM2_FULL_STANDBY_RETENTION PWR_SRAM2_FULL_STANDBY
1767+
1768+
#define PWR_SRAM1_FULL_RUN_RETENTION PWR_SRAM1_FULL_RUN
1769+
#define PWR_SRAM2_FULL_RUN_RETENTION PWR_SRAM2_FULL_RUN
1770+
#define PWR_SRAM3_FULL_RUN_RETENTION PWR_SRAM3_FULL_RUN
1771+
#define PWR_SRAM4_FULL_RUN_RETENTION PWR_SRAM4_FULL_RUN
1772+
#define PWR_SRAM5_FULL_RUN_RETENTION PWR_SRAM5_FULL_RUN
1773+
1774+
#define PWR_ALL_RAM_RUN_RETENTION_MASK PWR_ALL_RAM_RUN_MASK
1775+
#endif
1776+
16491777
/**
16501778
* @}
16511779
*/
@@ -3404,7 +3532,21 @@ extern "C" {
34043532
#define __HAL_RCC_APB2_CLK_Disable_Clear __HAL_RCC_APB2_CLK_ENABLE
34053533
#define __HAL_RCC_APB3_CLK_Disable_Clear __HAL_RCC_APB3_CLK_ENABLE
34063534
#define IS_RCC_MSIPLLModeSelection IS_RCC_MSIPLLMODE_SELECT
3535+
#define RCC_PERIPHCLK_CLK48 RCC_PERIPHCLK_ICLK
3536+
#define RCC_CLK48CLKSOURCE_HSI48 RCC_ICLK_CLKSOURCE_HSI48
3537+
#define RCC_CLK48CLKSOURCE_PLL2 RCC_ICLK_CLKSOURCE_PLL2
3538+
#define RCC_CLK48CLKSOURCE_PLL1 RCC_ICLK_CLKSOURCE_PLL1
3539+
#define RCC_CLK48CLKSOURCE_MSIK RCC_ICLK_CLKSOURCE_MSIK
3540+
#define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
3541+
#define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
3542+
#define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
3543+
#define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
3544+
#define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
3545+
#define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
3546+
#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC12_CLK_SLEEP_ENABLE
3547+
#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC12_CLK_SLEEP_DISABLE
34073548
#endif
3549+
34083550
/**
34093551
* @}
34103552
*/
@@ -3474,6 +3616,7 @@ extern "C" {
34743616
#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE
34753617
#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE
34763618

3619+
34773620
/**
34783621
* @}
34793622
*/
@@ -3836,5 +3979,4 @@ extern "C" {
38363979

38373980
#endif /* STM32_HAL_LEGACY */
38383981

3839-
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
38403982

‎system/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32f4xx_hal_can_legacy.h

+5-25
Original file line numberDiff line numberDiff line change
@@ -6,29 +6,12 @@
66
******************************************************************************
77
* @attention
88
*
9-
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
9+
* Copyright (c) 2016 STMicroelectronics.
10+
* All rights reserved.
1011
*
11-
* Redistribution and use in source and binary forms, with or without modification,
12-
* are permitted provided that the following conditions are met:
13-
* 1. Redistributions of source code must retain the above copyright notice,
14-
* this list of conditions and the following disclaimer.
15-
* 2. Redistributions in binary form must reproduce the above copyright notice,
16-
* this list of conditions and the following disclaimer in the documentation
17-
* and/or other materials provided with the distribution.
18-
* 3. Neither the name of STMicroelectronics nor the names of its contributors
19-
* may be used to endorse or promote products derived from this software
20-
* without specific prior written permission.
21-
*
22-
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
23-
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24-
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
25-
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
26-
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27-
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28-
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
29-
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30-
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31-
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
12+
* This software is licensed under terms that can be found in the LICENSE file
13+
* in the root directory of this software component.
14+
* If no LICENSE file comes with this software, it is provided AS-IS.
3215
*
3316
******************************************************************************
3417
*/
@@ -780,6 +763,3 @@ HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan);
780763
#endif
781764

782765
#endif /* __STM32F4xx_HAL_CAN_LEGACY_H */
783-
784-
785-
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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