Skip to content

Commit 0fb3eff

Browse files
yp05327fpistm
authored andcommitted
variant(H7): add support for NUCLEO-H753ZI
Signed-off-by: yp05327 <[email protected]>
1 parent 6c48d73 commit 0fb3eff

File tree

5 files changed

+567
-0
lines changed

5 files changed

+567
-0
lines changed

Diff for: README.md

+1
Original file line numberDiff line numberDiff line change
@@ -99,6 +99,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d
9999
| :green_heart: | STM32H563ZI | [Nucleo H563ZI](https://www.st.com/en/evaluation-tools/nucleo-h563zi.html) | *2.6.0* | |
100100
| :green_heart: | STM32H723ZG | [Nucleo H723ZG](https://www.st.com/en/evaluation-tools/nucleo-h723zg.html) | *2.4.0* | |
101101
| :green_heart: | STM32H743ZI | [Nucleo H743ZI(2)](https://www.st.com/en/evaluation-tools/nucleo-h743zi.html) | *1.5.0* | Nucleo H743ZI2 since 1.6.0 |
102+
| :yellow_heart: | STM32H753ZI | [Nucleo H753ZI](https://www.st.com/en/evaluation-tools/nucleo-h753zi.html) | **2.7.0** | |
102103
| :green_heart: | STM32L496ZG | [Nucleo L496ZG](http://www.st.com/en/evaluation-tools/nucleo-l496zg.html) | *1.3.0* | |
103104
| :green_heart: | STM32L496ZG-P | [Nucleo L496ZG-P](http://www.st.com/en/evaluation-tools/nucleo-l496zg-p.html) | *1.3.0* | |
104105
| :green_heart: | STM32L4R5ZI | [Nucleo L4R5ZI](http://www.st.com/en/evaluation-tools/nucleo-l4r5zi.html) | *1.4.0* | |

Diff for: boards.txt

+14
Original file line numberDiff line numberDiff line change
@@ -195,6 +195,20 @@ Nucleo_144.menu.pnum.NUCLEO_H743ZI2.build.product_line=STM32H743xx
195195
Nucleo_144.menu.pnum.NUCLEO_H743ZI2.build.variant=STM32H7xx/H742Z(G-I)T_H743Z(G-I)T_H747A(G-I)I_H747I(G-I)T_H750ZBT_H753ZIT_H757AII_H757IIT
196196
Nucleo_144.menu.pnum.NUCLEO_H743ZI2.build.variant_h=variant_NUCLEO_H743ZI.h
197197

198+
# NUCLEO_H753ZI board
199+
Nucleo_144.menu.pnum.NUCLEO_H753ZI=Nucleo H753ZI
200+
Nucleo_144.menu.pnum.NUCLEO_H753ZI.node=NODE_H753ZI
201+
Nucleo_144.menu.pnum.NUCLEO_H753ZI.upload.maximum_size=2097152
202+
Nucleo_144.menu.pnum.NUCLEO_H753ZI.upload.maximum_data_size=524288
203+
Nucleo_144.menu.pnum.NUCLEO_H753ZI.build.mcu=cortex-m7
204+
Nucleo_144.menu.pnum.NUCLEO_H753ZI.build.fpu=-mfpu=fpv4-sp-d16
205+
Nucleo_144.menu.pnum.NUCLEO_H753ZI.build.float-abi=-mfloat-abi=hard
206+
Nucleo_144.menu.pnum.NUCLEO_H753ZI.build.board=NUCLEO_H753ZI
207+
Nucleo_144.menu.pnum.NUCLEO_H753ZI.build.series=STM32H7xx
208+
Nucleo_144.menu.pnum.NUCLEO_H753ZI.build.product_line=STM32H753xx
209+
Nucleo_144.menu.pnum.NUCLEO_H753ZI.build.variant=STM32H7xx/H742Z(G-I)T_H743Z(G-I)T_H747A(G-I)I_H747I(G-I)T_H750ZBT_H753ZIT_H757AII_H757IIT
210+
Nucleo_144.menu.pnum.NUCLEO_H753ZI.build.variant_h=variant_NUCLEO_H753ZI.h
211+
198212
# NUCLEO_L496ZG board
199213
Nucleo_144.menu.pnum.NUCLEO_L496ZG=Nucleo L496ZG
200214
Nucleo_144.menu.pnum.NUCLEO_L496ZG.node=NODE_L496ZG

Diff for: variants/STM32H7xx/H742Z(G-I)T_H743Z(G-I)T_H747A(G-I)I_H747I(G-I)T_H750ZBT_H753ZIT_H757AII_H757IIT/CMakeLists.txt

+1
Original file line numberDiff line numberDiff line change
@@ -23,6 +23,7 @@ add_library(variant_bin STATIC EXCLUDE_FROM_ALL
2323
PeripheralPins.c
2424
variant_generic.cpp
2525
variant_NUCLEO_H743ZI.cpp
26+
variant_NUCLEO_H753ZI.cpp
2627
)
2728
target_link_libraries(variant_bin PUBLIC variant_usage)
2829

Original file line numberDiff line numberDiff line change
@@ -0,0 +1,272 @@
1+
/*
2+
*******************************************************************************
3+
* Copyright (c) 2023, STMicroelectronics
4+
* All rights reserved.
5+
*
6+
* This software component is licensed by ST under BSD 3-Clause license,
7+
* the "License"; You may not use this file except in compliance with the
8+
* License. You may obtain a copy of the License at:
9+
* opensource.org/licenses/BSD-3-Clause
10+
*
11+
*******************************************************************************
12+
*/
13+
#if defined(ARDUINO_NUCLEO_H753ZI)
14+
#include "pins_arduino.h"
15+
16+
// Pin number
17+
const PinName digitalPin[] = {
18+
PB_7,
19+
PB_6,
20+
PG_14,
21+
PE_13,
22+
PE_14,
23+
PE_11,
24+
PE_9,
25+
PG_12,
26+
PF_3,
27+
PD_15,
28+
PD_14,
29+
PB_5,
30+
PA_6,
31+
PA_5,
32+
PB_9,
33+
PB_8,
34+
PC_6,
35+
PB_15,
36+
PB_13,
37+
PB_12,
38+
PA_15,
39+
PC_7,
40+
PB_5,
41+
PB_3,
42+
PA_4,
43+
PB_4,
44+
PG_6,
45+
PB_2,
46+
PD_13,
47+
PD_12,
48+
PD_11,
49+
PE_2,
50+
PA_0,
51+
PB_0,
52+
PE_0,
53+
PB_11,
54+
PB_10,
55+
PE_15,
56+
PE_6,
57+
PE_12,
58+
PE_10,
59+
PE_7,
60+
PE_8,
61+
PC_8,
62+
PC_9,
63+
PC_10,
64+
PC_11,
65+
PC_12,
66+
PD_2,
67+
PG_2,
68+
PG_3,
69+
PD_7,
70+
PD_6,
71+
PD_5,
72+
PD_4,
73+
PD_3,
74+
PE_2,
75+
PE_4,
76+
PE_5,
77+
PE_6,
78+
PE_3,
79+
PF_8,
80+
PF_7,
81+
PF_9,
82+
PG_1,
83+
PG_0,
84+
PD_1,
85+
PD_0,
86+
PF_0,
87+
PF_1,
88+
PF_2,
89+
PE_9,
90+
PB_2,
91+
PA_3,
92+
PC_0,
93+
PC_3_C,
94+
PB_1,
95+
PC_2_C,
96+
PF_10,
97+
PF_4,
98+
PF_5,
99+
PF_6,
100+
PF_11,
101+
PA_1,
102+
PA_2,
103+
PA_7,
104+
PA_8,
105+
PA_9,
106+
PA_10,
107+
PA_11,
108+
PA_12,
109+
PA_13,
110+
PA_14,
111+
PB_14,
112+
PC_1,
113+
PC_4,
114+
PC_5,
115+
PC_13,
116+
PC_14,
117+
PC_15,
118+
PD_8,
119+
PD_9,
120+
PD_10,
121+
PE_1,
122+
PF_12,
123+
PF_13,
124+
PF_14,
125+
PF_15,
126+
PG_4,
127+
PG_5,
128+
PG_7,
129+
PG_8,
130+
PG_9,
131+
PG_10,
132+
PG_11,
133+
PG_13,
134+
PG_15,
135+
PH_0,
136+
PH_1
137+
};
138+
139+
// Analog (Ax) pin number array
140+
const uint32_t analogInputPin[] = {
141+
73, // A0
142+
74, // A1
143+
75, // A2
144+
76, // A3
145+
77, // A4
146+
78, // A5
147+
79, // A6
148+
80, // A7
149+
81, // A8
150+
82, // A9
151+
83, // A10
152+
84, // A11
153+
85, // A12
154+
94, // A13
155+
95, // A14
156+
96, // A15
157+
104, // A16
158+
105, // A17
159+
106, // A18
160+
8, // A19
161+
12, // A20
162+
13, // A21
163+
24, // A22
164+
32, // A23
165+
33, // A24
166+
61, // A25
167+
62, // A26
168+
63 // A27
169+
};
170+
171+
// ----------------------------------------------------------------------------
172+
173+
#ifdef __cplusplus
174+
extern "C" {
175+
#endif
176+
177+
/**
178+
* @brief System Clock Configuration
179+
* @param None
180+
* @retval None
181+
*/
182+
WEAK void SystemClock_Config(void)
183+
{
184+
RCC_OscInitTypeDef RCC_OscInitStruct = {};
185+
RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
186+
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {};
187+
188+
/* Supply configuration update enable */
189+
HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
190+
/* Configure the main internal regulator output voltage */
191+
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0);
192+
193+
while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
194+
/* Macro to configure the PLL clock source */
195+
__HAL_RCC_PLL_PLLSOURCE_CONFIG(RCC_PLLSOURCE_HSE);
196+
/** Initializes the RCC Oscillators according to the specified parameters
197+
* in the RCC_OscInitTypeDef structure.
198+
*/
199+
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSE;
200+
RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
201+
RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
202+
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
203+
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
204+
RCC_OscInitStruct.PLL.PLLM = 1;
205+
RCC_OscInitStruct.PLL.PLLN = 120;
206+
RCC_OscInitStruct.PLL.PLLP = 2;
207+
RCC_OscInitStruct.PLL.PLLQ = 8;
208+
RCC_OscInitStruct.PLL.PLLR = 2;
209+
RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_3;
210+
RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
211+
RCC_OscInitStruct.PLL.PLLFRACN = 0;
212+
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
213+
Error_Handler();
214+
}
215+
/* Initializes the CPU, AHB and APB buses clocks */
216+
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
217+
| RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2
218+
| RCC_CLOCKTYPE_D3PCLK1 | RCC_CLOCKTYPE_D1PCLK1;
219+
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
220+
RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
221+
RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
222+
RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
223+
RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
224+
RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
225+
RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
226+
227+
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
228+
Error_Handler();
229+
}
230+
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB | RCC_PERIPHCLK_QSPI
231+
| RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_ADC
232+
| RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_USART16
233+
| RCC_PERIPHCLK_USART234578 | RCC_PERIPHCLK_I2C123
234+
| RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_SPI123
235+
| RCC_PERIPHCLK_SPI45 | RCC_PERIPHCLK_SPI6;
236+
PeriphClkInitStruct.PLL2.PLL2M = 1;
237+
PeriphClkInitStruct.PLL2.PLL2N = 20;
238+
PeriphClkInitStruct.PLL2.PLL2P = 2;
239+
PeriphClkInitStruct.PLL2.PLL2Q = 2;
240+
PeriphClkInitStruct.PLL2.PLL2R = 2;
241+
PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2VCIRANGE_3;
242+
PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2VCOMEDIUM;
243+
PeriphClkInitStruct.PLL2.PLL2FRACN = 0.0;
244+
PeriphClkInitStruct.PLL3.PLL3M = 1;
245+
PeriphClkInitStruct.PLL3.PLL3N = 24;
246+
PeriphClkInitStruct.PLL3.PLL3P = 2;
247+
PeriphClkInitStruct.PLL3.PLL3Q = 6;
248+
PeriphClkInitStruct.PLL3.PLL3R = 2;
249+
PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3VCIRANGE_3;
250+
PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3VCOWIDE;
251+
PeriphClkInitStruct.PLL3.PLL3FRACN = 0.0;
252+
PeriphClkInitStruct.AdcClockSelection = RCC_ADCCLKSOURCE_PLL2;
253+
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
254+
PeriphClkInitStruct.QspiClockSelection = RCC_QSPICLKSOURCE_D1HCLK;
255+
PeriphClkInitStruct.SdmmcClockSelection = RCC_SDMMCCLKSOURCE_PLL;
256+
PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PLL3;
257+
PeriphClkInitStruct.Usart16ClockSelection = RCC_USART16CLKSOURCE_D2PCLK2;
258+
PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1;
259+
PeriphClkInitStruct.I2c123ClockSelection = RCC_I2C123CLKSOURCE_D2PCLK1;
260+
PeriphClkInitStruct.I2c4ClockSelection = RCC_I2C4CLKSOURCE_D3PCLK1;
261+
PeriphClkInitStruct.Spi123ClockSelection = RCC_SPI123CLKSOURCE_PLL;
262+
PeriphClkInitStruct.Spi45ClockSelection = RCC_SPI45CLKSOURCE_D2PCLK1;
263+
PeriphClkInitStruct.Spi6ClockSelection = RCC_SPI6CLKSOURCE_D3PCLK1;
264+
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
265+
Error_Handler();
266+
}
267+
}
268+
269+
#ifdef __cplusplus
270+
}
271+
#endif
272+
#endif /* ARDUINO_ */

0 commit comments

Comments
 (0)