Skip to content

Commit 08d6b13

Browse files
fpistmfpistm
committed
Add STM32G0xx system source file
CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File. This provides system initialization template function is case of an application using a STM32G0 device Signed-off-by: Frederic.Pillon <[email protected]>
1 parent fe1dcf4 commit 08d6b13

File tree

2 files changed

+293
-0
lines changed

2 files changed

+293
-0
lines changed

‎cores/arduino/stm32/system_stm32yyxx.c

+3
Original file line numberDiff line numberDiff line change
@@ -16,6 +16,9 @@
1616
#ifdef STM32F7xx
1717
#include "system_stm32f7xx.c"
1818
#endif
19+
#ifdef STM32G0xx
20+
#include "system_stm32g0xx.c"
21+
#endif
1922
#ifdef STM32H7xx
2023
#include "system_stm32h7xx.c"
2124
#endif

‎system/STM32G0xx/system_stm32g0xx.c

+290
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,290 @@
1+
/**
2+
******************************************************************************
3+
* @file system_stm32g0xx.c
4+
* @author MCD Application Team
5+
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File
6+
*
7+
* This file provides two functions and one global variable to be called from
8+
* user application:
9+
* - SystemInit(): This function is called at startup just after reset and
10+
* before branch to main program. This call is made inside
11+
* the "startup_stm32g0xx.s" file.
12+
*
13+
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
14+
* by the user application to setup the SysTick
15+
* timer or configure other parameters.
16+
*
17+
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
18+
* be called whenever the core clock is changed
19+
* during program execution.
20+
*
21+
* After each device reset the HSI (8 MHz then 16 MHz) is used as system clock source.
22+
* Then SystemInit() function is called, in "startup_stm32g0xx.s" file, to
23+
* configure the system clock before to branch to main program.
24+
*
25+
* This file configures the system clock as follows:
26+
*=============================================================================
27+
*-----------------------------------------------------------------------------
28+
* System Clock source | HSI
29+
*-----------------------------------------------------------------------------
30+
* SYSCLK(Hz) | 16000000
31+
*-----------------------------------------------------------------------------
32+
* HCLK(Hz) | 16000000
33+
*-----------------------------------------------------------------------------
34+
* AHB Prescaler | 1
35+
*-----------------------------------------------------------------------------
36+
* APB Prescaler | 1
37+
*-----------------------------------------------------------------------------
38+
* HSI Division factor | 1
39+
*-----------------------------------------------------------------------------
40+
* PLL_M | 1
41+
*-----------------------------------------------------------------------------
42+
* PLL_N | 8
43+
*-----------------------------------------------------------------------------
44+
* PLL_P | 7
45+
*-----------------------------------------------------------------------------
46+
* PLL_Q | 2
47+
*-----------------------------------------------------------------------------
48+
* PLL_R | 2
49+
*-----------------------------------------------------------------------------
50+
* Require 48MHz for RNG | Disabled
51+
*-----------------------------------------------------------------------------
52+
*=============================================================================
53+
******************************************************************************
54+
* @attention
55+
*
56+
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
57+
* All rights reserved.</center></h2>
58+
*
59+
* This software component is licensed by ST under BSD 3-Clause license,
60+
* the "License"; You may not use this file except in compliance with the
61+
* License. You may obtain a copy of the License at:
62+
* opensource.org/licenses/BSD-3-Clause
63+
*
64+
******************************************************************************
65+
*/
66+
67+
/** @addtogroup CMSIS
68+
* @{
69+
*/
70+
71+
/** @addtogroup stm32g0xx_system
72+
* @{
73+
*/
74+
75+
/** @addtogroup STM32G0xx_System_Private_Includes
76+
* @{
77+
*/
78+
79+
#include "stm32g0xx.h"
80+
81+
#if !defined (HSE_VALUE)
82+
#define HSE_VALUE (8000000UL) /*!< Value of the External oscillator in Hz */
83+
#endif /* HSE_VALUE */
84+
85+
#if !defined (HSI_VALUE)
86+
#define HSI_VALUE (16000000UL) /*!< Value of the Internal oscillator in Hz*/
87+
#endif /* HSI_VALUE */
88+
89+
#if !defined (LSI_VALUE)
90+
#define LSI_VALUE (32000UL) /*!< Value of LSI in Hz*/
91+
#endif /* LSI_VALUE */
92+
93+
#if !defined (LSE_VALUE)
94+
#define LSE_VALUE (32768UL) /*!< Value of LSE in Hz*/
95+
#endif /* LSE_VALUE */
96+
97+
/**
98+
* @}
99+
*/
100+
101+
/** @addtogroup STM32G0xx_System_Private_TypesDefinitions
102+
* @{
103+
*/
104+
105+
/**
106+
* @}
107+
*/
108+
109+
/** @addtogroup STM32G0xx_System_Private_Defines
110+
* @{
111+
*/
112+
113+
/************************* Miscellaneous Configuration ************************/
114+
/*!< Uncomment the following line if you need to relocate your vector Table in
115+
Internal SRAM. */
116+
/* #define VECT_TAB_SRAM */
117+
#ifndef VECT_TAB_OFFSET
118+
#define VECT_TAB_OFFSET 0x0U /*!< Vector Table base offset field.
119+
This value must be a multiple of 0x100. */
120+
#endif
121+
/******************************************************************************/
122+
/**
123+
* @}
124+
*/
125+
126+
/** @addtogroup STM32G0xx_System_Private_Macros
127+
* @{
128+
*/
129+
130+
/**
131+
* @}
132+
*/
133+
134+
/** @addtogroup STM32G0xx_System_Private_Variables
135+
* @{
136+
*/
137+
/* The SystemCoreClock variable is updated in three ways:
138+
1) by calling CMSIS function SystemCoreClockUpdate()
139+
2) by calling HAL API function HAL_RCC_GetHCLKFreq()
140+
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
141+
Note: If you use this function to configure the system clock; then there
142+
is no need to call the 2 first functions listed above, since SystemCoreClock
143+
variable is updated automatically.
144+
*/
145+
uint32_t SystemCoreClock = 16000000UL;
146+
147+
const uint32_t AHBPrescTable[16UL] = {0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL, 6UL, 7UL, 8UL, 9UL};
148+
const uint32_t APBPrescTable[8UL] = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
149+
150+
/**
151+
* @}
152+
*/
153+
154+
/** @addtogroup STM32G0xx_System_Private_FunctionPrototypes
155+
* @{
156+
*/
157+
158+
/**
159+
* @}
160+
*/
161+
162+
/** @addtogroup STM32G0xx_System_Private_Functions
163+
* @{
164+
*/
165+
166+
/**
167+
* @brief Setup the microcontroller system.
168+
* @param None
169+
* @retval None
170+
*/
171+
void SystemInit(void)
172+
{
173+
/* Configure the Vector Table location add offset address ------------------*/
174+
#ifdef VECT_TAB_SRAM
175+
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
176+
#else
177+
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
178+
#endif
179+
}
180+
181+
/**
182+
* @brief Update SystemCoreClock variable according to Clock Register Values.
183+
* The SystemCoreClock variable contains the core clock (HCLK), it can
184+
* be used by the user application to setup the SysTick timer or configure
185+
* other parameters.
186+
*
187+
* @note Each time the core clock (HCLK) changes, this function must be called
188+
* to update SystemCoreClock variable value. Otherwise, any configuration
189+
* based on this variable will be incorrect.
190+
*
191+
* @note - The system frequency computed by this function is not the real
192+
* frequency in the chip. It is calculated based on the predefined
193+
* constant and the selected clock source:
194+
*
195+
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) / HSI division factor
196+
*
197+
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
198+
*
199+
* - If SYSCLK source is LSI, SystemCoreClock will contain the LSI_VALUE
200+
*
201+
* - If SYSCLK source is LSE, SystemCoreClock will contain the LSE_VALUE
202+
*
203+
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
204+
* or HSI_VALUE(*) multiplied/divided by the PLL factors.
205+
*
206+
* (**) HSI_VALUE is a constant defined in stm32g0xx_hal_conf.h file (default value
207+
* 16 MHz) but the real value may vary depending on the variations
208+
* in voltage and temperature.
209+
*
210+
* (***) HSE_VALUE is a constant defined in stm32g0xx_hal_conf.h file (default value
211+
* 8 MHz), user has to ensure that HSE_VALUE is same as the real
212+
* frequency of the crystal used. Otherwise, this function may
213+
* have wrong result.
214+
*
215+
* - The result of this function could be not correct when using fractional
216+
* value for HSE crystal.
217+
*
218+
* @param None
219+
* @retval None
220+
*/
221+
void SystemCoreClockUpdate(void)
222+
{
223+
uint32_t tmp;
224+
uint32_t pllvco;
225+
uint32_t pllr;
226+
uint32_t pllsource;
227+
uint32_t pllm;
228+
uint32_t hsidiv;
229+
230+
/* Get SYSCLK source -------------------------------------------------------*/
231+
switch (RCC->CFGR & RCC_CFGR_SWS)
232+
{
233+
case RCC_CFGR_SWS_HSE: /* HSE used as system clock */
234+
SystemCoreClock = HSE_VALUE;
235+
break;
236+
237+
case RCC_CFGR_SWS_LSI: /* LSI used as system clock */
238+
SystemCoreClock = LSI_VALUE;
239+
break;
240+
241+
case RCC_CFGR_SWS_LSE: /* LSE used as system clock */
242+
SystemCoreClock = LSE_VALUE;
243+
break;
244+
245+
case RCC_CFGR_SWS_PLL: /* PLL used as system clock */
246+
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
247+
SYSCLK = PLL_VCO / PLLR
248+
*/
249+
pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
250+
pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL;
251+
252+
if(pllsource == 0x03UL) /* HSE used as PLL clock source */
253+
{
254+
pllvco = (HSE_VALUE / pllm);
255+
}
256+
else /* HSI used as PLL clock source */
257+
{
258+
pllvco = (HSI_VALUE / pllm);
259+
}
260+
pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
261+
pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
262+
SystemCoreClock = pllvco/pllr;
263+
break;
264+
case RCC_CFGR_SWS_HSI: /* HSI used as system clock */
265+
default: /* HSI used as system clock */
266+
hsidiv = (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV))>> RCC_CR_HSIDIV_Pos));
267+
SystemCoreClock = (HSI_VALUE/hsidiv);
268+
break;
269+
}
270+
/* Compute HCLK clock frequency --------------------------------------------*/
271+
/* Get HCLK prescaler */
272+
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
273+
/* HCLK clock frequency */
274+
SystemCoreClock >>= tmp;
275+
}
276+
277+
278+
/**
279+
* @}
280+
*/
281+
282+
/**
283+
* @}
284+
*/
285+
286+
/**
287+
* @}
288+
*/
289+
290+
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

0 commit comments

Comments
 (0)