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richardeoinrichardeoin
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Merge remote-tracking branch 'quartiq/feature/dma-buffer-swap-logic' into dma
This merge involved re-working much of #173
2 parents 2954e70 + 5f97920 commit 7b62474

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5 files changed

+261
-380
lines changed

5 files changed

+261
-380
lines changed

‎src/dma/bdma.rs

Lines changed: 32 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -431,38 +431,31 @@ macro_rules! bdma_stream {
431431

432432
impl<I: Instance> DoubleBufferedStream for $name<I> {
433433
#[inline(always)]
434-
unsafe fn set_peripheral_address(&mut self, value: u32) {
434+
unsafe fn set_peripheral_address(&mut self, value: usize) {
435435
//NOTE(unsafe) We only access the registers that belongs to the StreamX
436436
let dma = &*I::ptr();
437-
dma.ch[Self::NUMBER].par.write(|w| w.pa().bits(value));
437+
dma.ch[Self::NUMBER].par.write(|w| w.pa().bits(value as u32));
438438
}
439439

440440
#[inline(always)]
441-
unsafe fn set_memory_address(&mut self, value: u32) {
441+
unsafe fn set_memory_address(&mut self, buffer: CurrentBuffer, value: usize) {
442442
//NOTE(unsafe) We only access the registers that belongs to the StreamX
443443
let dma = &*I::ptr();
444-
dma.ch[Self::NUMBER].m0ar.write(|w| w.ma().bits(value));
445-
}
446-
447-
#[inline(always)]
448-
fn get_memory_address(&self) -> u32 {
449-
//NOTE(unsafe) We only access the registers that belongs to the StreamX
450-
let dma = unsafe { &*I::ptr() };
451-
dma.ch[Self::NUMBER].m0ar.read().ma().bits()
452-
}
453-
454-
#[inline(always)]
455-
unsafe fn set_memory_double_buffer_address(&mut self, value: u32) {
456-
//NOTE(unsafe) We only access the registers that belongs to the StreamX
457-
let dma = &*I::ptr();
458-
dma.ch[Self::NUMBER].m1ar.write(|w| w.ma().bits(value));
444+
match buffer {
445+
CurrentBuffer::Buffer0 => dma.ch[Self::NUMBER].m0ar.write(|w| w.ma().bits(value as u32)),
446+
CurrentBuffer::Buffer1 => dma.ch[Self::NUMBER].m1ar.write(|w| w.ma().bits(value as u32)),
447+
}
459448
}
460449

461450
#[inline(always)]
462-
fn get_memory_double_buffer_address(&self) -> u32 {
451+
fn get_memory_address(&self, buffer: CurrentBuffer) -> usize {
463452
//NOTE(unsafe) We only access the registers that belongs to the StreamX
464453
let dma = unsafe { &*I::ptr() };
465-
dma.ch[Self::NUMBER].m1ar.read().ma().bits()
454+
let addr = match buffer {
455+
CurrentBuffer::Buffer0 => dma.ch[Self::NUMBER].m0ar.read().ma().bits(),
456+
CurrentBuffer::Buffer1 => dma.ch[Self::NUMBER].m1ar.read().ma().bits(),
457+
};
458+
addr as usize
466459
}
467460

468461
#[inline(always)]
@@ -543,13 +536,29 @@ macro_rules! bdma_stream {
543536
}
544537

545538
#[inline(always)]
546-
fn current_buffer() -> CurrentBuffer {
539+
fn get_current_buffer() -> CurrentBuffer {
547540
//NOTE(unsafe) Atomic read with no side effects
548541
let dma = unsafe { &*I::ptr() };
549542
if dma.ch[Self::NUMBER].cr.read().ct().bit_is_set() {
550-
CurrentBuffer::DoubleBuffer
543+
CurrentBuffer::Buffer0
544+
} else {
545+
CurrentBuffer::Buffer1
546+
}
547+
}
548+
549+
#[inline(always)]
550+
fn get_inactive_buffer() -> Option<CurrentBuffer> {
551+
//NOTE(unsafe) Atomic read with no side effects
552+
let dma = unsafe { &*I::ptr() };
553+
let cr = dma.ch[Self::NUMBER].cr.read();
554+
if cr.dbm().bit_is_set() {
555+
Some(if cr.ct().bit_is_set() {
556+
CurrentBuffer::Buffer0
557+
} else {
558+
CurrentBuffer::Buffer1
559+
})
551560
} else {
552-
CurrentBuffer::FirstBuffer
561+
None
553562
}
554563
}
555564
}

‎src/dma/dma.rs

Lines changed: 33 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -521,38 +521,31 @@ macro_rules! dma_stream {
521521

522522
impl<I: Instance> DoubleBufferedStream for $name<I> {
523523
#[inline(always)]
524-
unsafe fn set_peripheral_address(&mut self, value: u32) {
524+
unsafe fn set_peripheral_address(&mut self, value: usize) {
525525
//NOTE(unsafe) We only access the registers that belongs to the StreamX
526526
let dma = &*I::ptr();
527-
dma.st[Self::NUMBER].par.write(|w| w.pa().bits(value));
527+
dma.st[Self::NUMBER].par.write(|w| w.pa().bits(value as u32));
528528
}
529529

530530
#[inline(always)]
531-
unsafe fn set_memory_address(&mut self, value: u32) {
531+
unsafe fn set_memory_address(&mut self, buffer: CurrentBuffer, value: usize) {
532532
//NOTE(unsafe) We only access the registers that belongs to the StreamX
533533
let dma = &*I::ptr();
534-
dma.st[Self::NUMBER].m0ar.write(|w| w.m0a().bits(value));
535-
}
536-
537-
#[inline(always)]
538-
fn get_memory_address(&self) -> u32 {
539-
//NOTE(unsafe) We only access the registers that belongs to the StreamX
540-
let dma = unsafe { &*I::ptr() };
541-
dma.st[Self::NUMBER].m0ar.read().m0a().bits()
542-
}
543-
544-
#[inline(always)]
545-
unsafe fn set_memory_double_buffer_address(&mut self, value: u32) {
546-
//NOTE(unsafe) We only access the registers that belongs to the StreamX
547-
let dma = &*I::ptr();
548-
dma.st[Self::NUMBER].m1ar.write(|w| w.m1a().bits(value));
534+
match buffer {
535+
CurrentBuffer::Buffer0 => dma.st[Self::NUMBER].m0ar.write(|w| w.m0a().bits(value as u32)),
536+
CurrentBuffer::Buffer1 => dma.st[Self::NUMBER].m1ar.write(|w| w.m1a().bits(value as u32)),
537+
}
549538
}
550539

551540
#[inline(always)]
552-
fn get_memory_double_buffer_address(&self) -> u32 {
541+
fn get_memory_address(&self, buffer: CurrentBuffer) -> usize {
553542
//NOTE(unsafe) We only access the registers that belongs to the StreamX
554543
let dma = unsafe { &*I::ptr() };
555-
dma.st[Self::NUMBER].m1ar.read().m1a().bits()
544+
let addr = match buffer {
545+
CurrentBuffer::Buffer0 => dma.st[Self::NUMBER].m0ar.read().m0a().bits(),
546+
CurrentBuffer::Buffer1 => dma.st[Self::NUMBER].m1ar.read().m1a().bits(),
547+
};
548+
addr as usize
556549
}
557550

558551
#[inline(always)]
@@ -631,13 +624,30 @@ macro_rules! dma_stream {
631624
dma.st[Self::NUMBER].cr.modify(|_, w| w.dbm().bit(double_buffer));
632625
}
633626

634-
fn current_buffer() -> CurrentBuffer {
627+
#[inline(always)]
628+
fn get_current_buffer() -> CurrentBuffer {
635629
//NOTE(unsafe) Atomic read with no side effects
636630
let dma = unsafe { &*I::ptr() };
637631
if dma.st[Self::NUMBER].cr.read().ct().bit_is_set() {
638-
CurrentBuffer::DoubleBuffer
632+
CurrentBuffer::Buffer0
633+
} else {
634+
CurrentBuffer::Buffer1
635+
}
636+
}
637+
638+
#[inline(always)]
639+
fn get_inactive_buffer() -> Option<CurrentBuffer> {
640+
//NOTE(unsafe) Atomic read with no side effects
641+
let dma = unsafe { &*I::ptr() };
642+
let cr = dma.st[Self::NUMBER].cr.read();
643+
if cr.dbm().bit_is_set() {
644+
Some(if cr.ct().bit_is_set() {
645+
CurrentBuffer::Buffer0
646+
} else {
647+
CurrentBuffer::Buffer1
648+
})
639649
} else {
640-
CurrentBuffer::FirstBuffer
650+
None
641651
}
642652
}
643653
}

‎src/dma/macros.rs

Lines changed: 14 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -15,8 +15,8 @@ macro_rules! peripheral_target_instance {
1515
$dir:ty $(, $mux:expr)*)) => {
1616
unsafe impl TargetAddress<$dir> for $peripheral {
1717
#[inline(always)]
18-
fn address(&self) -> u32 {
19-
&self.$register as *const _ as u32
18+
fn address(&self) -> usize {
19+
&self.$register as *const _ as usize
2020
}
2121

2222
type MemSize = $size;
@@ -33,8 +33,8 @@ macro_rules! peripheral_target_instance {
3333
// Access via PAC peripheral structures implies u8 sizing, as the sizing is unknown.
3434
unsafe impl TargetAddress<M2P> for $peripheral {
3535
#[inline(always)]
36-
fn address(&self) -> u32 {
37-
&self.$txreg as *const _ as u32
36+
fn address(&self) -> usize {
37+
&self.$txreg as *const _ as usize
3838
}
3939

4040
type MemSize = u8;
@@ -44,8 +44,8 @@ macro_rules! peripheral_target_instance {
4444

4545
unsafe impl TargetAddress<P2M> for $peripheral {
4646
#[inline(always)]
47-
fn address(&self) -> u32 {
48-
&self.$rxreg as *const _ as u32
47+
fn address(&self) -> usize {
48+
&self.$rxreg as *const _ as usize
4949
}
5050

5151
type MemSize = u8;
@@ -57,8 +57,8 @@ macro_rules! peripheral_target_instance {
5757
$(
5858
unsafe impl TargetAddress<M2P> for spi::Spi<$peripheral, spi::Disabled, $size> {
5959
#[inline(always)]
60-
fn address(&self) -> u32 {
61-
&self.inner().$txreg as *const _ as u32
60+
fn address(&self) -> usize {
61+
&self.inner().$txreg as *const _ as usize
6262
}
6363

6464
type MemSize = $size;
@@ -68,8 +68,8 @@ macro_rules! peripheral_target_instance {
6868

6969
unsafe impl TargetAddress<P2M> for spi::Spi<$peripheral, spi::Disabled, $size> {
7070
#[inline(always)]
71-
fn address(&self) -> u32 {
72-
&self.inner().$rxreg as *const _ as u32
71+
fn address(&self) -> usize {
72+
&self.inner().$rxreg as *const _ as usize
7373
}
7474

7575
type MemSize = $size;
@@ -83,8 +83,8 @@ macro_rules! peripheral_target_instance {
8383
$dir:ty $(, $mux:expr)*)) => {
8484
unsafe impl TargetAddress<$dir> for $peripheral {
8585
#[inline(always)]
86-
fn address(&self) -> u32 {
87-
&self.inner().$register as *const _ as u32
86+
fn address(&self) -> usize {
87+
&self.inner().$register as *const _ as usize
8888
}
8989

9090
type MemSize = $size;
@@ -101,8 +101,8 @@ macro_rules! peripheral_target_instance {
101101
$dir:ty $(, $mux:expr)*)) => {
102102
unsafe impl TargetAddress<$dir> for $peripheral {
103103
#[inline(always)]
104-
fn address(&self) -> u32 {
105-
&self.$channel.$register as *const _ as u32
104+
fn address(&self) -> usize {
105+
&self.$channel.$register as *const _ as usize
106106
}
107107

108108
type MemSize = $size;

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