Merge #121

121: Ethernet merge r=richardeoin a=hargoniX

This PR adds stm32h7-ethernet into the HAL behind the ethernet feature flag, trying to introduce as little diff as possible in the process of doing so.

Closes: #102 

Co-authored-by: Henrik Böving <[email protected]>
Co-authored-by: Richard Meadows <[email protected]>

Author: 3 people

Cargo.toml

@@ -36,6 +36,12 @@ sdio-host = { version = "0.4", optional = true }
 version = "0.2.5"
 features = ["const-fn"]
 
+[dependencies.smoltcp]
+version = "0.6.0"
+default-features = false
+features = ["ethernet", "proto-ipv4", "proto-dhcpv4", "socket-tcp", "socket-raw"]
+optional = true
+
 [dev-dependencies]
 cortex-m-rtic = "0.5.3"
 log = "0.4.11"
@@ -49,6 +55,11 @@ panic-itm = { version = "~0.4.1" }
 panic-semihosting = { version = "0.5.3" }
 cortex-m-semihosting = { version = "0.3.5" }
 
+[dev-dependencies.smoltcp]
+version = "0.6.0"
+default-features = false
+features = ["ethernet", "proto-ipv4", "proto-ipv6", "socket-raw"]
+
 [features]
 default = ["unproven"]
 unproven = ["embedded-hal/unproven"]
@@ -61,6 +72,9 @@ cm4 = []
 cm7 = []
 quadspi = []
 sdmmc = ["sdio-host"]
+ethernet = ["smoltcp"]
+phy_ksz8081r = []
+phy_lan8742a = []
 rt = ["stm32h7/rt"]
 stm32h742 = ["stm32h7/stm32h743", "device-selected", "singlecore"]
 stm32h743 = ["stm32h7/stm32h743", "device-selected", "singlecore"]
@@ -75,7 +89,6 @@ log-itm = []
 log-rtt = []
 log-semihost  = []
 
-
 [profile.dev]
 codegen-units = 1 # better optimizations
 debug = true # symbols are nice and they don't increase the size in flash
@@ -106,3 +119,15 @@ required-features = ["quadspi"]
 [[example]]
 name = "sdmmc"
 required-features = ["sdmmc"]
+
+[[example]]
+name = "ethernet-stm32h747i-disco"
+required-features = ["phy_lan8742a", "rt", "stm32h747cm7", "ethernet"]
+
+[[example]]
+name = "ethernet-rtic-stm32h747i-disco"
+required-features = ["phy_lan8742a", "rt", "stm32h747cm7", "ethernet"]
+
+[[example]]
+name = "ethernet-nucleo-h743zi2"
+required-features = ["phy_lan8742a", "rt", "revision_v", "stm32h743v", "ethernet"]

README.md

@@ -114,7 +114,6 @@ other core functionality. An incomplete list of additional peripheral
 support crates is given here:
 
 - [stm32h7-fmc](https://crates.io/crates/stm32h7-fmc)
-- [stm32h7-ethernet](https://crates.io/crates/stm32h7-ethernet)
 - _[Search crates.io...](https://crates.io/search?q=stm32h7)_
 
 Changelog

examples/ethernet-nucleo-h743zi2.rs

@@ -0,0 +1,174 @@
+#![no_main]
+#![no_std]
+
+extern crate cortex_m_rt as rt;
+use core::sync::atomic::{AtomicU32, Ordering};
+use rt::{entry, exception};
+
+extern crate cortex_m;
+
+#[path = "utilities/logger.rs"]
+mod logger;
+use log::info;
+
+use stm32h7xx_hal::ethernet;
+use stm32h7xx_hal::gpio::Speed;
+use stm32h7xx_hal::hal::digital::v2::OutputPin;
+use stm32h7xx_hal::rcc::CoreClocks;
+use stm32h7xx_hal::{prelude::*, stm32, stm32::interrupt};
+use Speed::*;
+
+/// Configure SYSTICK for 1ms timebase
+fn systick_init(syst: &mut stm32::SYST, clocks: CoreClocks) {
+    let c_ck_mhz = clocks.c_ck().0 / 1_000_000;
+
+    let syst_calib = 0x3E8;
+
+    syst.set_clock_source(cortex_m::peripheral::syst::SystClkSource::Core);
+    syst.set_reload((syst_calib * c_ck_mhz) - 1);
+    syst.enable_interrupt();
+    syst.enable_counter();
+}
+
+/// ======================================================================
+/// Entry point
+/// ======================================================================
+
+/// TIME is an atomic u32 that counts milliseconds. Although not used
+/// here, it is very useful to have for network protocols
+static TIME: AtomicU32 = AtomicU32::new(0);
+
+/// Locally administered MAC address
+const MAC_ADDRESS: [u8; 6] = [0x02, 0x00, 0x11, 0x22, 0x33, 0x44];
+
+/// Ethernet descriptor rings are a global singleton
+#[link_section = ".sram3.eth"]
+static mut DES_RING: ethernet::DesRing = ethernet::DesRing::new();
+
+// the program entry point
+#[entry]
+fn main() -> ! {
+    logger::init();
+    let dp = stm32::Peripherals::take().unwrap();
+    let mut cp = stm32::CorePeripherals::take().unwrap();
+
+    // Initialise power...
+    info!("Setup PWR...                  ");
+    let pwr = dp.PWR.constrain();
+    let vos = pwr.freeze();
+
+    // Initialise SRAM3
+    info!("Setup RCC...                  ");
+    dp.RCC.ahb2enr.modify(|_, w| w.sram3en().set_bit());
+
+    // Initialise clocks...
+    let rcc = dp.RCC.constrain();
+    let ccdr = rcc
+        .sys_ck(200.mhz())
+        .hclk(200.mhz())
+        .pll1_r_ck(100.mhz()) // for TRACECK
+        .freeze(vos, &dp.SYSCFG);
+
+    // Get the delay provider.
+    let delay = cp.SYST.delay(ccdr.clocks);
+
+    // Initialise system...
+    cp.SCB.invalidate_icache();
+    cp.SCB.enable_icache();
+    // TODO: ETH DMA coherence issues
+    // cp.SCB.enable_dcache(&mut cp.CPUID);
+    cp.DWT.enable_cycle_counter();
+
+    // Initialise IO...
+    let gpioa = dp.GPIOA.split(ccdr.peripheral.GPIOA);
+    let gpiob = dp.GPIOB.split(ccdr.peripheral.GPIOB);
+    let gpioc = dp.GPIOC.split(ccdr.peripheral.GPIOC);
+    let gpiog = dp.GPIOG.split(ccdr.peripheral.GPIOG);
+    let mut link_led = gpiob.pb0.into_push_pull_output(); // LED1, green
+    link_led.set_high().ok();
+
+    let _rmii_ref_clk = gpioa.pa1.into_alternate_af11().set_speed(VeryHigh);
+    let _rmii_mdio = gpioa.pa2.into_alternate_af11().set_speed(VeryHigh);
+    let _rmii_mdc = gpioc.pc1.into_alternate_af11().set_speed(VeryHigh);
+    let _rmii_crs_dv = gpioa.pa7.into_alternate_af11().set_speed(VeryHigh);
+    let _rmii_rxd0 = gpioc.pc4.into_alternate_af11().set_speed(VeryHigh);
+    let _rmii_rxd1 = gpioc.pc5.into_alternate_af11().set_speed(VeryHigh);
+    let _rmii_tx_en = gpiog.pg11.into_alternate_af11().set_speed(VeryHigh);
+    let _rmii_txd0 = gpiog.pg13.into_alternate_af11().set_speed(VeryHigh);
+    let _rmii_txd1 = gpiob.pb13.into_alternate_af11().set_speed(VeryHigh);
+
+    // Initialise ethernet...
+    assert_eq!(ccdr.clocks.hclk().0, 200_000_000); // HCLK 200MHz
+    assert_eq!(ccdr.clocks.pclk1().0, 100_000_000); // PCLK 100MHz
+    assert_eq!(ccdr.clocks.pclk2().0, 100_000_000); // PCLK 100MHz
+    assert_eq!(ccdr.clocks.pclk4().0, 100_000_000); // PCLK 100MHz
+
+    let mac_addr = smoltcp::wire::EthernetAddress::from_bytes(&MAC_ADDRESS);
+    let (_eth_dma, mut eth_mac) = unsafe {
+        ethernet::new_unchecked(
+            dp.ETHERNET_MAC,
+            dp.ETHERNET_MTL,
+            dp.ETHERNET_DMA,
+            &mut DES_RING,
+            mac_addr.clone(),
+        )
+    };
+    unsafe {
+        ethernet::enable_interrupt();
+        cp.NVIC.set_priority(stm32::Interrupt::ETH, 196); // Mid prio
+        cortex_m::peripheral::NVIC::unmask(stm32::Interrupt::ETH);
+    }
+
+    // ----------------------------------------------------------
+    // Begin periodic tasks
+
+    systick_init(&mut delay.free(), ccdr.clocks);
+    unsafe {
+        cp.SCB.shpr[15 - 4].write(128);
+    } // systick exception priority
+
+    // ----------------------------------------------------------
+    // Main application loop
+
+    let mut eth_up = false;
+    loop {
+        let _time = TIME.load(Ordering::Relaxed);
+
+        // Ethernet
+        let eth_last = eth_up;
+        eth_up = eth_mac.phy_poll_link();
+        match eth_up {
+            true => link_led.set_low(),
+            _ => link_led.set_high(),
+        }
+        .ok();
+
+        if eth_up != eth_last {
+            // Interface state change
+            match eth_up {
+                true => info!("Ethernet UP"),
+                _ => info!("Ethernet DOWN"),
+            }
+        }
+    }
+}
+
+#[interrupt]
+fn ETH() {
+    unsafe { ethernet::interrupt_handler() }
+}
+
+#[exception]
+fn SysTick() {
+    TIME.fetch_add(1, Ordering::Relaxed);
+}
+
+#[exception]
+fn HardFault(ef: &cortex_m_rt::ExceptionFrame) -> ! {
+    panic!("HardFault at {:#?}", ef);
+}
+
+#[exception]
+fn DefaultHandler(irqn: i16) {
+    panic!("Unhandled exception (IRQn = {})", irqn);
+}