Merge pull request #167 from quartiq/feature/dma-rtic-example

richardeoin · web-flow · commit 0bfeeca4ce12 · 2020-11-11T20:53:55.000+01:00
[DMA] Adding DMA+SPI+RTIC example
diff --git a/Cargo.toml b/Cargo.toml
@@ -185,4 +185,8 @@ required-features = ["rm0433"]
 
 [[example]]
 name = "spi_dma"
-required-features = ["rm0433"]
+required-features = ["rm0433"]
+
+[[example]]
+name = "spi-dma-rtic"
+required-features = ["rm0433","rt"]
diff --git a/examples/digital_read.rs b/examples/digital_read.rs
@@ -0,0 +1,41 @@
+#![deny(warnings)]
+#![no_main]
+#![no_std]
+
+use stm32h7xx_hal::hal::digital::v2::InputPin;
+
+use cortex_m_rt::entry;
+use stm32h7xx_hal::{pac, prelude::*};
+
+#[macro_use]
+mod utilities;
+
+use log::info;
+
+#[entry]
+fn main() -> ! {
+    utilities::logger::init();
+    info!("stm32h7xx-hal example - digitalRead");
+
+    let _cp = cortex_m::Peripherals::take().unwrap();
+    let dp = pac::Peripherals::take().unwrap();
+
+    info!("Setup PWR...                  ");
+    let pwr = dp.PWR.constrain();
+    let pwrcfg = example_power!(pwr).freeze();
+
+    info!("Setup RCC...                  ");
+    let rcc = dp.RCC.constrain();
+    let ccdr = rcc.sys_ck(100.mhz()).freeze(pwrcfg, &dp.SYSCFG);
+
+    // Push button configuration
+    let gpioc = dp.GPIOC.split(ccdr.peripheral.GPIOC);
+
+    let button1 = gpioc.pc5.into_pull_up_input();
+
+    loop {
+        let result = button1.is_high().unwrap();
+        info!("{}", result);
+        cortex_m::asm::delay(10000000);
+    }
+}
diff --git a/examples/exti_interrupt.rs b/examples/exti_interrupt.rs
@@ -0,0 +1,129 @@
+#![deny(warnings)]
+#![no_main]
+#![no_std]
+
+use core::cell::{Cell, RefCell};
+use cortex_m::interrupt::{free, Mutex};
+use cortex_m::peripheral::NVIC;
+use cortex_m_rt::entry;
+use stm32h7xx_hal::gpio::{Edge, ExtiPin, Input, Output, PullUp, PushPull};
+use stm32h7xx_hal::hal::digital::v2::OutputPin;
+use stm32h7xx_hal::{interrupt, pac, prelude::*};
+
+// LED pin
+use stm32h7xx_hal::gpio::gpioa::PA1;
+
+// Button pins
+use stm32h7xx_hal::gpio::gpioc::PC5;
+use stm32h7xx_hal::gpio::gpioe::PE3;
+
+#[macro_use]
+mod utilities;
+
+use log::info;
+
+// Semaphore for synchronization
+static SEMAPHORE: Mutex<Cell<bool>> = Mutex::new(Cell::new(true));
+
+// Setup the sharing of pins between the main loop and the interrupts
+static BUTTON1_PIN: Mutex<RefCell<Option<PE3<Input<PullUp>>>>> =
+    Mutex::new(RefCell::new(None));
+static BUTTON2_PIN: Mutex<RefCell<Option<PC5<Input<PullUp>>>>> =
+    Mutex::new(RefCell::new(None));
+static LED: Mutex<RefCell<Option<PA1<Output<PushPull>>>>> =
+    Mutex::new(RefCell::new(None));
+
+#[entry]
+fn main() -> ! {
+    utilities::logger::init();
+    info!("stm32h7xx-hal example - EXTI Interrupt");
+
+    let mut cp = cortex_m::Peripherals::take().unwrap();
+    let dp = pac::Peripherals::take().unwrap();
+
+    info!("Setup PWR...");
+    let pwr = dp.PWR.constrain();
+    let pwrcfg = example_power!(pwr).freeze();
+
+    info!("Setup RCC...");
+    let rcc = dp.RCC.constrain();
+    let ccdr = rcc.sys_ck(100.mhz()).freeze(pwrcfg, &dp.SYSCFG);
+
+    // Push button configuration
+    let mut syscfg = dp.SYSCFG;
+    let mut exti = dp.EXTI;
+
+    let gpioe = dp.GPIOE.split(ccdr.peripheral.GPIOE);
+    let mut button1 = gpioe.pe3.into_pull_up_input();
+    button1.make_interrupt_source(&mut syscfg);
+    button1.trigger_on_edge(&mut exti, Edge::RISING);
+    button1.enable_interrupt(&mut exti);
+
+    let gpioc = dp.GPIOC.split(ccdr.peripheral.GPIOC);
+    let mut button2 = gpioc.pc5.into_pull_up_input();
+    button2.make_interrupt_source(&mut syscfg);
+    button2.trigger_on_edge(&mut exti, Edge::RISING);
+    button2.enable_interrupt(&mut exti);
+
+    let gpioa = dp.GPIOA.split(ccdr.peripheral.GPIOA);
+    let led = gpioa.pa1.into_push_pull_output();
+
+    // Save information needed by the interrupt handlers to the global variable
+    free(|cs| {
+        BUTTON1_PIN.borrow(cs).replace(Some(button1));
+        BUTTON2_PIN.borrow(cs).replace(Some(button2));
+        LED.borrow(cs).replace(Some(led));
+    });
+
+    // Enable the button interrupts
+    unsafe {
+        cp.NVIC.set_priority(interrupt::EXTI3, 1);
+        cp.NVIC.set_priority(interrupt::EXTI9_5, 1);
+        NVIC::unmask::<interrupt>(interrupt::EXTI3);
+        NVIC::unmask::<interrupt>(interrupt::EXTI9_5);
+    }
+
+    loop {
+        cortex_m::asm::nop();
+    }
+}
+
+fn toggle_led(on_or_off: bool) {
+    free(|cs| {
+        if let Some(b) = LED.borrow(cs).borrow_mut().as_mut() {
+            if on_or_off {
+                b.set_high().unwrap();
+            } else {
+                b.set_low().unwrap();
+            }
+        }
+    });
+}
+
+#[interrupt]
+fn EXTI9_5() {
+    info!("EXTI9_5 fired!");
+    toggle_led(true);
+    free(|cs| {
+        if let Some(b) = BUTTON2_PIN.borrow(cs).borrow_mut().as_mut() {
+            b.clear_interrupt_pending_bit()
+        }
+
+        // Signal that the interrupt fired
+        SEMAPHORE.borrow(cs).set(false);
+    });
+}
+
+#[interrupt]
+fn EXTI3() {
+    info!("EXTI3 fired!");
+    toggle_led(false);
+    free(|cs| {
+        if let Some(b) = BUTTON1_PIN.borrow(cs).borrow_mut().as_mut() {
+            b.clear_interrupt_pending_bit()
+        }
+
+        // Signal that the interrupt fired
+        SEMAPHORE.borrow(cs).set(false);
+    });
+}
diff --git a/examples/spi-dma-rtic.rs b/examples/spi-dma-rtic.rs
@@ -0,0 +1,169 @@
+//! Demo for STM32H747I-NUCLEO eval board using the Real Time Interrupt-driven Concurrency (RTIC)
+//! framework.
+//!
+//! This example demonstrates using DMA to write data over a TX-only SPI interface.
+#![deny(warnings)]
+#![no_main]
+#![no_std]
+
+use core::mem::MaybeUninit;
+
+use embedded_hal::digital::v2::OutputPin;
+use rtic::app;
+
+#[macro_use]
+#[allow(unused)]
+mod utilities;
+
+use hal::prelude::*;
+use stm32h7xx_hal as hal;
+
+// The number of bytes to transfer.
+const BUFFER_SIZE: usize = 100;
+
+// DMA1/DMA2 cannot interact with our stack. Instead, buffers for use with the
+// DMA must be placed somewhere that DMA1/DMA2 can access. In this case we use
+// AXI SRAM.
+//
+// The runtime does not initialise these SRAM banks
+#[link_section = ".axisram.buffers"]
+static mut BUFFER: MaybeUninit<[u8; BUFFER_SIZE]> = MaybeUninit::uninit();
+
+#[app(device = stm32h7xx_hal::stm32, peripherals = true)]
+const APP: () = {
+    struct Resources {
+        transfer: hal::dma::Transfer<
+            hal::dma::dma::Stream1<hal::stm32::DMA1>,
+            hal::spi::Spi<hal::stm32::SPI2, hal::spi::Disabled, u8>,
+            hal::dma::MemoryToPeripheral,
+            &'static mut [u8; BUFFER_SIZE],
+        >,
+        cs: hal::gpio::gpiob::PB12<hal::gpio::Output<hal::gpio::PushPull>>,
+    }
+
+    #[init]
+    fn init(ctx: init::Context) -> init::LateResources {
+        utilities::logger::init();
+
+        // Initialise power...
+        let pwr = ctx.device.PWR.constrain();
+        let pwrcfg = example_power!(pwr).freeze();
+
+        // Initialise clocks...
+        let rcc = ctx.device.RCC.constrain();
+        let ccdr = rcc
+            .sys_ck(200.mhz())
+            .hclk(200.mhz())
+            .pll1_q_ck(200.mhz())
+            .freeze(pwrcfg, &ctx.device.SYSCFG);
+
+        let gpiob = ctx.device.GPIOB.split(ccdr.peripheral.GPIOB);
+
+        // Initialize a SPI transmitter on SPI2.
+        let spi = {
+            let mosi = gpiob
+                .pb15
+                .into_alternate_af5()
+                .set_speed(hal::gpio::Speed::VeryHigh);
+            let sck = gpiob
+                .pb10
+                .into_alternate_af5()
+                .set_speed(hal::gpio::Speed::VeryHigh);
+            let config = hal::spi::Config::new(hal::spi::MODE_0)
+                .communication_mode(hal::spi::CommunicationMode::Transmitter);
+
+            let spi: hal::spi::Spi<_, _, u8> = ctx.device.SPI2.spi(
+                (sck, hal::spi::NoMiso, mosi),
+                config,
+                3.mhz(),
+                ccdr.peripheral.SPI2,
+                &ccdr.clocks,
+            );
+
+            spi.disable()
+        };
+
+        let mut cs = gpiob
+            .pb12
+            .into_push_pull_output()
+            .set_speed(hal::gpio::Speed::VeryHigh);
+        cs.set_high().unwrap();
+
+        // Initialize our transmit buffer.
+        let buffer: &'static mut [u8; BUFFER_SIZE] = {
+            let buf: &mut [MaybeUninit<u8>; BUFFER_SIZE] = unsafe {
+                &mut *(&mut BUFFER as *mut MaybeUninit<[u8; BUFFER_SIZE]>
+                    as *mut [MaybeUninit<u8>; BUFFER_SIZE])
+            };
+
+            for (i, value) in buf.iter_mut().enumerate() {
+                unsafe {
+                    value.as_mut_ptr().write(i as u8 + 0x60); // 0x60, 0x61, 0x62...
+                }
+            }
+
+            unsafe {
+                &mut *(buf as *mut [MaybeUninit<u8>; BUFFER_SIZE]
+                    as *mut [u8; BUFFER_SIZE])
+            }
+        };
+
+        let streams = hal::dma::dma::StreamsTuple::new(
+            ctx.device.DMA1,
+            ccdr.peripheral.DMA1,
+        );
+
+        // Configure the DMA stream to increment the memory address and generate a transfer complete
+        // interrupt so we know when transmission is done.
+        let config = hal::dma::dma::DmaConfig::default()
+            .memory_increment(true)
+            .transfer_complete_interrupt(true);
+
+        let transfer: hal::dma::Transfer<
+            _,
+            _,
+            hal::dma::MemoryToPeripheral,
+            _,
+        > = hal::dma::Transfer::init(streams.1, spi, buffer, None, config);
+
+        init::LateResources { transfer, cs }
+    }
+
+    #[task(binds=DMA1_STR1, resources=[transfer, cs], priority=2)]
+    fn dma_complete(mut ctx: dma_complete::Context) {
+        // If desired, the transfer can scheduled again here to continue transmitting.
+        let cs = &mut ctx.resources.cs;
+        ctx.resources.transfer.clear_transfer_complete_interrupt();
+        ctx.resources.transfer.pause(|spi| {
+            // At this point, the DMA transfer is done, but the data is still in the SPI output
+            // FIFO. Wait for it to complete before disabling CS.
+            while spi.inner().sr.read().txc().bit_is_clear() {}
+            cs.set_high().unwrap();
+        });
+    }
+
+    #[idle(resources=[transfer, cs])]
+    fn idle(mut ctx: idle::Context) -> ! {
+        // Start the DMA transfer over SPI.
+        let mut cs = ctx.resources.cs;
+        ctx.resources.transfer.lock(|transfer| {
+            cs.lock(|cs| {
+                transfer.start(|spi| {
+                    // Set CS low for the transfer.
+                    cs.set_low().unwrap();
+
+                    // Enable TX DMA support, enable the SPI peripheral, and start the transaction.
+                    spi.enable_dma_tx();
+                    spi.inner_mut().cr1.modify(|_, w| w.spe().enabled());
+                    spi.inner_mut().cr1.modify(|_, w| w.cstart().started());
+
+                    // The transaction immediately begins as the TX FIFO is now being filled by DMA.
+                });
+            });
+        });
+
+        loop {
+            cortex_m::asm::nop();
+        }
+    }
+};
diff --git a/src/qspi.rs b/src/qspi.rs
@@ -341,9 +341,17 @@ impl Qspi {
             _ => panic!("Invalid QSPI frequency requested"),
         };
 
-        // Write the prescaler
-        regs.cr
-            .write(|w| unsafe { w.prescaler().bits(divisor as u8) });
+        // Write the prescaler and the SSHIFT bit. Note that SSHIFT is required because it appears
+        // that the QSPI may have signal contention issues when reading. SSHIFT forces the read to
+        // occur on the falling edge instead of the rising edge. Refer to
+        // https://github.com/quartiq/stabilizer/issues/101 for more information
+        //
+        // This is also noted in the docstring for the read() method.
+        //
+        // SSHIFT must not be set in DDR mode.
+        regs.cr.write(|w| unsafe {
+            w.prescaler().bits(divisor as u8).sshift().set_bit()
+        });
 
         match bank {
             Bank::One => regs.cr.modify(|_, w| w.fsel().clear_bit()),
@@ -447,10 +455,17 @@ impl Qspi {
     /// Read data over the QSPI interface.
     ///
     /// # Note
-    /// There is an issue where the QSPI peripheral will erroneously drive the output pins for an
-    /// extra half clock cycle before IO is swapped from output to input. Refer to
+    ///
+    /// Without any dummy cycles, the QSPI peripheral will erroneously drive the
+    /// output pins for an extra half clock cycle before IO is swapped from
+    /// output to input. Refer to
     /// https://github.com/quartiq/stabilizer/issues/101 for more information.
     ///
+    /// Although it doesn't stop the possible bus contention, this HAL sets the
+    /// SSHIFT bit in the CR register. With this bit set, the QSPI receiver
+    /// sampling point is delayed by an extra half cycle. Then the receiver
+    /// sampling point is after the bus contention.
+    ///
     /// # Args
     /// * `addr` - The address to read data from.
     /// * `dest` - An array to store the result of the read into.
diff --git a/src/spi.rs b/src/spi.rs
