@@ -354,34 +354,73 @@ ap3_err_t ap3_change_channel(uint8_t padNumber)
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}
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+ bool ap3_pwm_is_running (uint32_t ui32TimerNumber, uint32_t ui32TimerSegment){
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+ volatile uint32_t *pui32ConfigReg;
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+ bool is_enabled = false ;
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+
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+ //
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+ // Find the correct control register.
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+ //
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+ pui32ConfigReg = (uint32_t *)CTIMERADDRn (CTIMER, ui32TimerNumber, CTRL0);
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+
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+ //
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+ // Begin critical section while config registers are read and modified.
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+ //
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+ AM_CRITICAL_BEGIN
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+
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+ //
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+ // Read the current value.
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+ //
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+ uint32_t ui32ConfigVal = *pui32ConfigReg;
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+
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+ //
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+ // Check the "enable bit"
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+ //
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+ if ( ui32ConfigVal & (CTIMER_CTRL0_TMRA0EN_Msk | CTIMER_CTRL0_TMRB0EN_Msk) ){
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+ is_enabled = true ;
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+ }
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+
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+ //
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+ // Done with critical section.
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+ //
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+ AM_CRITICAL_END
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+
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+ return is_enabled;
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+ }
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+
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+
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void ap3_pwm_wait_for_pulse (uint32_t timer, uint32_t segment, uint32_t output, uint32_t margin){
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volatile uint32_t *pui32CompareReg;
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volatile uint32_t ctimer_val;
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uint32_t cmpr0;
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- // Get the comapre register address
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- if ( segment == AM_HAL_CTIMER_TIMERA ){
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- if ( output == AM_HAL_CTIMER_OUTPUT_NORMAL ){
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- pui32CompareReg = ( uint32_t *) CTIMERADDRn (CTIMER, timer, CMPRA0);
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- } else {
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- pui32CompareReg = ( uint32_t *) CTIMERADDRn (CTIMER, timer, CMPRAUXA0);
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- }
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- }else {
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- if ( output == AM_HAL_CTIMER_OUTPUT_NORMAL ){
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- pui32CompareReg = ( uint32_t *) CTIMERADDRn (CTIMER, timer, CMPRB0);
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+ // Only wait if the ctimer is running to avoid a deadlock
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+ if ( ap3_pwm_is_running ( timer, segment) ){
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+
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+ // Get the comapre register address
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+ if ( segment == AM_HAL_CTIMER_TIMERA ) {
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+ if ( output == AM_HAL_CTIMER_OUTPUT_NORMAL ){
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+ pui32CompareReg = ( uint32_t *) CTIMERADDRn (CTIMER, timer, CMPRA0);
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+ }else {
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+ pui32CompareReg = ( uint32_t *) CTIMERADDRn (CTIMER, timer, CMPRAUXA0);
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+ }
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}else {
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- pui32CompareReg = (uint32_t *)CTIMERADDRn (CTIMER, timer, CMPRAUXB0);
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+ if ( output == AM_HAL_CTIMER_OUTPUT_NORMAL ){
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+ pui32CompareReg = (uint32_t *)CTIMERADDRn (CTIMER, timer, CMPRB0);
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+ }else {
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+ pui32CompareReg = (uint32_t *)CTIMERADDRn (CTIMER, timer, CMPRAUXB0);
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+ }
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}
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- }
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- // Get the compare value
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- cmpr0 = ((uint32_t )(*(pui32CompareReg)) & 0x0000FFFF );
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-
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- // Wait for the timer value to be less than the compare value so that it is safe to change
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- ctimer_val = am_hal_ctimer_read ( timer, segment);
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- while ( (ctimer_val + 0 ) > cmpr0 ){
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+ // Get the compare value
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+ cmpr0 = ((uint32_t )(*(pui32CompareReg)) & 0x0000FFFF );
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+
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+ // Wait for the timer value to be less than the compare value so that it is safe to change
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ctimer_val = am_hal_ctimer_read ( timer, segment);
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+ while ( (ctimer_val + 0 ) > cmpr0 ){
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+ ctimer_val = am_hal_ctimer_read ( timer, segment);
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+ }
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}
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}
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@@ -494,6 +533,9 @@ ap3_err_t ap3_pwm_output(uint8_t pin, uint32_t th, uint32_t fw, uint32_t clk)
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output = AM_HAL_CTIMER_OUTPUT_FORCE1;
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}
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+ // Wait until after high pulse to change the state (avoids inversion)
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+ ap3_pwm_wait_for_pulse ( timer, segment, output, 10 );
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+
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// Configure the pin
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am_hal_ctimer_output_config (timer,
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segment,
@@ -507,9 +549,6 @@ ap3_err_t ap3_pwm_output(uint8_t pin, uint32_t th, uint32_t fw, uint32_t clk)
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// (AM_HAL_CTIMER_FN_PWM_REPEAT | AP3_ANALOG_CLK | AM_HAL_CTIMER_INT_ENABLE) );
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(AM_HAL_CTIMER_FN_PWM_REPEAT | clk));
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- // Wait until after high pulse to change the state (avoids inversion)
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- ap3_pwm_wait_for_pulse ( timer, segment, output, 10 );
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-
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// If this pad uses secondary output:
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if (output == AM_HAL_CTIMER_OUTPUT_SECONDARY)
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{
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