diff --git a/crates/core_arch/src/x86/eflags.rs b/crates/core_arch/src/x86/eflags.rs index d73314c237..5ae656db38 100644 --- a/crates/core_arch/src/x86/eflags.rs +++ b/crates/core_arch/src/x86/eflags.rs @@ -73,7 +73,7 @@ mod tests { #[test] #[cfg_attr(miri, ignore)] // Uses inline assembly #[allow(deprecated)] - fn test_eflags() { + fn test_readeflags() { unsafe { // reads eflags, writes them back, reads them again, // and compare for equality: diff --git a/crates/core_arch/src/x86/f16c.rs b/crates/core_arch/src/x86/f16c.rs index d7182390dd..9feb0f44f9 100644 --- a/crates/core_arch/src/x86/f16c.rs +++ b/crates/core_arch/src/x86/f16c.rs @@ -98,23 +98,48 @@ mod tests { use crate::{core_arch::x86::*, mem::transmute}; use stdarch_test::simd_test; + const F16_ONE: i16 = 0x3c00; + const F16_TWO: i16 = 0x4000; + const F16_THREE: i16 = 0x4200; + const F16_FOUR: i16 = 0x4400; + const F16_FIVE: i16 = 0x4500; + const F16_SIX: i16 = 0x4600; + const F16_SEVEN: i16 = 0x4700; + const F16_EIGHT: i16 = 0x4800; + #[simd_test(enable = "f16c")] unsafe fn test_mm_cvtph_ps() { - let array = [1_f32, 2_f32, 3_f32, 4_f32]; - let float_vec: __m128 = transmute(array); - let halfs: __m128i = _mm_cvtps_ph::<0>(float_vec); - let floats: __m128 = _mm_cvtph_ps(halfs); - let result: [f32; 4] = transmute(floats); - assert_eq!(result, array); + let a = _mm_set_epi16(0, 0, 0, 0, F16_ONE, F16_TWO, F16_THREE, F16_FOUR); + let r = _mm_cvtph_ps(a); + let e = _mm_set_ps(1.0, 2.0, 3.0, 4.0); + assert_eq_m128(r, e); } #[simd_test(enable = "f16c")] unsafe fn test_mm256_cvtph_ps() { - let array = [1_f32, 2_f32, 3_f32, 4_f32, 5_f32, 6_f32, 7_f32, 8_f32]; - let float_vec: __m256 = transmute(array); - let halfs: __m128i = _mm256_cvtps_ph::<0>(float_vec); - let floats: __m256 = _mm256_cvtph_ps(halfs); - let result: [f32; 8] = transmute(floats); - assert_eq!(result, array); + let a = _mm_set_epi16( + F16_ONE, F16_TWO, F16_THREE, F16_FOUR, F16_FIVE, F16_SIX, F16_SEVEN, F16_EIGHT, + ); + let r = _mm256_cvtph_ps(a); + let e = _mm256_set_ps(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0); + assert_eq_m256(r, e); + } + + #[simd_test(enable = "f16c")] + unsafe fn test_mm_cvtps_ph() { + let a = _mm_set_ps(1.0, 2.0, 3.0, 4.0); + let r = _mm_cvtps_ph::<_MM_FROUND_CUR_DIRECTION>(a); + let e = _mm_set_epi16(0, 0, 0, 0, F16_ONE, F16_TWO, F16_THREE, F16_FOUR); + assert_eq_m128i(r, e); + } + + #[simd_test(enable = "f16c")] + unsafe fn test_mm256_cvtps_ph() { + let a = _mm256_set_ps(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0); + let r = _mm256_cvtps_ph::<_MM_FROUND_CUR_DIRECTION>(a); + let e = _mm_set_epi16( + F16_ONE, F16_TWO, F16_THREE, F16_FOUR, F16_FIVE, F16_SIX, F16_SEVEN, F16_EIGHT, + ); + assert_eq_m128i(r, e); } } diff --git a/crates/core_arch/src/x86/rdtsc.rs b/crates/core_arch/src/x86/rdtsc.rs index 36422f2fc8..c8f3c418ce 100644 --- a/crates/core_arch/src/x86/rdtsc.rs +++ b/crates/core_arch/src/x86/rdtsc.rs @@ -63,15 +63,15 @@ mod tests { use stdarch_test::simd_test; #[simd_test(enable = "sse2")] - unsafe fn _rdtsc() { - let r = rdtsc::_rdtsc(); + unsafe fn test_rdtsc() { + let r = _rdtsc(); assert_ne!(r, 0); // The chances of this being 0 are infinitesimal } #[simd_test(enable = "sse2")] - unsafe fn _rdtscp() { + unsafe fn test_rdtscp() { let mut aux = 0; - let r = rdtsc::__rdtscp(&mut aux); + let r = __rdtscp(&mut aux); assert_ne!(r, 0); // The chances of this being 0 are infinitesimal } } diff --git a/crates/core_arch/src/x86/rtm.rs b/crates/core_arch/src/x86/rtm.rs index 1f7539e97f..65a9f0e3cb 100644 --- a/crates/core_arch/src/x86/rtm.rs +++ b/crates/core_arch/src/x86/rtm.rs @@ -120,13 +120,13 @@ mod tests { use crate::core_arch::x86::*; #[simd_test(enable = "rtm")] - unsafe fn test_xbegin_xend() { + unsafe fn test_xbegin() { let mut x = 0; for _ in 0..10 { - let code = rtm::_xbegin(); + let code = _xbegin(); if code == _XBEGIN_STARTED { x += 1; - rtm::_xend(); + _xend(); assert_eq!(x, 1); break; } diff --git a/crates/core_arch/src/x86/sse.rs b/crates/core_arch/src/x86/sse.rs index 358d551bdc..ee03628cba 100644 --- a/crates/core_arch/src/x86/sse.rs +++ b/crates/core_arch/src/x86/sse.rs @@ -1738,7 +1738,7 @@ pub unsafe fn _MM_GET_ROUNDING_MODE() -> u32 { note = "see `_mm_setcsr` documentation - use inline assembly instead" )] pub unsafe fn _MM_SET_EXCEPTION_MASK(x: u32) { - _mm_setcsr((_mm_getcsr() & !_MM_MASK_MASK) | x) + _mm_setcsr((_mm_getcsr() & !_MM_MASK_MASK) | (x & _MM_MASK_MASK)) } /// See [`_mm_setcsr`](fn._mm_setcsr.html) @@ -1754,7 +1754,7 @@ pub unsafe fn _MM_SET_EXCEPTION_MASK(x: u32) { note = "see `_mm_setcsr` documentation - use inline assembly instead" )] pub unsafe fn _MM_SET_EXCEPTION_STATE(x: u32) { - _mm_setcsr((_mm_getcsr() & !_MM_EXCEPT_MASK) | x) + _mm_setcsr((_mm_getcsr() & !_MM_EXCEPT_MASK) | (x & _MM_EXCEPT_MASK)) } /// See [`_mm_setcsr`](fn._mm_setcsr.html) @@ -1770,9 +1770,7 @@ pub unsafe fn _MM_SET_EXCEPTION_STATE(x: u32) { note = "see `_mm_setcsr` documentation - use inline assembly instead" )] pub unsafe fn _MM_SET_FLUSH_ZERO_MODE(x: u32) { - let val = (_mm_getcsr() & !_MM_FLUSH_ZERO_MASK) | x; - // println!("setting csr={:x}", val); - _mm_setcsr(val) + _mm_setcsr((_mm_getcsr() & !_MM_FLUSH_ZERO_MASK) | (x & _MM_FLUSH_ZERO_MASK)) } /// See [`_mm_setcsr`](fn._mm_setcsr.html) @@ -1788,7 +1786,7 @@ pub unsafe fn _MM_SET_FLUSH_ZERO_MODE(x: u32) { note = "see `_mm_setcsr` documentation - use inline assembly instead" )] pub unsafe fn _MM_SET_ROUNDING_MODE(x: u32) { - _mm_setcsr((_mm_getcsr() & !_MM_ROUND_MASK) | x) + _mm_setcsr((_mm_getcsr() & !_MM_ROUND_MASK) | (x & _MM_ROUND_MASK)) } /// See [`_mm_prefetch`](fn._mm_prefetch.html). @@ -2901,57 +2899,6 @@ mod tests { } } - #[allow(deprecated)] // FIXME: This test uses deprecated CSR access functions - #[simd_test(enable = "sse")] - #[cfg_attr(miri, ignore)] // Uses _mm_setcsr, which is not supported by Miri - unsafe fn test_mm_comieq_ss_vs_ucomieq_ss() { - // If one of the arguments is a quiet NaN `comieq_ss` should signal an - // Invalid Operation Exception while `ucomieq_ss` should not. - let aa = &[3.0f32, NAN, 23.0, NAN]; - let bb = &[3.0f32, 47.5, NAN, NAN]; - - let ee = &[1i32, 0, 0, 0]; - let exc = &[0u32, 1, 1, 1]; // Should comieq_ss signal an exception? - - for i in 0..4 { - let a = _mm_setr_ps(aa[i], 1.0, 2.0, 3.0); - let b = _mm_setr_ps(bb[i], 0.0, 2.0, 4.0); - - _MM_SET_EXCEPTION_STATE(0); - let r1 = _mm_comieq_ss(*black_box(&a), b); - let s1 = _MM_GET_EXCEPTION_STATE(); - - _MM_SET_EXCEPTION_STATE(0); - let r2 = _mm_ucomieq_ss(*black_box(&a), b); - let s2 = _MM_GET_EXCEPTION_STATE(); - - assert_eq!( - ee[i], r1, - "_mm_comeq_ss({:?}, {:?}) = {}, expected: {} (i={})", - a, b, r1, ee[i], i - ); - assert_eq!( - ee[i], r2, - "_mm_ucomeq_ss({:?}, {:?}) = {}, expected: {} (i={})", - a, b, r2, ee[i], i - ); - assert_eq!( - s1, - exc[i] * _MM_EXCEPT_INVALID, - "_mm_comieq_ss() set exception flags: {} (i={})", - s1, - i - ); - assert_eq!( - s2, - 0, // ucomieq_ss should not signal an exception - "_mm_ucomieq_ss() set exception flags: {} (i={})", - s2, - i - ); - } - } - #[simd_test(enable = "sse")] unsafe fn test_mm_cvtss_si32() { let inputs = &[42.0f32, -3.1, 4.0e10, 4.0e-20, NAN, 2147483500.1]; @@ -3320,64 +3267,6 @@ mod tests { _mm_sfence(); } - #[allow(deprecated)] // FIXME: This tests functions that are immediate UB - #[simd_test(enable = "sse")] - #[cfg_attr(miri, ignore)] // Miri does not support accesing the CSR - unsafe fn test_mm_getcsr_setcsr_1() { - let saved_csr = _mm_getcsr(); - - let a = _mm_setr_ps(1.1e-36, 0.0, 0.0, 1.0); - let b = _mm_setr_ps(0.001, 0.0, 0.0, 1.0); - - _MM_SET_FLUSH_ZERO_MODE(_MM_FLUSH_ZERO_ON); - let r = _mm_mul_ps(*black_box(&a), *black_box(&b)); - - _mm_setcsr(saved_csr); - - let exp = _mm_setr_ps(0.0, 0.0, 0.0, 1.0); - assert_eq_m128(r, exp); // first component is a denormalized f32 - } - - #[allow(deprecated)] // FIXME: This tests functions that are immediate UB - #[simd_test(enable = "sse")] - #[cfg_attr(miri, ignore)] // Miri does not support accesing the CSR - unsafe fn test_mm_getcsr_setcsr_2() { - // Same as _mm_setcsr_1 test, but with opposite flag value. - - let saved_csr = _mm_getcsr(); - - let a = _mm_setr_ps(1.1e-36, 0.0, 0.0, 1.0); - let b = _mm_setr_ps(0.001, 0.0, 0.0, 1.0); - - _MM_SET_FLUSH_ZERO_MODE(_MM_FLUSH_ZERO_OFF); - let r = _mm_mul_ps(*black_box(&a), *black_box(&b)); - - _mm_setcsr(saved_csr); - - let exp = _mm_setr_ps(1.1e-39, 0.0, 0.0, 1.0); - assert_eq_m128(r, exp); // first component is a denormalized f32 - } - - #[allow(deprecated)] // FIXME: This tests functions that are immediate UB - #[simd_test(enable = "sse")] - #[cfg_attr(miri, ignore)] // Miri does not support accesing the CSR - unsafe fn test_mm_getcsr_setcsr_underflow() { - _MM_SET_EXCEPTION_STATE(0); - - let a = _mm_setr_ps(1.1e-36, 0.0, 0.0, 1.0); - let b = _mm_setr_ps(1e-5, 0.0, 0.0, 1.0); - - assert_eq!(_MM_GET_EXCEPTION_STATE(), 0); // just to be sure - - let r = _mm_mul_ps(*black_box(&a), *black_box(&b)); - - let exp = _mm_setr_ps(1.1e-41, 0.0, 0.0, 1.0); - assert_eq_m128(r, exp); - - let underflow = _MM_GET_EXCEPTION_STATE() & _MM_EXCEPT_UNDERFLOW != 0; - assert!(underflow); - } - #[simd_test(enable = "sse")] unsafe fn test_MM_TRANSPOSE4_PS() { let mut a = _mm_setr_ps(1.0, 2.0, 3.0, 4.0); diff --git a/crates/core_arch/src/x86/sse41.rs b/crates/core_arch/src/x86/sse41.rs index 5115f497bb..17d3e719ba 100644 --- a/crates/core_arch/src/x86/sse41.rs +++ b/crates/core_arch/src/x86/sse41.rs @@ -1310,7 +1310,7 @@ mod tests { } #[simd_test(enable = "sse4.1")] - unsafe fn test_mm_min_epi8_1() { + unsafe fn test_mm_min_epi8() { #[rustfmt::skip] let a = _mm_setr_epi8( 1, 4, 5, 8, 9, 12, 13, 16, @@ -1328,10 +1328,7 @@ mod tests { 17, 19, 21, 23, 25, 27, 29, 31, ); assert_eq_m128i(r, e); - } - #[simd_test(enable = "sse4.1")] - unsafe fn test_mm_min_epi8_2() { #[rustfmt::skip] let a = _mm_setr_epi8( 1, -4, -5, 8, -9, -12, 13, -16, @@ -1361,16 +1358,13 @@ mod tests { } #[simd_test(enable = "sse4.1")] - unsafe fn test_mm_min_epi32_1() { + unsafe fn test_mm_min_epi32() { let a = _mm_setr_epi32(1, 4, 5, 8); let b = _mm_setr_epi32(2, 3, 6, 7); let r = _mm_min_epi32(a, b); let e = _mm_setr_epi32(1, 3, 5, 7); assert_eq_m128i(r, e); - } - #[simd_test(enable = "sse4.1")] - unsafe fn test_mm_min_epi32_2() { let a = _mm_setr_epi32(-1, 4, 5, -7); let b = _mm_setr_epi32(-2, 3, -6, 8); let r = _mm_min_epi32(a, b); diff --git a/crates/core_arch/src/x86/xsave.rs b/crates/core_arch/src/x86/xsave.rs index bfbaba67e0..a05fd05b9f 100644 --- a/crates/core_arch/src/x86/xsave.rs +++ b/crates/core_arch/src/x86/xsave.rs @@ -185,10 +185,6 @@ mod tests { } } - // We cannot test for `_xsave`, `xrstor`, `_xsetbv`, `_xsaveopt`, `_xsaves`, `_xrstors` as they - // are privileged instructions and will need access to kernel mode to execute and test them. - // see https://github.com/rust-lang/stdarch/issues/209 - #[cfg_attr(stdarch_intel_sde, ignore)] #[simd_test(enable = "xsave")] #[cfg_attr(miri, ignore)] // Register saving/restoring is not supported in Miri diff --git a/crates/core_arch/src/x86_64/tbm.rs b/crates/core_arch/src/x86_64/tbm.rs index 7a9dc21f3c..119f637ebd 100644 --- a/crates/core_arch/src/x86_64/tbm.rs +++ b/crates/core_arch/src/x86_64/tbm.rs @@ -206,7 +206,7 @@ mod tests { } #[simd_test(enable = "tbm")] - unsafe fn test_t1mksc_u64() { + unsafe fn test_t1mskc_u64() { assert_eq!( _t1mskc_u64(0b0101_0111u64), 0b1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1000u64 diff --git a/crates/core_arch/src/x86_64/xsave.rs b/crates/core_arch/src/x86_64/xsave.rs index eebb5669f9..9177069100 100644 --- a/crates/core_arch/src/x86_64/xsave.rs +++ b/crates/core_arch/src/x86_64/xsave.rs @@ -149,10 +149,6 @@ mod tests { } } - // We cannot test `_xsave64`, `_xrstor64`, `_xsaveopt64`, `_xsaves64` and `_xrstors64` directly - // as they are privileged instructions and will need access to the kernel to run and test them. - // See https://github.com/rust-lang/stdarch/issues/209 - #[cfg_attr(stdarch_intel_sde, ignore)] #[simd_test(enable = "xsave")] #[cfg_attr(miri, ignore)] // Register saving/restoring is not supported in Miri diff --git a/crates/std_detect/tests/cpu-detection.rs b/crates/std_detect/tests/cpu-detection.rs index 69b7075bb1..2c9cd95d29 100644 --- a/crates/std_detect/tests/cpu-detection.rs +++ b/crates/std_detect/tests/cpu-detection.rs @@ -1,14 +1,13 @@ #![allow(internal_features)] #![feature(stdarch_internal)] #![cfg_attr(target_arch = "arm", feature(stdarch_arm_feature_detection))] -#![cfg_attr(target_arch = "aarch64", feature(stdarch_aarch64_feature_detection))] +#![cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + feature(stdarch_aarch64_feature_detection) +)] #![cfg_attr(target_arch = "powerpc", feature(stdarch_powerpc_feature_detection))] #![cfg_attr(target_arch = "powerpc64", feature(stdarch_powerpc_feature_detection))] #![cfg_attr(target_arch = "s390x", feature(stdarch_s390x_feature_detection))] -#![cfg_attr( - any(target_arch = "x86", target_arch = "x86_64"), - feature(sha512_sm_x86, x86_amx_intrinsics, xop_target_feature) -)] #![allow(clippy::unwrap_used, clippy::use_debug, clippy::print_stdout)] #[cfg_attr( @@ -16,8 +15,6 @@ target_arch = "arm", target_arch = "aarch64", target_arch = "arm64ec", - target_arch = "x86", - target_arch = "x86_64", target_arch = "powerpc", target_arch = "powerpc64", target_arch = "s390x", @@ -247,87 +244,3 @@ fn powerpc64_linux_or_freebsd() { fn s390x_linux() { println!("vector: {}", is_s390x_feature_detected!("vector")); } - -#[test] -#[cfg(any(target_arch = "x86", target_arch = "x86_64"))] -fn x86_all() { - println!("aes: {:?}", is_x86_feature_detected!("aes")); - println!("pcmulqdq: {:?}", is_x86_feature_detected!("pclmulqdq")); - println!("rdrand: {:?}", is_x86_feature_detected!("rdrand")); - println!("rdseed: {:?}", is_x86_feature_detected!("rdseed")); - println!("tsc: {:?}", is_x86_feature_detected!("tsc")); - println!("mmx: {:?}", is_x86_feature_detected!("mmx")); - println!("sse: {:?}", is_x86_feature_detected!("sse")); - println!("sse2: {:?}", is_x86_feature_detected!("sse2")); - println!("sse3: {:?}", is_x86_feature_detected!("sse3")); - println!("ssse3: {:?}", is_x86_feature_detected!("ssse3")); - println!("sse4.1: {:?}", is_x86_feature_detected!("sse4.1")); - println!("sse4.2: {:?}", is_x86_feature_detected!("sse4.2")); - println!("sse4a: {:?}", is_x86_feature_detected!("sse4a")); - println!("sha: {:?}", is_x86_feature_detected!("sha")); - println!("avx: {:?}", is_x86_feature_detected!("avx")); - println!("avx2: {:?}", is_x86_feature_detected!("avx2")); - println!("sha512: {:?}", is_x86_feature_detected!("sha512")); - println!("sm3: {:?}", is_x86_feature_detected!("sm3")); - println!("sm4: {:?}", is_x86_feature_detected!("sm4")); - println!("avx512f: {:?}", is_x86_feature_detected!("avx512f")); - println!("avx512cd: {:?}", is_x86_feature_detected!("avx512cd")); - println!("avx512er: {:?}", is_x86_feature_detected!("avx512er")); - println!("avx512pf: {:?}", is_x86_feature_detected!("avx512pf")); - println!("avx512bw: {:?}", is_x86_feature_detected!("avx512bw")); - println!("avx512dq: {:?}", is_x86_feature_detected!("avx512dq")); - println!("avx512vl: {:?}", is_x86_feature_detected!("avx512vl")); - println!("avx512ifma: {:?}", is_x86_feature_detected!("avx512ifma")); - println!("avx512vbmi: {:?}", is_x86_feature_detected!("avx512vbmi")); - println!( - "avx512vpopcntdq: {:?}", - is_x86_feature_detected!("avx512vpopcntdq") - ); - println!("avx512vbmi2 {:?}", is_x86_feature_detected!("avx512vbmi2")); - println!("gfni {:?}", is_x86_feature_detected!("gfni")); - println!("vaes {:?}", is_x86_feature_detected!("vaes")); - println!("vpclmulqdq {:?}", is_x86_feature_detected!("vpclmulqdq")); - println!("avx512vnni {:?}", is_x86_feature_detected!("avx512vnni")); - println!( - "avx512bitalg {:?}", - is_x86_feature_detected!("avx512bitalg") - ); - println!("avx512bf16 {:?}", is_x86_feature_detected!("avx512bf16")); - println!( - "avx512vp2intersect {:?}", - is_x86_feature_detected!("avx512vp2intersect") - ); - println!("avx512fp16 {:?}", is_x86_feature_detected!("avx512fp16")); - println!("f16c: {:?}", is_x86_feature_detected!("f16c")); - println!("fma: {:?}", is_x86_feature_detected!("fma")); - println!("bmi1: {:?}", is_x86_feature_detected!("bmi1")); - println!("bmi2: {:?}", is_x86_feature_detected!("bmi2")); - println!("abm: {:?}", is_x86_feature_detected!("abm")); - println!("lzcnt: {:?}", is_x86_feature_detected!("lzcnt")); - println!("tbm: {:?}", is_x86_feature_detected!("tbm")); - println!("movbe: {:?}", is_x86_feature_detected!("movbe")); - println!("popcnt: {:?}", is_x86_feature_detected!("popcnt")); - println!("fxsr: {:?}", is_x86_feature_detected!("fxsr")); - println!("xsave: {:?}", is_x86_feature_detected!("xsave")); - println!("xsaveopt: {:?}", is_x86_feature_detected!("xsaveopt")); - println!("xsaves: {:?}", is_x86_feature_detected!("xsaves")); - println!("xsavec: {:?}", is_x86_feature_detected!("xsavec")); - println!("amx-bf16: {:?}", is_x86_feature_detected!("amx-bf16")); - println!("amx-tile: {:?}", is_x86_feature_detected!("amx-tile")); - println!("amx-int8: {:?}", is_x86_feature_detected!("amx-int8")); - println!("amx-fp16: {:?}", is_x86_feature_detected!("amx-fp16")); - println!("amx-complex: {:?}", is_x86_feature_detected!("amx-complex")); - println!("xop: {:?}", is_x86_feature_detected!("xop")); -} - -#[test] -#[cfg(any(target_arch = "x86", target_arch = "x86_64"))] -#[allow(deprecated)] -fn x86_deprecated() { - println!("avx512gfni {:?}", is_x86_feature_detected!("avx512gfni")); - println!("avx512vaes {:?}", is_x86_feature_detected!("avx512vaes")); - println!( - "avx512vpclmulqdq {:?}", - is_x86_feature_detected!("avx512vpclmulqdq") - ); -} diff --git a/crates/std_detect/tests/x86-specific.rs b/crates/std_detect/tests/x86-specific.rs index 60b6756f86..349bba8635 100644 --- a/crates/std_detect/tests/x86-specific.rs +++ b/crates/std_detect/tests/x86-specific.rs @@ -185,3 +185,14 @@ fn compare_with_cupid() { assert_eq!(is_x86_feature_detected!("rtm"), information.rtm(),); assert_eq!(is_x86_feature_detected!("movbe"), information.movbe(),); } + +#[test] +#[allow(deprecated)] +fn x86_deprecated() { + println!("avx512gfni {:?}", is_x86_feature_detected!("avx512gfni")); + println!("avx512vaes {:?}", is_x86_feature_detected!("avx512vaes")); + println!( + "avx512vpclmulqdq {:?}", + is_x86_feature_detected!("avx512vpclmulqdq") + ); +} diff --git a/crates/stdarch-verify/tests/x86-intel.rs b/crates/stdarch-verify/tests/x86-intel.rs index f24f696e9d..92a3388ded 100644 --- a/crates/stdarch-verify/tests/x86-intel.rs +++ b/crates/stdarch-verify/tests/x86-intel.rs @@ -8,9 +8,8 @@ use std::io::{BufWriter, Write}; use serde::Deserialize; const PRINT_INSTRUCTION_VIOLATIONS: bool = false; -const PRINT_MISSING_LISTS: bool = false; -const PRINT_MISSING_LISTS_MARKDOWN: bool = false; -const SS: u8 = (8 * core::mem::size_of::()) as u8; +const GENERATE_MISSING_X86_MD: bool = false; +const SS: u8 = (8 * size_of::()) as u8; struct Function { name: &'static str, @@ -181,12 +180,7 @@ fn verify_all_signatures() { if !rust.has_test { // FIXME: this list should be almost empty let skip = [ - // EFLAGS - "__readeflags", - "__readeflags", - "__writeeflags", - "__writeeflags", - // MXCSR - deprecated + // MXCSR - deprecated, immediate UB "_mm_getcsr", "_mm_setcsr", "_MM_GET_EXCEPTION_MASK", @@ -207,14 +201,6 @@ fn verify_all_signatures() { "_xrstors", "_xsaves64", "_xrstors64", - // TSC - "_rdtsc", - "__rdtscp", - // TBM - "_t1mskc_u64", - // RTM - "_xbegin", - "_xend", // RDRAND "_rdrand16_step", "_rdrand32_step", @@ -250,16 +236,13 @@ fn verify_all_signatures() { "_mm256_unpacklo_epi32", "_mm256_unpackhi_epi64", "_mm256_unpacklo_epi64", - // Has tests with different name - "_mm_min_epi8", - "_mm_min_epi32", + // Has tests with some other intrinsic + "__writeeflags", "_xrstor", "_xrstor64", "_fxrstor", "_fxrstor64", - // Needs `f16` to test - "_mm_cvtps_ph", - "_mm256_cvtps_ph", + "_xend", // Aliases "_mm_comige_ss", "_mm_cvt_ss2si", @@ -307,16 +290,13 @@ fn verify_all_signatures() { "__cpuid" | "__get_cpuid_max" | // Not listed with intel, but manually verified - "cmpxchg16b" - => continue, + "cmpxchg16b" | // Intel requires the mask argument for _mm_shuffle_ps to be an // unsigned integer, but all other _mm_shuffle_.. intrinsics // take a signed-integer. This breaks `_MM_SHUFFLE` for - // `_mm_shuffle_ps`: - name@"_mm_shuffle_ps" => { - map.remove(name); - continue; - }, + // `_mm_shuffle_ps` + "_mm_shuffle_ps" + => continue, _ => {} } @@ -347,10 +327,7 @@ fn verify_all_signatures() { } assert!(all_valid); - if PRINT_MISSING_LISTS { - print_missing(&map, io::stdout()).unwrap(); - } - if PRINT_MISSING_LISTS_MARKDOWN { + if GENERATE_MISSING_X86_MD { print_missing( &map, BufWriter::new(File::create("../core_arch/missing-x86.md").unwrap()), @@ -383,23 +360,16 @@ fn print_missing(map: &HashMap<&str, Vec<&Intrinsic>>, mut f: impl Write) -> io: for (k, v) in &mut missing { v.sort_by_key(|intrinsic| &intrinsic.name); // sort to make the order of everything same - if PRINT_MISSING_LISTS_MARKDOWN { - writeln!(f, "\n
{k:?}

\n")?; - for intel in v { - let url = format!( - "https://software.intel.com/sites/landingpage\ + writeln!(f, "\n

{k:?}

\n")?; + for intel in v { + let url = format!( + "https://software.intel.com/sites/landingpage\ /IntrinsicsGuide/#text={}", - intel.name - ); - writeln!(f, " * [ ] [`{}`]({url})", intel.name)?; - } - writeln!(f, "

\n")?; - } else { - writeln!(f, "\n{k:?}\n")?; - for intel in v { - writeln!(f, "\t{}", intel.name)?; - } + intel.name + ); + writeln!(f, " * [ ] [`{}`]({url})", intel.name)?; } + writeln!(f, "

\n")?; } f.flush() @@ -470,51 +440,18 @@ fn check_target_features(rust: &Function, intel: &Intrinsic) -> Result<(), Strin continue; } - let cpuid = cpuid.to_lowercase(); + let cpuid = cpuid.to_lowercase().replace('_', ""); // Fix mismatching feature names: - let fixup_cpuid = |cpuid: String| match cpuid.as_ref() { + let fixed_cpuid = match cpuid.as_ref() { // The XML file names IFMA as "avx512ifma52", while Rust calls // it "avx512ifma". "avx512ifma52" => String::from("avx512ifma"), - // The XML file names BITALG as "avx512_bitalg", while Rust calls - // it "avx512bitalg". - "avx512_bitalg" => String::from("avx512bitalg"), - // The XML file names VBMI as "avx512_vbmi", while Rust calls - // it "avx512vbmi". - "avx512_vbmi" => String::from("avx512vbmi"), - // The XML file names VBMI2 as "avx512_vbmi2", while Rust calls - // it "avx512vbmi2". - "avx512_vbmi2" => String::from("avx512vbmi2"), - // The XML file names VNNI as "avx512_vnni", while Rust calls - // it "avx512vnni". - "avx512_vnni" => String::from("avx512vnni"), - // The XML file names BF16 as "avx512_bf16", while Rust calls - // it "avx512bf16". - "avx512_bf16" => String::from("avx512bf16"), - // The XML file names FP16 as "avx512_fp16", while Rust calls - // it "avx512fp16". - "avx512_fp16" => String::from("avx512fp16"), - // The XML file names AVX-VNNI as "avx_vnni", while Rust calls - // it "avxvnni" - "avx_vnni" => String::from("avxvnni"), - // The XML file names AVX-VNNI_INT8 as "avx_vnni_int8", while Rust calls - // it "avxvnniint8" - "avx_vnni_int8" => String::from("avxvnniint8"), - // The XML file names AVX-NE-CONVERT as "avx_ne_convert", while Rust calls - // it "avxvnni" - "avx_ne_convert" => String::from("avxneconvert"), - // The XML file names AVX-IFMA as "avx_ifma", while Rust calls - // it "avxifma" - "avx_ifma" => String::from("avxifma"), - // The XML file names AVX-VNNI_INT16 as "avx_vnni_int16", while Rust calls - // it "avxvnniint16" - "avx_vnni_int16" => String::from("avxvnniint16"), "xss" => String::from("xsaves"), _ => cpuid, }; - intel_cpuids.insert(fixup_cpuid(cpuid)); + intel_cpuids.insert(fixed_cpuid); } if intel_cpuids.contains("gfni") {