Fix names of several tests

sayantn · sayantn · commit 211c94cebfe0 · 2025-02-06T03:38:54.000+05:30
Rewrote `_mm_cvtps_ph` and `_mm_cvtph_ps` tests
diff --git a/crates/core_arch/src/x86/eflags.rs b/crates/core_arch/src/x86/eflags.rs
@@ -73,7 +73,7 @@ mod tests {
     #[test]
     #[cfg_attr(miri, ignore)] // Uses inline assembly
     #[allow(deprecated)]
-    fn test_eflags() {
+    fn test_readeflags() {
         unsafe {
             // reads eflags, writes them back, reads them again,
             // and compare for equality:
diff --git a/crates/core_arch/src/x86/f16c.rs b/crates/core_arch/src/x86/f16c.rs
@@ -98,23 +98,48 @@ mod tests {
     use crate::{core_arch::x86::*, mem::transmute};
     use stdarch_test::simd_test;
 
+    const F16_ONE: i16 = 0x3c00;
+    const F16_TWO: i16 = 0x4000;
+    const F16_THREE: i16 = 0x4200;
+    const F16_FOUR: i16 = 0x4400;
+    const F16_FIVE: i16 = 0x4500;
+    const F16_SIX: i16 = 0x4600;
+    const F16_SEVEN: i16 = 0x4700;
+    const F16_EIGHT: i16 = 0x4800;
+
     #[simd_test(enable = "f16c")]
     unsafe fn test_mm_cvtph_ps() {
-        let array = [1_f32, 2_f32, 3_f32, 4_f32];
-        let float_vec: __m128 = transmute(array);
-        let halfs: __m128i = _mm_cvtps_ph::<0>(float_vec);
-        let floats: __m128 = _mm_cvtph_ps(halfs);
-        let result: [f32; 4] = transmute(floats);
-        assert_eq!(result, array);
+        let a = _mm_set_epi16(0, 0, 0, 0, F16_ONE, F16_TWO, F16_THREE, F16_FOUR);
+        let r = _mm_cvtph_ps(a);
+        let e = _mm_set_ps(1.0, 2.0, 3.0, 4.0);
+        assert_eq_m128(r, e);
     }
 
     #[simd_test(enable = "f16c")]
     unsafe fn test_mm256_cvtph_ps() {
-        let array = [1_f32, 2_f32, 3_f32, 4_f32, 5_f32, 6_f32, 7_f32, 8_f32];
-        let float_vec: __m256 = transmute(array);
-        let halfs: __m128i = _mm256_cvtps_ph::<0>(float_vec);
-        let floats: __m256 = _mm256_cvtph_ps(halfs);
-        let result: [f32; 8] = transmute(floats);
-        assert_eq!(result, array);
+        let a = _mm_set_epi16(
+            F16_ONE, F16_TWO, F16_THREE, F16_FOUR, F16_FIVE, F16_SIX, F16_SEVEN, F16_EIGHT,
+        );
+        let r = _mm256_cvtph_ps(a);
+        let e = _mm256_set_ps(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
+        assert_eq_m256(r, e);
+    }
+
+    #[simd_test(enable = "f16c")]
+    unsafe fn test_mm_cvtps_ph() {
+        let a = _mm_set_ps(1.0, 2.0, 3.0, 4.0);
+        let r = _mm_cvtps_ph::<_MM_FROUND_CUR_DIRECTION>(a);
+        let e = _mm_set_epi16(0, 0, 0, 0, F16_ONE, F16_TWO, F16_THREE, F16_FOUR);
+        assert_eq_m128i(r, e);
+    }
+
+    #[simd_test(enable = "f16c")]
+    unsafe fn test_mm256_cvtps_ph() {
+        let a = _mm256_set_ps(1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0);
+        let r = _mm256_cvtps_ph::<_MM_FROUND_CUR_DIRECTION>(a);
+        let e = _mm_set_epi16(
+            F16_ONE, F16_TWO, F16_THREE, F16_FOUR, F16_FIVE, F16_SIX, F16_SEVEN, F16_EIGHT,
+        );
+        assert_eq_m128i(r, e);
     }
 }
diff --git a/crates/core_arch/src/x86/rdtsc.rs b/crates/core_arch/src/x86/rdtsc.rs
@@ -63,15 +63,15 @@ mod tests {
     use stdarch_test::simd_test;
 
     #[simd_test(enable = "sse2")]
-    unsafe fn _rdtsc() {
-        let r = rdtsc::_rdtsc();
+    unsafe fn test_rdtsc() {
+        let r = _rdtsc();
         assert_ne!(r, 0); // The chances of this being 0 are infinitesimal
     }
 
     #[simd_test(enable = "sse2")]
-    unsafe fn _rdtscp() {
+    unsafe fn test_rdtscp() {
         let mut aux = 0;
-        let r = rdtsc::__rdtscp(&mut aux);
+        let r = __rdtscp(&mut aux);
         assert_ne!(r, 0); // The chances of this being 0 are infinitesimal
     }
 }
diff --git a/crates/core_arch/src/x86/rtm.rs b/crates/core_arch/src/x86/rtm.rs
@@ -120,13 +120,13 @@ mod tests {
     use crate::core_arch::x86::*;
 
     #[simd_test(enable = "rtm")]
-    unsafe fn test_xbegin_xend() {
+    unsafe fn test_xbegin() {
         let mut x = 0;
         for _ in 0..10 {
-            let code = rtm::_xbegin();
+            let code = _xbegin();
             if code == _XBEGIN_STARTED {
                 x += 1;
-                rtm::_xend();
+                _xend();
                 assert_eq!(x, 1);
                 break;
             }
diff --git a/crates/core_arch/src/x86/sse41.rs b/crates/core_arch/src/x86/sse41.rs
@@ -1310,7 +1310,7 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    unsafe fn test_mm_min_epi8_1() {
+    unsafe fn test_mm_min_epi8() {
         #[rustfmt::skip]
         let a = _mm_setr_epi8(
             1, 4, 5, 8, 9, 12, 13, 16,
@@ -1328,10 +1328,7 @@ mod tests {
             17, 19, 21, 23, 25, 27, 29, 31,
         );
         assert_eq_m128i(r, e);
-    }
 
-    #[simd_test(enable = "sse4.1")]
-    unsafe fn test_mm_min_epi8_2() {
         #[rustfmt::skip]
         let a = _mm_setr_epi8(
             1, -4, -5, 8, -9, -12, 13, -16,
@@ -1361,16 +1358,13 @@ mod tests {
     }
 
     #[simd_test(enable = "sse4.1")]
-    unsafe fn test_mm_min_epi32_1() {
+    unsafe fn test_mm_min_epi32() {
         let a = _mm_setr_epi32(1, 4, 5, 8);
         let b = _mm_setr_epi32(2, 3, 6, 7);
         let r = _mm_min_epi32(a, b);
         let e = _mm_setr_epi32(1, 3, 5, 7);
         assert_eq_m128i(r, e);
-    }
 
-    #[simd_test(enable = "sse4.1")]
-    unsafe fn test_mm_min_epi32_2() {
         let a = _mm_setr_epi32(-1, 4, 5, -7);
         let b = _mm_setr_epi32(-2, 3, -6, 8);
         let r = _mm_min_epi32(a, b);
diff --git a/crates/core_arch/src/x86/xsave.rs b/crates/core_arch/src/x86/xsave.rs
@@ -185,10 +185,6 @@ mod tests {
         }
     }
 
-    // We cannot test for `_xsave`, `xrstor`, `_xsetbv`, `_xsaveopt`, `_xsaves`, `_xrstors` as they
-    // are privileged instructions and will need access to kernel mode to execute and test them.
-    // see https://github.com/rust-lang/stdarch/issues/209
-
     #[cfg_attr(stdarch_intel_sde, ignore)]
     #[simd_test(enable = "xsave")]
     #[cfg_attr(miri, ignore)] // Register saving/restoring is not supported in Miri
diff --git a/crates/core_arch/src/x86_64/tbm.rs b/crates/core_arch/src/x86_64/tbm.rs
@@ -206,7 +206,7 @@ mod tests {
     }
 
     #[simd_test(enable = "tbm")]
-    unsafe fn test_t1mksc_u64() {
+    unsafe fn test_t1mskc_u64() {
         assert_eq!(
             _t1mskc_u64(0b0101_0111u64),
             0b1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1000u64
diff --git a/crates/core_arch/src/x86_64/xsave.rs b/crates/core_arch/src/x86_64/xsave.rs
@@ -149,10 +149,6 @@ mod tests {
         }
     }
 
-    // We cannot test `_xsave64`, `_xrstor64`, `_xsaveopt64`, `_xsaves64` and `_xrstors64` directly
-    // as they are privileged instructions and will need access to the kernel to run and test them.
-    // See https://github.com/rust-lang/stdarch/issues/209
-
     #[cfg_attr(stdarch_intel_sde, ignore)]
     #[simd_test(enable = "xsave")]
     #[cfg_attr(miri, ignore)] // Register saving/restoring is not supported in Miri
diff --git a/crates/stdarch-verify/tests/x86-intel.rs b/crates/stdarch-verify/tests/x86-intel.rs
@@ -181,12 +181,7 @@ fn verify_all_signatures() {
         if !rust.has_test {
             // FIXME: this list should be almost empty
             let skip = [
-                // EFLAGS
-                "__readeflags",
-                "__readeflags",
-                "__writeeflags",
-                "__writeeflags",
-                // MXCSR - deprecated
+                // MXCSR - deprecated, immediate UB
                 "_mm_getcsr",
                 "_mm_setcsr",
                 "_MM_GET_EXCEPTION_MASK",
@@ -207,14 +202,6 @@ fn verify_all_signatures() {
                 "_xrstors",
                 "_xsaves64",
                 "_xrstors64",
-                // TSC
-                "_rdtsc",
-                "__rdtscp",
-                // TBM
-                "_t1mskc_u64",
-                // RTM
-                "_xbegin",
-                "_xend",
                 // RDRAND
                 "_rdrand16_step",
                 "_rdrand32_step",
@@ -250,16 +237,13 @@ fn verify_all_signatures() {
                 "_mm256_unpacklo_epi32",
                 "_mm256_unpackhi_epi64",
                 "_mm256_unpacklo_epi64",
-                // Has tests with different name
-                "_mm_min_epi8",
-                "_mm_min_epi32",
+                // Has tests with some other intrinsic
+                "__writeeflags",
                 "_xrstor",
                 "_xrstor64",
                 "_fxrstor",
                 "_fxrstor64",
-                // Needs `f16` to test
-                "_mm_cvtps_ph",
-                "_mm256_cvtps_ph",
+                "_xend",
                 // Aliases
                 "_mm_comige_ss",
                 "_mm_cvt_ss2si",

Original file line number	Diff line number	Diff line change
`@@ -63,15 +63,15 @@ mod tests {`
`63`	`63`	`use stdarch_test::simd_test;`
`64`	`64`
`65`	`65`	`#[simd_test(enable = "sse2")]`
`66`		`- unsafe fn _rdtsc() {`
`67`		`- let r = rdtsc::_rdtsc();`
	`66`	`+ unsafe fn test_rdtsc() {`
	`67`	`+ let r = _rdtsc();`
`68`	`68`	`assert_ne!(r, 0); // The chances of this being 0 are infinitesimal`
`69`	`69`	`}`
`70`	`70`
`71`	`71`	`#[simd_test(enable = "sse2")]`
`72`		`- unsafe fn _rdtscp() {`
	`72`	`+ unsafe fn test_rdtscp() {`
`73`	`73`	`let mut aux = 0;`
`74`		`- let r = rdtsc::__rdtscp(&mut aux);`
	`74`	`+ let r = __rdtscp(&mut aux);`
`75`	`75`	`assert_ne!(r, 0); // The chances of this being 0 are infinitesimal`
`76`	`76`	`}`
`77`	`77`	`}`
Original file line number	Diff line number	Diff line change
`@@ -185,10 +185,6 @@ mod tests {`
`185`	`185`	`}`
`186`	`186`	`}`
`187`	`187`
`188`		- // We cannot test for `_xsave`, `xrstor`, `_xsetbv`, `_xsaveopt`, `_xsaves`, `_xrstors` as they
`189`		`- // are privileged instructions and will need access to kernel mode to execute and test them.`
`190`		`- // see https://github.com/rust-lang/stdarch/issues/209`
`191`		`-`
`192`	`188`	`#[cfg_attr(stdarch_intel_sde, ignore)]`
`193`	`189`	`#[simd_test(enable = "xsave")]`
`194`	`190`	`#[cfg_attr(miri, ignore)] // Register saving/restoring is not supported in Miri`
Original file line number	Diff line number	Diff line change
`@@ -206,7 +206,7 @@ mod tests {`
`206`	`206`	`}`
`207`	`207`
`208`	`208`	`#[simd_test(enable = "tbm")]`
`209`		`- unsafe fn test_t1mksc_u64() {`
	`209`	`+ unsafe fn test_t1mskc_u64() {`
`210`	`210`	`assert_eq!(`
`211`	`211`	`_t1mskc_u64(0b0101_0111u64),`
`212`	`212`	`0b1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1000u64`
Original file line number	Diff line number	Diff line change
`@@ -149,10 +149,6 @@ mod tests {`
`149`	`149`	`}`
`150`	`150`	`}`
`151`	`151`
`152`		- // We cannot test `_xsave64`, `_xrstor64`, `_xsaveopt64`, `_xsaves64` and `_xrstors64` directly
`153`		`- // as they are privileged instructions and will need access to the kernel to run and test them.`
`154`		`- // See https://github.com/rust-lang/stdarch/issues/209`
`155`		`-`
`156`	`152`	`#[cfg_attr(stdarch_intel_sde, ignore)]`
`157`	`153`	`#[simd_test(enable = "xsave")]`
`158`	`154`	`#[cfg_attr(miri, ignore)] // Register saving/restoring is not supported in Miri`